1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/Support/TargetParser.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef _WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 68 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 69 // and so we must use an operating-system interface to determine the current 70 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 71 const char *generic = "generic"; 72 73 // The cpu line is second (after the 'processor: 0' line), so if this 74 // buffer is too small then something has changed (or is wrong). 75 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 76 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 77 78 StringRef::const_iterator CIP = CPUInfoStart; 79 80 StringRef::const_iterator CPUStart = 0; 81 size_t CPULen = 0; 82 83 // We need to find the first line which starts with cpu, spaces, and a colon. 84 // After the colon, there may be some additional spaces and then the cpu type. 85 while (CIP < CPUInfoEnd && CPUStart == 0) { 86 if (CIP < CPUInfoEnd && *CIP == '\n') 87 ++CIP; 88 89 if (CIP < CPUInfoEnd && *CIP == 'c') { 90 ++CIP; 91 if (CIP < CPUInfoEnd && *CIP == 'p') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'u') { 94 ++CIP; 95 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 96 ++CIP; 97 98 if (CIP < CPUInfoEnd && *CIP == ':') { 99 ++CIP; 100 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 101 ++CIP; 102 103 if (CIP < CPUInfoEnd) { 104 CPUStart = CIP; 105 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 106 *CIP != ',' && *CIP != '\n')) 107 ++CIP; 108 CPULen = CIP - CPUStart; 109 } 110 } 111 } 112 } 113 } 114 115 if (CPUStart == 0) 116 while (CIP < CPUInfoEnd && *CIP != '\n') 117 ++CIP; 118 } 119 120 if (CPUStart == 0) 121 return generic; 122 123 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 124 .Case("604e", "604e") 125 .Case("604", "604") 126 .Case("7400", "7400") 127 .Case("7410", "7400") 128 .Case("7447", "7400") 129 .Case("7455", "7450") 130 .Case("G4", "g4") 131 .Case("POWER4", "970") 132 .Case("PPC970FX", "970") 133 .Case("PPC970MP", "970") 134 .Case("G5", "g5") 135 .Case("POWER5", "g5") 136 .Case("A2", "a2") 137 .Case("POWER6", "pwr6") 138 .Case("POWER7", "pwr7") 139 .Case("POWER8", "pwr8") 140 .Case("POWER8E", "pwr8") 141 .Case("POWER8NVL", "pwr8") 142 .Case("POWER9", "pwr9") 143 .Default(generic); 144 } 145 146 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 147 // The cpuid register on arm is not accessible from user space. On Linux, 148 // it is exposed through the /proc/cpuinfo file. 149 150 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 151 // in all cases. 152 SmallVector<StringRef, 32> Lines; 153 ProcCpuinfoContent.split(Lines, "\n"); 154 155 // Look for the CPU implementer line. 156 StringRef Implementer; 157 StringRef Hardware; 158 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 159 if (Lines[I].startswith("CPU implementer")) 160 Implementer = Lines[I].substr(15).ltrim("\t :"); 161 if (Lines[I].startswith("Hardware")) 162 Hardware = Lines[I].substr(8).ltrim("\t :"); 163 } 164 165 if (Implementer == "0x41") { // ARM Ltd. 166 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 167 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 168 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 169 return "cortex-a53"; 170 171 172 // Look for the CPU part line. 173 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 174 if (Lines[I].startswith("CPU part")) 175 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 176 // values correspond to the "Part number" in the CP15/c0 register. The 177 // contents are specified in the various processor manuals. 178 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 179 .Case("0x926", "arm926ej-s") 180 .Case("0xb02", "mpcore") 181 .Case("0xb36", "arm1136j-s") 182 .Case("0xb56", "arm1156t2-s") 183 .Case("0xb76", "arm1176jz-s") 184 .Case("0xc08", "cortex-a8") 185 .Case("0xc09", "cortex-a9") 186 .Case("0xc0f", "cortex-a15") 187 .Case("0xc20", "cortex-m0") 188 .Case("0xc23", "cortex-m3") 189 .Case("0xc24", "cortex-m4") 190 .Case("0xd04", "cortex-a35") 191 .Case("0xd03", "cortex-a53") 192 .Case("0xd07", "cortex-a57") 193 .Case("0xd08", "cortex-a72") 194 .Case("0xd09", "cortex-a73") 195 .Default("generic"); 196 } 197 198 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 199 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 200 if (Lines[I].startswith("CPU part")) { 201 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 202 .Case("0x516", "thunderx2t99") 203 .Case("0x0516", "thunderx2t99") 204 .Case("0xaf", "thunderx2t99") 205 .Case("0x0af", "thunderx2t99") 206 .Case("0xa1", "thunderxt88") 207 .Case("0x0a1", "thunderxt88") 208 .Default("generic"); 209 } 210 } 211 } 212 213 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 214 // Look for the CPU part line. 215 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 216 if (Lines[I].startswith("CPU part")) 217 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 218 // values correspond to the "Part number" in the CP15/c0 register. The 219 // contents are specified in the various processor manuals. 220 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 221 .Case("0xd01", "tsv110") 222 .Default("generic"); 223 224 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 225 // Look for the CPU part line. 226 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 227 if (Lines[I].startswith("CPU part")) 228 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 229 // values correspond to the "Part number" in the CP15/c0 register. The 230 // contents are specified in the various processor manuals. 231 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 232 .Case("0x06f", "krait") // APQ8064 233 .Case("0x201", "kryo") 234 .Case("0x205", "kryo") 235 .Case("0x211", "kryo") 236 .Case("0x800", "cortex-a73") 237 .Case("0x801", "cortex-a73") 238 .Case("0xc00", "falkor") 239 .Case("0xc01", "saphira") 240 .Default("generic"); 241 242 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 243 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 244 // any predictive pattern across variants and parts. 245 unsigned Variant = 0, Part = 0; 246 247 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 248 // number, corresponding to the Variant bits in the CP15/C0 register. 249 for (auto I : Lines) 250 if (I.consume_front("CPU variant")) 251 I.ltrim("\t :").getAsInteger(0, Variant); 252 253 // Look for the CPU part line, whose value is a 3 digit hexadecimal 254 // number, corresponding to the PartNum bits in the CP15/C0 register. 255 for (auto I : Lines) 256 if (I.consume_front("CPU part")) 257 I.ltrim("\t :").getAsInteger(0, Part); 258 259 unsigned Exynos = (Variant << 12) | Part; 260 switch (Exynos) { 261 default: 262 // Default by falling through to Exynos M1. 263 LLVM_FALLTHROUGH; 264 265 case 0x1001: 266 return "exynos-m1"; 267 268 case 0x4001: 269 return "exynos-m2"; 270 } 271 } 272 273 return "generic"; 274 } 275 276 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 277 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 278 279 // The "processor 0:" line comes after a fair amount of other information, 280 // including a cache breakdown, but this should be plenty. 281 SmallVector<StringRef, 32> Lines; 282 ProcCpuinfoContent.split(Lines, "\n"); 283 284 // Look for the CPU features. 285 SmallVector<StringRef, 32> CPUFeatures; 286 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 287 if (Lines[I].startswith("features")) { 288 size_t Pos = Lines[I].find(":"); 289 if (Pos != StringRef::npos) { 290 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 291 break; 292 } 293 } 294 295 // We need to check for the presence of vector support independently of 296 // the machine type, since we may only use the vector register set when 297 // supported by the kernel (and hypervisor). 298 bool HaveVectorSupport = false; 299 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 300 if (CPUFeatures[I] == "vx") 301 HaveVectorSupport = true; 302 } 303 304 // Now check the processor machine type. 305 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 306 if (Lines[I].startswith("processor ")) { 307 size_t Pos = Lines[I].find("machine = "); 308 if (Pos != StringRef::npos) { 309 Pos += sizeof("machine = ") - 1; 310 unsigned int Id; 311 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 312 if (Id >= 3906 && HaveVectorSupport) 313 return "z14"; 314 if (Id >= 2964 && HaveVectorSupport) 315 return "z13"; 316 if (Id >= 2827) 317 return "zEC12"; 318 if (Id >= 2817) 319 return "z196"; 320 } 321 } 322 break; 323 } 324 } 325 326 return "generic"; 327 } 328 329 StringRef sys::detail::getHostCPUNameForBPF() { 330 #if !defined(__linux__) || !defined(__x86_64__) 331 return "generic"; 332 #else 333 uint8_t insns[40] __attribute__ ((aligned (8))) = 334 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 335 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 336 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 337 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 338 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 339 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 340 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 341 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 342 /* BPF_EXIT_INSN() */ 343 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 344 345 struct bpf_prog_load_attr { 346 uint32_t prog_type; 347 uint32_t insn_cnt; 348 uint64_t insns; 349 uint64_t license; 350 uint32_t log_level; 351 uint32_t log_size; 352 uint64_t log_buf; 353 uint32_t kern_version; 354 uint32_t prog_flags; 355 } attr = {}; 356 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 357 attr.insn_cnt = 5; 358 attr.insns = (uint64_t)insns; 359 attr.license = (uint64_t)"DUMMY"; 360 361 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 362 if (fd >= 0) { 363 close(fd); 364 return "v2"; 365 } 366 return "v1"; 367 #endif 368 } 369 370 #if defined(__i386__) || defined(_M_IX86) || \ 371 defined(__x86_64__) || defined(_M_X64) 372 373 enum VendorSignatures { 374 SIG_INTEL = 0x756e6547 /* Genu */, 375 SIG_AMD = 0x68747541 /* Auth */ 376 }; 377 378 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 379 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 380 // support. Consequently, for i386, the presence of CPUID is checked first 381 // via the corresponding eflags bit. 382 // Removal of cpuid.h header motivated by PR30384 383 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 384 // or test-suite, but are used in external projects e.g. libstdcxx 385 static bool isCpuIdSupported() { 386 #if defined(__GNUC__) || defined(__clang__) 387 #if defined(__i386__) 388 int __cpuid_supported; 389 __asm__(" pushfl\n" 390 " popl %%eax\n" 391 " movl %%eax,%%ecx\n" 392 " xorl $0x00200000,%%eax\n" 393 " pushl %%eax\n" 394 " popfl\n" 395 " pushfl\n" 396 " popl %%eax\n" 397 " movl $0,%0\n" 398 " cmpl %%eax,%%ecx\n" 399 " je 1f\n" 400 " movl $1,%0\n" 401 "1:" 402 : "=r"(__cpuid_supported) 403 : 404 : "eax", "ecx"); 405 if (!__cpuid_supported) 406 return false; 407 #endif 408 return true; 409 #endif 410 return true; 411 } 412 413 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 414 /// the specified arguments. If we can't run cpuid on the host, return true. 415 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 416 unsigned *rECX, unsigned *rEDX) { 417 #if defined(__GNUC__) || defined(__clang__) 418 #if defined(__x86_64__) 419 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 420 // FIXME: should we save this for Clang? 421 __asm__("movq\t%%rbx, %%rsi\n\t" 422 "cpuid\n\t" 423 "xchgq\t%%rbx, %%rsi\n\t" 424 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 425 : "a"(value)); 426 return false; 427 #elif defined(__i386__) 428 __asm__("movl\t%%ebx, %%esi\n\t" 429 "cpuid\n\t" 430 "xchgl\t%%ebx, %%esi\n\t" 431 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 432 : "a"(value)); 433 return false; 434 #else 435 return true; 436 #endif 437 #elif defined(_MSC_VER) 438 // The MSVC intrinsic is portable across x86 and x64. 439 int registers[4]; 440 __cpuid(registers, value); 441 *rEAX = registers[0]; 442 *rEBX = registers[1]; 443 *rECX = registers[2]; 444 *rEDX = registers[3]; 445 return false; 446 #else 447 return true; 448 #endif 449 } 450 451 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 452 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 453 /// return true. 454 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 455 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 456 unsigned *rEDX) { 457 #if defined(__GNUC__) || defined(__clang__) 458 #if defined(__x86_64__) 459 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 460 // FIXME: should we save this for Clang? 461 __asm__("movq\t%%rbx, %%rsi\n\t" 462 "cpuid\n\t" 463 "xchgq\t%%rbx, %%rsi\n\t" 464 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 465 : "a"(value), "c"(subleaf)); 466 return false; 467 #elif defined(__i386__) 468 __asm__("movl\t%%ebx, %%esi\n\t" 469 "cpuid\n\t" 470 "xchgl\t%%ebx, %%esi\n\t" 471 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 472 : "a"(value), "c"(subleaf)); 473 return false; 474 #else 475 return true; 476 #endif 477 #elif defined(_MSC_VER) 478 int registers[4]; 479 __cpuidex(registers, value, subleaf); 480 *rEAX = registers[0]; 481 *rEBX = registers[1]; 482 *rECX = registers[2]; 483 *rEDX = registers[3]; 484 return false; 485 #else 486 return true; 487 #endif 488 } 489 490 // Read control register 0 (XCR0). Used to detect features such as AVX. 491 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 492 #if defined(__GNUC__) || defined(__clang__) 493 // Check xgetbv; this uses a .byte sequence instead of the instruction 494 // directly because older assemblers do not include support for xgetbv and 495 // there is no easy way to conditionally compile based on the assembler used. 496 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 497 return false; 498 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 499 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 500 *rEAX = Result; 501 *rEDX = Result >> 32; 502 return false; 503 #else 504 return true; 505 #endif 506 } 507 508 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 509 unsigned *Model) { 510 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 511 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 512 if (*Family == 6 || *Family == 0xf) { 513 if (*Family == 0xf) 514 // Examine extended family ID if family ID is F. 515 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 516 // Examine extended model ID if family ID is 6 or F. 517 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 518 } 519 } 520 521 static void 522 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 523 unsigned Brand_id, unsigned Features, 524 unsigned Features2, unsigned Features3, 525 unsigned *Type, unsigned *Subtype) { 526 if (Brand_id != 0) 527 return; 528 switch (Family) { 529 case 3: 530 *Type = X86::INTEL_i386; 531 break; 532 case 4: 533 *Type = X86::INTEL_i486; 534 break; 535 case 5: 536 if (Features & (1 << X86::FEATURE_MMX)) { 537 *Type = X86::INTEL_PENTIUM_MMX; 538 break; 539 } 540 *Type = X86::INTEL_PENTIUM; 541 break; 542 case 6: 543 switch (Model) { 544 case 0x01: // Pentium Pro processor 545 *Type = X86::INTEL_PENTIUM_PRO; 546 break; 547 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 548 // model 03 549 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 550 // model 05, and Intel Celeron processor, model 05 551 case 0x06: // Celeron processor, model 06 552 *Type = X86::INTEL_PENTIUM_II; 553 break; 554 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 555 // processor, model 07 556 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 557 // model 08, and Celeron processor, model 08 558 case 0x0a: // Pentium III Xeon processor, model 0Ah 559 case 0x0b: // Pentium III processor, model 0Bh 560 *Type = X86::INTEL_PENTIUM_III; 561 break; 562 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 563 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 564 // 0Dh. All processors are manufactured using the 90 nm process. 565 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 566 // Integrated Processor with Intel QuickAssist Technology 567 *Type = X86::INTEL_PENTIUM_M; 568 break; 569 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 570 // 0Eh. All processors are manufactured using the 65 nm process. 571 *Type = X86::INTEL_CORE_DUO; 572 break; // yonah 573 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 574 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 575 // mobile processor, Intel Core 2 Extreme processor, Intel 576 // Pentium Dual-Core processor, Intel Xeon processor, model 577 // 0Fh. All processors are manufactured using the 65 nm process. 578 case 0x16: // Intel Celeron processor model 16h. All processors are 579 // manufactured using the 65 nm process 580 *Type = X86::INTEL_CORE2; // "core2" 581 *Subtype = X86::INTEL_CORE2_65; 582 break; 583 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 584 // 17h. All processors are manufactured using the 45 nm process. 585 // 586 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 587 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 588 // the 45 nm process. 589 *Type = X86::INTEL_CORE2; // "penryn" 590 *Subtype = X86::INTEL_CORE2_45; 591 break; 592 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 593 // processors are manufactured using the 45 nm process. 594 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 595 // As found in a Summer 2010 model iMac. 596 case 0x1f: 597 case 0x2e: // Nehalem EX 598 *Type = X86::INTEL_COREI7; // "nehalem" 599 *Subtype = X86::INTEL_COREI7_NEHALEM; 600 break; 601 case 0x25: // Intel Core i7, laptop version. 602 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 603 // processors are manufactured using the 32 nm process. 604 case 0x2f: // Westmere EX 605 *Type = X86::INTEL_COREI7; // "westmere" 606 *Subtype = X86::INTEL_COREI7_WESTMERE; 607 break; 608 case 0x2a: // Intel Core i7 processor. All processors are manufactured 609 // using the 32 nm process. 610 case 0x2d: 611 *Type = X86::INTEL_COREI7; //"sandybridge" 612 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 613 break; 614 case 0x3a: 615 case 0x3e: // Ivy Bridge EP 616 *Type = X86::INTEL_COREI7; // "ivybridge" 617 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 618 break; 619 620 // Haswell: 621 case 0x3c: 622 case 0x3f: 623 case 0x45: 624 case 0x46: 625 *Type = X86::INTEL_COREI7; // "haswell" 626 *Subtype = X86::INTEL_COREI7_HASWELL; 627 break; 628 629 // Broadwell: 630 case 0x3d: 631 case 0x47: 632 case 0x4f: 633 case 0x56: 634 *Type = X86::INTEL_COREI7; // "broadwell" 635 *Subtype = X86::INTEL_COREI7_BROADWELL; 636 break; 637 638 // Skylake: 639 case 0x4e: // Skylake mobile 640 case 0x5e: // Skylake desktop 641 case 0x8e: // Kaby Lake mobile 642 case 0x9e: // Kaby Lake desktop 643 *Type = X86::INTEL_COREI7; // "skylake" 644 *Subtype = X86::INTEL_COREI7_SKYLAKE; 645 break; 646 647 // Skylake Xeon: 648 case 0x55: 649 *Type = X86::INTEL_COREI7; 650 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 651 break; 652 653 // Cannonlake: 654 case 0x66: 655 *Type = X86::INTEL_COREI7; 656 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 657 break; 658 659 case 0x1c: // Most 45 nm Intel Atom processors 660 case 0x26: // 45 nm Atom Lincroft 661 case 0x27: // 32 nm Atom Medfield 662 case 0x35: // 32 nm Atom Midview 663 case 0x36: // 32 nm Atom Midview 664 *Type = X86::INTEL_BONNELL; 665 break; // "bonnell" 666 667 // Atom Silvermont codes from the Intel software optimization guide. 668 case 0x37: 669 case 0x4a: 670 case 0x4d: 671 case 0x5a: 672 case 0x5d: 673 case 0x4c: // really airmont 674 *Type = X86::INTEL_SILVERMONT; 675 break; // "silvermont" 676 // Goldmont: 677 case 0x5c: // Apollo Lake 678 case 0x5f: // Denverton 679 *Type = X86::INTEL_GOLDMONT; 680 break; // "goldmont" 681 case 0x7a: 682 *Type = X86::INTEL_GOLDMONT_PLUS; 683 break; 684 case 0x57: 685 *Type = X86::INTEL_KNL; // knl 686 break; 687 case 0x85: 688 *Type = X86::INTEL_KNM; // knm 689 break; 690 691 default: // Unknown family 6 CPU, try to guess. 692 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 693 *Type = X86::INTEL_COREI7; 694 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 695 break; 696 } 697 698 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 699 *Type = X86::INTEL_COREI7; 700 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 701 break; 702 } 703 704 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 705 *Type = X86::INTEL_COREI7; 706 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 707 break; 708 } 709 710 if (Features & (1 << X86::FEATURE_AVX512VL)) { 711 *Type = X86::INTEL_COREI7; 712 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 713 break; 714 } 715 716 if (Features & (1 << X86::FEATURE_AVX512ER)) { 717 *Type = X86::INTEL_KNL; // knl 718 break; 719 } 720 721 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 722 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 723 *Type = X86::INTEL_GOLDMONT; 724 } else { 725 *Type = X86::INTEL_COREI7; 726 *Subtype = X86::INTEL_COREI7_SKYLAKE; 727 } 728 break; 729 } 730 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 731 *Type = X86::INTEL_COREI7; 732 *Subtype = X86::INTEL_COREI7_BROADWELL; 733 break; 734 } 735 if (Features & (1 << X86::FEATURE_AVX2)) { 736 *Type = X86::INTEL_COREI7; 737 *Subtype = X86::INTEL_COREI7_HASWELL; 738 break; 739 } 740 if (Features & (1 << X86::FEATURE_AVX)) { 741 *Type = X86::INTEL_COREI7; 742 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 743 break; 744 } 745 if (Features & (1 << X86::FEATURE_SSE4_2)) { 746 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 747 *Type = X86::INTEL_SILVERMONT; 748 } else { 749 *Type = X86::INTEL_COREI7; 750 *Subtype = X86::INTEL_COREI7_NEHALEM; 751 } 752 break; 753 } 754 if (Features & (1 << X86::FEATURE_SSE4_1)) { 755 *Type = X86::INTEL_CORE2; // "penryn" 756 *Subtype = X86::INTEL_CORE2_45; 757 break; 758 } 759 if (Features & (1 << X86::FEATURE_SSSE3)) { 760 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 761 *Type = X86::INTEL_BONNELL; // "bonnell" 762 } else { 763 *Type = X86::INTEL_CORE2; // "core2" 764 *Subtype = X86::INTEL_CORE2_65; 765 } 766 break; 767 } 768 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 769 *Type = X86::INTEL_CORE2; // "core2" 770 *Subtype = X86::INTEL_CORE2_65; 771 break; 772 } 773 if (Features & (1 << X86::FEATURE_SSE3)) { 774 *Type = X86::INTEL_CORE_DUO; 775 break; 776 } 777 if (Features & (1 << X86::FEATURE_SSE2)) { 778 *Type = X86::INTEL_PENTIUM_M; 779 break; 780 } 781 if (Features & (1 << X86::FEATURE_SSE)) { 782 *Type = X86::INTEL_PENTIUM_III; 783 break; 784 } 785 if (Features & (1 << X86::FEATURE_MMX)) { 786 *Type = X86::INTEL_PENTIUM_II; 787 break; 788 } 789 *Type = X86::INTEL_PENTIUM_PRO; 790 break; 791 } 792 break; 793 case 15: { 794 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 795 *Type = X86::INTEL_NOCONA; 796 break; 797 } 798 if (Features & (1 << X86::FEATURE_SSE3)) { 799 *Type = X86::INTEL_PRESCOTT; 800 break; 801 } 802 *Type = X86::INTEL_PENTIUM_IV; 803 break; 804 } 805 default: 806 break; /*"generic"*/ 807 } 808 } 809 810 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 811 unsigned Features, unsigned *Type, 812 unsigned *Subtype) { 813 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 814 // appears to be no way to generate the wide variety of AMD-specific targets 815 // from the information returned from CPUID. 816 switch (Family) { 817 case 4: 818 *Type = X86::AMD_i486; 819 break; 820 case 5: 821 *Type = X86::AMDPENTIUM; 822 switch (Model) { 823 case 6: 824 case 7: 825 *Subtype = X86::AMDPENTIUM_K6; 826 break; // "k6" 827 case 8: 828 *Subtype = X86::AMDPENTIUM_K62; 829 break; // "k6-2" 830 case 9: 831 case 13: 832 *Subtype = X86::AMDPENTIUM_K63; 833 break; // "k6-3" 834 case 10: 835 *Subtype = X86::AMDPENTIUM_GEODE; 836 break; // "geode" 837 } 838 break; 839 case 6: 840 if (Features & (1 << X86::FEATURE_SSE)) { 841 *Type = X86::AMD_ATHLON_XP; 842 break; // "athlon-xp" 843 } 844 *Type = X86::AMD_ATHLON; 845 break; // "athlon" 846 case 15: 847 if (Features & (1 << X86::FEATURE_SSE3)) { 848 *Type = X86::AMD_K8SSE3; 849 break; // "k8-sse3" 850 } 851 *Type = X86::AMD_K8; 852 break; // "k8" 853 case 16: 854 *Type = X86::AMDFAM10H; // "amdfam10" 855 switch (Model) { 856 case 2: 857 *Subtype = X86::AMDFAM10H_BARCELONA; 858 break; 859 case 4: 860 *Subtype = X86::AMDFAM10H_SHANGHAI; 861 break; 862 case 8: 863 *Subtype = X86::AMDFAM10H_ISTANBUL; 864 break; 865 } 866 break; 867 case 20: 868 *Type = X86::AMD_BTVER1; 869 break; // "btver1"; 870 case 21: 871 *Type = X86::AMDFAM15H; 872 if (Model >= 0x60 && Model <= 0x7f) { 873 *Subtype = X86::AMDFAM15H_BDVER4; 874 break; // "bdver4"; 60h-7Fh: Excavator 875 } 876 if (Model >= 0x30 && Model <= 0x3f) { 877 *Subtype = X86::AMDFAM15H_BDVER3; 878 break; // "bdver3"; 30h-3Fh: Steamroller 879 } 880 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 881 *Subtype = X86::AMDFAM15H_BDVER2; 882 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 883 } 884 if (Model <= 0x0f) { 885 *Subtype = X86::AMDFAM15H_BDVER1; 886 break; // "bdver1"; 00h-0Fh: Bulldozer 887 } 888 break; 889 case 22: 890 *Type = X86::AMD_BTVER2; 891 break; // "btver2" 892 case 23: 893 *Type = X86::AMDFAM17H; 894 *Subtype = X86::AMDFAM17H_ZNVER1; 895 break; 896 default: 897 break; // "generic" 898 } 899 } 900 901 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 902 unsigned *FeaturesOut, unsigned *Features2Out, 903 unsigned *Features3Out) { 904 unsigned Features = 0; 905 unsigned Features2 = 0; 906 unsigned Features3 = 0; 907 unsigned EAX, EBX; 908 909 auto setFeature = [&](unsigned F) { 910 if (F < 32) 911 Features |= 1U << (F & 0x1f); 912 else if (F < 64) 913 Features2 |= 1U << ((F - 32) & 0x1f); 914 else if (F < 96) 915 Features3 |= 1U << ((F - 64) & 0x1f); 916 else 917 llvm_unreachable("Unexpected FeatureBit"); 918 }; 919 920 if ((EDX >> 15) & 1) 921 setFeature(X86::FEATURE_CMOV); 922 if ((EDX >> 23) & 1) 923 setFeature(X86::FEATURE_MMX); 924 if ((EDX >> 25) & 1) 925 setFeature(X86::FEATURE_SSE); 926 if ((EDX >> 26) & 1) 927 setFeature(X86::FEATURE_SSE2); 928 929 if ((ECX >> 0) & 1) 930 setFeature(X86::FEATURE_SSE3); 931 if ((ECX >> 1) & 1) 932 setFeature(X86::FEATURE_PCLMUL); 933 if ((ECX >> 9) & 1) 934 setFeature(X86::FEATURE_SSSE3); 935 if ((ECX >> 12) & 1) 936 setFeature(X86::FEATURE_FMA); 937 if ((ECX >> 19) & 1) 938 setFeature(X86::FEATURE_SSE4_1); 939 if ((ECX >> 20) & 1) 940 setFeature(X86::FEATURE_SSE4_2); 941 if ((ECX >> 23) & 1) 942 setFeature(X86::FEATURE_POPCNT); 943 if ((ECX >> 25) & 1) 944 setFeature(X86::FEATURE_AES); 945 946 if ((ECX >> 22) & 1) 947 setFeature(X86::FEATURE_MOVBE); 948 949 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 950 // indicates that the AVX registers will be saved and restored on context 951 // switch, then we have full AVX support. 952 const unsigned AVXBits = (1 << 27) | (1 << 28); 953 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 954 ((EAX & 0x6) == 0x6); 955 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 956 957 if (HasAVX) 958 setFeature(X86::FEATURE_AVX); 959 960 bool HasLeaf7 = 961 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 962 963 if (HasLeaf7 && ((EBX >> 3) & 1)) 964 setFeature(X86::FEATURE_BMI); 965 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 966 setFeature(X86::FEATURE_AVX2); 967 if (HasLeaf7 && ((EBX >> 9) & 1)) 968 setFeature(X86::FEATURE_BMI2); 969 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 970 setFeature(X86::FEATURE_AVX512F); 971 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 972 setFeature(X86::FEATURE_AVX512DQ); 973 if (HasLeaf7 && ((EBX >> 19) & 1)) 974 setFeature(X86::FEATURE_ADX); 975 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 976 setFeature(X86::FEATURE_AVX512IFMA); 977 if (HasLeaf7 && ((EBX >> 23) & 1)) 978 setFeature(X86::FEATURE_CLFLUSHOPT); 979 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 980 setFeature(X86::FEATURE_AVX512PF); 981 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 982 setFeature(X86::FEATURE_AVX512ER); 983 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 984 setFeature(X86::FEATURE_AVX512CD); 985 if (HasLeaf7 && ((EBX >> 29) & 1)) 986 setFeature(X86::FEATURE_SHA); 987 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 988 setFeature(X86::FEATURE_AVX512BW); 989 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 990 setFeature(X86::FEATURE_AVX512VL); 991 992 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 993 setFeature(X86::FEATURE_AVX512VBMI); 994 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 995 setFeature(X86::FEATURE_AVX512VBMI2); 996 if (HasLeaf7 && ((ECX >> 8) & 1)) 997 setFeature(X86::FEATURE_GFNI); 998 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 999 setFeature(X86::FEATURE_VPCLMULQDQ); 1000 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1001 setFeature(X86::FEATURE_AVX512VNNI); 1002 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1003 setFeature(X86::FEATURE_AVX512BITALG); 1004 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1005 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1006 1007 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1008 setFeature(X86::FEATURE_AVX5124VNNIW); 1009 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1010 setFeature(X86::FEATURE_AVX5124FMAPS); 1011 1012 unsigned MaxExtLevel; 1013 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1014 1015 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1016 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1017 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1018 setFeature(X86::FEATURE_SSE4_A); 1019 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1020 setFeature(X86::FEATURE_XOP); 1021 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1022 setFeature(X86::FEATURE_FMA4); 1023 1024 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1025 setFeature(X86::FEATURE_EM64T); 1026 1027 *FeaturesOut = Features; 1028 *Features2Out = Features2; 1029 *Features3Out = Features3; 1030 } 1031 1032 StringRef sys::getHostCPUName() { 1033 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1034 unsigned MaxLeaf, Vendor; 1035 1036 #if defined(__GNUC__) || defined(__clang__) 1037 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1038 // and simplify it to not invoke __cpuid (like cpu_model.c in 1039 // compiler-rt/lib/builtins/cpu_model.c? 1040 // Opting for the second option. 1041 if(!isCpuIdSupported()) 1042 return "generic"; 1043 #endif 1044 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1045 return "generic"; 1046 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1047 1048 unsigned Brand_id = EBX & 0xff; 1049 unsigned Family = 0, Model = 0; 1050 unsigned Features = 0, Features2 = 0, Features3 = 0; 1051 detectX86FamilyModel(EAX, &Family, &Model); 1052 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1053 1054 unsigned Type = 0; 1055 unsigned Subtype = 0; 1056 1057 if (Vendor == SIG_INTEL) { 1058 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1059 Features2, Features3, &Type, &Subtype); 1060 } else if (Vendor == SIG_AMD) { 1061 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1062 } 1063 1064 // Check subtypes first since those are more specific. 1065 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1066 if (Subtype == X86::ENUM) \ 1067 return ARCHNAME; 1068 #include "llvm/Support/X86TargetParser.def" 1069 1070 // Now check types. 1071 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1072 if (Type == X86::ENUM) \ 1073 return ARCHNAME; 1074 #include "llvm/Support/X86TargetParser.def" 1075 1076 return "generic"; 1077 } 1078 1079 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1080 StringRef sys::getHostCPUName() { 1081 host_basic_info_data_t hostInfo; 1082 mach_msg_type_number_t infoCount; 1083 1084 infoCount = HOST_BASIC_INFO_COUNT; 1085 mach_port_t hostPort = mach_host_self(); 1086 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1087 &infoCount); 1088 mach_port_deallocate(mach_task_self(), hostPort); 1089 1090 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1091 return "generic"; 1092 1093 switch (hostInfo.cpu_subtype) { 1094 case CPU_SUBTYPE_POWERPC_601: 1095 return "601"; 1096 case CPU_SUBTYPE_POWERPC_602: 1097 return "602"; 1098 case CPU_SUBTYPE_POWERPC_603: 1099 return "603"; 1100 case CPU_SUBTYPE_POWERPC_603e: 1101 return "603e"; 1102 case CPU_SUBTYPE_POWERPC_603ev: 1103 return "603ev"; 1104 case CPU_SUBTYPE_POWERPC_604: 1105 return "604"; 1106 case CPU_SUBTYPE_POWERPC_604e: 1107 return "604e"; 1108 case CPU_SUBTYPE_POWERPC_620: 1109 return "620"; 1110 case CPU_SUBTYPE_POWERPC_750: 1111 return "750"; 1112 case CPU_SUBTYPE_POWERPC_7400: 1113 return "7400"; 1114 case CPU_SUBTYPE_POWERPC_7450: 1115 return "7450"; 1116 case CPU_SUBTYPE_POWERPC_970: 1117 return "970"; 1118 default:; 1119 } 1120 1121 return "generic"; 1122 } 1123 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1124 StringRef sys::getHostCPUName() { 1125 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1126 StringRef Content = P ? P->getBuffer() : ""; 1127 return detail::getHostCPUNameForPowerPC(Content); 1128 } 1129 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1130 StringRef sys::getHostCPUName() { 1131 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1132 StringRef Content = P ? P->getBuffer() : ""; 1133 return detail::getHostCPUNameForARM(Content); 1134 } 1135 #elif defined(__linux__) && defined(__s390x__) 1136 StringRef sys::getHostCPUName() { 1137 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1138 StringRef Content = P ? P->getBuffer() : ""; 1139 return detail::getHostCPUNameForS390x(Content); 1140 } 1141 #else 1142 StringRef sys::getHostCPUName() { return "generic"; } 1143 #endif 1144 1145 #if defined(__linux__) && defined(__x86_64__) 1146 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1147 // using the number of unique physical/core id pairs. The following 1148 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1149 static int computeHostNumPhysicalCores() { 1150 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1151 // mmapped because it appears to have 0 size. 1152 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1153 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1154 if (std::error_code EC = Text.getError()) { 1155 llvm::errs() << "Can't read " 1156 << "/proc/cpuinfo: " << EC.message() << "\n"; 1157 return -1; 1158 } 1159 SmallVector<StringRef, 8> strs; 1160 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1161 /*KeepEmpty=*/false); 1162 int CurPhysicalId = -1; 1163 int CurCoreId = -1; 1164 SmallSet<std::pair<int, int>, 32> UniqueItems; 1165 for (auto &Line : strs) { 1166 Line = Line.trim(); 1167 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1168 continue; 1169 std::pair<StringRef, StringRef> Data = Line.split(':'); 1170 auto Name = Data.first.trim(); 1171 auto Val = Data.second.trim(); 1172 if (Name == "physical id") { 1173 assert(CurPhysicalId == -1 && 1174 "Expected a core id before seeing another physical id"); 1175 Val.getAsInteger(10, CurPhysicalId); 1176 } 1177 if (Name == "core id") { 1178 assert(CurCoreId == -1 && 1179 "Expected a physical id before seeing another core id"); 1180 Val.getAsInteger(10, CurCoreId); 1181 } 1182 if (CurPhysicalId != -1 && CurCoreId != -1) { 1183 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1184 CurPhysicalId = -1; 1185 CurCoreId = -1; 1186 } 1187 } 1188 return UniqueItems.size(); 1189 } 1190 #elif defined(__APPLE__) && defined(__x86_64__) 1191 #include <sys/param.h> 1192 #include <sys/sysctl.h> 1193 1194 // Gets the number of *physical cores* on the machine. 1195 static int computeHostNumPhysicalCores() { 1196 uint32_t count; 1197 size_t len = sizeof(count); 1198 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1199 if (count < 1) { 1200 int nm[2]; 1201 nm[0] = CTL_HW; 1202 nm[1] = HW_AVAILCPU; 1203 sysctl(nm, 2, &count, &len, NULL, 0); 1204 if (count < 1) 1205 return -1; 1206 } 1207 return count; 1208 } 1209 #else 1210 // On other systems, return -1 to indicate unknown. 1211 static int computeHostNumPhysicalCores() { return -1; } 1212 #endif 1213 1214 int sys::getHostNumPhysicalCores() { 1215 static int NumCores = computeHostNumPhysicalCores(); 1216 return NumCores; 1217 } 1218 1219 #if defined(__i386__) || defined(_M_IX86) || \ 1220 defined(__x86_64__) || defined(_M_X64) 1221 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1222 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1223 unsigned MaxLevel; 1224 union { 1225 unsigned u[3]; 1226 char c[12]; 1227 } text; 1228 1229 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1230 MaxLevel < 1) 1231 return false; 1232 1233 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1234 1235 Features["cmov"] = (EDX >> 15) & 1; 1236 Features["mmx"] = (EDX >> 23) & 1; 1237 Features["sse"] = (EDX >> 25) & 1; 1238 Features["sse2"] = (EDX >> 26) & 1; 1239 1240 Features["sse3"] = (ECX >> 0) & 1; 1241 Features["pclmul"] = (ECX >> 1) & 1; 1242 Features["ssse3"] = (ECX >> 9) & 1; 1243 Features["cx16"] = (ECX >> 13) & 1; 1244 Features["sse4.1"] = (ECX >> 19) & 1; 1245 Features["sse4.2"] = (ECX >> 20) & 1; 1246 Features["movbe"] = (ECX >> 22) & 1; 1247 Features["popcnt"] = (ECX >> 23) & 1; 1248 Features["aes"] = (ECX >> 25) & 1; 1249 Features["rdrnd"] = (ECX >> 30) & 1; 1250 1251 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1252 // indicates that the AVX registers will be saved and restored on context 1253 // switch, then we have full AVX support. 1254 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1255 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1256 // AVX512 requires additional context to be saved by the OS. 1257 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1258 1259 Features["avx"] = HasAVXSave; 1260 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1261 // Only enable XSAVE if OS has enabled support for saving YMM state. 1262 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1263 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1264 1265 unsigned MaxExtLevel; 1266 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1267 1268 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1269 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1270 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1271 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1272 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1273 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1274 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1275 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1276 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1277 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1278 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1279 1280 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1281 1282 // Miscellaneous memory related features, detected by 1283 // using the 0x80000008 leaf of the CPUID instruction 1284 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1285 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1286 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1287 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1288 1289 bool HasLeaf7 = 1290 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1291 1292 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1293 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1294 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1295 // AVX2 is only supported if we have the OS save support from AVX. 1296 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1297 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1298 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1299 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1300 // AVX512 is only supported if the OS supports the context save for it. 1301 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1302 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1303 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1304 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1305 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1306 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1307 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1308 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1309 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1310 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1311 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1312 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1313 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1314 1315 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1316 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1317 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1318 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1319 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1320 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1321 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1322 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1323 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1324 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1325 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1326 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1327 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1328 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1329 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1330 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1331 1332 // There are two CPUID leafs which information associated with the pconfig 1333 // instruction: 1334 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1335 // bit of EDX), while the EAX=0x1b leaf returns information on the 1336 // availability of specific pconfig leafs. 1337 // The target feature here only refers to the the first of these two. 1338 // Users might need to check for the availability of specific pconfig 1339 // leaves using cpuid, since that information is ignored while 1340 // detecting features using the "-march=native" flag. 1341 // For more info, see X86 ISA docs. 1342 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1343 1344 bool HasLeafD = MaxLevel >= 0xd && 1345 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1346 1347 // Only enable XSAVE if OS has enabled support for saving YMM state. 1348 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1349 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1350 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1351 1352 bool HasLeaf14 = MaxLevel >= 0x14 && 1353 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1354 1355 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1356 1357 return true; 1358 } 1359 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1360 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1361 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1362 if (!P) 1363 return false; 1364 1365 SmallVector<StringRef, 32> Lines; 1366 P->getBuffer().split(Lines, "\n"); 1367 1368 SmallVector<StringRef, 32> CPUFeatures; 1369 1370 // Look for the CPU features. 1371 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1372 if (Lines[I].startswith("Features")) { 1373 Lines[I].split(CPUFeatures, ' '); 1374 break; 1375 } 1376 1377 #if defined(__aarch64__) 1378 // Keep track of which crypto features we have seen 1379 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1380 uint32_t crypto = 0; 1381 #endif 1382 1383 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1384 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1385 #if defined(__aarch64__) 1386 .Case("asimd", "neon") 1387 .Case("fp", "fp-armv8") 1388 .Case("crc32", "crc") 1389 #else 1390 .Case("half", "fp16") 1391 .Case("neon", "neon") 1392 .Case("vfpv3", "vfp3") 1393 .Case("vfpv3d16", "d16") 1394 .Case("vfpv4", "vfp4") 1395 .Case("idiva", "hwdiv-arm") 1396 .Case("idivt", "hwdiv") 1397 #endif 1398 .Default(""); 1399 1400 #if defined(__aarch64__) 1401 // We need to check crypto separately since we need all of the crypto 1402 // extensions to enable the subtarget feature 1403 if (CPUFeatures[I] == "aes") 1404 crypto |= CAP_AES; 1405 else if (CPUFeatures[I] == "pmull") 1406 crypto |= CAP_PMULL; 1407 else if (CPUFeatures[I] == "sha1") 1408 crypto |= CAP_SHA1; 1409 else if (CPUFeatures[I] == "sha2") 1410 crypto |= CAP_SHA2; 1411 #endif 1412 1413 if (LLVMFeatureStr != "") 1414 Features[LLVMFeatureStr] = true; 1415 } 1416 1417 #if defined(__aarch64__) 1418 // If we have all crypto bits we can add the feature 1419 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1420 Features["crypto"] = true; 1421 #endif 1422 1423 return true; 1424 } 1425 #else 1426 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1427 #endif 1428 1429 std::string sys::getProcessTriple() { 1430 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1431 Triple PT(Triple::normalize(TargetTripleString)); 1432 1433 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1434 PT = PT.get64BitArchVariant(); 1435 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1436 PT = PT.get32BitArchVariant(); 1437 1438 return PT.str(); 1439 } 1440