1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //  This file implements the operating system Host concept.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include <string.h>
24 
25 // Include the platform-specific parts of this class.
26 #ifdef LLVM_ON_UNIX
27 #include "Unix/Host.inc"
28 #endif
29 #ifdef LLVM_ON_WIN32
30 #include "Windows/Host.inc"
31 #endif
32 #ifdef _MSC_VER
33 #include <intrin.h>
34 #endif
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/host_info.h>
37 #include <mach/mach.h>
38 #include <mach/mach_host.h>
39 #include <mach/machine.h>
40 #endif
41 
42 #define DEBUG_TYPE "host-detection"
43 
44 //===----------------------------------------------------------------------===//
45 //
46 //  Implementations of the CPU detection routines
47 //
48 //===----------------------------------------------------------------------===//
49 
50 using namespace llvm;
51 
52 #if defined(__linux__)
53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
54   // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
55   // memory buffer because the 'file' has 0 size (it can be read from only
56   // as a stream).
57 
58   int FD;
59   std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD);
60   if (EC) {
61     DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n");
62     return -1;
63   }
64   int Ret = read(FD, Buf, Size);
65   int CloseStatus = close(FD);
66   if (CloseStatus)
67     return -1;
68   return Ret;
69 }
70 #endif
71 
72 #if defined(i386) || defined(__i386__) || defined(__x86__) ||                  \
73     defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) ||            \
74     defined(_M_X64)
75 
76 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
77 /// the specified arguments.  If we can't run cpuid on the host, return true.
78 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
79                                unsigned *rECX, unsigned *rEDX) {
80 #if defined(__GNUC__) || defined(__clang__)
81 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
82   // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
83   asm("movq\t%%rbx, %%rsi\n\t"
84       "cpuid\n\t"
85       "xchgq\t%%rbx, %%rsi\n\t"
86       : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
87       : "a"(value));
88   return false;
89 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
90   asm("movl\t%%ebx, %%esi\n\t"
91       "cpuid\n\t"
92       "xchgl\t%%ebx, %%esi\n\t"
93       : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
94       : "a"(value));
95   return false;
96 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
97 // postprocessed code that looks like "return true; return false;")
98 #else
99   return true;
100 #endif
101 #elif defined(_MSC_VER)
102   // The MSVC intrinsic is portable across x86 and x64.
103   int registers[4];
104   __cpuid(registers, value);
105   *rEAX = registers[0];
106   *rEBX = registers[1];
107   *rECX = registers[2];
108   *rEDX = registers[3];
109   return false;
110 #else
111   return true;
112 #endif
113 }
114 
115 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
116 /// the 4 values in the specified arguments.  If we can't run cpuid on the host,
117 /// return true.
118 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
119                                  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
120                                  unsigned *rEDX) {
121 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
122 #if defined(__GNUC__)
123   // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
124   asm("movq\t%%rbx, %%rsi\n\t"
125       "cpuid\n\t"
126       "xchgq\t%%rbx, %%rsi\n\t"
127       : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
128       : "a"(value), "c"(subleaf));
129   return false;
130 #elif defined(_MSC_VER)
131   int registers[4];
132   __cpuidex(registers, value, subleaf);
133   *rEAX = registers[0];
134   *rEBX = registers[1];
135   *rECX = registers[2];
136   *rEDX = registers[3];
137   return false;
138 #else
139   return true;
140 #endif
141 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
142 #if defined(__GNUC__)
143   asm("movl\t%%ebx, %%esi\n\t"
144       "cpuid\n\t"
145       "xchgl\t%%ebx, %%esi\n\t"
146       : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
147       : "a"(value), "c"(subleaf));
148   return false;
149 #elif defined(_MSC_VER)
150   __asm {
151       mov   eax,value
152       mov   ecx,subleaf
153       cpuid
154       mov   esi,rEAX
155       mov   dword ptr [esi],eax
156       mov   esi,rEBX
157       mov   dword ptr [esi],ebx
158       mov   esi,rECX
159       mov   dword ptr [esi],ecx
160       mov   esi,rEDX
161       mov   dword ptr [esi],edx
162   }
163   return false;
164 #else
165   return true;
166 #endif
167 #else
168   return true;
169 #endif
170 }
171 
172 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
173 #if defined(__GNUC__)
174   // Check xgetbv; this uses a .byte sequence instead of the instruction
175   // directly because older assemblers do not include support for xgetbv and
176   // there is no easy way to conditionally compile based on the assembler used.
177   __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
178   return false;
179 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
180   unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
181   *rEAX = Result;
182   *rEDX = Result >> 32;
183   return false;
184 #else
185   return true;
186 #endif
187 }
188 
189 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
190                                  unsigned *Model) {
191   *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
192   *Model = (EAX >> 4) & 0xf;  // Bits 4 - 7
193   if (*Family == 6 || *Family == 0xf) {
194     if (*Family == 0xf)
195       // Examine extended family ID if family ID is F.
196       *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
197     // Examine extended model ID if family ID is 6 or F.
198     *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
199   }
200 }
201 
202 StringRef sys::getHostCPUName() {
203   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
204   if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
205     return "generic";
206   unsigned Family = 0;
207   unsigned Model = 0;
208   detectX86FamilyModel(EAX, &Family, &Model);
209 
210   union {
211     unsigned u[3];
212     char c[12];
213   } text;
214 
215   unsigned MaxLeaf;
216   getX86CpuIDAndInfo(0, &MaxLeaf, text.u + 0, text.u + 2, text.u + 1);
217 
218   bool HasMMX = (EDX >> 23) & 1;
219   bool HasSSE = (EDX >> 25) & 1;
220   bool HasSSE2 = (EDX >> 26) & 1;
221   bool HasSSE3 = (ECX >> 0) & 1;
222   bool HasSSSE3 = (ECX >> 9) & 1;
223   bool HasSSE41 = (ECX >> 19) & 1;
224   bool HasSSE42 = (ECX >> 20) & 1;
225   bool HasMOVBE = (ECX >> 22) & 1;
226   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
227   // indicates that the AVX registers will be saved and restored on context
228   // switch, then we have full AVX support.
229   const unsigned AVXBits = (1 << 27) | (1 << 28);
230   bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
231                 ((EAX & 0x6) == 0x6);
232   bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
233   bool HasLeaf7 =
234       MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
235   bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
236   bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
237   bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
238 
239   getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
240   bool Em64T = (EDX >> 29) & 0x1;
241   bool HasTBM = (ECX >> 21) & 0x1;
242 
243   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
244     switch (Family) {
245     case 3:
246       return "i386";
247     case 4:
248       switch (Model) {
249       case 0: // Intel486 DX processors
250       case 1: // Intel486 DX processors
251       case 2: // Intel486 SX processors
252       case 3: // Intel487 processors, IntelDX2 OverDrive processors,
253               // IntelDX2 processors
254       case 4: // Intel486 SL processor
255       case 5: // IntelSX2 processors
256       case 7: // Write-Back Enhanced IntelDX2 processors
257       case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
258       default:
259         return "i486";
260       }
261     case 5:
262       switch (Model) {
263       case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
264               // Pentium processors (60, 66)
265       case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
266               // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
267               // 150, 166, 200)
268       case 3: // Pentium OverDrive processors for Intel486 processor-based
269               // systems
270         return "pentium";
271 
272       case 4: // Pentium OverDrive processor with MMX technology for Pentium
273               // processor (75, 90, 100, 120, 133), Pentium processor with
274               // MMX technology (166, 200)
275         return "pentium-mmx";
276 
277       default:
278         return "pentium";
279       }
280     case 6:
281       switch (Model) {
282       case 0x01: // Pentium Pro processor
283         return "pentiumpro";
284 
285       case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
286                  // model 03
287       case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
288                  // model 05, and Intel Celeron processor, model 05
289       case 0x06: // Celeron processor, model 06
290         return "pentium2";
291 
292       case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
293                  // processor, model 07
294       case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
295                  // model 08, and Celeron processor, model 08
296       case 0x0a: // Pentium III Xeon processor, model 0Ah
297       case 0x0b: // Pentium III processor, model 0Bh
298         return "pentium3";
299 
300       case 0x09: // Intel Pentium M processor, Intel Celeron M processor model
301                  // 09.
302       case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
303                  // 0Dh. All processors are manufactured using the 90 nm
304                  // process.
305       case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
306                  // Integrated Processor with Intel QuickAssist Technology
307         return "pentium-m";
308 
309       case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
310                  // 0Eh. All processors are manufactured using the 65 nm
311                  // process.
312         return "yonah";
313 
314       case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
315                  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
316                  // mobile processor, Intel Core 2 Extreme processor, Intel
317                  // Pentium Dual-Core processor, Intel Xeon processor, model
318                  // 0Fh. All processors are manufactured using the 65 nm
319                  // process.
320       case 0x16: // Intel Celeron processor model 16h. All processors are
321                  // manufactured using the 65 nm process
322         return "core2";
323 
324       case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
325                  // 17h. All processors are manufactured using the 45 nm
326                  // process.
327                  //
328                  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
329       case 0x1d: // Intel Xeon processor MP. All processors are manufactured
330                  // using
331                  // the 45 nm process.
332         return "penryn";
333 
334       case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
335                  // processors are manufactured using the 45 nm process.
336       case 0x1e: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
337                  // As found in a Summer 2010 model iMac.
338       case 0x2e: // Nehalem EX
339         return "nehalem";
340       case 0x25: // Intel Core i7, laptop version.
341       case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
342                  // processors are manufactured using the 32 nm process.
343       case 0x2f: // Westmere EX
344         return "westmere";
345 
346       case 0x2a: // Intel Core i7 processor. All processors are manufactured
347                  // using the 32 nm process.
348       case 0x2d:
349         return "sandybridge";
350 
351       case 0x3a:
352       case 0x3e: // Ivy Bridge EP
353         return "ivybridge";
354 
355       // Haswell:
356       case 0x3c:
357       case 0x3f:
358       case 0x45:
359       case 0x46:
360         return "haswell";
361 
362       // Broadwell:
363       case 0x3d:
364       case 0x47:
365       case 0x4f:
366       case 0x56:
367         return "broadwell";
368 
369       // Skylake:
370       case 0x4e:
371         return "skylake-avx512";
372       case 0x5e:
373         return "skylake";
374 
375       case 0x1c: // Most 45 nm Intel Atom processors
376       case 0x26: // 45 nm Atom Lincroft
377       case 0x27: // 32 nm Atom Medfield
378       case 0x35: // 32 nm Atom Midview
379       case 0x36: // 32 nm Atom Midview
380         return "bonnell";
381 
382       // Atom Silvermont codes from the Intel software optimization guide.
383       case 0x37:
384       case 0x4a:
385       case 0x4d:
386       case 0x5a:
387       case 0x5d:
388       case 0x4c: // really airmont
389         return "silvermont";
390 
391       case 0x57:
392         return "knl";
393 
394       default: // Unknown family 6 CPU, try to guess.
395         if (HasAVX512)
396           return "knl";
397         if (HasADX)
398           return "broadwell";
399         if (HasAVX2)
400           return "haswell";
401         if (HasAVX)
402           return "sandybridge";
403         if (HasSSE42)
404           return HasMOVBE ? "silvermont" : "nehalem";
405         if (HasSSE41)
406           return "penryn";
407         if (HasSSSE3)
408           return HasMOVBE ? "bonnell" : "core2";
409         if (Em64T)
410           return "x86-64";
411         if (HasSSE2)
412           return "pentium-m";
413         if (HasSSE)
414           return "pentium3";
415         if (HasMMX)
416           return "pentium2";
417         return "pentiumpro";
418       }
419     case 15: {
420       switch (Model) {
421       case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
422               // model 00h and manufactured using the 0.18 micron process.
423       case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
424               // processor MP, and Intel Celeron processor. All processors are
425               // model 01h and manufactured using the 0.18 micron process.
426       case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
427               // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
428               // processor, and Mobile Intel Celeron processor. All processors
429               // are model 02h and manufactured using the 0.13 micron process.
430         return (Em64T) ? "x86-64" : "pentium4";
431 
432       case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
433               // processor. All processors are model 03h and manufactured using
434               // the 90 nm process.
435       case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
436               // Pentium D processor, Intel Xeon processor, Intel Xeon
437               // processor MP, Intel Celeron D processor. All processors are
438               // model 04h and manufactured using the 90 nm process.
439       case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
440               // Extreme Edition, Intel Xeon processor, Intel Xeon processor
441               // MP, Intel Celeron D processor. All processors are model 06h
442               // and manufactured using the 65 nm process.
443         return (Em64T) ? "nocona" : "prescott";
444 
445       default:
446         return (Em64T) ? "x86-64" : "pentium4";
447       }
448     }
449 
450     default:
451       return "generic";
452     }
453   } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
454     // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
455     // appears to be no way to generate the wide variety of AMD-specific targets
456     // from the information returned from CPUID.
457     switch (Family) {
458     case 4:
459       return "i486";
460     case 5:
461       switch (Model) {
462       case 6:
463       case 7:
464         return "k6";
465       case 8:
466         return "k6-2";
467       case 9:
468       case 13:
469         return "k6-3";
470       case 10:
471         return "geode";
472       default:
473         return "pentium";
474       }
475     case 6:
476       switch (Model) {
477       case 4:
478         return "athlon-tbird";
479       case 6:
480       case 7:
481       case 8:
482         return "athlon-mp";
483       case 10:
484         return "athlon-xp";
485       default:
486         return "athlon";
487       }
488     case 15:
489       if (HasSSE3)
490         return "k8-sse3";
491       switch (Model) {
492       case 1:
493         return "opteron";
494       case 5:
495         return "athlon-fx"; // also opteron
496       default:
497         return "athlon64";
498       }
499     case 16:
500       return "amdfam10";
501     case 20:
502       return "btver1";
503     case 21:
504       if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
505         return "btver1";
506       if (Model >= 0x50)
507         return "bdver4"; // 50h-6Fh: Excavator
508       if (Model >= 0x30)
509         return "bdver3"; // 30h-3Fh: Steamroller
510       if (Model >= 0x10 || HasTBM)
511         return "bdver2"; // 10h-1Fh: Piledriver
512       return "bdver1";   // 00h-0Fh: Bulldozer
513     case 22:
514       if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
515         return "btver1";
516       return "btver2";
517     default:
518       return "generic";
519     }
520   }
521   return "generic";
522 }
523 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
524 StringRef sys::getHostCPUName() {
525   host_basic_info_data_t hostInfo;
526   mach_msg_type_number_t infoCount;
527 
528   infoCount = HOST_BASIC_INFO_COUNT;
529   host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
530             &infoCount);
531 
532   if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
533     return "generic";
534 
535   switch (hostInfo.cpu_subtype) {
536   case CPU_SUBTYPE_POWERPC_601:
537     return "601";
538   case CPU_SUBTYPE_POWERPC_602:
539     return "602";
540   case CPU_SUBTYPE_POWERPC_603:
541     return "603";
542   case CPU_SUBTYPE_POWERPC_603e:
543     return "603e";
544   case CPU_SUBTYPE_POWERPC_603ev:
545     return "603ev";
546   case CPU_SUBTYPE_POWERPC_604:
547     return "604";
548   case CPU_SUBTYPE_POWERPC_604e:
549     return "604e";
550   case CPU_SUBTYPE_POWERPC_620:
551     return "620";
552   case CPU_SUBTYPE_POWERPC_750:
553     return "750";
554   case CPU_SUBTYPE_POWERPC_7400:
555     return "7400";
556   case CPU_SUBTYPE_POWERPC_7450:
557     return "7450";
558   case CPU_SUBTYPE_POWERPC_970:
559     return "970";
560   default:;
561   }
562 
563   return "generic";
564 }
565 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
566 StringRef sys::getHostCPUName() {
567   // Access to the Processor Version Register (PVR) on PowerPC is privileged,
568   // and so we must use an operating-system interface to determine the current
569   // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
570   const char *generic = "generic";
571 
572   // The cpu line is second (after the 'processor: 0' line), so if this
573   // buffer is too small then something has changed (or is wrong).
574   char buffer[1024];
575   ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
576   if (CPUInfoSize == -1)
577     return generic;
578 
579   const char *CPUInfoStart = buffer;
580   const char *CPUInfoEnd = buffer + CPUInfoSize;
581 
582   const char *CIP = CPUInfoStart;
583 
584   const char *CPUStart = 0;
585   size_t CPULen = 0;
586 
587   // We need to find the first line which starts with cpu, spaces, and a colon.
588   // After the colon, there may be some additional spaces and then the cpu type.
589   while (CIP < CPUInfoEnd && CPUStart == 0) {
590     if (CIP < CPUInfoEnd && *CIP == '\n')
591       ++CIP;
592 
593     if (CIP < CPUInfoEnd && *CIP == 'c') {
594       ++CIP;
595       if (CIP < CPUInfoEnd && *CIP == 'p') {
596         ++CIP;
597         if (CIP < CPUInfoEnd && *CIP == 'u') {
598           ++CIP;
599           while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
600             ++CIP;
601 
602           if (CIP < CPUInfoEnd && *CIP == ':') {
603             ++CIP;
604             while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
605               ++CIP;
606 
607             if (CIP < CPUInfoEnd) {
608               CPUStart = CIP;
609               while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
610                                           *CIP != ',' && *CIP != '\n'))
611                 ++CIP;
612               CPULen = CIP - CPUStart;
613             }
614           }
615         }
616       }
617     }
618 
619     if (CPUStart == 0)
620       while (CIP < CPUInfoEnd && *CIP != '\n')
621         ++CIP;
622   }
623 
624   if (CPUStart == 0)
625     return generic;
626 
627   return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
628       .Case("604e", "604e")
629       .Case("604", "604")
630       .Case("7400", "7400")
631       .Case("7410", "7400")
632       .Case("7447", "7400")
633       .Case("7455", "7450")
634       .Case("G4", "g4")
635       .Case("POWER4", "970")
636       .Case("PPC970FX", "970")
637       .Case("PPC970MP", "970")
638       .Case("G5", "g5")
639       .Case("POWER5", "g5")
640       .Case("A2", "a2")
641       .Case("POWER6", "pwr6")
642       .Case("POWER7", "pwr7")
643       .Case("POWER8", "pwr8")
644       .Case("POWER8E", "pwr8")
645       .Case("POWER9", "pwr9")
646       .Default(generic);
647 }
648 #elif defined(__linux__) && defined(__arm__)
649 StringRef sys::getHostCPUName() {
650   // The cpuid register on arm is not accessible from user space. On Linux,
651   // it is exposed through the /proc/cpuinfo file.
652 
653   // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
654   // in all cases.
655   char buffer[1024];
656   ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
657   if (CPUInfoSize == -1)
658     return "generic";
659 
660   StringRef Str(buffer, CPUInfoSize);
661 
662   SmallVector<StringRef, 32> Lines;
663   Str.split(Lines, "\n");
664 
665   // Look for the CPU implementer line.
666   StringRef Implementer;
667   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
668     if (Lines[I].startswith("CPU implementer"))
669       Implementer = Lines[I].substr(15).ltrim("\t :");
670 
671   if (Implementer == "0x41") // ARM Ltd.
672     // Look for the CPU part line.
673     for (unsigned I = 0, E = Lines.size(); I != E; ++I)
674       if (Lines[I].startswith("CPU part"))
675         // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
676         // values correspond to the "Part number" in the CP15/c0 register. The
677         // contents are specified in the various processor manuals.
678         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
679             .Case("0x926", "arm926ej-s")
680             .Case("0xb02", "mpcore")
681             .Case("0xb36", "arm1136j-s")
682             .Case("0xb56", "arm1156t2-s")
683             .Case("0xb76", "arm1176jz-s")
684             .Case("0xc08", "cortex-a8")
685             .Case("0xc09", "cortex-a9")
686             .Case("0xc0f", "cortex-a15")
687             .Case("0xc20", "cortex-m0")
688             .Case("0xc23", "cortex-m3")
689             .Case("0xc24", "cortex-m4")
690             .Default("generic");
691 
692   if (Implementer == "0x51") // Qualcomm Technologies, Inc.
693     // Look for the CPU part line.
694     for (unsigned I = 0, E = Lines.size(); I != E; ++I)
695       if (Lines[I].startswith("CPU part"))
696         // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
697         // values correspond to the "Part number" in the CP15/c0 register. The
698         // contents are specified in the various processor manuals.
699         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
700             .Case("0x06f", "krait") // APQ8064
701             .Default("generic");
702 
703   return "generic";
704 }
705 #elif defined(__linux__) && defined(__s390x__)
706 StringRef sys::getHostCPUName() {
707   // STIDP is a privileged operation, so use /proc/cpuinfo instead.
708 
709   // The "processor 0:" line comes after a fair amount of other information,
710   // including a cache breakdown, but this should be plenty.
711   char buffer[2048];
712   ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
713   if (CPUInfoSize == -1)
714     return "generic";
715 
716   StringRef Str(buffer, CPUInfoSize);
717   SmallVector<StringRef, 32> Lines;
718   Str.split(Lines, "\n");
719 
720   // Look for the CPU features.
721   SmallVector<StringRef, 32> CPUFeatures;
722   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
723     if (Lines[I].startswith("features")) {
724       size_t Pos = Lines[I].find(":");
725       if (Pos != StringRef::npos) {
726         Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
727         break;
728       }
729     }
730 
731   // We need to check for the presence of vector support independently of
732   // the machine type, since we may only use the vector register set when
733   // supported by the kernel (and hypervisor).
734   bool HaveVectorSupport = false;
735   for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
736     if (CPUFeatures[I] == "vx")
737       HaveVectorSupport = true;
738   }
739 
740   // Now check the processor machine type.
741   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
742     if (Lines[I].startswith("processor ")) {
743       size_t Pos = Lines[I].find("machine = ");
744       if (Pos != StringRef::npos) {
745         Pos += sizeof("machine = ") - 1;
746         unsigned int Id;
747         if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
748           if (Id >= 2964 && HaveVectorSupport)
749             return "z13";
750           if (Id >= 2827)
751             return "zEC12";
752           if (Id >= 2817)
753             return "z196";
754         }
755       }
756       break;
757     }
758   }
759 
760   return "generic";
761 }
762 #else
763 StringRef sys::getHostCPUName() { return "generic"; }
764 #endif
765 
766 #if defined(i386) || defined(__i386__) || defined(__x86__) ||                  \
767     defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) ||            \
768     defined(_M_X64)
769 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
770   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
771   unsigned MaxLevel;
772   union {
773     unsigned u[3];
774     char c[12];
775   } text;
776 
777   if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
778       MaxLevel < 1)
779     return false;
780 
781   getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
782 
783   Features["cmov"] = (EDX >> 15) & 1;
784   Features["mmx"] = (EDX >> 23) & 1;
785   Features["sse"] = (EDX >> 25) & 1;
786   Features["sse2"] = (EDX >> 26) & 1;
787   Features["sse3"] = (ECX >> 0) & 1;
788   Features["ssse3"] = (ECX >> 9) & 1;
789   Features["sse4.1"] = (ECX >> 19) & 1;
790   Features["sse4.2"] = (ECX >> 20) & 1;
791 
792   Features["pclmul"] = (ECX >> 1) & 1;
793   Features["cx16"] = (ECX >> 13) & 1;
794   Features["movbe"] = (ECX >> 22) & 1;
795   Features["popcnt"] = (ECX >> 23) & 1;
796   Features["aes"] = (ECX >> 25) & 1;
797   Features["rdrnd"] = (ECX >> 30) & 1;
798 
799   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
800   // indicates that the AVX registers will be saved and restored on context
801   // switch, then we have full AVX support.
802   bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
803                     !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
804   Features["avx"] = HasAVXSave;
805   Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
806   Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
807 
808   // Only enable XSAVE if OS has enabled support for saving YMM state.
809   Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
810 
811   // AVX512 requires additional context to be saved by the OS.
812   bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
813 
814   unsigned MaxExtLevel;
815   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
816 
817   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
818                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
819   Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
820   Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
821   Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
822   Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
823   Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
824   Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
825   Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
826 
827   bool HasLeaf7 =
828       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
829 
830   // AVX2 is only supported if we have the OS save support from AVX.
831   Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
832 
833   Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
834   Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
835   Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
836   Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
837   Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
838   Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
839   Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
840   Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
841   Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
842   Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
843   Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
844   Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
845   Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
846   Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
847 
848   // AVX512 is only supported if the OS supports the context save for it.
849   Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
850   Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
851   Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
852   Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
853   Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
854   Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
855   Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
856   Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
857 
858   Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
859   Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
860   // Enable protection keys
861   Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
862 
863   bool HasLeafD = MaxLevel >= 0xd &&
864                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
865 
866   // Only enable XSAVE if OS has enabled support for saving YMM state.
867   Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
868   Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
869   Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
870 
871   return true;
872 }
873 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
874 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
875   // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
876   // in all cases.
877   char buffer[1024];
878   ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
879   if (CPUInfoSize == -1)
880     return false;
881 
882   StringRef Str(buffer, CPUInfoSize);
883 
884   SmallVector<StringRef, 32> Lines;
885   Str.split(Lines, "\n");
886 
887   SmallVector<StringRef, 32> CPUFeatures;
888 
889   // Look for the CPU features.
890   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
891     if (Lines[I].startswith("Features")) {
892       Lines[I].split(CPUFeatures, ' ');
893       break;
894     }
895 
896 #if defined(__aarch64__)
897   // Keep track of which crypto features we have seen
898   enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
899   uint32_t crypto = 0;
900 #endif
901 
902   for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
903     StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
904 #if defined(__aarch64__)
905                                    .Case("asimd", "neon")
906                                    .Case("fp", "fp-armv8")
907                                    .Case("crc32", "crc")
908 #else
909                                    .Case("half", "fp16")
910                                    .Case("neon", "neon")
911                                    .Case("vfpv3", "vfp3")
912                                    .Case("vfpv3d16", "d16")
913                                    .Case("vfpv4", "vfp4")
914                                    .Case("idiva", "hwdiv-arm")
915                                    .Case("idivt", "hwdiv")
916 #endif
917                                    .Default("");
918 
919 #if defined(__aarch64__)
920     // We need to check crypto separately since we need all of the crypto
921     // extensions to enable the subtarget feature
922     if (CPUFeatures[I] == "aes")
923       crypto |= CAP_AES;
924     else if (CPUFeatures[I] == "pmull")
925       crypto |= CAP_PMULL;
926     else if (CPUFeatures[I] == "sha1")
927       crypto |= CAP_SHA1;
928     else if (CPUFeatures[I] == "sha2")
929       crypto |= CAP_SHA2;
930 #endif
931 
932     if (LLVMFeatureStr != "")
933       Features[LLVMFeatureStr] = true;
934   }
935 
936 #if defined(__aarch64__)
937   // If we have all crypto bits we can add the feature
938   if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
939     Features["crypto"] = true;
940 #endif
941 
942   return true;
943 }
944 #else
945 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
946 #endif
947 
948 std::string sys::getProcessTriple() {
949   Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
950 
951   if (sizeof(void *) == 8 && PT.isArch32Bit())
952     PT = PT.get64BitArchVariant();
953   if (sizeof(void *) == 4 && PT.isArch64Bit())
954     PT = PT.get32BitArchVariant();
955 
956   return PT.str();
957 }
958