1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/Support/TargetParser.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef _WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (!defined(__x86_64__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 68 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 69 // and so we must use an operating-system interface to determine the current 70 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 71 const char *generic = "generic"; 72 73 // The cpu line is second (after the 'processor: 0' line), so if this 74 // buffer is too small then something has changed (or is wrong). 75 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 76 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 77 78 StringRef::const_iterator CIP = CPUInfoStart; 79 80 StringRef::const_iterator CPUStart = 0; 81 size_t CPULen = 0; 82 83 // We need to find the first line which starts with cpu, spaces, and a colon. 84 // After the colon, there may be some additional spaces and then the cpu type. 85 while (CIP < CPUInfoEnd && CPUStart == 0) { 86 if (CIP < CPUInfoEnd && *CIP == '\n') 87 ++CIP; 88 89 if (CIP < CPUInfoEnd && *CIP == 'c') { 90 ++CIP; 91 if (CIP < CPUInfoEnd && *CIP == 'p') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'u') { 94 ++CIP; 95 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 96 ++CIP; 97 98 if (CIP < CPUInfoEnd && *CIP == ':') { 99 ++CIP; 100 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 101 ++CIP; 102 103 if (CIP < CPUInfoEnd) { 104 CPUStart = CIP; 105 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 106 *CIP != ',' && *CIP != '\n')) 107 ++CIP; 108 CPULen = CIP - CPUStart; 109 } 110 } 111 } 112 } 113 } 114 115 if (CPUStart == 0) 116 while (CIP < CPUInfoEnd && *CIP != '\n') 117 ++CIP; 118 } 119 120 if (CPUStart == 0) 121 return generic; 122 123 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 124 .Case("604e", "604e") 125 .Case("604", "604") 126 .Case("7400", "7400") 127 .Case("7410", "7400") 128 .Case("7447", "7400") 129 .Case("7455", "7450") 130 .Case("G4", "g4") 131 .Case("POWER4", "970") 132 .Case("PPC970FX", "970") 133 .Case("PPC970MP", "970") 134 .Case("G5", "g5") 135 .Case("POWER5", "g5") 136 .Case("A2", "a2") 137 .Case("POWER6", "pwr6") 138 .Case("POWER7", "pwr7") 139 .Case("POWER8", "pwr8") 140 .Case("POWER8E", "pwr8") 141 .Case("POWER8NVL", "pwr8") 142 .Case("POWER9", "pwr9") 143 // FIXME: If we get a simulator or machine with the capabilities of 144 // mcpu=future, we should revisit this and add the name reported by the 145 // simulator/machine. 146 .Default(generic); 147 } 148 149 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 150 // The cpuid register on arm is not accessible from user space. On Linux, 151 // it is exposed through the /proc/cpuinfo file. 152 153 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 154 // in all cases. 155 SmallVector<StringRef, 32> Lines; 156 ProcCpuinfoContent.split(Lines, "\n"); 157 158 // Look for the CPU implementer line. 159 StringRef Implementer; 160 StringRef Hardware; 161 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 162 if (Lines[I].startswith("CPU implementer")) 163 Implementer = Lines[I].substr(15).ltrim("\t :"); 164 if (Lines[I].startswith("Hardware")) 165 Hardware = Lines[I].substr(8).ltrim("\t :"); 166 } 167 168 if (Implementer == "0x41") { // ARM Ltd. 169 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 170 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 171 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 172 return "cortex-a53"; 173 174 175 // Look for the CPU part line. 176 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 177 if (Lines[I].startswith("CPU part")) 178 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 179 // values correspond to the "Part number" in the CP15/c0 register. The 180 // contents are specified in the various processor manuals. 181 // This corresponds to the Main ID Register in Technical Reference Manuals. 182 // and is used in programs like sys-utils 183 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 184 .Case("0x926", "arm926ej-s") 185 .Case("0xb02", "mpcore") 186 .Case("0xb36", "arm1136j-s") 187 .Case("0xb56", "arm1156t2-s") 188 .Case("0xb76", "arm1176jz-s") 189 .Case("0xc08", "cortex-a8") 190 .Case("0xc09", "cortex-a9") 191 .Case("0xc0f", "cortex-a15") 192 .Case("0xc20", "cortex-m0") 193 .Case("0xc23", "cortex-m3") 194 .Case("0xc24", "cortex-m4") 195 .Case("0xd22", "cortex-m55") 196 .Case("0xd02", "cortex-a34") 197 .Case("0xd04", "cortex-a35") 198 .Case("0xd03", "cortex-a53") 199 .Case("0xd07", "cortex-a57") 200 .Case("0xd08", "cortex-a72") 201 .Case("0xd09", "cortex-a73") 202 .Case("0xd0a", "cortex-a75") 203 .Case("0xd0b", "cortex-a76") 204 .Default("generic"); 205 } 206 207 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 208 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 209 if (Lines[I].startswith("CPU part")) { 210 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 211 .Case("0x516", "thunderx2t99") 212 .Case("0x0516", "thunderx2t99") 213 .Case("0xaf", "thunderx2t99") 214 .Case("0x0af", "thunderx2t99") 215 .Case("0xa1", "thunderxt88") 216 .Case("0x0a1", "thunderxt88") 217 .Default("generic"); 218 } 219 } 220 } 221 222 if (Implementer == "0x46") { // Fujitsu Ltd. 223 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 224 if (Lines[I].startswith("CPU part")) { 225 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 226 .Case("0x001", "a64fx") 227 .Default("generic"); 228 } 229 } 230 } 231 232 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 233 // Look for the CPU part line. 234 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 235 if (Lines[I].startswith("CPU part")) 236 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 237 // values correspond to the "Part number" in the CP15/c0 register. The 238 // contents are specified in the various processor manuals. 239 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 240 .Case("0xd01", "tsv110") 241 .Default("generic"); 242 243 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 244 // Look for the CPU part line. 245 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 246 if (Lines[I].startswith("CPU part")) 247 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 248 // values correspond to the "Part number" in the CP15/c0 register. The 249 // contents are specified in the various processor manuals. 250 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 251 .Case("0x06f", "krait") // APQ8064 252 .Case("0x201", "kryo") 253 .Case("0x205", "kryo") 254 .Case("0x211", "kryo") 255 .Case("0x800", "cortex-a73") 256 .Case("0x801", "cortex-a73") 257 .Case("0x802", "cortex-a73") 258 .Case("0x803", "cortex-a73") 259 .Case("0x804", "cortex-a73") 260 .Case("0x805", "cortex-a73") 261 .Case("0xc00", "falkor") 262 .Case("0xc01", "saphira") 263 .Default("generic"); 264 265 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 266 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 267 // any predictive pattern across variants and parts. 268 unsigned Variant = 0, Part = 0; 269 270 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 271 // number, corresponding to the Variant bits in the CP15/C0 register. 272 for (auto I : Lines) 273 if (I.consume_front("CPU variant")) 274 I.ltrim("\t :").getAsInteger(0, Variant); 275 276 // Look for the CPU part line, whose value is a 3 digit hexadecimal 277 // number, corresponding to the PartNum bits in the CP15/C0 register. 278 for (auto I : Lines) 279 if (I.consume_front("CPU part")) 280 I.ltrim("\t :").getAsInteger(0, Part); 281 282 unsigned Exynos = (Variant << 12) | Part; 283 switch (Exynos) { 284 default: 285 // Default by falling through to Exynos M3. 286 LLVM_FALLTHROUGH; 287 case 0x1002: 288 return "exynos-m3"; 289 case 0x1003: 290 return "exynos-m4"; 291 } 292 } 293 294 return "generic"; 295 } 296 297 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 298 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 299 300 // The "processor 0:" line comes after a fair amount of other information, 301 // including a cache breakdown, but this should be plenty. 302 SmallVector<StringRef, 32> Lines; 303 ProcCpuinfoContent.split(Lines, "\n"); 304 305 // Look for the CPU features. 306 SmallVector<StringRef, 32> CPUFeatures; 307 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 308 if (Lines[I].startswith("features")) { 309 size_t Pos = Lines[I].find(":"); 310 if (Pos != StringRef::npos) { 311 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 312 break; 313 } 314 } 315 316 // We need to check for the presence of vector support independently of 317 // the machine type, since we may only use the vector register set when 318 // supported by the kernel (and hypervisor). 319 bool HaveVectorSupport = false; 320 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 321 if (CPUFeatures[I] == "vx") 322 HaveVectorSupport = true; 323 } 324 325 // Now check the processor machine type. 326 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 327 if (Lines[I].startswith("processor ")) { 328 size_t Pos = Lines[I].find("machine = "); 329 if (Pos != StringRef::npos) { 330 Pos += sizeof("machine = ") - 1; 331 unsigned int Id; 332 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 333 if (Id >= 8561 && HaveVectorSupport) 334 return "z15"; 335 if (Id >= 3906 && HaveVectorSupport) 336 return "z14"; 337 if (Id >= 2964 && HaveVectorSupport) 338 return "z13"; 339 if (Id >= 2827) 340 return "zEC12"; 341 if (Id >= 2817) 342 return "z196"; 343 } 344 } 345 break; 346 } 347 } 348 349 return "generic"; 350 } 351 352 StringRef sys::detail::getHostCPUNameForBPF() { 353 #if !defined(__linux__) || !defined(__x86_64__) 354 return "generic"; 355 #else 356 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 357 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 358 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 359 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 360 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 361 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 362 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 363 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 364 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 365 /* BPF_EXIT_INSN() */ 366 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 367 368 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 369 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 370 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 371 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 372 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 373 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 374 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 375 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 376 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 377 /* BPF_EXIT_INSN() */ 378 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 379 380 struct bpf_prog_load_attr { 381 uint32_t prog_type; 382 uint32_t insn_cnt; 383 uint64_t insns; 384 uint64_t license; 385 uint32_t log_level; 386 uint32_t log_size; 387 uint64_t log_buf; 388 uint32_t kern_version; 389 uint32_t prog_flags; 390 } attr = {}; 391 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 392 attr.insn_cnt = 5; 393 attr.insns = (uint64_t)v3_insns; 394 attr.license = (uint64_t)"DUMMY"; 395 396 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 397 sizeof(attr)); 398 if (fd >= 0) { 399 close(fd); 400 return "v3"; 401 } 402 403 /* Clear the whole attr in case its content changed by syscall. */ 404 memset(&attr, 0, sizeof(attr)); 405 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 406 attr.insn_cnt = 5; 407 attr.insns = (uint64_t)v2_insns; 408 attr.license = (uint64_t)"DUMMY"; 409 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 410 if (fd >= 0) { 411 close(fd); 412 return "v2"; 413 } 414 return "v1"; 415 #endif 416 } 417 418 #if defined(__i386__) || defined(_M_IX86) || \ 419 defined(__x86_64__) || defined(_M_X64) 420 421 enum VendorSignatures { 422 SIG_INTEL = 0x756e6547 /* Genu */, 423 SIG_AMD = 0x68747541 /* Auth */ 424 }; 425 426 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 427 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 428 // support. Consequently, for i386, the presence of CPUID is checked first 429 // via the corresponding eflags bit. 430 // Removal of cpuid.h header motivated by PR30384 431 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 432 // or test-suite, but are used in external projects e.g. libstdcxx 433 static bool isCpuIdSupported() { 434 #if defined(__GNUC__) || defined(__clang__) 435 #if defined(__i386__) 436 int __cpuid_supported; 437 __asm__(" pushfl\n" 438 " popl %%eax\n" 439 " movl %%eax,%%ecx\n" 440 " xorl $0x00200000,%%eax\n" 441 " pushl %%eax\n" 442 " popfl\n" 443 " pushfl\n" 444 " popl %%eax\n" 445 " movl $0,%0\n" 446 " cmpl %%eax,%%ecx\n" 447 " je 1f\n" 448 " movl $1,%0\n" 449 "1:" 450 : "=r"(__cpuid_supported) 451 : 452 : "eax", "ecx"); 453 if (!__cpuid_supported) 454 return false; 455 #endif 456 return true; 457 #endif 458 return true; 459 } 460 461 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 462 /// the specified arguments. If we can't run cpuid on the host, return true. 463 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 464 unsigned *rECX, unsigned *rEDX) { 465 #if defined(__GNUC__) || defined(__clang__) 466 #if defined(__x86_64__) 467 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 468 // FIXME: should we save this for Clang? 469 __asm__("movq\t%%rbx, %%rsi\n\t" 470 "cpuid\n\t" 471 "xchgq\t%%rbx, %%rsi\n\t" 472 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 473 : "a"(value)); 474 return false; 475 #elif defined(__i386__) 476 __asm__("movl\t%%ebx, %%esi\n\t" 477 "cpuid\n\t" 478 "xchgl\t%%ebx, %%esi\n\t" 479 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 480 : "a"(value)); 481 return false; 482 #else 483 return true; 484 #endif 485 #elif defined(_MSC_VER) 486 // The MSVC intrinsic is portable across x86 and x64. 487 int registers[4]; 488 __cpuid(registers, value); 489 *rEAX = registers[0]; 490 *rEBX = registers[1]; 491 *rECX = registers[2]; 492 *rEDX = registers[3]; 493 return false; 494 #else 495 return true; 496 #endif 497 } 498 499 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 500 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 501 /// return true. 502 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 503 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 504 unsigned *rEDX) { 505 #if defined(__GNUC__) || defined(__clang__) 506 #if defined(__x86_64__) 507 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 508 // FIXME: should we save this for Clang? 509 __asm__("movq\t%%rbx, %%rsi\n\t" 510 "cpuid\n\t" 511 "xchgq\t%%rbx, %%rsi\n\t" 512 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 513 : "a"(value), "c"(subleaf)); 514 return false; 515 #elif defined(__i386__) 516 __asm__("movl\t%%ebx, %%esi\n\t" 517 "cpuid\n\t" 518 "xchgl\t%%ebx, %%esi\n\t" 519 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 520 : "a"(value), "c"(subleaf)); 521 return false; 522 #else 523 return true; 524 #endif 525 #elif defined(_MSC_VER) 526 int registers[4]; 527 __cpuidex(registers, value, subleaf); 528 *rEAX = registers[0]; 529 *rEBX = registers[1]; 530 *rECX = registers[2]; 531 *rEDX = registers[3]; 532 return false; 533 #else 534 return true; 535 #endif 536 } 537 538 // Read control register 0 (XCR0). Used to detect features such as AVX. 539 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 540 #if defined(__GNUC__) || defined(__clang__) 541 // Check xgetbv; this uses a .byte sequence instead of the instruction 542 // directly because older assemblers do not include support for xgetbv and 543 // there is no easy way to conditionally compile based on the assembler used. 544 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 545 return false; 546 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 547 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 548 *rEAX = Result; 549 *rEDX = Result >> 32; 550 return false; 551 #else 552 return true; 553 #endif 554 } 555 556 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 557 unsigned *Model) { 558 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 559 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 560 if (*Family == 6 || *Family == 0xf) { 561 if (*Family == 0xf) 562 // Examine extended family ID if family ID is F. 563 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 564 // Examine extended model ID if family ID is 6 or F. 565 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 566 } 567 } 568 569 static void 570 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 571 unsigned Brand_id, unsigned Features, 572 unsigned Features2, unsigned Features3, 573 unsigned *Type, unsigned *Subtype) { 574 if (Brand_id != 0) 575 return; 576 switch (Family) { 577 case 3: 578 *Type = X86::INTEL_i386; 579 break; 580 case 4: 581 *Type = X86::INTEL_i486; 582 break; 583 case 5: 584 if (Features & (1 << X86::FEATURE_MMX)) { 585 *Type = X86::INTEL_PENTIUM_MMX; 586 break; 587 } 588 *Type = X86::INTEL_PENTIUM; 589 break; 590 case 6: 591 switch (Model) { 592 case 0x01: // Pentium Pro processor 593 *Type = X86::INTEL_PENTIUM_PRO; 594 break; 595 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 596 // model 03 597 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 598 // model 05, and Intel Celeron processor, model 05 599 case 0x06: // Celeron processor, model 06 600 *Type = X86::INTEL_PENTIUM_II; 601 break; 602 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 603 // processor, model 07 604 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 605 // model 08, and Celeron processor, model 08 606 case 0x0a: // Pentium III Xeon processor, model 0Ah 607 case 0x0b: // Pentium III processor, model 0Bh 608 *Type = X86::INTEL_PENTIUM_III; 609 break; 610 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 611 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 612 // 0Dh. All processors are manufactured using the 90 nm process. 613 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 614 // Integrated Processor with Intel QuickAssist Technology 615 *Type = X86::INTEL_PENTIUM_M; 616 break; 617 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 618 // 0Eh. All processors are manufactured using the 65 nm process. 619 *Type = X86::INTEL_CORE_DUO; 620 break; // yonah 621 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 622 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 623 // mobile processor, Intel Core 2 Extreme processor, Intel 624 // Pentium Dual-Core processor, Intel Xeon processor, model 625 // 0Fh. All processors are manufactured using the 65 nm process. 626 case 0x16: // Intel Celeron processor model 16h. All processors are 627 // manufactured using the 65 nm process 628 *Type = X86::INTEL_CORE2; // "core2" 629 *Subtype = X86::INTEL_CORE2_65; 630 break; 631 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 632 // 17h. All processors are manufactured using the 45 nm process. 633 // 634 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 635 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 636 // the 45 nm process. 637 *Type = X86::INTEL_CORE2; // "penryn" 638 *Subtype = X86::INTEL_CORE2_45; 639 break; 640 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 641 // processors are manufactured using the 45 nm process. 642 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 643 // As found in a Summer 2010 model iMac. 644 case 0x1f: 645 case 0x2e: // Nehalem EX 646 *Type = X86::INTEL_COREI7; // "nehalem" 647 *Subtype = X86::INTEL_COREI7_NEHALEM; 648 break; 649 case 0x25: // Intel Core i7, laptop version. 650 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 651 // processors are manufactured using the 32 nm process. 652 case 0x2f: // Westmere EX 653 *Type = X86::INTEL_COREI7; // "westmere" 654 *Subtype = X86::INTEL_COREI7_WESTMERE; 655 break; 656 case 0x2a: // Intel Core i7 processor. All processors are manufactured 657 // using the 32 nm process. 658 case 0x2d: 659 *Type = X86::INTEL_COREI7; //"sandybridge" 660 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 661 break; 662 case 0x3a: 663 case 0x3e: // Ivy Bridge EP 664 *Type = X86::INTEL_COREI7; // "ivybridge" 665 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 666 break; 667 668 // Haswell: 669 case 0x3c: 670 case 0x3f: 671 case 0x45: 672 case 0x46: 673 *Type = X86::INTEL_COREI7; // "haswell" 674 *Subtype = X86::INTEL_COREI7_HASWELL; 675 break; 676 677 // Broadwell: 678 case 0x3d: 679 case 0x47: 680 case 0x4f: 681 case 0x56: 682 *Type = X86::INTEL_COREI7; // "broadwell" 683 *Subtype = X86::INTEL_COREI7_BROADWELL; 684 break; 685 686 // Skylake: 687 case 0x4e: // Skylake mobile 688 case 0x5e: // Skylake desktop 689 case 0x8e: // Kaby Lake mobile 690 case 0x9e: // Kaby Lake desktop 691 *Type = X86::INTEL_COREI7; // "skylake" 692 *Subtype = X86::INTEL_COREI7_SKYLAKE; 693 break; 694 695 // Skylake Xeon: 696 case 0x55: 697 *Type = X86::INTEL_COREI7; 698 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) 699 *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" 700 else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) 701 *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" 702 else 703 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 704 break; 705 706 // Cannonlake: 707 case 0x66: 708 *Type = X86::INTEL_COREI7; 709 *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" 710 break; 711 712 // Icelake: 713 case 0x7d: 714 case 0x7e: 715 *Type = X86::INTEL_COREI7; 716 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" 717 break; 718 719 // Icelake Xeon: 720 case 0x6a: 721 case 0x6c: 722 *Type = X86::INTEL_COREI7; 723 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" 724 break; 725 726 case 0x1c: // Most 45 nm Intel Atom processors 727 case 0x26: // 45 nm Atom Lincroft 728 case 0x27: // 32 nm Atom Medfield 729 case 0x35: // 32 nm Atom Midview 730 case 0x36: // 32 nm Atom Midview 731 *Type = X86::INTEL_BONNELL; 732 break; // "bonnell" 733 734 // Atom Silvermont codes from the Intel software optimization guide. 735 case 0x37: 736 case 0x4a: 737 case 0x4d: 738 case 0x5a: 739 case 0x5d: 740 case 0x4c: // really airmont 741 *Type = X86::INTEL_SILVERMONT; 742 break; // "silvermont" 743 // Goldmont: 744 case 0x5c: // Apollo Lake 745 case 0x5f: // Denverton 746 *Type = X86::INTEL_GOLDMONT; 747 break; // "goldmont" 748 case 0x7a: 749 *Type = X86::INTEL_GOLDMONT_PLUS; 750 break; 751 case 0x86: 752 *Type = X86::INTEL_TREMONT; 753 break; 754 755 case 0x57: 756 *Type = X86::INTEL_KNL; // knl 757 break; 758 759 case 0x85: 760 *Type = X86::INTEL_KNM; // knm 761 break; 762 763 default: // Unknown family 6 CPU, try to guess. 764 // TODO detect tigerlake host 765 if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { 766 *Type = X86::INTEL_COREI7; 767 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 768 break; 769 } 770 771 if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { 772 *Type = X86::INTEL_COREI7; 773 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 774 break; 775 } 776 777 if (Features & (1 << X86::FEATURE_AVX512VBMI)) { 778 *Type = X86::INTEL_COREI7; 779 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 780 break; 781 } 782 783 if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) { 784 *Type = X86::INTEL_COREI7; 785 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 786 break; 787 } 788 789 if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { 790 *Type = X86::INTEL_COREI7; 791 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 792 break; 793 } 794 795 if (Features & (1 << X86::FEATURE_AVX512VL)) { 796 *Type = X86::INTEL_COREI7; 797 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 798 break; 799 } 800 801 if (Features & (1 << X86::FEATURE_AVX512ER)) { 802 *Type = X86::INTEL_KNL; // knl 803 break; 804 } 805 806 if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { 807 if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { 808 *Type = X86::INTEL_GOLDMONT; 809 } else { 810 *Type = X86::INTEL_COREI7; 811 *Subtype = X86::INTEL_COREI7_SKYLAKE; 812 } 813 break; 814 } 815 if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { 816 *Type = X86::INTEL_COREI7; 817 *Subtype = X86::INTEL_COREI7_BROADWELL; 818 break; 819 } 820 if (Features & (1 << X86::FEATURE_AVX2)) { 821 *Type = X86::INTEL_COREI7; 822 *Subtype = X86::INTEL_COREI7_HASWELL; 823 break; 824 } 825 if (Features & (1 << X86::FEATURE_AVX)) { 826 *Type = X86::INTEL_COREI7; 827 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 828 break; 829 } 830 if (Features & (1 << X86::FEATURE_SSE4_2)) { 831 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 832 *Type = X86::INTEL_SILVERMONT; 833 } else { 834 *Type = X86::INTEL_COREI7; 835 *Subtype = X86::INTEL_COREI7_NEHALEM; 836 } 837 break; 838 } 839 if (Features & (1 << X86::FEATURE_SSE4_1)) { 840 *Type = X86::INTEL_CORE2; // "penryn" 841 *Subtype = X86::INTEL_CORE2_45; 842 break; 843 } 844 if (Features & (1 << X86::FEATURE_SSSE3)) { 845 if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { 846 *Type = X86::INTEL_BONNELL; // "bonnell" 847 } else { 848 *Type = X86::INTEL_CORE2; // "core2" 849 *Subtype = X86::INTEL_CORE2_65; 850 } 851 break; 852 } 853 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 854 *Type = X86::INTEL_CORE2; // "core2" 855 *Subtype = X86::INTEL_CORE2_65; 856 break; 857 } 858 if (Features & (1 << X86::FEATURE_SSE3)) { 859 *Type = X86::INTEL_CORE_DUO; 860 break; 861 } 862 if (Features & (1 << X86::FEATURE_SSE2)) { 863 *Type = X86::INTEL_PENTIUM_M; 864 break; 865 } 866 if (Features & (1 << X86::FEATURE_SSE)) { 867 *Type = X86::INTEL_PENTIUM_III; 868 break; 869 } 870 if (Features & (1 << X86::FEATURE_MMX)) { 871 *Type = X86::INTEL_PENTIUM_II; 872 break; 873 } 874 *Type = X86::INTEL_PENTIUM_PRO; 875 break; 876 } 877 break; 878 case 15: { 879 if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { 880 *Type = X86::INTEL_NOCONA; 881 break; 882 } 883 if (Features & (1 << X86::FEATURE_SSE3)) { 884 *Type = X86::INTEL_PRESCOTT; 885 break; 886 } 887 *Type = X86::INTEL_PENTIUM_IV; 888 break; 889 } 890 default: 891 break; /*"generic"*/ 892 } 893 } 894 895 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 896 unsigned Features, unsigned *Type, 897 unsigned *Subtype) { 898 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 899 // appears to be no way to generate the wide variety of AMD-specific targets 900 // from the information returned from CPUID. 901 switch (Family) { 902 case 4: 903 *Type = X86::AMD_i486; 904 break; 905 case 5: 906 *Type = X86::AMDPENTIUM; 907 switch (Model) { 908 case 6: 909 case 7: 910 *Subtype = X86::AMDPENTIUM_K6; 911 break; // "k6" 912 case 8: 913 *Subtype = X86::AMDPENTIUM_K62; 914 break; // "k6-2" 915 case 9: 916 case 13: 917 *Subtype = X86::AMDPENTIUM_K63; 918 break; // "k6-3" 919 case 10: 920 *Subtype = X86::AMDPENTIUM_GEODE; 921 break; // "geode" 922 } 923 break; 924 case 6: 925 if (Features & (1 << X86::FEATURE_SSE)) { 926 *Type = X86::AMD_ATHLON_XP; 927 break; // "athlon-xp" 928 } 929 *Type = X86::AMD_ATHLON; 930 break; // "athlon" 931 case 15: 932 if (Features & (1 << X86::FEATURE_SSE3)) { 933 *Type = X86::AMD_K8SSE3; 934 break; // "k8-sse3" 935 } 936 *Type = X86::AMD_K8; 937 break; // "k8" 938 case 16: 939 *Type = X86::AMDFAM10H; // "amdfam10" 940 switch (Model) { 941 case 2: 942 *Subtype = X86::AMDFAM10H_BARCELONA; 943 break; 944 case 4: 945 *Subtype = X86::AMDFAM10H_SHANGHAI; 946 break; 947 case 8: 948 *Subtype = X86::AMDFAM10H_ISTANBUL; 949 break; 950 } 951 break; 952 case 20: 953 *Type = X86::AMD_BTVER1; 954 break; // "btver1"; 955 case 21: 956 *Type = X86::AMDFAM15H; 957 if (Model >= 0x60 && Model <= 0x7f) { 958 *Subtype = X86::AMDFAM15H_BDVER4; 959 break; // "bdver4"; 60h-7Fh: Excavator 960 } 961 if (Model >= 0x30 && Model <= 0x3f) { 962 *Subtype = X86::AMDFAM15H_BDVER3; 963 break; // "bdver3"; 30h-3Fh: Steamroller 964 } 965 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 966 *Subtype = X86::AMDFAM15H_BDVER2; 967 break; // "bdver2"; 02h, 10h-1Fh: Piledriver 968 } 969 if (Model <= 0x0f) { 970 *Subtype = X86::AMDFAM15H_BDVER1; 971 break; // "bdver1"; 00h-0Fh: Bulldozer 972 } 973 break; 974 case 22: 975 *Type = X86::AMD_BTVER2; 976 break; // "btver2" 977 case 23: 978 *Type = X86::AMDFAM17H; 979 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 980 *Subtype = X86::AMDFAM17H_ZNVER2; 981 break; // "znver2"; 30h-3fh, 71h: Zen2 982 } 983 if (Model <= 0x0f) { 984 *Subtype = X86::AMDFAM17H_ZNVER1; 985 break; // "znver1"; 00h-0Fh: Zen1 986 } 987 break; 988 default: 989 break; // "generic" 990 } 991 } 992 993 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 994 unsigned *FeaturesOut, unsigned *Features2Out, 995 unsigned *Features3Out) { 996 unsigned Features = 0; 997 unsigned Features2 = 0; 998 unsigned Features3 = 0; 999 unsigned EAX, EBX; 1000 1001 auto setFeature = [&](unsigned F) { 1002 if (F < 32) 1003 Features |= 1U << (F & 0x1f); 1004 else if (F < 64) 1005 Features2 |= 1U << ((F - 32) & 0x1f); 1006 else if (F < 96) 1007 Features3 |= 1U << ((F - 64) & 0x1f); 1008 else 1009 llvm_unreachable("Unexpected FeatureBit"); 1010 }; 1011 1012 if ((EDX >> 15) & 1) 1013 setFeature(X86::FEATURE_CMOV); 1014 if ((EDX >> 23) & 1) 1015 setFeature(X86::FEATURE_MMX); 1016 if ((EDX >> 25) & 1) 1017 setFeature(X86::FEATURE_SSE); 1018 if ((EDX >> 26) & 1) 1019 setFeature(X86::FEATURE_SSE2); 1020 1021 if ((ECX >> 0) & 1) 1022 setFeature(X86::FEATURE_SSE3); 1023 if ((ECX >> 1) & 1) 1024 setFeature(X86::FEATURE_PCLMUL); 1025 if ((ECX >> 9) & 1) 1026 setFeature(X86::FEATURE_SSSE3); 1027 if ((ECX >> 12) & 1) 1028 setFeature(X86::FEATURE_FMA); 1029 if ((ECX >> 19) & 1) 1030 setFeature(X86::FEATURE_SSE4_1); 1031 if ((ECX >> 20) & 1) 1032 setFeature(X86::FEATURE_SSE4_2); 1033 if ((ECX >> 23) & 1) 1034 setFeature(X86::FEATURE_POPCNT); 1035 if ((ECX >> 25) & 1) 1036 setFeature(X86::FEATURE_AES); 1037 1038 if ((ECX >> 22) & 1) 1039 setFeature(X86::FEATURE_MOVBE); 1040 1041 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1042 // indicates that the AVX registers will be saved and restored on context 1043 // switch, then we have full AVX support. 1044 const unsigned AVXBits = (1 << 27) | (1 << 28); 1045 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1046 ((EAX & 0x6) == 0x6); 1047 #if defined(__APPLE__) 1048 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1049 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1050 // set right now. 1051 bool HasAVX512Save = true; 1052 #else 1053 // AVX512 requires additional context to be saved by the OS. 1054 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1055 #endif 1056 1057 if (HasAVX) 1058 setFeature(X86::FEATURE_AVX); 1059 1060 bool HasLeaf7 = 1061 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1062 1063 if (HasLeaf7 && ((EBX >> 3) & 1)) 1064 setFeature(X86::FEATURE_BMI); 1065 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1066 setFeature(X86::FEATURE_AVX2); 1067 if (HasLeaf7 && ((EBX >> 8) & 1)) 1068 setFeature(X86::FEATURE_BMI2); 1069 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1070 setFeature(X86::FEATURE_AVX512F); 1071 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1072 setFeature(X86::FEATURE_AVX512DQ); 1073 if (HasLeaf7 && ((EBX >> 19) & 1)) 1074 setFeature(X86::FEATURE_ADX); 1075 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1076 setFeature(X86::FEATURE_AVX512IFMA); 1077 if (HasLeaf7 && ((EBX >> 23) & 1)) 1078 setFeature(X86::FEATURE_CLFLUSHOPT); 1079 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1080 setFeature(X86::FEATURE_AVX512PF); 1081 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1082 setFeature(X86::FEATURE_AVX512ER); 1083 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1084 setFeature(X86::FEATURE_AVX512CD); 1085 if (HasLeaf7 && ((EBX >> 29) & 1)) 1086 setFeature(X86::FEATURE_SHA); 1087 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1088 setFeature(X86::FEATURE_AVX512BW); 1089 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1090 setFeature(X86::FEATURE_AVX512VL); 1091 1092 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1093 setFeature(X86::FEATURE_AVX512VBMI); 1094 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1095 setFeature(X86::FEATURE_AVX512VBMI2); 1096 if (HasLeaf7 && ((ECX >> 8) & 1)) 1097 setFeature(X86::FEATURE_GFNI); 1098 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1099 setFeature(X86::FEATURE_VPCLMULQDQ); 1100 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1101 setFeature(X86::FEATURE_AVX512VNNI); 1102 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1103 setFeature(X86::FEATURE_AVX512BITALG); 1104 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1105 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1106 1107 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1108 setFeature(X86::FEATURE_AVX5124VNNIW); 1109 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1110 setFeature(X86::FEATURE_AVX5124FMAPS); 1111 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1112 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1113 1114 bool HasLeaf7Subleaf1 = 1115 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1116 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1117 setFeature(X86::FEATURE_AVX512BF16); 1118 1119 unsigned MaxExtLevel; 1120 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1121 1122 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1123 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1124 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1125 setFeature(X86::FEATURE_SSE4_A); 1126 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1127 setFeature(X86::FEATURE_XOP); 1128 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1129 setFeature(X86::FEATURE_FMA4); 1130 1131 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1132 setFeature(X86::FEATURE_EM64T); 1133 1134 *FeaturesOut = Features; 1135 *Features2Out = Features2; 1136 *Features3Out = Features3; 1137 } 1138 1139 StringRef sys::getHostCPUName() { 1140 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1141 unsigned MaxLeaf, Vendor; 1142 1143 #if defined(__GNUC__) || defined(__clang__) 1144 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1145 // and simplify it to not invoke __cpuid (like cpu_model.c in 1146 // compiler-rt/lib/builtins/cpu_model.c? 1147 // Opting for the second option. 1148 if(!isCpuIdSupported()) 1149 return "generic"; 1150 #endif 1151 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1152 return "generic"; 1153 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1154 1155 unsigned Brand_id = EBX & 0xff; 1156 unsigned Family = 0, Model = 0; 1157 unsigned Features = 0, Features2 = 0, Features3 = 0; 1158 detectX86FamilyModel(EAX, &Family, &Model); 1159 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); 1160 1161 unsigned Type = 0; 1162 unsigned Subtype = 0; 1163 1164 if (Vendor == SIG_INTEL) { 1165 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1166 Features2, Features3, &Type, &Subtype); 1167 } else if (Vendor == SIG_AMD) { 1168 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1169 } 1170 1171 // Check subtypes first since those are more specific. 1172 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ 1173 if (Subtype == X86::ENUM) \ 1174 return ARCHNAME; 1175 #include "llvm/Support/X86TargetParser.def" 1176 1177 // Now check types. 1178 #define X86_CPU_TYPE(ARCHNAME, ENUM) \ 1179 if (Type == X86::ENUM) \ 1180 return ARCHNAME; 1181 #include "llvm/Support/X86TargetParser.def" 1182 1183 return "generic"; 1184 } 1185 1186 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1187 StringRef sys::getHostCPUName() { 1188 host_basic_info_data_t hostInfo; 1189 mach_msg_type_number_t infoCount; 1190 1191 infoCount = HOST_BASIC_INFO_COUNT; 1192 mach_port_t hostPort = mach_host_self(); 1193 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1194 &infoCount); 1195 mach_port_deallocate(mach_task_self(), hostPort); 1196 1197 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1198 return "generic"; 1199 1200 switch (hostInfo.cpu_subtype) { 1201 case CPU_SUBTYPE_POWERPC_601: 1202 return "601"; 1203 case CPU_SUBTYPE_POWERPC_602: 1204 return "602"; 1205 case CPU_SUBTYPE_POWERPC_603: 1206 return "603"; 1207 case CPU_SUBTYPE_POWERPC_603e: 1208 return "603e"; 1209 case CPU_SUBTYPE_POWERPC_603ev: 1210 return "603ev"; 1211 case CPU_SUBTYPE_POWERPC_604: 1212 return "604"; 1213 case CPU_SUBTYPE_POWERPC_604e: 1214 return "604e"; 1215 case CPU_SUBTYPE_POWERPC_620: 1216 return "620"; 1217 case CPU_SUBTYPE_POWERPC_750: 1218 return "750"; 1219 case CPU_SUBTYPE_POWERPC_7400: 1220 return "7400"; 1221 case CPU_SUBTYPE_POWERPC_7450: 1222 return "7450"; 1223 case CPU_SUBTYPE_POWERPC_970: 1224 return "970"; 1225 default:; 1226 } 1227 1228 return "generic"; 1229 } 1230 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1231 StringRef sys::getHostCPUName() { 1232 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1233 StringRef Content = P ? P->getBuffer() : ""; 1234 return detail::getHostCPUNameForPowerPC(Content); 1235 } 1236 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1237 StringRef sys::getHostCPUName() { 1238 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1239 StringRef Content = P ? P->getBuffer() : ""; 1240 return detail::getHostCPUNameForARM(Content); 1241 } 1242 #elif defined(__linux__) && defined(__s390x__) 1243 StringRef sys::getHostCPUName() { 1244 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1245 StringRef Content = P ? P->getBuffer() : ""; 1246 return detail::getHostCPUNameForS390x(Content); 1247 } 1248 #elif defined(__APPLE__) && defined(__aarch64__) 1249 StringRef sys::getHostCPUName() { 1250 return "cyclone"; 1251 } 1252 #elif defined(__APPLE__) && defined(__arm__) 1253 StringRef sys::getHostCPUName() { 1254 host_basic_info_data_t hostInfo; 1255 mach_msg_type_number_t infoCount; 1256 1257 infoCount = HOST_BASIC_INFO_COUNT; 1258 mach_port_t hostPort = mach_host_self(); 1259 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1260 &infoCount); 1261 mach_port_deallocate(mach_task_self(), hostPort); 1262 1263 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1264 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1265 return "generic"; 1266 } 1267 switch (hostInfo.cpu_subtype) { 1268 case CPU_SUBTYPE_ARM_V7S: 1269 return "swift"; 1270 default:; 1271 } 1272 1273 return "generic"; 1274 } 1275 #else 1276 StringRef sys::getHostCPUName() { return "generic"; } 1277 #endif 1278 1279 #if defined(__linux__) && defined(__x86_64__) 1280 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1281 // using the number of unique physical/core id pairs. The following 1282 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1283 int computeHostNumPhysicalCores() { 1284 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1285 // mmapped because it appears to have 0 size. 1286 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1287 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1288 if (std::error_code EC = Text.getError()) { 1289 llvm::errs() << "Can't read " 1290 << "/proc/cpuinfo: " << EC.message() << "\n"; 1291 return -1; 1292 } 1293 SmallVector<StringRef, 8> strs; 1294 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1295 /*KeepEmpty=*/false); 1296 int CurPhysicalId = -1; 1297 int CurCoreId = -1; 1298 SmallSet<std::pair<int, int>, 32> UniqueItems; 1299 for (auto &Line : strs) { 1300 Line = Line.trim(); 1301 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1302 continue; 1303 std::pair<StringRef, StringRef> Data = Line.split(':'); 1304 auto Name = Data.first.trim(); 1305 auto Val = Data.second.trim(); 1306 if (Name == "physical id") { 1307 assert(CurPhysicalId == -1 && 1308 "Expected a core id before seeing another physical id"); 1309 Val.getAsInteger(10, CurPhysicalId); 1310 } 1311 if (Name == "core id") { 1312 assert(CurCoreId == -1 && 1313 "Expected a physical id before seeing another core id"); 1314 Val.getAsInteger(10, CurCoreId); 1315 } 1316 if (CurPhysicalId != -1 && CurCoreId != -1) { 1317 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1318 CurPhysicalId = -1; 1319 CurCoreId = -1; 1320 } 1321 } 1322 return UniqueItems.size(); 1323 } 1324 #elif defined(__APPLE__) && defined(__x86_64__) 1325 #include <sys/param.h> 1326 #include <sys/sysctl.h> 1327 1328 // Gets the number of *physical cores* on the machine. 1329 int computeHostNumPhysicalCores() { 1330 uint32_t count; 1331 size_t len = sizeof(count); 1332 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1333 if (count < 1) { 1334 int nm[2]; 1335 nm[0] = CTL_HW; 1336 nm[1] = HW_AVAILCPU; 1337 sysctl(nm, 2, &count, &len, NULL, 0); 1338 if (count < 1) 1339 return -1; 1340 } 1341 return count; 1342 } 1343 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1344 // Defined in llvm/lib/Support/Windows/Threading.inc 1345 int computeHostNumPhysicalCores(); 1346 #else 1347 // On other systems, return -1 to indicate unknown. 1348 static int computeHostNumPhysicalCores() { return -1; } 1349 #endif 1350 1351 int sys::getHostNumPhysicalCores() { 1352 static int NumCores = computeHostNumPhysicalCores(); 1353 return NumCores; 1354 } 1355 1356 #if defined(__i386__) || defined(_M_IX86) || \ 1357 defined(__x86_64__) || defined(_M_X64) 1358 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1359 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1360 unsigned MaxLevel; 1361 union { 1362 unsigned u[3]; 1363 char c[12]; 1364 } text; 1365 1366 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1367 MaxLevel < 1) 1368 return false; 1369 1370 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1371 1372 Features["cx8"] = (EDX >> 8) & 1; 1373 Features["cmov"] = (EDX >> 15) & 1; 1374 Features["mmx"] = (EDX >> 23) & 1; 1375 Features["fxsr"] = (EDX >> 24) & 1; 1376 Features["sse"] = (EDX >> 25) & 1; 1377 Features["sse2"] = (EDX >> 26) & 1; 1378 1379 Features["sse3"] = (ECX >> 0) & 1; 1380 Features["pclmul"] = (ECX >> 1) & 1; 1381 Features["ssse3"] = (ECX >> 9) & 1; 1382 Features["cx16"] = (ECX >> 13) & 1; 1383 Features["sse4.1"] = (ECX >> 19) & 1; 1384 Features["sse4.2"] = (ECX >> 20) & 1; 1385 Features["movbe"] = (ECX >> 22) & 1; 1386 Features["popcnt"] = (ECX >> 23) & 1; 1387 Features["aes"] = (ECX >> 25) & 1; 1388 Features["rdrnd"] = (ECX >> 30) & 1; 1389 1390 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1391 // indicates that the AVX registers will be saved and restored on context 1392 // switch, then we have full AVX support. 1393 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1394 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1395 #if defined(__APPLE__) 1396 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1397 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1398 // set right now. 1399 bool HasAVX512Save = true; 1400 #else 1401 // AVX512 requires additional context to be saved by the OS. 1402 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1403 #endif 1404 1405 Features["avx"] = HasAVXSave; 1406 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1407 // Only enable XSAVE if OS has enabled support for saving YMM state. 1408 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1409 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1410 1411 unsigned MaxExtLevel; 1412 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1413 1414 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1415 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1416 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1417 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1418 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1419 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1420 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1421 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1422 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1423 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1424 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1425 1426 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1427 1428 // Miscellaneous memory related features, detected by 1429 // using the 0x80000008 leaf of the CPUID instruction 1430 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1431 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1432 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1433 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1434 1435 bool HasLeaf7 = 1436 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1437 1438 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1439 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1440 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1441 // AVX2 is only supported if we have the OS save support from AVX. 1442 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1443 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1444 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1445 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1446 // AVX512 is only supported if the OS supports the context save for it. 1447 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1448 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1449 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1450 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1451 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1452 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1453 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1454 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1455 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1456 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1457 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1458 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1459 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1460 1461 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1462 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1463 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1464 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1465 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1466 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1467 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1468 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1469 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1470 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1471 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1472 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1473 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1474 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1475 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1476 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1477 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1478 1479 // There are two CPUID leafs which information associated with the pconfig 1480 // instruction: 1481 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1482 // bit of EDX), while the EAX=0x1b leaf returns information on the 1483 // availability of specific pconfig leafs. 1484 // The target feature here only refers to the the first of these two. 1485 // Users might need to check for the availability of specific pconfig 1486 // leaves using cpuid, since that information is ignored while 1487 // detecting features using the "-march=native" flag. 1488 // For more info, see X86 ISA docs. 1489 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1490 bool HasLeaf7Subleaf1 = 1491 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1492 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1493 1494 bool HasLeafD = MaxLevel >= 0xd && 1495 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1496 1497 // Only enable XSAVE if OS has enabled support for saving YMM state. 1498 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1499 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1500 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1501 1502 bool HasLeaf14 = MaxLevel >= 0x14 && 1503 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1504 1505 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1506 1507 return true; 1508 } 1509 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1510 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1511 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1512 if (!P) 1513 return false; 1514 1515 SmallVector<StringRef, 32> Lines; 1516 P->getBuffer().split(Lines, "\n"); 1517 1518 SmallVector<StringRef, 32> CPUFeatures; 1519 1520 // Look for the CPU features. 1521 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1522 if (Lines[I].startswith("Features")) { 1523 Lines[I].split(CPUFeatures, ' '); 1524 break; 1525 } 1526 1527 #if defined(__aarch64__) 1528 // Keep track of which crypto features we have seen 1529 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1530 uint32_t crypto = 0; 1531 #endif 1532 1533 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1534 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1535 #if defined(__aarch64__) 1536 .Case("asimd", "neon") 1537 .Case("fp", "fp-armv8") 1538 .Case("crc32", "crc") 1539 #else 1540 .Case("half", "fp16") 1541 .Case("neon", "neon") 1542 .Case("vfpv3", "vfp3") 1543 .Case("vfpv3d16", "d16") 1544 .Case("vfpv4", "vfp4") 1545 .Case("idiva", "hwdiv-arm") 1546 .Case("idivt", "hwdiv") 1547 #endif 1548 .Default(""); 1549 1550 #if defined(__aarch64__) 1551 // We need to check crypto separately since we need all of the crypto 1552 // extensions to enable the subtarget feature 1553 if (CPUFeatures[I] == "aes") 1554 crypto |= CAP_AES; 1555 else if (CPUFeatures[I] == "pmull") 1556 crypto |= CAP_PMULL; 1557 else if (CPUFeatures[I] == "sha1") 1558 crypto |= CAP_SHA1; 1559 else if (CPUFeatures[I] == "sha2") 1560 crypto |= CAP_SHA2; 1561 #endif 1562 1563 if (LLVMFeatureStr != "") 1564 Features[LLVMFeatureStr] = true; 1565 } 1566 1567 #if defined(__aarch64__) 1568 // If we have all crypto bits we can add the feature 1569 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1570 Features["crypto"] = true; 1571 #endif 1572 1573 return true; 1574 } 1575 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1576 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1577 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1578 Features["neon"] = true; 1579 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1580 Features["crc"] = true; 1581 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1582 Features["crypto"] = true; 1583 1584 return true; 1585 } 1586 #else 1587 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1588 #endif 1589 1590 std::string sys::getProcessTriple() { 1591 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1592 Triple PT(Triple::normalize(TargetTripleString)); 1593 1594 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1595 PT = PT.get64BitArchVariant(); 1596 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1597 PT = PT.get32BitArchVariant(); 1598 1599 return PT.str(); 1600 } 1601