1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //  This file implements the operating system Host concept.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/config.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/FileSystem.h"
23 #include "llvm/Support/MemoryBuffer.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include <assert.h>
26 #include <string.h>
27 
28 // Include the platform-specific parts of this class.
29 #ifdef LLVM_ON_UNIX
30 #include "Unix/Host.inc"
31 #endif
32 #ifdef LLVM_ON_WIN32
33 #include "Windows/Host.inc"
34 #endif
35 #ifdef _MSC_VER
36 #include <intrin.h>
37 #endif
38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39 #include <mach/host_info.h>
40 #include <mach/mach.h>
41 #include <mach/mach_host.h>
42 #include <mach/machine.h>
43 #endif
44 
45 #define DEBUG_TYPE "host-detection"
46 
47 //===----------------------------------------------------------------------===//
48 //
49 //  Implementations of the CPU detection routines
50 //
51 //===----------------------------------------------------------------------===//
52 
53 using namespace llvm;
54 
55 static std::unique_ptr<llvm::MemoryBuffer>
56     LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
57   llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
58       llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59   if (std::error_code EC = Text.getError()) {
60     llvm::errs() << "Can't read "
61                  << "/proc/cpuinfo: " << EC.message() << "\n";
62     return nullptr;
63   }
64   return std::move(*Text);
65 }
66 
67 StringRef sys::detail::getHostCPUNameForPowerPC(
68     const StringRef &ProcCpuinfoContent) {
69   // Access to the Processor Version Register (PVR) on PowerPC is privileged,
70   // and so we must use an operating-system interface to determine the current
71   // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
72   const char *generic = "generic";
73 
74   // The cpu line is second (after the 'processor: 0' line), so if this
75   // buffer is too small then something has changed (or is wrong).
76   StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
77   StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
78 
79   StringRef::const_iterator CIP = CPUInfoStart;
80 
81   StringRef::const_iterator CPUStart = 0;
82   size_t CPULen = 0;
83 
84   // We need to find the first line which starts with cpu, spaces, and a colon.
85   // After the colon, there may be some additional spaces and then the cpu type.
86   while (CIP < CPUInfoEnd && CPUStart == 0) {
87     if (CIP < CPUInfoEnd && *CIP == '\n')
88       ++CIP;
89 
90     if (CIP < CPUInfoEnd && *CIP == 'c') {
91       ++CIP;
92       if (CIP < CPUInfoEnd && *CIP == 'p') {
93         ++CIP;
94         if (CIP < CPUInfoEnd && *CIP == 'u') {
95           ++CIP;
96           while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
97             ++CIP;
98 
99           if (CIP < CPUInfoEnd && *CIP == ':') {
100             ++CIP;
101             while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
102               ++CIP;
103 
104             if (CIP < CPUInfoEnd) {
105               CPUStart = CIP;
106               while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
107                                           *CIP != ',' && *CIP != '\n'))
108                 ++CIP;
109               CPULen = CIP - CPUStart;
110             }
111           }
112         }
113       }
114     }
115 
116     if (CPUStart == 0)
117       while (CIP < CPUInfoEnd && *CIP != '\n')
118         ++CIP;
119   }
120 
121   if (CPUStart == 0)
122     return generic;
123 
124   return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
125       .Case("604e", "604e")
126       .Case("604", "604")
127       .Case("7400", "7400")
128       .Case("7410", "7400")
129       .Case("7447", "7400")
130       .Case("7455", "7450")
131       .Case("G4", "g4")
132       .Case("POWER4", "970")
133       .Case("PPC970FX", "970")
134       .Case("PPC970MP", "970")
135       .Case("G5", "g5")
136       .Case("POWER5", "g5")
137       .Case("A2", "a2")
138       .Case("POWER6", "pwr6")
139       .Case("POWER7", "pwr7")
140       .Case("POWER8", "pwr8")
141       .Case("POWER8E", "pwr8")
142       .Case("POWER8NVL", "pwr8")
143       .Case("POWER9", "pwr9")
144       .Default(generic);
145 }
146 
147 StringRef sys::detail::getHostCPUNameForARM(
148     const StringRef &ProcCpuinfoContent) {
149   // The cpuid register on arm is not accessible from user space. On Linux,
150   // it is exposed through the /proc/cpuinfo file.
151 
152   // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
153   // in all cases.
154   SmallVector<StringRef, 32> Lines;
155   ProcCpuinfoContent.split(Lines, "\n");
156 
157   // Look for the CPU implementer line.
158   StringRef Implementer;
159   StringRef Hardware;
160   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
161     if (Lines[I].startswith("CPU implementer"))
162       Implementer = Lines[I].substr(15).ltrim("\t :");
163     if (Lines[I].startswith("Hardware"))
164       Hardware = Lines[I].substr(8).ltrim("\t :");
165   }
166 
167   if (Implementer == "0x41") { // ARM Ltd.
168     // MSM8992/8994 may give cpu part for the core that the kernel is running on,
169     // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
170     if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
171       return "cortex-a53";
172 
173 
174     // Look for the CPU part line.
175     for (unsigned I = 0, E = Lines.size(); I != E; ++I)
176       if (Lines[I].startswith("CPU part"))
177         // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
178         // values correspond to the "Part number" in the CP15/c0 register. The
179         // contents are specified in the various processor manuals.
180         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
181             .Case("0x926", "arm926ej-s")
182             .Case("0xb02", "mpcore")
183             .Case("0xb36", "arm1136j-s")
184             .Case("0xb56", "arm1156t2-s")
185             .Case("0xb76", "arm1176jz-s")
186             .Case("0xc08", "cortex-a8")
187             .Case("0xc09", "cortex-a9")
188             .Case("0xc0f", "cortex-a15")
189             .Case("0xc20", "cortex-m0")
190             .Case("0xc23", "cortex-m3")
191             .Case("0xc24", "cortex-m4")
192             .Case("0xd04", "cortex-a35")
193             .Case("0xd03", "cortex-a53")
194             .Case("0xd07", "cortex-a57")
195             .Case("0xd08", "cortex-a72")
196             .Case("0xd09", "cortex-a73")
197             .Default("generic");
198   }
199 
200   if (Implementer == "0x51") // Qualcomm Technologies, Inc.
201     // Look for the CPU part line.
202     for (unsigned I = 0, E = Lines.size(); I != E; ++I)
203       if (Lines[I].startswith("CPU part"))
204         // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
205         // values correspond to the "Part number" in the CP15/c0 register. The
206         // contents are specified in the various processor manuals.
207         return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
208             .Case("0x06f", "krait") // APQ8064
209             .Case("0x201", "kryo")
210             .Case("0x205", "kryo")
211             .Default("generic");
212 
213   return "generic";
214 }
215 
216 StringRef sys::detail::getHostCPUNameForS390x(
217     const StringRef &ProcCpuinfoContent) {
218   // STIDP is a privileged operation, so use /proc/cpuinfo instead.
219 
220   // The "processor 0:" line comes after a fair amount of other information,
221   // including a cache breakdown, but this should be plenty.
222   SmallVector<StringRef, 32> Lines;
223   ProcCpuinfoContent.split(Lines, "\n");
224 
225   // Look for the CPU features.
226   SmallVector<StringRef, 32> CPUFeatures;
227   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
228     if (Lines[I].startswith("features")) {
229       size_t Pos = Lines[I].find(":");
230       if (Pos != StringRef::npos) {
231         Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
232         break;
233       }
234     }
235 
236   // We need to check for the presence of vector support independently of
237   // the machine type, since we may only use the vector register set when
238   // supported by the kernel (and hypervisor).
239   bool HaveVectorSupport = false;
240   for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
241     if (CPUFeatures[I] == "vx")
242       HaveVectorSupport = true;
243   }
244 
245   // Now check the processor machine type.
246   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
247     if (Lines[I].startswith("processor ")) {
248       size_t Pos = Lines[I].find("machine = ");
249       if (Pos != StringRef::npos) {
250         Pos += sizeof("machine = ") - 1;
251         unsigned int Id;
252         if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
253           if (Id >= 3906 && HaveVectorSupport)
254             return "z14";
255           if (Id >= 2964 && HaveVectorSupport)
256             return "z13";
257           if (Id >= 2827)
258             return "zEC12";
259           if (Id >= 2817)
260             return "z196";
261         }
262       }
263       break;
264     }
265   }
266 
267   return "generic";
268 }
269 
270 #if defined(__i386__) || defined(_M_IX86) || \
271     defined(__x86_64__) || defined(_M_X64)
272 
273 enum VendorSignatures {
274   SIG_INTEL = 0x756e6547 /* Genu */,
275   SIG_AMD = 0x68747541 /* Auth */
276 };
277 
278 enum ProcessorVendors {
279   VENDOR_INTEL = 1,
280   VENDOR_AMD,
281   VENDOR_OTHER,
282   VENDOR_MAX
283 };
284 
285 enum ProcessorTypes {
286   INTEL_BONNELL = 1,
287   INTEL_CORE2,
288   INTEL_COREI7,
289   AMDFAM10H,
290   AMDFAM15H,
291   INTEL_SILVERMONT,
292   INTEL_KNL,
293   AMD_BTVER1,
294   AMD_BTVER2,
295   AMDFAM17H,
296   // Entries below this are not in libgcc/compiler-rt.
297   INTEL_i386,
298   INTEL_i486,
299   INTEL_PENTIUM,
300   INTEL_PENTIUM_PRO,
301   INTEL_PENTIUM_II,
302   INTEL_PENTIUM_III,
303   INTEL_PENTIUM_IV,
304   INTEL_PENTIUM_M,
305   INTEL_CORE_DUO,
306   INTEL_X86_64,
307   INTEL_NOCONA,
308   INTEL_PRESCOTT,
309   AMD_i486,
310   AMDPENTIUM,
311   AMDATHLON,
312   INTEL_GOLDMONT,
313   CPU_TYPE_MAX
314 };
315 
316 enum ProcessorSubtypes {
317   INTEL_COREI7_NEHALEM = 1,
318   INTEL_COREI7_WESTMERE,
319   INTEL_COREI7_SANDYBRIDGE,
320   AMDFAM10H_BARCELONA,
321   AMDFAM10H_SHANGHAI,
322   AMDFAM10H_ISTANBUL,
323   AMDFAM15H_BDVER1,
324   AMDFAM15H_BDVER2,
325   AMDFAM15H_BDVER3,
326   AMDFAM15H_BDVER4,
327   AMDFAM17H_ZNVER1,
328   INTEL_COREI7_IVYBRIDGE,
329   INTEL_COREI7_HASWELL,
330   INTEL_COREI7_BROADWELL,
331   INTEL_COREI7_SKYLAKE,
332   INTEL_COREI7_SKYLAKE_AVX512,
333   // Entries below this are not in libgcc/compiler-rt.
334   INTEL_PENTIUM_MMX,
335   INTEL_CORE2_65,
336   INTEL_CORE2_45,
337   AMDPENTIUM_K6,
338   AMDPENTIUM_K62,
339   AMDPENTIUM_K63,
340   AMDPENTIUM_GEODE,
341   AMDATHLON_CLASSIC,
342   AMDATHLON_XP,
343   AMDATHLON_K8,
344   AMDATHLON_K8SSE3,
345   CPU_SUBTYPE_MAX
346 };
347 
348 enum ProcessorFeatures {
349   FEATURE_CMOV = 0,
350   FEATURE_MMX,
351   FEATURE_POPCNT,
352   FEATURE_SSE,
353   FEATURE_SSE2,
354   FEATURE_SSE3,
355   FEATURE_SSSE3,
356   FEATURE_SSE4_1,
357   FEATURE_SSE4_2,
358   FEATURE_AVX,
359   FEATURE_AVX2,
360   FEATURE_SSE4_A,
361   FEATURE_FMA4,
362   FEATURE_XOP,
363   FEATURE_FMA,
364   FEATURE_AVX512F,
365   FEATURE_BMI,
366   FEATURE_BMI2,
367   FEATURE_AES,
368   FEATURE_PCLMUL,
369   FEATURE_AVX512VL,
370   FEATURE_AVX512BW,
371   FEATURE_AVX512DQ,
372   FEATURE_AVX512CD,
373   FEATURE_AVX512ER,
374   FEATURE_AVX512PF,
375   FEATURE_AVX512VBMI,
376   FEATURE_AVX512IFMA,
377   FEATURE_AVX5124VNNIW,
378   FEATURE_AVX5124FMAPS,
379   FEATURE_AVX512VPOPCNTDQ,
380   // Only one bit free left in the first 32 features.
381   FEATURE_MOVBE = 32,
382   FEATURE_ADX,
383   FEATURE_EM64T
384 };
385 
386 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
387 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
388 // support. Consequently, for i386, the presence of CPUID is checked first
389 // via the corresponding eflags bit.
390 // Removal of cpuid.h header motivated by PR30384
391 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
392 // or test-suite, but are used in external projects e.g. libstdcxx
393 static bool isCpuIdSupported() {
394 #if defined(__GNUC__) || defined(__clang__)
395 #if defined(__i386__)
396   int __cpuid_supported;
397   __asm__("  pushfl\n"
398           "  popl   %%eax\n"
399           "  movl   %%eax,%%ecx\n"
400           "  xorl   $0x00200000,%%eax\n"
401           "  pushl  %%eax\n"
402           "  popfl\n"
403           "  pushfl\n"
404           "  popl   %%eax\n"
405           "  movl   $0,%0\n"
406           "  cmpl   %%eax,%%ecx\n"
407           "  je     1f\n"
408           "  movl   $1,%0\n"
409           "1:"
410           : "=r"(__cpuid_supported)
411           :
412           : "eax", "ecx");
413   if (!__cpuid_supported)
414     return false;
415 #endif
416   return true;
417 #endif
418   return true;
419 }
420 
421 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
422 /// the specified arguments.  If we can't run cpuid on the host, return true.
423 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
424                                unsigned *rECX, unsigned *rEDX) {
425 #if defined(__GNUC__) || defined(__clang__)
426 #if defined(__x86_64__)
427   // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
428   // FIXME: should we save this for Clang?
429   __asm__("movq\t%%rbx, %%rsi\n\t"
430           "cpuid\n\t"
431           "xchgq\t%%rbx, %%rsi\n\t"
432           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
433           : "a"(value));
434   return false;
435 #elif defined(__i386__)
436   __asm__("movl\t%%ebx, %%esi\n\t"
437           "cpuid\n\t"
438           "xchgl\t%%ebx, %%esi\n\t"
439           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
440           : "a"(value));
441   return false;
442 #else
443   return true;
444 #endif
445 #elif defined(_MSC_VER)
446   // The MSVC intrinsic is portable across x86 and x64.
447   int registers[4];
448   __cpuid(registers, value);
449   *rEAX = registers[0];
450   *rEBX = registers[1];
451   *rECX = registers[2];
452   *rEDX = registers[3];
453   return false;
454 #else
455   return true;
456 #endif
457 }
458 
459 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
460 /// the 4 values in the specified arguments.  If we can't run cpuid on the host,
461 /// return true.
462 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
463                                  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
464                                  unsigned *rEDX) {
465 #if defined(__GNUC__) || defined(__clang__)
466 #if defined(__x86_64__)
467   // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
468   // FIXME: should we save this for Clang?
469   __asm__("movq\t%%rbx, %%rsi\n\t"
470           "cpuid\n\t"
471           "xchgq\t%%rbx, %%rsi\n\t"
472           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
473           : "a"(value), "c"(subleaf));
474   return false;
475 #elif defined(__i386__)
476   __asm__("movl\t%%ebx, %%esi\n\t"
477           "cpuid\n\t"
478           "xchgl\t%%ebx, %%esi\n\t"
479           : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
480           : "a"(value), "c"(subleaf));
481   return false;
482 #else
483   return true;
484 #endif
485 #elif defined(_MSC_VER)
486   int registers[4];
487   __cpuidex(registers, value, subleaf);
488   *rEAX = registers[0];
489   *rEBX = registers[1];
490   *rECX = registers[2];
491   *rEDX = registers[3];
492   return false;
493 #else
494   return true;
495 #endif
496 }
497 
498 // Read control register 0 (XCR0). Used to detect features such as AVX.
499 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
500 #if defined(__GNUC__) || defined(__clang__)
501   // Check xgetbv; this uses a .byte sequence instead of the instruction
502   // directly because older assemblers do not include support for xgetbv and
503   // there is no easy way to conditionally compile based on the assembler used.
504   __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
505   return false;
506 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
507   unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
508   *rEAX = Result;
509   *rEDX = Result >> 32;
510   return false;
511 #else
512   return true;
513 #endif
514 }
515 
516 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
517                                  unsigned *Model) {
518   *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
519   *Model = (EAX >> 4) & 0xf;  // Bits 4 - 7
520   if (*Family == 6 || *Family == 0xf) {
521     if (*Family == 0xf)
522       // Examine extended family ID if family ID is F.
523       *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
524     // Examine extended model ID if family ID is 6 or F.
525     *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
526   }
527 }
528 
529 static void
530 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
531                                 unsigned Brand_id, unsigned Features,
532                                 unsigned Features2, unsigned *Type,
533                                 unsigned *Subtype) {
534   if (Brand_id != 0)
535     return;
536   switch (Family) {
537   case 3:
538     *Type = INTEL_i386;
539     break;
540   case 4:
541     switch (Model) {
542     case 0: // Intel486 DX processors
543     case 1: // Intel486 DX processors
544     case 2: // Intel486 SX processors
545     case 3: // Intel487 processors, IntelDX2 OverDrive processors,
546             // IntelDX2 processors
547     case 4: // Intel486 SL processor
548     case 5: // IntelSX2 processors
549     case 7: // Write-Back Enhanced IntelDX2 processors
550     case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
551     default:
552       *Type = INTEL_i486;
553       break;
554     }
555     break;
556   case 5:
557     switch (Model) {
558     case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
559             // Pentium processors (60, 66)
560     case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
561             // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
562             // 150, 166, 200)
563     case 3: // Pentium OverDrive processors for Intel486 processor-based
564             // systems
565       *Type = INTEL_PENTIUM;
566       break;
567     case 4: // Pentium OverDrive processor with MMX technology for Pentium
568             // processor (75, 90, 100, 120, 133), Pentium processor with
569             // MMX technology (166, 200)
570       *Type = INTEL_PENTIUM;
571       *Subtype = INTEL_PENTIUM_MMX;
572       break;
573     default:
574       *Type = INTEL_PENTIUM;
575       break;
576     }
577     break;
578   case 6:
579     switch (Model) {
580     case 0x01: // Pentium Pro processor
581       *Type = INTEL_PENTIUM_PRO;
582       break;
583     case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
584                // model 03
585     case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
586                // model 05, and Intel Celeron processor, model 05
587     case 0x06: // Celeron processor, model 06
588       *Type = INTEL_PENTIUM_II;
589       break;
590     case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
591                // processor, model 07
592     case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
593                // model 08, and Celeron processor, model 08
594     case 0x0a: // Pentium III Xeon processor, model 0Ah
595     case 0x0b: // Pentium III processor, model 0Bh
596       *Type = INTEL_PENTIUM_III;
597       break;
598     case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
599     case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
600                // 0Dh. All processors are manufactured using the 90 nm process.
601     case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
602                // Integrated Processor with Intel QuickAssist Technology
603       *Type = INTEL_PENTIUM_M;
604       break;
605     case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
606                // 0Eh. All processors are manufactured using the 65 nm process.
607       *Type = INTEL_CORE_DUO;
608       break;   // yonah
609     case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
610                // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
611                // mobile processor, Intel Core 2 Extreme processor, Intel
612                // Pentium Dual-Core processor, Intel Xeon processor, model
613                // 0Fh. All processors are manufactured using the 65 nm process.
614     case 0x16: // Intel Celeron processor model 16h. All processors are
615                // manufactured using the 65 nm process
616       *Type = INTEL_CORE2; // "core2"
617       *Subtype = INTEL_CORE2_65;
618       break;
619     case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
620                // 17h. All processors are manufactured using the 45 nm process.
621                //
622                // 45nm: Penryn , Wolfdale, Yorkfield (XE)
623     case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
624                // the 45 nm process.
625       *Type = INTEL_CORE2; // "penryn"
626       *Subtype = INTEL_CORE2_45;
627       break;
628     case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
629                // processors are manufactured using the 45 nm process.
630     case 0x1e: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
631                // As found in a Summer 2010 model iMac.
632     case 0x1f:
633     case 0x2e:             // Nehalem EX
634       *Type = INTEL_COREI7; // "nehalem"
635       *Subtype = INTEL_COREI7_NEHALEM;
636       break;
637     case 0x25: // Intel Core i7, laptop version.
638     case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
639                // processors are manufactured using the 32 nm process.
640     case 0x2f: // Westmere EX
641       *Type = INTEL_COREI7; // "westmere"
642       *Subtype = INTEL_COREI7_WESTMERE;
643       break;
644     case 0x2a: // Intel Core i7 processor. All processors are manufactured
645                // using the 32 nm process.
646     case 0x2d:
647       *Type = INTEL_COREI7; //"sandybridge"
648       *Subtype = INTEL_COREI7_SANDYBRIDGE;
649       break;
650     case 0x3a:
651     case 0x3e:             // Ivy Bridge EP
652       *Type = INTEL_COREI7; // "ivybridge"
653       *Subtype = INTEL_COREI7_IVYBRIDGE;
654       break;
655 
656     // Haswell:
657     case 0x3c:
658     case 0x3f:
659     case 0x45:
660     case 0x46:
661       *Type = INTEL_COREI7; // "haswell"
662       *Subtype = INTEL_COREI7_HASWELL;
663       break;
664 
665     // Broadwell:
666     case 0x3d:
667     case 0x47:
668     case 0x4f:
669     case 0x56:
670       *Type = INTEL_COREI7; // "broadwell"
671       *Subtype = INTEL_COREI7_BROADWELL;
672       break;
673 
674     // Skylake:
675     case 0x4e: // Skylake mobile
676     case 0x5e: // Skylake desktop
677     case 0x8e: // Kaby Lake mobile
678     case 0x9e: // Kaby Lake desktop
679       *Type = INTEL_COREI7; // "skylake"
680       *Subtype = INTEL_COREI7_SKYLAKE;
681       break;
682 
683     // Skylake Xeon:
684     case 0x55:
685       *Type = INTEL_COREI7;
686       *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
687       break;
688 
689     case 0x1c: // Most 45 nm Intel Atom processors
690     case 0x26: // 45 nm Atom Lincroft
691     case 0x27: // 32 nm Atom Medfield
692     case 0x35: // 32 nm Atom Midview
693     case 0x36: // 32 nm Atom Midview
694       *Type = INTEL_BONNELL;
695       break; // "bonnell"
696 
697     // Atom Silvermont codes from the Intel software optimization guide.
698     case 0x37:
699     case 0x4a:
700     case 0x4d:
701     case 0x5a:
702     case 0x5d:
703     case 0x4c: // really airmont
704       *Type = INTEL_SILVERMONT;
705       break; // "silvermont"
706     // Goldmont:
707     case 0x5c:
708     case 0x5f:
709       *Type = INTEL_GOLDMONT;
710       break; // "goldmont"
711     case 0x57:
712       *Type = INTEL_KNL; // knl
713       break;
714 
715     default: // Unknown family 6 CPU, try to guess.
716       if (Features & (1 << FEATURE_AVX512F)) {
717         *Type = INTEL_KNL; // knl
718         break;
719       }
720       if (Features2 & (1 << (FEATURE_ADX - 32))) {
721         *Type = INTEL_COREI7;
722         *Subtype = INTEL_COREI7_BROADWELL;
723         break;
724       }
725       if (Features & (1 << FEATURE_AVX2)) {
726         *Type = INTEL_COREI7;
727         *Subtype = INTEL_COREI7_HASWELL;
728         break;
729       }
730       if (Features & (1 << FEATURE_AVX)) {
731         *Type = INTEL_COREI7;
732         *Subtype = INTEL_COREI7_SANDYBRIDGE;
733         break;
734       }
735       if (Features & (1 << FEATURE_SSE4_2)) {
736         if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
737           *Type = INTEL_SILVERMONT;
738         } else {
739           *Type = INTEL_COREI7;
740           *Subtype = INTEL_COREI7_NEHALEM;
741         }
742         break;
743       }
744       if (Features & (1 << FEATURE_SSE4_1)) {
745         *Type = INTEL_CORE2; // "penryn"
746         *Subtype = INTEL_CORE2_45;
747         break;
748       }
749       if (Features & (1 << FEATURE_SSSE3)) {
750         if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
751           *Type = INTEL_BONNELL; // "bonnell"
752         } else {
753           *Type = INTEL_CORE2; // "core2"
754           *Subtype = INTEL_CORE2_65;
755         }
756         break;
757       }
758       if (Features2 & (1 << (FEATURE_EM64T - 32))) {
759         *Type = INTEL_X86_64;
760         break; // x86-64
761       }
762       if (Features & (1 << FEATURE_SSE2)) {
763         *Type = INTEL_PENTIUM_M;
764         break;
765       }
766       if (Features & (1 << FEATURE_SSE)) {
767         *Type = INTEL_PENTIUM_III;
768         break;
769       }
770       if (Features & (1 << FEATURE_MMX)) {
771         *Type = INTEL_PENTIUM_II;
772         break;
773       }
774       *Type = INTEL_PENTIUM_PRO;
775       break;
776     }
777     break;
778   case 15: {
779     switch (Model) {
780     case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
781             // model 00h and manufactured using the 0.18 micron process.
782     case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
783             // processor MP, and Intel Celeron processor. All processors are
784             // model 01h and manufactured using the 0.18 micron process.
785     case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
786             // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
787             // processor, and Mobile Intel Celeron processor. All processors
788             // are model 02h and manufactured using the 0.13 micron process.
789       *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64
790                                                          : INTEL_PENTIUM_IV);
791       break;
792 
793     case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
794             // processor. All processors are model 03h and manufactured using
795             // the 90 nm process.
796     case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
797             // Pentium D processor, Intel Xeon processor, Intel Xeon
798             // processor MP, Intel Celeron D processor. All processors are
799             // model 04h and manufactured using the 90 nm process.
800     case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
801             // Extreme Edition, Intel Xeon processor, Intel Xeon processor
802             // MP, Intel Celeron D processor. All processors are model 06h
803             // and manufactured using the 65 nm process.
804       *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA
805                                                          : INTEL_PRESCOTT);
806       break;
807 
808     default:
809       *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64
810                                                          : INTEL_PENTIUM_IV);
811       break;
812     }
813     break;
814   }
815   default:
816     break; /*"generic"*/
817   }
818 }
819 
820 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
821                                           unsigned Features, unsigned *Type,
822                                           unsigned *Subtype) {
823   // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
824   // appears to be no way to generate the wide variety of AMD-specific targets
825   // from the information returned from CPUID.
826   switch (Family) {
827   case 4:
828     *Type = AMD_i486;
829     break;
830   case 5:
831     *Type = AMDPENTIUM;
832     switch (Model) {
833     case 6:
834     case 7:
835       *Subtype = AMDPENTIUM_K6;
836       break; // "k6"
837     case 8:
838       *Subtype = AMDPENTIUM_K62;
839       break; // "k6-2"
840     case 9:
841     case 13:
842       *Subtype = AMDPENTIUM_K63;
843       break; // "k6-3"
844     case 10:
845       *Subtype = AMDPENTIUM_GEODE;
846       break; // "geode"
847     }
848     break;
849   case 6:
850     *Type = AMDATHLON;
851     if (Features & (1 << FEATURE_SSE)) {
852       *Subtype = AMDATHLON_XP;
853       break; // "athlon-xp"
854     }
855     *Subtype = AMDATHLON_CLASSIC;
856     break; // "athlon"
857   case 15:
858     *Type = AMDATHLON;
859     if (Features & (1 << FEATURE_SSE3)) {
860       *Subtype = AMDATHLON_K8SSE3;
861       break; // "k8-sse3"
862     }
863     *Subtype = AMDATHLON_K8;
864     break; // "k8"
865   case 16:
866     *Type = AMDFAM10H; // "amdfam10"
867     switch (Model) {
868     case 2:
869       *Subtype = AMDFAM10H_BARCELONA;
870       break;
871     case 4:
872       *Subtype = AMDFAM10H_SHANGHAI;
873       break;
874     case 8:
875       *Subtype = AMDFAM10H_ISTANBUL;
876       break;
877     }
878     break;
879   case 20:
880     *Type = AMD_BTVER1;
881     break; // "btver1";
882   case 21:
883     *Type = AMDFAM15H;
884     if (Model >= 0x60 && Model <= 0x7f) {
885       *Subtype = AMDFAM15H_BDVER4;
886       break; // "bdver4"; 60h-7Fh: Excavator
887     }
888     if (Model >= 0x30 && Model <= 0x3f) {
889       *Subtype = AMDFAM15H_BDVER3;
890       break; // "bdver3"; 30h-3Fh: Steamroller
891     }
892     if (Model >= 0x10 && Model <= 0x1f) {
893       *Subtype = AMDFAM15H_BDVER2;
894       break; // "bdver2"; 10h-1Fh: Piledriver
895     }
896     if (Model <= 0x0f) {
897       *Subtype = AMDFAM15H_BDVER1;
898       break; // "bdver1"; 00h-0Fh: Bulldozer
899     }
900     break;
901   case 22:
902     *Type = AMD_BTVER2;
903     break; // "btver2"
904   case 23:
905     *Type = AMDFAM17H;
906     *Subtype = AMDFAM17H_ZNVER1;
907     break;
908   default:
909     break; // "generic"
910   }
911 }
912 
913 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
914                                  unsigned *FeaturesOut,
915                                  unsigned *Features2Out) {
916   unsigned Features = 0;
917   unsigned Features2 = 0;
918   unsigned EAX, EBX;
919 
920   if ((EDX >> 15) & 1)
921     Features |= 1 << FEATURE_CMOV;
922   if ((EDX >> 23) & 1)
923     Features |= 1 << FEATURE_MMX;
924   if ((EDX >> 25) & 1)
925     Features |= 1 << FEATURE_SSE;
926   if ((EDX >> 26) & 1)
927     Features |= 1 << FEATURE_SSE2;
928 
929   if ((ECX >> 0) & 1)
930     Features |= 1 << FEATURE_SSE3;
931   if ((ECX >> 1) & 1)
932     Features |= 1 << FEATURE_PCLMUL;
933   if ((ECX >> 9) & 1)
934     Features |= 1 << FEATURE_SSSE3;
935   if ((ECX >> 12) & 1)
936     Features |= 1 << FEATURE_FMA;
937   if ((ECX >> 19) & 1)
938     Features |= 1 << FEATURE_SSE4_1;
939   if ((ECX >> 20) & 1)
940     Features |= 1 << FEATURE_SSE4_2;
941   if ((ECX >> 23) & 1)
942     Features |= 1 << FEATURE_POPCNT;
943   if ((ECX >> 25) & 1)
944     Features |= 1 << FEATURE_AES;
945 
946   if ((ECX >> 22) & 1)
947     Features2 |= 1 << (FEATURE_MOVBE - 32);
948 
949   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
950   // indicates that the AVX registers will be saved and restored on context
951   // switch, then we have full AVX support.
952   const unsigned AVXBits = (1 << 27) | (1 << 28);
953   bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
954                 ((EAX & 0x6) == 0x6);
955   bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
956 
957   if (HasAVX)
958     Features |= 1 << FEATURE_AVX;
959 
960   bool HasLeaf7 =
961       MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
962 
963   if (HasLeaf7 && ((EBX >> 3) & 1))
964     Features |= 1 << FEATURE_BMI;
965   if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
966     Features |= 1 << FEATURE_AVX2;
967   if (HasLeaf7 && ((EBX >> 9) & 1))
968     Features |= 1 << FEATURE_BMI2;
969   if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
970     Features |= 1 << FEATURE_AVX512F;
971   if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
972     Features |= 1 << FEATURE_AVX512DQ;
973   if (HasLeaf7 && ((EBX >> 19) & 1))
974     Features2 |= 1 << (FEATURE_ADX - 32);
975   if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
976     Features |= 1 << FEATURE_AVX512IFMA;
977   if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
978     Features |= 1 << FEATURE_AVX512PF;
979   if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
980     Features |= 1 << FEATURE_AVX512ER;
981   if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
982     Features |= 1 << FEATURE_AVX512CD;
983   if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
984     Features |= 1 << FEATURE_AVX512BW;
985   if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
986     Features |= 1 << FEATURE_AVX512VL;
987 
988   if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
989     Features |= 1 << FEATURE_AVX512VBMI;
990   if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
991     Features |= 1 << FEATURE_AVX512VPOPCNTDQ;
992 
993   if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
994     Features |= 1 << FEATURE_AVX5124VNNIW;
995   if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
996     Features |= 1 << FEATURE_AVX5124FMAPS;
997 
998   unsigned MaxExtLevel;
999   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1000 
1001   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1002                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1003   if (HasExtLeaf1 && ((ECX >> 6) & 1))
1004     Features |= 1 << FEATURE_SSE4_A;
1005   if (HasExtLeaf1 && ((ECX >> 11) & 1))
1006     Features |= 1 << FEATURE_XOP;
1007   if (HasExtLeaf1 && ((ECX >> 16) & 1))
1008     Features |= 1 << FEATURE_FMA4;
1009 
1010   if (HasExtLeaf1 && ((EDX >> 29) & 1))
1011     Features2 |= 1 << (FEATURE_EM64T - 32);
1012 
1013   *FeaturesOut  = Features;
1014   *Features2Out = Features2;
1015 }
1016 
1017 StringRef sys::getHostCPUName() {
1018   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1019   unsigned MaxLeaf, Vendor;
1020 
1021 #if defined(__GNUC__) || defined(__clang__)
1022   //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1023   // and simplify it to not invoke __cpuid (like cpu_model.c in
1024   // compiler-rt/lib/builtins/cpu_model.c?
1025   // Opting for the second option.
1026   if(!isCpuIdSupported())
1027     return "generic";
1028 #endif
1029   if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1030     return "generic";
1031   getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1032 
1033   unsigned Brand_id = EBX & 0xff;
1034   unsigned Family = 0, Model = 0;
1035   unsigned Features = 0, Features2 = 0;
1036   detectX86FamilyModel(EAX, &Family, &Model);
1037   getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2);
1038 
1039   unsigned Type;
1040   unsigned Subtype;
1041 
1042   if (Vendor == SIG_INTEL) {
1043     getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1044                                     Features2, &Type, &Subtype);
1045     switch (Type) {
1046     case INTEL_i386:
1047       return "i386";
1048     case INTEL_i486:
1049       return "i486";
1050     case INTEL_PENTIUM:
1051       if (Subtype == INTEL_PENTIUM_MMX)
1052         return "pentium-mmx";
1053       return "pentium";
1054     case INTEL_PENTIUM_PRO:
1055       return "pentiumpro";
1056     case INTEL_PENTIUM_II:
1057       return "pentium2";
1058     case INTEL_PENTIUM_III:
1059       return "pentium3";
1060     case INTEL_PENTIUM_IV:
1061       return "pentium4";
1062     case INTEL_PENTIUM_M:
1063       return "pentium-m";
1064     case INTEL_CORE_DUO:
1065       return "yonah";
1066     case INTEL_CORE2:
1067       switch (Subtype) {
1068       case INTEL_CORE2_65:
1069         return "core2";
1070       case INTEL_CORE2_45:
1071         return "penryn";
1072       default:
1073         llvm_unreachable("Unexpected subtype!");
1074       }
1075     case INTEL_COREI7:
1076       switch (Subtype) {
1077       case INTEL_COREI7_NEHALEM:
1078         return "nehalem";
1079       case INTEL_COREI7_WESTMERE:
1080         return "westmere";
1081       case INTEL_COREI7_SANDYBRIDGE:
1082         return "sandybridge";
1083       case INTEL_COREI7_IVYBRIDGE:
1084         return "ivybridge";
1085       case INTEL_COREI7_HASWELL:
1086         return "haswell";
1087       case INTEL_COREI7_BROADWELL:
1088         return "broadwell";
1089       case INTEL_COREI7_SKYLAKE:
1090         return "skylake";
1091       case INTEL_COREI7_SKYLAKE_AVX512:
1092         return "skylake-avx512";
1093       default:
1094         llvm_unreachable("Unexpected subtype!");
1095       }
1096     case INTEL_BONNELL:
1097       return "bonnell";
1098     case INTEL_SILVERMONT:
1099       return "silvermont";
1100     case INTEL_GOLDMONT:
1101       return "goldmont";
1102     case INTEL_KNL:
1103       return "knl";
1104     case INTEL_X86_64:
1105       return "x86-64";
1106     case INTEL_NOCONA:
1107       return "nocona";
1108     case INTEL_PRESCOTT:
1109       return "prescott";
1110     default:
1111       break;
1112     }
1113   } else if (Vendor == SIG_AMD) {
1114     getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1115     switch (Type) {
1116     case AMD_i486:
1117       return "i486";
1118     case AMDPENTIUM:
1119       switch (Subtype) {
1120       case AMDPENTIUM_K6:
1121         return "k6";
1122       case AMDPENTIUM_K62:
1123         return "k6-2";
1124       case AMDPENTIUM_K63:
1125         return "k6-3";
1126       case AMDPENTIUM_GEODE:
1127         return "geode";
1128       default:
1129         return "pentium";
1130       }
1131     case AMDATHLON:
1132       switch (Subtype) {
1133       case AMDATHLON_CLASSIC:
1134         return "athlon";
1135       case AMDATHLON_XP:
1136         return "athlon-xp";
1137       case AMDATHLON_K8:
1138         return "k8";
1139       case AMDATHLON_K8SSE3:
1140         return "k8-sse3";
1141       default:
1142         llvm_unreachable("Unexpected subtype!");
1143       }
1144     case AMDFAM10H:
1145       return "amdfam10";
1146     case AMD_BTVER1:
1147       return "btver1";
1148     case AMDFAM15H:
1149       switch (Subtype) {
1150       default: // There are gaps in the subtype detection.
1151       case AMDFAM15H_BDVER1:
1152         return "bdver1";
1153       case AMDFAM15H_BDVER2:
1154         return "bdver2";
1155       case AMDFAM15H_BDVER3:
1156         return "bdver3";
1157       case AMDFAM15H_BDVER4:
1158         return "bdver4";
1159       }
1160     case AMD_BTVER2:
1161       return "btver2";
1162     case AMDFAM17H:
1163       return "znver1";
1164     default:
1165       break;
1166     }
1167   }
1168   return "generic";
1169 }
1170 
1171 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1172 StringRef sys::getHostCPUName() {
1173   host_basic_info_data_t hostInfo;
1174   mach_msg_type_number_t infoCount;
1175 
1176   infoCount = HOST_BASIC_INFO_COUNT;
1177   host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
1178             &infoCount);
1179 
1180   if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1181     return "generic";
1182 
1183   switch (hostInfo.cpu_subtype) {
1184   case CPU_SUBTYPE_POWERPC_601:
1185     return "601";
1186   case CPU_SUBTYPE_POWERPC_602:
1187     return "602";
1188   case CPU_SUBTYPE_POWERPC_603:
1189     return "603";
1190   case CPU_SUBTYPE_POWERPC_603e:
1191     return "603e";
1192   case CPU_SUBTYPE_POWERPC_603ev:
1193     return "603ev";
1194   case CPU_SUBTYPE_POWERPC_604:
1195     return "604";
1196   case CPU_SUBTYPE_POWERPC_604e:
1197     return "604e";
1198   case CPU_SUBTYPE_POWERPC_620:
1199     return "620";
1200   case CPU_SUBTYPE_POWERPC_750:
1201     return "750";
1202   case CPU_SUBTYPE_POWERPC_7400:
1203     return "7400";
1204   case CPU_SUBTYPE_POWERPC_7450:
1205     return "7450";
1206   case CPU_SUBTYPE_POWERPC_970:
1207     return "970";
1208   default:;
1209   }
1210 
1211   return "generic";
1212 }
1213 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1214 StringRef sys::getHostCPUName() {
1215   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1216   const StringRef& Content = P ? P->getBuffer() : "";
1217   return detail::getHostCPUNameForPowerPC(Content);
1218 }
1219 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1220 StringRef sys::getHostCPUName() {
1221   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1222   const StringRef& Content = P ? P->getBuffer() : "";
1223   return detail::getHostCPUNameForARM(Content);
1224 }
1225 #elif defined(__linux__) && defined(__s390x__)
1226 StringRef sys::getHostCPUName() {
1227   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1228   const StringRef& Content = P ? P->getBuffer() : "";
1229   return detail::getHostCPUNameForS390x(Content);
1230 }
1231 #else
1232 StringRef sys::getHostCPUName() { return "generic"; }
1233 #endif
1234 
1235 #if defined(__linux__) && defined(__x86_64__)
1236 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1237 // using the number of unique physical/core id pairs. The following
1238 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1239 static int computeHostNumPhysicalCores() {
1240   // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1241   // mmapped because it appears to have 0 size.
1242   llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
1243       llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1244   if (std::error_code EC = Text.getError()) {
1245     llvm::errs() << "Can't read "
1246                  << "/proc/cpuinfo: " << EC.message() << "\n";
1247     return -1;
1248   }
1249   SmallVector<StringRef, 8> strs;
1250   (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1251                              /*KeepEmpty=*/false);
1252   int CurPhysicalId = -1;
1253   int CurCoreId = -1;
1254   SmallSet<std::pair<int, int>, 32> UniqueItems;
1255   for (auto &Line : strs) {
1256     Line = Line.trim();
1257     if (!Line.startswith("physical id") && !Line.startswith("core id"))
1258       continue;
1259     std::pair<StringRef, StringRef> Data = Line.split(':');
1260     auto Name = Data.first.trim();
1261     auto Val = Data.second.trim();
1262     if (Name == "physical id") {
1263       assert(CurPhysicalId == -1 &&
1264              "Expected a core id before seeing another physical id");
1265       Val.getAsInteger(10, CurPhysicalId);
1266     }
1267     if (Name == "core id") {
1268       assert(CurCoreId == -1 &&
1269              "Expected a physical id before seeing another core id");
1270       Val.getAsInteger(10, CurCoreId);
1271     }
1272     if (CurPhysicalId != -1 && CurCoreId != -1) {
1273       UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1274       CurPhysicalId = -1;
1275       CurCoreId = -1;
1276     }
1277   }
1278   return UniqueItems.size();
1279 }
1280 #elif defined(__APPLE__) && defined(__x86_64__)
1281 #include <sys/param.h>
1282 #include <sys/sysctl.h>
1283 
1284 // Gets the number of *physical cores* on the machine.
1285 static int computeHostNumPhysicalCores() {
1286   uint32_t count;
1287   size_t len = sizeof(count);
1288   sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1289   if (count < 1) {
1290     int nm[2];
1291     nm[0] = CTL_HW;
1292     nm[1] = HW_AVAILCPU;
1293     sysctl(nm, 2, &count, &len, NULL, 0);
1294     if (count < 1)
1295       return -1;
1296   }
1297   return count;
1298 }
1299 #else
1300 // On other systems, return -1 to indicate unknown.
1301 static int computeHostNumPhysicalCores() { return -1; }
1302 #endif
1303 
1304 int sys::getHostNumPhysicalCores() {
1305   static int NumCores = computeHostNumPhysicalCores();
1306   return NumCores;
1307 }
1308 
1309 #if defined(__i386__) || defined(_M_IX86) || \
1310     defined(__x86_64__) || defined(_M_X64)
1311 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1312   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1313   unsigned MaxLevel;
1314   union {
1315     unsigned u[3];
1316     char c[12];
1317   } text;
1318 
1319   if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1320       MaxLevel < 1)
1321     return false;
1322 
1323   getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1324 
1325   Features["cmov"] = (EDX >> 15) & 1;
1326   Features["mmx"] = (EDX >> 23) & 1;
1327   Features["sse"] = (EDX >> 25) & 1;
1328   Features["sse2"] = (EDX >> 26) & 1;
1329   Features["sse3"] = (ECX >> 0) & 1;
1330   Features["ssse3"] = (ECX >> 9) & 1;
1331   Features["sse4.1"] = (ECX >> 19) & 1;
1332   Features["sse4.2"] = (ECX >> 20) & 1;
1333 
1334   Features["pclmul"] = (ECX >> 1) & 1;
1335   Features["cx16"] = (ECX >> 13) & 1;
1336   Features["movbe"] = (ECX >> 22) & 1;
1337   Features["popcnt"] = (ECX >> 23) & 1;
1338   Features["aes"] = (ECX >> 25) & 1;
1339   Features["rdrnd"] = (ECX >> 30) & 1;
1340 
1341   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1342   // indicates that the AVX registers will be saved and restored on context
1343   // switch, then we have full AVX support.
1344   bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1345                     !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1346   Features["avx"] = HasAVXSave;
1347   Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
1348   Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
1349 
1350   // Only enable XSAVE if OS has enabled support for saving YMM state.
1351   Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
1352 
1353   // AVX512 requires additional context to be saved by the OS.
1354   bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1355 
1356   unsigned MaxExtLevel;
1357   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1358 
1359   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1360                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1361   Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1362   Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1363   Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1364   Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1365   Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1366   Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1367   Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1368   Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1369 
1370   bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1371                      !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX);
1372   Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1373 
1374   bool HasLeaf7 =
1375       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1376 
1377   // AVX2 is only supported if we have the OS save support from AVX.
1378   Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
1379 
1380   Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1381   Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1382   Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1383   Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1384   Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1385   Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1386   Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1387   Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1388   Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1389   Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1390 
1391   // AVX512 is only supported if the OS supports the context save for it.
1392   Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1393   Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1394   Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1395   Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1396   Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1397   Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1398   Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1399   Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1400 
1401   Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
1402   Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1403   Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1404   // Enable protection keys
1405   Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1406 
1407   bool HasLeafD = MaxLevel >= 0xd &&
1408                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1409 
1410   // Only enable XSAVE if OS has enabled support for saving YMM state.
1411   Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
1412   Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
1413   Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
1414 
1415   return true;
1416 }
1417 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1418 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1419   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1420   if (!P)
1421     return false;
1422 
1423   SmallVector<StringRef, 32> Lines;
1424   P->getBuffer().split(Lines, "\n");
1425 
1426   SmallVector<StringRef, 32> CPUFeatures;
1427 
1428   // Look for the CPU features.
1429   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1430     if (Lines[I].startswith("Features")) {
1431       Lines[I].split(CPUFeatures, ' ');
1432       break;
1433     }
1434 
1435 #if defined(__aarch64__)
1436   // Keep track of which crypto features we have seen
1437   enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1438   uint32_t crypto = 0;
1439 #endif
1440 
1441   for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1442     StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1443 #if defined(__aarch64__)
1444                                    .Case("asimd", "neon")
1445                                    .Case("fp", "fp-armv8")
1446                                    .Case("crc32", "crc")
1447 #else
1448                                    .Case("half", "fp16")
1449                                    .Case("neon", "neon")
1450                                    .Case("vfpv3", "vfp3")
1451                                    .Case("vfpv3d16", "d16")
1452                                    .Case("vfpv4", "vfp4")
1453                                    .Case("idiva", "hwdiv-arm")
1454                                    .Case("idivt", "hwdiv")
1455 #endif
1456                                    .Default("");
1457 
1458 #if defined(__aarch64__)
1459     // We need to check crypto separately since we need all of the crypto
1460     // extensions to enable the subtarget feature
1461     if (CPUFeatures[I] == "aes")
1462       crypto |= CAP_AES;
1463     else if (CPUFeatures[I] == "pmull")
1464       crypto |= CAP_PMULL;
1465     else if (CPUFeatures[I] == "sha1")
1466       crypto |= CAP_SHA1;
1467     else if (CPUFeatures[I] == "sha2")
1468       crypto |= CAP_SHA2;
1469 #endif
1470 
1471     if (LLVMFeatureStr != "")
1472       Features[LLVMFeatureStr] = true;
1473   }
1474 
1475 #if defined(__aarch64__)
1476   // If we have all crypto bits we can add the feature
1477   if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1478     Features["crypto"] = true;
1479 #endif
1480 
1481   return true;
1482 }
1483 #else
1484 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1485 #endif
1486 
1487 std::string sys::getProcessTriple() {
1488   std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1489   Triple PT(Triple::normalize(TargetTripleString));
1490 
1491   if (sizeof(void *) == 8 && PT.isArch32Bit())
1492     PT = PT.get64BitArchVariant();
1493   if (sizeof(void *) == 4 && PT.isArch64Bit())
1494     PT = PT.get32BitArchVariant();
1495 
1496   return PT.str();
1497 }
1498