1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallVector.h" 15 #include "llvm/ADT/StringMap.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Config/llvm-config.h" 20 #include "llvm/Support/MemoryBuffer.h" 21 #include "llvm/Support/X86TargetParser.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include <string.h> 24 25 // Include the platform-specific parts of this class. 26 #ifdef LLVM_ON_UNIX 27 #include "Unix/Host.inc" 28 #include <sched.h> 29 #endif 30 #ifdef _WIN32 31 #include "Windows/Host.inc" 32 #endif 33 #ifdef _MSC_VER 34 #include <intrin.h> 35 #endif 36 #ifdef __MVS__ 37 #include "llvm/Support/BCD.h" 38 #endif 39 #if defined(__APPLE__) 40 #include <mach/host_info.h> 41 #include <mach/mach.h> 42 #include <mach/mach_host.h> 43 #include <mach/machine.h> 44 #include <sys/param.h> 45 #include <sys/sysctl.h> 46 #endif 47 #ifdef _AIX 48 #include <sys/systemcfg.h> 49 #endif 50 51 #define DEBUG_TYPE "host-detection" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // Implementations of the CPU detection routines 56 // 57 //===----------------------------------------------------------------------===// 58 59 using namespace llvm; 60 61 static std::unique_ptr<llvm::MemoryBuffer> 62 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 63 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 64 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 65 if (std::error_code EC = Text.getError()) { 66 llvm::errs() << "Can't read " 67 << "/proc/cpuinfo: " << EC.message() << "\n"; 68 return nullptr; 69 } 70 return std::move(*Text); 71 } 72 73 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 74 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 75 // and so we must use an operating-system interface to determine the current 76 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 77 const char *generic = "generic"; 78 79 // The cpu line is second (after the 'processor: 0' line), so if this 80 // buffer is too small then something has changed (or is wrong). 81 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 82 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 83 84 StringRef::const_iterator CIP = CPUInfoStart; 85 86 StringRef::const_iterator CPUStart = nullptr; 87 size_t CPULen = 0; 88 89 // We need to find the first line which starts with cpu, spaces, and a colon. 90 // After the colon, there may be some additional spaces and then the cpu type. 91 while (CIP < CPUInfoEnd && CPUStart == nullptr) { 92 if (CIP < CPUInfoEnd && *CIP == '\n') 93 ++CIP; 94 95 if (CIP < CPUInfoEnd && *CIP == 'c') { 96 ++CIP; 97 if (CIP < CPUInfoEnd && *CIP == 'p') { 98 ++CIP; 99 if (CIP < CPUInfoEnd && *CIP == 'u') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd && *CIP == ':') { 105 ++CIP; 106 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 107 ++CIP; 108 109 if (CIP < CPUInfoEnd) { 110 CPUStart = CIP; 111 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 112 *CIP != ',' && *CIP != '\n')) 113 ++CIP; 114 CPULen = CIP - CPUStart; 115 } 116 } 117 } 118 } 119 } 120 121 if (CPUStart == nullptr) 122 while (CIP < CPUInfoEnd && *CIP != '\n') 123 ++CIP; 124 } 125 126 if (CPUStart == nullptr) 127 return generic; 128 129 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 130 .Case("604e", "604e") 131 .Case("604", "604") 132 .Case("7400", "7400") 133 .Case("7410", "7400") 134 .Case("7447", "7400") 135 .Case("7455", "7450") 136 .Case("G4", "g4") 137 .Case("POWER4", "970") 138 .Case("PPC970FX", "970") 139 .Case("PPC970MP", "970") 140 .Case("G5", "g5") 141 .Case("POWER5", "g5") 142 .Case("A2", "a2") 143 .Case("POWER6", "pwr6") 144 .Case("POWER7", "pwr7") 145 .Case("POWER8", "pwr8") 146 .Case("POWER8E", "pwr8") 147 .Case("POWER8NVL", "pwr8") 148 .Case("POWER9", "pwr9") 149 .Case("POWER10", "pwr10") 150 // FIXME: If we get a simulator or machine with the capabilities of 151 // mcpu=future, we should revisit this and add the name reported by the 152 // simulator/machine. 153 .Default(generic); 154 } 155 156 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 157 // The cpuid register on arm is not accessible from user space. On Linux, 158 // it is exposed through the /proc/cpuinfo file. 159 160 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 161 // in all cases. 162 SmallVector<StringRef, 32> Lines; 163 ProcCpuinfoContent.split(Lines, "\n"); 164 165 // Look for the CPU implementer line. 166 StringRef Implementer; 167 StringRef Hardware; 168 StringRef Part; 169 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 170 if (Lines[I].startswith("CPU implementer")) 171 Implementer = Lines[I].substr(15).ltrim("\t :"); 172 if (Lines[I].startswith("Hardware")) 173 Hardware = Lines[I].substr(8).ltrim("\t :"); 174 if (Lines[I].startswith("CPU part")) 175 Part = Lines[I].substr(8).ltrim("\t :"); 176 } 177 178 if (Implementer == "0x41") { // ARM Ltd. 179 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 180 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 181 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 182 return "cortex-a53"; 183 184 185 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 186 // values correspond to the "Part number" in the CP15/c0 register. The 187 // contents are specified in the various processor manuals. 188 // This corresponds to the Main ID Register in Technical Reference Manuals. 189 // and is used in programs like sys-utils 190 return StringSwitch<const char *>(Part) 191 .Case("0x926", "arm926ej-s") 192 .Case("0xb02", "mpcore") 193 .Case("0xb36", "arm1136j-s") 194 .Case("0xb56", "arm1156t2-s") 195 .Case("0xb76", "arm1176jz-s") 196 .Case("0xc08", "cortex-a8") 197 .Case("0xc09", "cortex-a9") 198 .Case("0xc0f", "cortex-a15") 199 .Case("0xc20", "cortex-m0") 200 .Case("0xc23", "cortex-m3") 201 .Case("0xc24", "cortex-m4") 202 .Case("0xd22", "cortex-m55") 203 .Case("0xd02", "cortex-a34") 204 .Case("0xd04", "cortex-a35") 205 .Case("0xd03", "cortex-a53") 206 .Case("0xd07", "cortex-a57") 207 .Case("0xd08", "cortex-a72") 208 .Case("0xd09", "cortex-a73") 209 .Case("0xd0a", "cortex-a75") 210 .Case("0xd0b", "cortex-a76") 211 .Case("0xd0d", "cortex-a77") 212 .Case("0xd41", "cortex-a78") 213 .Case("0xd44", "cortex-x1") 214 .Case("0xd4c", "cortex-x1c") 215 .Case("0xd0c", "neoverse-n1") 216 .Case("0xd49", "neoverse-n2") 217 .Case("0xd40", "neoverse-v1") 218 .Default("generic"); 219 } 220 221 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 222 return StringSwitch<const char *>(Part) 223 .Case("0x516", "thunderx2t99") 224 .Case("0x0516", "thunderx2t99") 225 .Case("0xaf", "thunderx2t99") 226 .Case("0x0af", "thunderx2t99") 227 .Case("0xa1", "thunderxt88") 228 .Case("0x0a1", "thunderxt88") 229 .Default("generic"); 230 } 231 232 if (Implementer == "0x46") { // Fujitsu Ltd. 233 return StringSwitch<const char *>(Part) 234 .Case("0x001", "a64fx") 235 .Default("generic"); 236 } 237 238 if (Implementer == "0x4e") { // NVIDIA Corporation 239 return StringSwitch<const char *>(Part) 240 .Case("0x004", "carmel") 241 .Default("generic"); 242 } 243 244 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 245 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 246 // values correspond to the "Part number" in the CP15/c0 register. The 247 // contents are specified in the various processor manuals. 248 return StringSwitch<const char *>(Part) 249 .Case("0xd01", "tsv110") 250 .Default("generic"); 251 252 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 253 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 254 // values correspond to the "Part number" in the CP15/c0 register. The 255 // contents are specified in the various processor manuals. 256 return StringSwitch<const char *>(Part) 257 .Case("0x06f", "krait") // APQ8064 258 .Case("0x201", "kryo") 259 .Case("0x205", "kryo") 260 .Case("0x211", "kryo") 261 .Case("0x800", "cortex-a73") // Kryo 2xx Gold 262 .Case("0x801", "cortex-a73") // Kryo 2xx Silver 263 .Case("0x802", "cortex-a75") // Kryo 3xx Gold 264 .Case("0x803", "cortex-a75") // Kryo 3xx Silver 265 .Case("0x804", "cortex-a76") // Kryo 4xx Gold 266 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver 267 .Case("0xc00", "falkor") 268 .Case("0xc01", "saphira") 269 .Default("generic"); 270 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 271 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 272 // any predictive pattern across variants and parts. 273 unsigned Variant = 0, Part = 0; 274 275 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 276 // number, corresponding to the Variant bits in the CP15/C0 register. 277 for (auto I : Lines) 278 if (I.consume_front("CPU variant")) 279 I.ltrim("\t :").getAsInteger(0, Variant); 280 281 // Look for the CPU part line, whose value is a 3 digit hexadecimal 282 // number, corresponding to the PartNum bits in the CP15/C0 register. 283 for (auto I : Lines) 284 if (I.consume_front("CPU part")) 285 I.ltrim("\t :").getAsInteger(0, Part); 286 287 unsigned Exynos = (Variant << 12) | Part; 288 switch (Exynos) { 289 default: 290 // Default by falling through to Exynos M3. 291 LLVM_FALLTHROUGH; 292 case 0x1002: 293 return "exynos-m3"; 294 case 0x1003: 295 return "exynos-m4"; 296 } 297 } 298 299 if (Implementer == "0xc0") { // Ampere Computing 300 return StringSwitch<const char *>(Part) 301 .Case("0xac3", "ampere1") 302 .Default("generic"); 303 } 304 305 return "generic"; 306 } 307 308 namespace { 309 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) { 310 switch (Id) { 311 case 2064: // z900 not supported by LLVM 312 case 2066: 313 case 2084: // z990 not supported by LLVM 314 case 2086: 315 case 2094: // z9-109 not supported by LLVM 316 case 2096: 317 return "generic"; 318 case 2097: 319 case 2098: 320 return "z10"; 321 case 2817: 322 case 2818: 323 return "z196"; 324 case 2827: 325 case 2828: 326 return "zEC12"; 327 case 2964: 328 case 2965: 329 return HaveVectorSupport? "z13" : "zEC12"; 330 case 3906: 331 case 3907: 332 return HaveVectorSupport? "z14" : "zEC12"; 333 case 8561: 334 case 8562: 335 return HaveVectorSupport? "z15" : "zEC12"; 336 case 3931: 337 case 3932: 338 default: 339 return HaveVectorSupport? "z16" : "zEC12"; 340 } 341 } 342 } // end anonymous namespace 343 344 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 345 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 346 347 // The "processor 0:" line comes after a fair amount of other information, 348 // including a cache breakdown, but this should be plenty. 349 SmallVector<StringRef, 32> Lines; 350 ProcCpuinfoContent.split(Lines, "\n"); 351 352 // Look for the CPU features. 353 SmallVector<StringRef, 32> CPUFeatures; 354 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 355 if (Lines[I].startswith("features")) { 356 size_t Pos = Lines[I].find(':'); 357 if (Pos != StringRef::npos) { 358 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 359 break; 360 } 361 } 362 363 // We need to check for the presence of vector support independently of 364 // the machine type, since we may only use the vector register set when 365 // supported by the kernel (and hypervisor). 366 bool HaveVectorSupport = false; 367 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 368 if (CPUFeatures[I] == "vx") 369 HaveVectorSupport = true; 370 } 371 372 // Now check the processor machine type. 373 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 374 if (Lines[I].startswith("processor ")) { 375 size_t Pos = Lines[I].find("machine = "); 376 if (Pos != StringRef::npos) { 377 Pos += sizeof("machine = ") - 1; 378 unsigned int Id; 379 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) 380 return getCPUNameFromS390Model(Id, HaveVectorSupport); 381 } 382 break; 383 } 384 } 385 386 return "generic"; 387 } 388 389 StringRef sys::detail::getHostCPUNameForBPF() { 390 #if !defined(__linux__) || !defined(__x86_64__) 391 return "generic"; 392 #else 393 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 394 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 395 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 396 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 397 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 398 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 399 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 400 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 401 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 402 /* BPF_EXIT_INSN() */ 403 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 404 405 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 406 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 407 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 408 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 409 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 410 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 411 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 412 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 413 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 414 /* BPF_EXIT_INSN() */ 415 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 416 417 struct bpf_prog_load_attr { 418 uint32_t prog_type; 419 uint32_t insn_cnt; 420 uint64_t insns; 421 uint64_t license; 422 uint32_t log_level; 423 uint32_t log_size; 424 uint64_t log_buf; 425 uint32_t kern_version; 426 uint32_t prog_flags; 427 } attr = {}; 428 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 429 attr.insn_cnt = 5; 430 attr.insns = (uint64_t)v3_insns; 431 attr.license = (uint64_t)"DUMMY"; 432 433 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 434 sizeof(attr)); 435 if (fd >= 0) { 436 close(fd); 437 return "v3"; 438 } 439 440 /* Clear the whole attr in case its content changed by syscall. */ 441 memset(&attr, 0, sizeof(attr)); 442 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 443 attr.insn_cnt = 5; 444 attr.insns = (uint64_t)v2_insns; 445 attr.license = (uint64_t)"DUMMY"; 446 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 447 if (fd >= 0) { 448 close(fd); 449 return "v2"; 450 } 451 return "v1"; 452 #endif 453 } 454 455 #if defined(__i386__) || defined(_M_IX86) || \ 456 defined(__x86_64__) || defined(_M_X64) 457 458 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 459 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 460 // support. Consequently, for i386, the presence of CPUID is checked first 461 // via the corresponding eflags bit. 462 // Removal of cpuid.h header motivated by PR30384 463 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 464 // or test-suite, but are used in external projects e.g. libstdcxx 465 static bool isCpuIdSupported() { 466 #if defined(__GNUC__) || defined(__clang__) 467 #if defined(__i386__) 468 int __cpuid_supported; 469 __asm__(" pushfl\n" 470 " popl %%eax\n" 471 " movl %%eax,%%ecx\n" 472 " xorl $0x00200000,%%eax\n" 473 " pushl %%eax\n" 474 " popfl\n" 475 " pushfl\n" 476 " popl %%eax\n" 477 " movl $0,%0\n" 478 " cmpl %%eax,%%ecx\n" 479 " je 1f\n" 480 " movl $1,%0\n" 481 "1:" 482 : "=r"(__cpuid_supported) 483 : 484 : "eax", "ecx"); 485 if (!__cpuid_supported) 486 return false; 487 #endif 488 return true; 489 #endif 490 return true; 491 } 492 493 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 494 /// the specified arguments. If we can't run cpuid on the host, return true. 495 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 496 unsigned *rECX, unsigned *rEDX) { 497 #if defined(__GNUC__) || defined(__clang__) 498 #if defined(__x86_64__) 499 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 500 // FIXME: should we save this for Clang? 501 __asm__("movq\t%%rbx, %%rsi\n\t" 502 "cpuid\n\t" 503 "xchgq\t%%rbx, %%rsi\n\t" 504 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 505 : "a"(value)); 506 return false; 507 #elif defined(__i386__) 508 __asm__("movl\t%%ebx, %%esi\n\t" 509 "cpuid\n\t" 510 "xchgl\t%%ebx, %%esi\n\t" 511 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 512 : "a"(value)); 513 return false; 514 #else 515 return true; 516 #endif 517 #elif defined(_MSC_VER) 518 // The MSVC intrinsic is portable across x86 and x64. 519 int registers[4]; 520 __cpuid(registers, value); 521 *rEAX = registers[0]; 522 *rEBX = registers[1]; 523 *rECX = registers[2]; 524 *rEDX = registers[3]; 525 return false; 526 #else 527 return true; 528 #endif 529 } 530 531 namespace llvm { 532 namespace sys { 533 namespace detail { 534 namespace x86 { 535 536 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 537 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 538 if (MaxLeaf == nullptr) 539 MaxLeaf = &EAX; 540 else 541 *MaxLeaf = 0; 542 543 if (!isCpuIdSupported()) 544 return VendorSignatures::UNKNOWN; 545 546 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1) 547 return VendorSignatures::UNKNOWN; 548 549 // "Genu ineI ntel" 550 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e) 551 return VendorSignatures::GENUINE_INTEL; 552 553 // "Auth enti cAMD" 554 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163) 555 return VendorSignatures::AUTHENTIC_AMD; 556 557 return VendorSignatures::UNKNOWN; 558 } 559 560 } // namespace x86 561 } // namespace detail 562 } // namespace sys 563 } // namespace llvm 564 565 using namespace llvm::sys::detail::x86; 566 567 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 568 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 569 /// return true. 570 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 571 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 572 unsigned *rEDX) { 573 #if defined(__GNUC__) || defined(__clang__) 574 #if defined(__x86_64__) 575 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 576 // FIXME: should we save this for Clang? 577 __asm__("movq\t%%rbx, %%rsi\n\t" 578 "cpuid\n\t" 579 "xchgq\t%%rbx, %%rsi\n\t" 580 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 581 : "a"(value), "c"(subleaf)); 582 return false; 583 #elif defined(__i386__) 584 __asm__("movl\t%%ebx, %%esi\n\t" 585 "cpuid\n\t" 586 "xchgl\t%%ebx, %%esi\n\t" 587 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 588 : "a"(value), "c"(subleaf)); 589 return false; 590 #else 591 return true; 592 #endif 593 #elif defined(_MSC_VER) 594 int registers[4]; 595 __cpuidex(registers, value, subleaf); 596 *rEAX = registers[0]; 597 *rEBX = registers[1]; 598 *rECX = registers[2]; 599 *rEDX = registers[3]; 600 return false; 601 #else 602 return true; 603 #endif 604 } 605 606 // Read control register 0 (XCR0). Used to detect features such as AVX. 607 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 608 #if defined(__GNUC__) || defined(__clang__) 609 // Check xgetbv; this uses a .byte sequence instead of the instruction 610 // directly because older assemblers do not include support for xgetbv and 611 // there is no easy way to conditionally compile based on the assembler used. 612 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 613 return false; 614 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 615 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 616 *rEAX = Result; 617 *rEDX = Result >> 32; 618 return false; 619 #else 620 return true; 621 #endif 622 } 623 624 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 625 unsigned *Model) { 626 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 627 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 628 if (*Family == 6 || *Family == 0xf) { 629 if (*Family == 0xf) 630 // Examine extended family ID if family ID is F. 631 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 632 // Examine extended model ID if family ID is 6 or F. 633 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 634 } 635 } 636 637 static StringRef 638 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 639 const unsigned *Features, 640 unsigned *Type, unsigned *Subtype) { 641 auto testFeature = [&](unsigned F) { 642 return (Features[F / 32] & (1U << (F % 32))) != 0; 643 }; 644 645 StringRef CPU; 646 647 switch (Family) { 648 case 3: 649 CPU = "i386"; 650 break; 651 case 4: 652 CPU = "i486"; 653 break; 654 case 5: 655 if (testFeature(X86::FEATURE_MMX)) { 656 CPU = "pentium-mmx"; 657 break; 658 } 659 CPU = "pentium"; 660 break; 661 case 6: 662 switch (Model) { 663 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 664 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 665 // mobile processor, Intel Core 2 Extreme processor, Intel 666 // Pentium Dual-Core processor, Intel Xeon processor, model 667 // 0Fh. All processors are manufactured using the 65 nm process. 668 case 0x16: // Intel Celeron processor model 16h. All processors are 669 // manufactured using the 65 nm process 670 CPU = "core2"; 671 *Type = X86::INTEL_CORE2; 672 break; 673 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 674 // 17h. All processors are manufactured using the 45 nm process. 675 // 676 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 677 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 678 // the 45 nm process. 679 CPU = "penryn"; 680 *Type = X86::INTEL_CORE2; 681 break; 682 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 683 // processors are manufactured using the 45 nm process. 684 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 685 // As found in a Summer 2010 model iMac. 686 case 0x1f: 687 case 0x2e: // Nehalem EX 688 CPU = "nehalem"; 689 *Type = X86::INTEL_COREI7; 690 *Subtype = X86::INTEL_COREI7_NEHALEM; 691 break; 692 case 0x25: // Intel Core i7, laptop version. 693 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 694 // processors are manufactured using the 32 nm process. 695 case 0x2f: // Westmere EX 696 CPU = "westmere"; 697 *Type = X86::INTEL_COREI7; 698 *Subtype = X86::INTEL_COREI7_WESTMERE; 699 break; 700 case 0x2a: // Intel Core i7 processor. All processors are manufactured 701 // using the 32 nm process. 702 case 0x2d: 703 CPU = "sandybridge"; 704 *Type = X86::INTEL_COREI7; 705 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 706 break; 707 case 0x3a: 708 case 0x3e: // Ivy Bridge EP 709 CPU = "ivybridge"; 710 *Type = X86::INTEL_COREI7; 711 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 712 break; 713 714 // Haswell: 715 case 0x3c: 716 case 0x3f: 717 case 0x45: 718 case 0x46: 719 CPU = "haswell"; 720 *Type = X86::INTEL_COREI7; 721 *Subtype = X86::INTEL_COREI7_HASWELL; 722 break; 723 724 // Broadwell: 725 case 0x3d: 726 case 0x47: 727 case 0x4f: 728 case 0x56: 729 CPU = "broadwell"; 730 *Type = X86::INTEL_COREI7; 731 *Subtype = X86::INTEL_COREI7_BROADWELL; 732 break; 733 734 // Skylake: 735 case 0x4e: // Skylake mobile 736 case 0x5e: // Skylake desktop 737 case 0x8e: // Kaby Lake mobile 738 case 0x9e: // Kaby Lake desktop 739 case 0xa5: // Comet Lake-H/S 740 case 0xa6: // Comet Lake-U 741 CPU = "skylake"; 742 *Type = X86::INTEL_COREI7; 743 *Subtype = X86::INTEL_COREI7_SKYLAKE; 744 break; 745 746 // Rocketlake: 747 case 0xa7: 748 CPU = "rocketlake"; 749 *Type = X86::INTEL_COREI7; 750 *Subtype = X86::INTEL_COREI7_ROCKETLAKE; 751 break; 752 753 // Skylake Xeon: 754 case 0x55: 755 *Type = X86::INTEL_COREI7; 756 if (testFeature(X86::FEATURE_AVX512BF16)) { 757 CPU = "cooperlake"; 758 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 759 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 760 CPU = "cascadelake"; 761 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 762 } else { 763 CPU = "skylake-avx512"; 764 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 765 } 766 break; 767 768 // Cannonlake: 769 case 0x66: 770 CPU = "cannonlake"; 771 *Type = X86::INTEL_COREI7; 772 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 773 break; 774 775 // Icelake: 776 case 0x7d: 777 case 0x7e: 778 CPU = "icelake-client"; 779 *Type = X86::INTEL_COREI7; 780 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 781 break; 782 783 // Tigerlake: 784 case 0x8c: 785 case 0x8d: 786 CPU = "tigerlake"; 787 *Type = X86::INTEL_COREI7; 788 *Subtype = X86::INTEL_COREI7_TIGERLAKE; 789 break; 790 791 // Alderlake: 792 case 0x97: 793 case 0x9a: 794 CPU = "alderlake"; 795 *Type = X86::INTEL_COREI7; 796 *Subtype = X86::INTEL_COREI7_ALDERLAKE; 797 break; 798 799 // Icelake Xeon: 800 case 0x6a: 801 case 0x6c: 802 CPU = "icelake-server"; 803 *Type = X86::INTEL_COREI7; 804 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; 805 break; 806 807 // Sapphire Rapids: 808 case 0x8f: 809 CPU = "sapphirerapids"; 810 *Type = X86::INTEL_COREI7; 811 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS; 812 break; 813 814 case 0x1c: // Most 45 nm Intel Atom processors 815 case 0x26: // 45 nm Atom Lincroft 816 case 0x27: // 32 nm Atom Medfield 817 case 0x35: // 32 nm Atom Midview 818 case 0x36: // 32 nm Atom Midview 819 CPU = "bonnell"; 820 *Type = X86::INTEL_BONNELL; 821 break; 822 823 // Atom Silvermont codes from the Intel software optimization guide. 824 case 0x37: 825 case 0x4a: 826 case 0x4d: 827 case 0x5a: 828 case 0x5d: 829 case 0x4c: // really airmont 830 CPU = "silvermont"; 831 *Type = X86::INTEL_SILVERMONT; 832 break; 833 // Goldmont: 834 case 0x5c: // Apollo Lake 835 case 0x5f: // Denverton 836 CPU = "goldmont"; 837 *Type = X86::INTEL_GOLDMONT; 838 break; 839 case 0x7a: 840 CPU = "goldmont-plus"; 841 *Type = X86::INTEL_GOLDMONT_PLUS; 842 break; 843 case 0x86: 844 CPU = "tremont"; 845 *Type = X86::INTEL_TREMONT; 846 break; 847 848 // Xeon Phi (Knights Landing + Knights Mill): 849 case 0x57: 850 CPU = "knl"; 851 *Type = X86::INTEL_KNL; 852 break; 853 case 0x85: 854 CPU = "knm"; 855 *Type = X86::INTEL_KNM; 856 break; 857 858 default: // Unknown family 6 CPU, try to guess. 859 // Don't both with Type/Subtype here, they aren't used by the caller. 860 // They're used above to keep the code in sync with compiler-rt. 861 // TODO detect tigerlake host from model 862 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 863 CPU = "tigerlake"; 864 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) { 865 CPU = "icelake-client"; 866 } else if (testFeature(X86::FEATURE_AVX512VBMI)) { 867 CPU = "cannonlake"; 868 } else if (testFeature(X86::FEATURE_AVX512BF16)) { 869 CPU = "cooperlake"; 870 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 871 CPU = "cascadelake"; 872 } else if (testFeature(X86::FEATURE_AVX512VL)) { 873 CPU = "skylake-avx512"; 874 } else if (testFeature(X86::FEATURE_AVX512ER)) { 875 CPU = "knl"; 876 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 877 if (testFeature(X86::FEATURE_SHA)) 878 CPU = "goldmont"; 879 else 880 CPU = "skylake"; 881 } else if (testFeature(X86::FEATURE_ADX)) { 882 CPU = "broadwell"; 883 } else if (testFeature(X86::FEATURE_AVX2)) { 884 CPU = "haswell"; 885 } else if (testFeature(X86::FEATURE_AVX)) { 886 CPU = "sandybridge"; 887 } else if (testFeature(X86::FEATURE_SSE4_2)) { 888 if (testFeature(X86::FEATURE_MOVBE)) 889 CPU = "silvermont"; 890 else 891 CPU = "nehalem"; 892 } else if (testFeature(X86::FEATURE_SSE4_1)) { 893 CPU = "penryn"; 894 } else if (testFeature(X86::FEATURE_SSSE3)) { 895 if (testFeature(X86::FEATURE_MOVBE)) 896 CPU = "bonnell"; 897 else 898 CPU = "core2"; 899 } else if (testFeature(X86::FEATURE_64BIT)) { 900 CPU = "core2"; 901 } else if (testFeature(X86::FEATURE_SSE3)) { 902 CPU = "yonah"; 903 } else if (testFeature(X86::FEATURE_SSE2)) { 904 CPU = "pentium-m"; 905 } else if (testFeature(X86::FEATURE_SSE)) { 906 CPU = "pentium3"; 907 } else if (testFeature(X86::FEATURE_MMX)) { 908 CPU = "pentium2"; 909 } else { 910 CPU = "pentiumpro"; 911 } 912 break; 913 } 914 break; 915 case 15: { 916 if (testFeature(X86::FEATURE_64BIT)) { 917 CPU = "nocona"; 918 break; 919 } 920 if (testFeature(X86::FEATURE_SSE3)) { 921 CPU = "prescott"; 922 break; 923 } 924 CPU = "pentium4"; 925 break; 926 } 927 default: 928 break; // Unknown. 929 } 930 931 return CPU; 932 } 933 934 static StringRef 935 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 936 const unsigned *Features, 937 unsigned *Type, unsigned *Subtype) { 938 auto testFeature = [&](unsigned F) { 939 return (Features[F / 32] & (1U << (F % 32))) != 0; 940 }; 941 942 StringRef CPU; 943 944 switch (Family) { 945 case 4: 946 CPU = "i486"; 947 break; 948 case 5: 949 CPU = "pentium"; 950 switch (Model) { 951 case 6: 952 case 7: 953 CPU = "k6"; 954 break; 955 case 8: 956 CPU = "k6-2"; 957 break; 958 case 9: 959 case 13: 960 CPU = "k6-3"; 961 break; 962 case 10: 963 CPU = "geode"; 964 break; 965 } 966 break; 967 case 6: 968 if (testFeature(X86::FEATURE_SSE)) { 969 CPU = "athlon-xp"; 970 break; 971 } 972 CPU = "athlon"; 973 break; 974 case 15: 975 if (testFeature(X86::FEATURE_SSE3)) { 976 CPU = "k8-sse3"; 977 break; 978 } 979 CPU = "k8"; 980 break; 981 case 16: 982 CPU = "amdfam10"; 983 *Type = X86::AMDFAM10H; // "amdfam10" 984 switch (Model) { 985 case 2: 986 *Subtype = X86::AMDFAM10H_BARCELONA; 987 break; 988 case 4: 989 *Subtype = X86::AMDFAM10H_SHANGHAI; 990 break; 991 case 8: 992 *Subtype = X86::AMDFAM10H_ISTANBUL; 993 break; 994 } 995 break; 996 case 20: 997 CPU = "btver1"; 998 *Type = X86::AMD_BTVER1; 999 break; 1000 case 21: 1001 CPU = "bdver1"; 1002 *Type = X86::AMDFAM15H; 1003 if (Model >= 0x60 && Model <= 0x7f) { 1004 CPU = "bdver4"; 1005 *Subtype = X86::AMDFAM15H_BDVER4; 1006 break; // 60h-7Fh: Excavator 1007 } 1008 if (Model >= 0x30 && Model <= 0x3f) { 1009 CPU = "bdver3"; 1010 *Subtype = X86::AMDFAM15H_BDVER3; 1011 break; // 30h-3Fh: Steamroller 1012 } 1013 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 1014 CPU = "bdver2"; 1015 *Subtype = X86::AMDFAM15H_BDVER2; 1016 break; // 02h, 10h-1Fh: Piledriver 1017 } 1018 if (Model <= 0x0f) { 1019 *Subtype = X86::AMDFAM15H_BDVER1; 1020 break; // 00h-0Fh: Bulldozer 1021 } 1022 break; 1023 case 22: 1024 CPU = "btver2"; 1025 *Type = X86::AMD_BTVER2; 1026 break; 1027 case 23: 1028 CPU = "znver1"; 1029 *Type = X86::AMDFAM17H; 1030 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 1031 CPU = "znver2"; 1032 *Subtype = X86::AMDFAM17H_ZNVER2; 1033 break; // 30h-3fh, 71h: Zen2 1034 } 1035 if (Model <= 0x0f) { 1036 *Subtype = X86::AMDFAM17H_ZNVER1; 1037 break; // 00h-0Fh: Zen1 1038 } 1039 break; 1040 case 25: 1041 CPU = "znver3"; 1042 *Type = X86::AMDFAM19H; 1043 if (Model <= 0x0f || Model == 0x21) { 1044 *Subtype = X86::AMDFAM19H_ZNVER3; 1045 break; // 00h-0Fh, 21h: Zen3 1046 } 1047 break; 1048 default: 1049 break; // Unknown AMD CPU. 1050 } 1051 1052 return CPU; 1053 } 1054 1055 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 1056 unsigned *Features) { 1057 unsigned EAX, EBX; 1058 1059 auto setFeature = [&](unsigned F) { 1060 Features[F / 32] |= 1U << (F % 32); 1061 }; 1062 1063 if ((EDX >> 15) & 1) 1064 setFeature(X86::FEATURE_CMOV); 1065 if ((EDX >> 23) & 1) 1066 setFeature(X86::FEATURE_MMX); 1067 if ((EDX >> 25) & 1) 1068 setFeature(X86::FEATURE_SSE); 1069 if ((EDX >> 26) & 1) 1070 setFeature(X86::FEATURE_SSE2); 1071 1072 if ((ECX >> 0) & 1) 1073 setFeature(X86::FEATURE_SSE3); 1074 if ((ECX >> 1) & 1) 1075 setFeature(X86::FEATURE_PCLMUL); 1076 if ((ECX >> 9) & 1) 1077 setFeature(X86::FEATURE_SSSE3); 1078 if ((ECX >> 12) & 1) 1079 setFeature(X86::FEATURE_FMA); 1080 if ((ECX >> 19) & 1) 1081 setFeature(X86::FEATURE_SSE4_1); 1082 if ((ECX >> 20) & 1) { 1083 setFeature(X86::FEATURE_SSE4_2); 1084 setFeature(X86::FEATURE_CRC32); 1085 } 1086 if ((ECX >> 23) & 1) 1087 setFeature(X86::FEATURE_POPCNT); 1088 if ((ECX >> 25) & 1) 1089 setFeature(X86::FEATURE_AES); 1090 1091 if ((ECX >> 22) & 1) 1092 setFeature(X86::FEATURE_MOVBE); 1093 1094 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1095 // indicates that the AVX registers will be saved and restored on context 1096 // switch, then we have full AVX support. 1097 const unsigned AVXBits = (1 << 27) | (1 << 28); 1098 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1099 ((EAX & 0x6) == 0x6); 1100 #if defined(__APPLE__) 1101 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1102 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1103 // set right now. 1104 bool HasAVX512Save = true; 1105 #else 1106 // AVX512 requires additional context to be saved by the OS. 1107 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1108 #endif 1109 1110 if (HasAVX) 1111 setFeature(X86::FEATURE_AVX); 1112 1113 bool HasLeaf7 = 1114 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1115 1116 if (HasLeaf7 && ((EBX >> 3) & 1)) 1117 setFeature(X86::FEATURE_BMI); 1118 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1119 setFeature(X86::FEATURE_AVX2); 1120 if (HasLeaf7 && ((EBX >> 8) & 1)) 1121 setFeature(X86::FEATURE_BMI2); 1122 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1123 setFeature(X86::FEATURE_AVX512F); 1124 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1125 setFeature(X86::FEATURE_AVX512DQ); 1126 if (HasLeaf7 && ((EBX >> 19) & 1)) 1127 setFeature(X86::FEATURE_ADX); 1128 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1129 setFeature(X86::FEATURE_AVX512IFMA); 1130 if (HasLeaf7 && ((EBX >> 23) & 1)) 1131 setFeature(X86::FEATURE_CLFLUSHOPT); 1132 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1133 setFeature(X86::FEATURE_AVX512PF); 1134 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1135 setFeature(X86::FEATURE_AVX512ER); 1136 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1137 setFeature(X86::FEATURE_AVX512CD); 1138 if (HasLeaf7 && ((EBX >> 29) & 1)) 1139 setFeature(X86::FEATURE_SHA); 1140 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1141 setFeature(X86::FEATURE_AVX512BW); 1142 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1143 setFeature(X86::FEATURE_AVX512VL); 1144 1145 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1146 setFeature(X86::FEATURE_AVX512VBMI); 1147 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1148 setFeature(X86::FEATURE_AVX512VBMI2); 1149 if (HasLeaf7 && ((ECX >> 8) & 1)) 1150 setFeature(X86::FEATURE_GFNI); 1151 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1152 setFeature(X86::FEATURE_VPCLMULQDQ); 1153 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1154 setFeature(X86::FEATURE_AVX512VNNI); 1155 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1156 setFeature(X86::FEATURE_AVX512BITALG); 1157 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1158 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1159 1160 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1161 setFeature(X86::FEATURE_AVX5124VNNIW); 1162 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1163 setFeature(X86::FEATURE_AVX5124FMAPS); 1164 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1165 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1166 1167 bool HasLeaf7Subleaf1 = 1168 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1169 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1170 setFeature(X86::FEATURE_AVX512BF16); 1171 1172 unsigned MaxExtLevel; 1173 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1174 1175 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1176 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1177 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1178 setFeature(X86::FEATURE_SSE4_A); 1179 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1180 setFeature(X86::FEATURE_XOP); 1181 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1182 setFeature(X86::FEATURE_FMA4); 1183 1184 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1185 setFeature(X86::FEATURE_64BIT); 1186 } 1187 1188 StringRef sys::getHostCPUName() { 1189 unsigned MaxLeaf = 0; 1190 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf); 1191 if (Vendor == VendorSignatures::UNKNOWN) 1192 return "generic"; 1193 1194 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1195 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1196 1197 unsigned Family = 0, Model = 0; 1198 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1199 detectX86FamilyModel(EAX, &Family, &Model); 1200 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1201 1202 // These aren't consumed in this file, but we try to keep some source code the 1203 // same or similar to compiler-rt. 1204 unsigned Type = 0; 1205 unsigned Subtype = 0; 1206 1207 StringRef CPU; 1208 1209 if (Vendor == VendorSignatures::GENUINE_INTEL) { 1210 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, 1211 &Subtype); 1212 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) { 1213 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, 1214 &Subtype); 1215 } 1216 1217 if (!CPU.empty()) 1218 return CPU; 1219 1220 return "generic"; 1221 } 1222 1223 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1224 StringRef sys::getHostCPUName() { 1225 host_basic_info_data_t hostInfo; 1226 mach_msg_type_number_t infoCount; 1227 1228 infoCount = HOST_BASIC_INFO_COUNT; 1229 mach_port_t hostPort = mach_host_self(); 1230 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1231 &infoCount); 1232 mach_port_deallocate(mach_task_self(), hostPort); 1233 1234 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1235 return "generic"; 1236 1237 switch (hostInfo.cpu_subtype) { 1238 case CPU_SUBTYPE_POWERPC_601: 1239 return "601"; 1240 case CPU_SUBTYPE_POWERPC_602: 1241 return "602"; 1242 case CPU_SUBTYPE_POWERPC_603: 1243 return "603"; 1244 case CPU_SUBTYPE_POWERPC_603e: 1245 return "603e"; 1246 case CPU_SUBTYPE_POWERPC_603ev: 1247 return "603ev"; 1248 case CPU_SUBTYPE_POWERPC_604: 1249 return "604"; 1250 case CPU_SUBTYPE_POWERPC_604e: 1251 return "604e"; 1252 case CPU_SUBTYPE_POWERPC_620: 1253 return "620"; 1254 case CPU_SUBTYPE_POWERPC_750: 1255 return "750"; 1256 case CPU_SUBTYPE_POWERPC_7400: 1257 return "7400"; 1258 case CPU_SUBTYPE_POWERPC_7450: 1259 return "7450"; 1260 case CPU_SUBTYPE_POWERPC_970: 1261 return "970"; 1262 default:; 1263 } 1264 1265 return "generic"; 1266 } 1267 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1268 StringRef sys::getHostCPUName() { 1269 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1270 StringRef Content = P ? P->getBuffer() : ""; 1271 return detail::getHostCPUNameForPowerPC(Content); 1272 } 1273 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1274 StringRef sys::getHostCPUName() { 1275 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1276 StringRef Content = P ? P->getBuffer() : ""; 1277 return detail::getHostCPUNameForARM(Content); 1278 } 1279 #elif defined(__linux__) && defined(__s390x__) 1280 StringRef sys::getHostCPUName() { 1281 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1282 StringRef Content = P ? P->getBuffer() : ""; 1283 return detail::getHostCPUNameForS390x(Content); 1284 } 1285 #elif defined(__MVS__) 1286 StringRef sys::getHostCPUName() { 1287 // Get pointer to Communications Vector Table (CVT). 1288 // The pointer is located at offset 16 of the Prefixed Save Area (PSA). 1289 // It is stored as 31 bit pointer and will be zero-extended to 64 bit. 1290 int *StartToCVTOffset = reinterpret_cast<int *>(0x10); 1291 // Since its stored as a 31-bit pointer, get the 4 bytes from the start 1292 // of address. 1293 int ReadValue = *StartToCVTOffset; 1294 // Explicitly clear the high order bit. 1295 ReadValue = (ReadValue & 0x7FFFFFFF); 1296 char *CVT = reinterpret_cast<char *>(ReadValue); 1297 // The model number is located in the CVT prefix at offset -6 and stored as 1298 // signless packed decimal. 1299 uint16_t Id = *(uint16_t *)&CVT[-6]; 1300 // Convert number to integer. 1301 Id = decodePackedBCD<uint16_t>(Id, false); 1302 // Check for vector support. It's stored in field CVTFLAG5 (offset 244), 1303 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector 1304 // extension can only be used if bit CVTVEF is on. 1305 bool HaveVectorSupport = CVT[244] & 0x80; 1306 return getCPUNameFromS390Model(Id, HaveVectorSupport); 1307 } 1308 #elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) 1309 #define CPUFAMILY_ARM_SWIFT 0x1e2d6381 1310 #define CPUFAMILY_ARM_CYCLONE 0x37a09642 1311 #define CPUFAMILY_ARM_TYPHOON 0x2c91a47e 1312 #define CPUFAMILY_ARM_TWISTER 0x92fb37c8 1313 #define CPUFAMILY_ARM_HURRICANE 0x67ceee93 1314 #define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6 1315 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f 1316 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2 1317 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3 1318 1319 StringRef sys::getHostCPUName() { 1320 uint32_t Family; 1321 size_t Length = sizeof(Family); 1322 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0); 1323 1324 switch (Family) { 1325 case CPUFAMILY_ARM_SWIFT: 1326 return "swift"; 1327 case CPUFAMILY_ARM_CYCLONE: 1328 return "apple-a7"; 1329 case CPUFAMILY_ARM_TYPHOON: 1330 return "apple-a8"; 1331 case CPUFAMILY_ARM_TWISTER: 1332 return "apple-a9"; 1333 case CPUFAMILY_ARM_HURRICANE: 1334 return "apple-a10"; 1335 case CPUFAMILY_ARM_MONSOON_MISTRAL: 1336 return "apple-a11"; 1337 case CPUFAMILY_ARM_VORTEX_TEMPEST: 1338 return "apple-a12"; 1339 case CPUFAMILY_ARM_LIGHTNING_THUNDER: 1340 return "apple-a13"; 1341 case CPUFAMILY_ARM_FIRESTORM_ICESTORM: 1342 return "apple-m1"; 1343 default: 1344 // Default to the newest CPU we know about. 1345 return "apple-m1"; 1346 } 1347 } 1348 #elif defined(_AIX) 1349 StringRef sys::getHostCPUName() { 1350 switch (_system_configuration.implementation) { 1351 case POWER_4: 1352 if (_system_configuration.version == PV_4_3) 1353 return "970"; 1354 return "pwr4"; 1355 case POWER_5: 1356 if (_system_configuration.version == PV_5) 1357 return "pwr5"; 1358 return "pwr5x"; 1359 case POWER_6: 1360 if (_system_configuration.version == PV_6_Compat) 1361 return "pwr6"; 1362 return "pwr6x"; 1363 case POWER_7: 1364 return "pwr7"; 1365 case POWER_8: 1366 return "pwr8"; 1367 case POWER_9: 1368 return "pwr9"; 1369 // TODO: simplify this once the macro is available in all OS levels. 1370 #ifdef POWER_10 1371 case POWER_10: 1372 #else 1373 case 0x40000: 1374 #endif 1375 return "pwr10"; 1376 default: 1377 return "generic"; 1378 } 1379 } 1380 #elif defined(__riscv) 1381 StringRef sys::getHostCPUName() { 1382 #if __riscv_xlen == 64 1383 return "generic-rv64"; 1384 #elif __riscv_xlen == 32 1385 return "generic-rv32"; 1386 #else 1387 #error "Unhandled value of __riscv_xlen" 1388 #endif 1389 } 1390 #else 1391 StringRef sys::getHostCPUName() { return "generic"; } 1392 namespace llvm { 1393 namespace sys { 1394 namespace detail { 1395 namespace x86 { 1396 1397 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 1398 return VendorSignatures::UNKNOWN; 1399 } 1400 1401 } // namespace x86 1402 } // namespace detail 1403 } // namespace sys 1404 } // namespace llvm 1405 #endif 1406 1407 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1408 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1409 // using the number of unique physical/core id pairs. The following 1410 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1411 int computeHostNumPhysicalCores() { 1412 // Enabled represents the number of physical id/core id pairs with at least 1413 // one processor id enabled by the CPU affinity mask. 1414 cpu_set_t Affinity, Enabled; 1415 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1416 return -1; 1417 CPU_ZERO(&Enabled); 1418 1419 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1420 // mmapped because it appears to have 0 size. 1421 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1422 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1423 if (std::error_code EC = Text.getError()) { 1424 llvm::errs() << "Can't read " 1425 << "/proc/cpuinfo: " << EC.message() << "\n"; 1426 return -1; 1427 } 1428 SmallVector<StringRef, 8> strs; 1429 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1430 /*KeepEmpty=*/false); 1431 int CurProcessor = -1; 1432 int CurPhysicalId = -1; 1433 int CurSiblings = -1; 1434 int CurCoreId = -1; 1435 for (StringRef Line : strs) { 1436 std::pair<StringRef, StringRef> Data = Line.split(':'); 1437 auto Name = Data.first.trim(); 1438 auto Val = Data.second.trim(); 1439 // These fields are available if the kernel is configured with CONFIG_SMP. 1440 if (Name == "processor") 1441 Val.getAsInteger(10, CurProcessor); 1442 else if (Name == "physical id") 1443 Val.getAsInteger(10, CurPhysicalId); 1444 else if (Name == "siblings") 1445 Val.getAsInteger(10, CurSiblings); 1446 else if (Name == "core id") { 1447 Val.getAsInteger(10, CurCoreId); 1448 // The processor id corresponds to an index into cpu_set_t. 1449 if (CPU_ISSET(CurProcessor, &Affinity)) 1450 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1451 } 1452 } 1453 return CPU_COUNT(&Enabled); 1454 } 1455 #elif defined(__linux__) && defined(__powerpc__) 1456 int computeHostNumPhysicalCores() { 1457 cpu_set_t Affinity; 1458 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0) 1459 return CPU_COUNT(&Affinity); 1460 1461 // The call to sched_getaffinity() may have failed because the Affinity 1462 // mask is too small for the number of CPU's on the system (i.e. the 1463 // system has more than 1024 CPUs). Allocate a mask large enough for 1464 // twice as many CPUs. 1465 cpu_set_t *DynAffinity; 1466 DynAffinity = CPU_ALLOC(2048); 1467 if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) { 1468 int NumCPUs = CPU_COUNT(DynAffinity); 1469 CPU_FREE(DynAffinity); 1470 return NumCPUs; 1471 } 1472 return -1; 1473 } 1474 #elif defined(__linux__) && defined(__s390x__) 1475 int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); } 1476 #elif defined(__APPLE__) 1477 // Gets the number of *physical cores* on the machine. 1478 int computeHostNumPhysicalCores() { 1479 uint32_t count; 1480 size_t len = sizeof(count); 1481 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1482 if (count < 1) { 1483 int nm[2]; 1484 nm[0] = CTL_HW; 1485 nm[1] = HW_AVAILCPU; 1486 sysctl(nm, 2, &count, &len, NULL, 0); 1487 if (count < 1) 1488 return -1; 1489 } 1490 return count; 1491 } 1492 #elif defined(__MVS__) 1493 int computeHostNumPhysicalCores() { 1494 enum { 1495 // Byte offset of the pointer to the Communications Vector Table (CVT) in 1496 // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and 1497 // will be zero-extended to uintptr_t. 1498 FLCCVT = 16, 1499 // Byte offset of the pointer to the Common System Data Area (CSD) in the 1500 // CVT. The table entry is a 31-bit pointer and will be zero-extended to 1501 // uintptr_t. 1502 CVTCSD = 660, 1503 // Byte offset to the number of live CPs in the LPAR, stored as a signed 1504 // 32-bit value in the table. 1505 CSD_NUMBER_ONLINE_STANDARD_CPS = 264, 1506 }; 1507 char *PSA = 0; 1508 char *CVT = reinterpret_cast<char *>( 1509 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT]))); 1510 char *CSD = reinterpret_cast<char *>( 1511 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD]))); 1512 return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]); 1513 } 1514 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1515 // Defined in llvm/lib/Support/Windows/Threading.inc 1516 int computeHostNumPhysicalCores(); 1517 #else 1518 // On other systems, return -1 to indicate unknown. 1519 static int computeHostNumPhysicalCores() { return -1; } 1520 #endif 1521 1522 int sys::getHostNumPhysicalCores() { 1523 static int NumCores = computeHostNumPhysicalCores(); 1524 return NumCores; 1525 } 1526 1527 #if defined(__i386__) || defined(_M_IX86) || \ 1528 defined(__x86_64__) || defined(_M_X64) 1529 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1530 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1531 unsigned MaxLevel; 1532 1533 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) 1534 return false; 1535 1536 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1537 1538 Features["cx8"] = (EDX >> 8) & 1; 1539 Features["cmov"] = (EDX >> 15) & 1; 1540 Features["mmx"] = (EDX >> 23) & 1; 1541 Features["fxsr"] = (EDX >> 24) & 1; 1542 Features["sse"] = (EDX >> 25) & 1; 1543 Features["sse2"] = (EDX >> 26) & 1; 1544 1545 Features["sse3"] = (ECX >> 0) & 1; 1546 Features["pclmul"] = (ECX >> 1) & 1; 1547 Features["ssse3"] = (ECX >> 9) & 1; 1548 Features["cx16"] = (ECX >> 13) & 1; 1549 Features["sse4.1"] = (ECX >> 19) & 1; 1550 Features["sse4.2"] = (ECX >> 20) & 1; 1551 Features["crc32"] = Features["sse4.2"]; 1552 Features["movbe"] = (ECX >> 22) & 1; 1553 Features["popcnt"] = (ECX >> 23) & 1; 1554 Features["aes"] = (ECX >> 25) & 1; 1555 Features["rdrnd"] = (ECX >> 30) & 1; 1556 1557 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1558 // indicates that the AVX registers will be saved and restored on context 1559 // switch, then we have full AVX support. 1560 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX); 1561 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); 1562 #if defined(__APPLE__) 1563 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1564 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1565 // set right now. 1566 bool HasAVX512Save = true; 1567 #else 1568 // AVX512 requires additional context to be saved by the OS. 1569 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1570 #endif 1571 // AMX requires additional context to be saved by the OS. 1572 const unsigned AMXBits = (1 << 17) | (1 << 18); 1573 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits); 1574 1575 Features["avx"] = HasAVXSave; 1576 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1577 // Only enable XSAVE if OS has enabled support for saving YMM state. 1578 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1579 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1580 1581 unsigned MaxExtLevel; 1582 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1583 1584 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1585 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1586 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1587 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1588 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1589 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1590 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1591 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1592 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1593 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1594 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1595 1596 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1597 1598 // Miscellaneous memory related features, detected by 1599 // using the 0x80000008 leaf of the CPUID instruction 1600 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1601 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1602 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1603 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1604 1605 bool HasLeaf7 = 1606 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1607 1608 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1609 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1610 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1611 // AVX2 is only supported if we have the OS save support from AVX. 1612 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1613 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1614 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1615 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1616 // AVX512 is only supported if the OS supports the context save for it. 1617 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1618 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1619 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1620 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1621 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1622 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1623 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1624 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1625 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1626 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1627 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1628 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1629 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1630 1631 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1632 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1633 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1634 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1635 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1636 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1637 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1638 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1639 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1640 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1641 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1642 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1643 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1644 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker 1645 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1646 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1647 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1648 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1649 1650 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1); 1651 Features["avx512vp2intersect"] = 1652 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1653 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1654 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1655 // There are two CPUID leafs which information associated with the pconfig 1656 // instruction: 1657 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1658 // bit of EDX), while the EAX=0x1b leaf returns information on the 1659 // availability of specific pconfig leafs. 1660 // The target feature here only refers to the the first of these two. 1661 // Users might need to check for the availability of specific pconfig 1662 // leaves using cpuid, since that information is ignored while 1663 // detecting features using the "-march=native" flag. 1664 // For more info, see X86 ISA docs. 1665 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1666 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave; 1667 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save; 1668 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; 1669 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; 1670 bool HasLeaf7Subleaf1 = 1671 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1672 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; 1673 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1674 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1); 1675 1676 bool HasLeafD = MaxLevel >= 0xd && 1677 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1678 1679 // Only enable XSAVE if OS has enabled support for saving YMM state. 1680 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1681 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1682 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1683 1684 bool HasLeaf14 = MaxLevel >= 0x14 && 1685 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1686 1687 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1688 1689 bool HasLeaf19 = 1690 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); 1691 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1); 1692 1693 return true; 1694 } 1695 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1696 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1697 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1698 if (!P) 1699 return false; 1700 1701 SmallVector<StringRef, 32> Lines; 1702 P->getBuffer().split(Lines, "\n"); 1703 1704 SmallVector<StringRef, 32> CPUFeatures; 1705 1706 // Look for the CPU features. 1707 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1708 if (Lines[I].startswith("Features")) { 1709 Lines[I].split(CPUFeatures, ' '); 1710 break; 1711 } 1712 1713 #if defined(__aarch64__) 1714 // Keep track of which crypto features we have seen 1715 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1716 uint32_t crypto = 0; 1717 #endif 1718 1719 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1720 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1721 #if defined(__aarch64__) 1722 .Case("asimd", "neon") 1723 .Case("fp", "fp-armv8") 1724 .Case("crc32", "crc") 1725 .Case("atomics", "lse") 1726 .Case("sve", "sve") 1727 .Case("sve2", "sve2") 1728 #else 1729 .Case("half", "fp16") 1730 .Case("neon", "neon") 1731 .Case("vfpv3", "vfp3") 1732 .Case("vfpv3d16", "d16") 1733 .Case("vfpv4", "vfp4") 1734 .Case("idiva", "hwdiv-arm") 1735 .Case("idivt", "hwdiv") 1736 #endif 1737 .Default(""); 1738 1739 #if defined(__aarch64__) 1740 // We need to check crypto separately since we need all of the crypto 1741 // extensions to enable the subtarget feature 1742 if (CPUFeatures[I] == "aes") 1743 crypto |= CAP_AES; 1744 else if (CPUFeatures[I] == "pmull") 1745 crypto |= CAP_PMULL; 1746 else if (CPUFeatures[I] == "sha1") 1747 crypto |= CAP_SHA1; 1748 else if (CPUFeatures[I] == "sha2") 1749 crypto |= CAP_SHA2; 1750 #endif 1751 1752 if (LLVMFeatureStr != "") 1753 Features[LLVMFeatureStr] = true; 1754 } 1755 1756 #if defined(__aarch64__) 1757 // If we have all crypto bits we can add the feature 1758 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1759 Features["crypto"] = true; 1760 #endif 1761 1762 return true; 1763 } 1764 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1765 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1766 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1767 Features["neon"] = true; 1768 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1769 Features["crc"] = true; 1770 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1771 Features["crypto"] = true; 1772 1773 return true; 1774 } 1775 #else 1776 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1777 #endif 1778 1779 std::string sys::getProcessTriple() { 1780 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1781 Triple PT(Triple::normalize(TargetTripleString)); 1782 1783 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1784 PT = PT.get64BitArchVariant(); 1785 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1786 PT = PT.get32BitArchVariant(); 1787 1788 return PT.str(); 1789 } 1790