1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This header file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/Config/config.h" 16 #include <string.h> 17 18 // Include the platform-specific parts of this class. 19 #ifdef LLVM_ON_UNIX 20 #include "Unix/Host.inc" 21 #endif 22 #ifdef LLVM_ON_WIN32 23 #include "Windows/Host.inc" 24 #endif 25 #ifdef _MSC_VER 26 #include <intrin.h> 27 #endif 28 29 //===----------------------------------------------------------------------===// 30 // 31 // Implementations of the CPU detection routines 32 // 33 //===----------------------------------------------------------------------===// 34 35 using namespace llvm; 36 37 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ 38 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 39 40 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 41 /// specified arguments. If we can't run cpuid on the host, return true. 42 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, 43 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 44 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 45 #if defined(__GNUC__) 46 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 47 asm ("movq\t%%rbx, %%rsi\n\t" 48 "cpuid\n\t" 49 "xchgq\t%%rbx, %%rsi\n\t" 50 : "=a" (*rEAX), 51 "=S" (*rEBX), 52 "=c" (*rECX), 53 "=d" (*rEDX) 54 : "a" (value)); 55 return false; 56 #elif defined(_MSC_VER) 57 int registers[4]; 58 __cpuid(registers, value); 59 *rEAX = registers[0]; 60 *rEBX = registers[1]; 61 *rECX = registers[2]; 62 *rEDX = registers[3]; 63 return false; 64 #else 65 return true; 66 #endif 67 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 68 #if defined(__GNUC__) 69 asm ("movl\t%%ebx, %%esi\n\t" 70 "cpuid\n\t" 71 "xchgl\t%%ebx, %%esi\n\t" 72 : "=a" (*rEAX), 73 "=S" (*rEBX), 74 "=c" (*rECX), 75 "=d" (*rEDX) 76 : "a" (value)); 77 return false; 78 #elif defined(_MSC_VER) 79 __asm { 80 mov eax,value 81 cpuid 82 mov esi,rEAX 83 mov dword ptr [esi],eax 84 mov esi,rEBX 85 mov dword ptr [esi],ebx 86 mov esi,rECX 87 mov dword ptr [esi],ecx 88 mov esi,rEDX 89 mov dword ptr [esi],edx 90 } 91 return false; 92 // pedantic #else returns to appease -Wunreachable-code (so we don't generate 93 // postprocessed code that looks like "return true; return false;") 94 #else 95 return true; 96 #endif 97 #else 98 return true; 99 #endif 100 } 101 102 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, 103 unsigned &Model) { 104 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 105 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 106 if (Family == 6 || Family == 0xf) { 107 if (Family == 0xf) 108 // Examine extended family ID if family ID is F. 109 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 110 // Examine extended model ID if family ID is 6 or F. 111 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 112 } 113 } 114 115 std::string sys::getHostCPUName() { 116 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 117 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 118 return "generic"; 119 unsigned Family = 0; 120 unsigned Model = 0; 121 DetectX86FamilyModel(EAX, Family, Model); 122 123 bool HasSSE3 = (ECX & 0x1); 124 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 125 bool Em64T = (EDX >> 29) & 0x1; 126 127 union { 128 unsigned u[3]; 129 char c[12]; 130 } text; 131 132 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1); 133 if (memcmp(text.c, "GenuineIntel", 12) == 0) { 134 switch (Family) { 135 case 3: 136 return "i386"; 137 case 4: 138 switch (Model) { 139 case 0: // Intel486 DX processors 140 case 1: // Intel486 DX processors 141 case 2: // Intel486 SX processors 142 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 143 // IntelDX2 processors 144 case 4: // Intel486 SL processor 145 case 5: // IntelSX2 processors 146 case 7: // Write-Back Enhanced IntelDX2 processors 147 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 148 default: return "i486"; 149 } 150 case 5: 151 switch (Model) { 152 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 153 // Pentium processors (60, 66) 154 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 155 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 156 // 150, 166, 200) 157 case 3: // Pentium OverDrive processors for Intel486 processor-based 158 // systems 159 return "pentium"; 160 161 case 4: // Pentium OverDrive processor with MMX technology for Pentium 162 // processor (75, 90, 100, 120, 133), Pentium processor with 163 // MMX technology (166, 200) 164 return "pentium-mmx"; 165 166 default: return "pentium"; 167 } 168 case 6: 169 switch (Model) { 170 case 1: // Pentium Pro processor 171 return "pentiumpro"; 172 173 case 3: // Intel Pentium II OverDrive processor, Pentium II processor, 174 // model 03 175 case 5: // Pentium II processor, model 05, Pentium II Xeon processor, 176 // model 05, and Intel Celeron processor, model 05 177 case 6: // Celeron processor, model 06 178 return "pentium2"; 179 180 case 7: // Pentium III processor, model 07, and Pentium III Xeon 181 // processor, model 07 182 case 8: // Pentium III processor, model 08, Pentium III Xeon processor, 183 // model 08, and Celeron processor, model 08 184 case 10: // Pentium III Xeon processor, model 0Ah 185 case 11: // Pentium III processor, model 0Bh 186 return "pentium3"; 187 188 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09. 189 case 13: // Intel Pentium M processor, Intel Celeron M processor, model 190 // 0Dh. All processors are manufactured using the 90 nm process. 191 return "pentium-m"; 192 193 case 14: // Intel Core Duo processor, Intel Core Solo processor, model 194 // 0Eh. All processors are manufactured using the 65 nm process. 195 return "yonah"; 196 197 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 198 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 199 // mobile processor, Intel Core 2 Extreme processor, Intel 200 // Pentium Dual-Core processor, Intel Xeon processor, model 201 // 0Fh. All processors are manufactured using the 65 nm process. 202 case 22: // Intel Celeron processor model 16h. All processors are 203 // manufactured using the 65 nm process 204 return "core2"; 205 206 case 21: // Intel EP80579 Integrated Processor and Intel EP80579 207 // Integrated Processor with Intel QuickAssist Technology 208 return "i686"; // FIXME: ??? 209 210 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model 211 // 17h. All processors are manufactured using the 45 nm process. 212 // 213 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 214 return "penryn"; 215 216 case 26: // Intel Core i7 processor and Intel Xeon processor. All 217 // processors are manufactured using the 45 nm process. 218 case 29: // Intel Xeon processor MP. All processors are manufactured using 219 // the 45 nm process. 220 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 221 // As found in a Summer 2010 model iMac. 222 case 37: // Intel Core i7, laptop version. 223 case 44: // Intel Core i7 processor and Intel Xeon processor. All 224 // processors are manufactured using the 32 nm process. 225 return "corei7"; 226 227 // SandyBridge: 228 case 42: // Intel Core i7 processor. All processors are manufactured 229 // using the 32 nm process. 230 case 45: 231 return "corei7-avx"; 232 233 // Ivy Bridge: 234 case 58: 235 return "core-avx-i"; 236 237 case 28: // Intel Atom processor. All processors are manufactured using 238 // the 45 nm process 239 return "atom"; 240 241 default: return "i686"; 242 } 243 case 15: { 244 switch (Model) { 245 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 246 // model 00h and manufactured using the 0.18 micron process. 247 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 248 // processor MP, and Intel Celeron processor. All processors are 249 // model 01h and manufactured using the 0.18 micron process. 250 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 251 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 252 // processor, and Mobile Intel Celeron processor. All processors 253 // are model 02h and manufactured using the 0.13 micron process. 254 return (Em64T) ? "x86-64" : "pentium4"; 255 256 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 257 // processor. All processors are model 03h and manufactured using 258 // the 90 nm process. 259 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 260 // Pentium D processor, Intel Xeon processor, Intel Xeon 261 // processor MP, Intel Celeron D processor. All processors are 262 // model 04h and manufactured using the 90 nm process. 263 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 264 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 265 // MP, Intel Celeron D processor. All processors are model 06h 266 // and manufactured using the 65 nm process. 267 return (Em64T) ? "nocona" : "prescott"; 268 269 default: 270 return (Em64T) ? "x86-64" : "pentium4"; 271 } 272 } 273 274 default: 275 return "generic"; 276 } 277 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) { 278 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 279 // appears to be no way to generate the wide variety of AMD-specific targets 280 // from the information returned from CPUID. 281 switch (Family) { 282 case 4: 283 return "i486"; 284 case 5: 285 switch (Model) { 286 case 6: 287 case 7: return "k6"; 288 case 8: return "k6-2"; 289 case 9: 290 case 13: return "k6-3"; 291 default: return "pentium"; 292 } 293 case 6: 294 switch (Model) { 295 case 4: return "athlon-tbird"; 296 case 6: 297 case 7: 298 case 8: return "athlon-mp"; 299 case 10: return "athlon-xp"; 300 default: return "athlon"; 301 } 302 case 15: 303 if (HasSSE3) 304 return "k8-sse3"; 305 switch (Model) { 306 case 1: return "opteron"; 307 case 5: return "athlon-fx"; // also opteron 308 default: return "athlon64"; 309 } 310 case 16: 311 return "amdfam10"; 312 case 20: 313 return "btver1"; 314 case 21: 315 return "bdver1"; 316 default: 317 return "generic"; 318 } 319 } 320 return "generic"; 321 } 322 #else 323 std::string sys::getHostCPUName() { 324 return "generic"; 325 } 326 #endif 327 328 bool sys::getHostCPUFeatures(StringMap<bool> &Features){ 329 return false; 330 } 331