1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/MC/MCAsmInfo.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/Target/TargetData.h" 18 #include "llvm/Target/TargetLoweringObjectFile.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include "llvm/Target/TargetRegisterInfo.h" 21 #include "llvm/GlobalVariable.h" 22 #include "llvm/DerivedTypes.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineJumpTableInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/SelectionDAG.h" 27 #include "llvm/ADT/STLExtras.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/MathExtras.h" 30 using namespace llvm; 31 32 namespace llvm { 33 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 34 bool isLocal = GV->hasLocalLinkage(); 35 bool isDeclaration = GV->isDeclaration(); 36 // FIXME: what should we do for protected and internal visibility? 37 // For variables, is internal different from hidden? 38 bool isHidden = GV->hasHiddenVisibility(); 39 40 if (reloc == Reloc::PIC_) { 41 if (isLocal || isHidden) 42 return TLSModel::LocalDynamic; 43 else 44 return TLSModel::GeneralDynamic; 45 } else { 46 if (!isDeclaration || isHidden) 47 return TLSModel::LocalExec; 48 else 49 return TLSModel::InitialExec; 50 } 51 } 52 } 53 54 /// InitLibcallNames - Set default libcall names. 55 /// 56 static void InitLibcallNames(const char **Names) { 57 Names[RTLIB::SHL_I16] = "__ashlhi3"; 58 Names[RTLIB::SHL_I32] = "__ashlsi3"; 59 Names[RTLIB::SHL_I64] = "__ashldi3"; 60 Names[RTLIB::SHL_I128] = "__ashlti3"; 61 Names[RTLIB::SRL_I16] = "__lshrhi3"; 62 Names[RTLIB::SRL_I32] = "__lshrsi3"; 63 Names[RTLIB::SRL_I64] = "__lshrdi3"; 64 Names[RTLIB::SRL_I128] = "__lshrti3"; 65 Names[RTLIB::SRA_I16] = "__ashrhi3"; 66 Names[RTLIB::SRA_I32] = "__ashrsi3"; 67 Names[RTLIB::SRA_I64] = "__ashrdi3"; 68 Names[RTLIB::SRA_I128] = "__ashrti3"; 69 Names[RTLIB::MUL_I8] = "__mulqi3"; 70 Names[RTLIB::MUL_I16] = "__mulhi3"; 71 Names[RTLIB::MUL_I32] = "__mulsi3"; 72 Names[RTLIB::MUL_I64] = "__muldi3"; 73 Names[RTLIB::MUL_I128] = "__multi3"; 74 Names[RTLIB::SDIV_I8] = "__divqi3"; 75 Names[RTLIB::SDIV_I16] = "__divhi3"; 76 Names[RTLIB::SDIV_I32] = "__divsi3"; 77 Names[RTLIB::SDIV_I64] = "__divdi3"; 78 Names[RTLIB::SDIV_I128] = "__divti3"; 79 Names[RTLIB::UDIV_I8] = "__udivqi3"; 80 Names[RTLIB::UDIV_I16] = "__udivhi3"; 81 Names[RTLIB::UDIV_I32] = "__udivsi3"; 82 Names[RTLIB::UDIV_I64] = "__udivdi3"; 83 Names[RTLIB::UDIV_I128] = "__udivti3"; 84 Names[RTLIB::SREM_I8] = "__modqi3"; 85 Names[RTLIB::SREM_I16] = "__modhi3"; 86 Names[RTLIB::SREM_I32] = "__modsi3"; 87 Names[RTLIB::SREM_I64] = "__moddi3"; 88 Names[RTLIB::SREM_I128] = "__modti3"; 89 Names[RTLIB::UREM_I8] = "__umodqi3"; 90 Names[RTLIB::UREM_I16] = "__umodhi3"; 91 Names[RTLIB::UREM_I32] = "__umodsi3"; 92 Names[RTLIB::UREM_I64] = "__umoddi3"; 93 Names[RTLIB::UREM_I128] = "__umodti3"; 94 Names[RTLIB::NEG_I32] = "__negsi2"; 95 Names[RTLIB::NEG_I64] = "__negdi2"; 96 Names[RTLIB::ADD_F32] = "__addsf3"; 97 Names[RTLIB::ADD_F64] = "__adddf3"; 98 Names[RTLIB::ADD_F80] = "__addxf3"; 99 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 100 Names[RTLIB::SUB_F32] = "__subsf3"; 101 Names[RTLIB::SUB_F64] = "__subdf3"; 102 Names[RTLIB::SUB_F80] = "__subxf3"; 103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 104 Names[RTLIB::MUL_F32] = "__mulsf3"; 105 Names[RTLIB::MUL_F64] = "__muldf3"; 106 Names[RTLIB::MUL_F80] = "__mulxf3"; 107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 108 Names[RTLIB::DIV_F32] = "__divsf3"; 109 Names[RTLIB::DIV_F64] = "__divdf3"; 110 Names[RTLIB::DIV_F80] = "__divxf3"; 111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 112 Names[RTLIB::REM_F32] = "fmodf"; 113 Names[RTLIB::REM_F64] = "fmod"; 114 Names[RTLIB::REM_F80] = "fmodl"; 115 Names[RTLIB::REM_PPCF128] = "fmodl"; 116 Names[RTLIB::POWI_F32] = "__powisf2"; 117 Names[RTLIB::POWI_F64] = "__powidf2"; 118 Names[RTLIB::POWI_F80] = "__powixf2"; 119 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 120 Names[RTLIB::SQRT_F32] = "sqrtf"; 121 Names[RTLIB::SQRT_F64] = "sqrt"; 122 Names[RTLIB::SQRT_F80] = "sqrtl"; 123 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 124 Names[RTLIB::LOG_F32] = "logf"; 125 Names[RTLIB::LOG_F64] = "log"; 126 Names[RTLIB::LOG_F80] = "logl"; 127 Names[RTLIB::LOG_PPCF128] = "logl"; 128 Names[RTLIB::LOG2_F32] = "log2f"; 129 Names[RTLIB::LOG2_F64] = "log2"; 130 Names[RTLIB::LOG2_F80] = "log2l"; 131 Names[RTLIB::LOG2_PPCF128] = "log2l"; 132 Names[RTLIB::LOG10_F32] = "log10f"; 133 Names[RTLIB::LOG10_F64] = "log10"; 134 Names[RTLIB::LOG10_F80] = "log10l"; 135 Names[RTLIB::LOG10_PPCF128] = "log10l"; 136 Names[RTLIB::EXP_F32] = "expf"; 137 Names[RTLIB::EXP_F64] = "exp"; 138 Names[RTLIB::EXP_F80] = "expl"; 139 Names[RTLIB::EXP_PPCF128] = "expl"; 140 Names[RTLIB::EXP2_F32] = "exp2f"; 141 Names[RTLIB::EXP2_F64] = "exp2"; 142 Names[RTLIB::EXP2_F80] = "exp2l"; 143 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 144 Names[RTLIB::SIN_F32] = "sinf"; 145 Names[RTLIB::SIN_F64] = "sin"; 146 Names[RTLIB::SIN_F80] = "sinl"; 147 Names[RTLIB::SIN_PPCF128] = "sinl"; 148 Names[RTLIB::COS_F32] = "cosf"; 149 Names[RTLIB::COS_F64] = "cos"; 150 Names[RTLIB::COS_F80] = "cosl"; 151 Names[RTLIB::COS_PPCF128] = "cosl"; 152 Names[RTLIB::POW_F32] = "powf"; 153 Names[RTLIB::POW_F64] = "pow"; 154 Names[RTLIB::POW_F80] = "powl"; 155 Names[RTLIB::POW_PPCF128] = "powl"; 156 Names[RTLIB::CEIL_F32] = "ceilf"; 157 Names[RTLIB::CEIL_F64] = "ceil"; 158 Names[RTLIB::CEIL_F80] = "ceill"; 159 Names[RTLIB::CEIL_PPCF128] = "ceill"; 160 Names[RTLIB::TRUNC_F32] = "truncf"; 161 Names[RTLIB::TRUNC_F64] = "trunc"; 162 Names[RTLIB::TRUNC_F80] = "truncl"; 163 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 164 Names[RTLIB::RINT_F32] = "rintf"; 165 Names[RTLIB::RINT_F64] = "rint"; 166 Names[RTLIB::RINT_F80] = "rintl"; 167 Names[RTLIB::RINT_PPCF128] = "rintl"; 168 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 169 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 170 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 171 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 172 Names[RTLIB::FLOOR_F32] = "floorf"; 173 Names[RTLIB::FLOOR_F64] = "floor"; 174 Names[RTLIB::FLOOR_F80] = "floorl"; 175 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 176 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 177 Names[RTLIB::COPYSIGN_F64] = "copysign"; 178 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 179 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 180 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 181 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 182 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 183 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 184 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 185 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 186 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 187 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 188 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 189 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 190 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 191 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 192 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 193 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 194 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 195 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 196 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 197 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 198 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 199 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 200 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 201 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 202 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 204 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 205 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 206 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 207 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 208 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 209 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 210 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 211 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 212 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 213 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 214 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 215 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 216 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 217 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 218 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 220 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 221 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 222 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 223 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 224 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 225 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 226 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 227 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 228 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 229 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 230 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 231 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 232 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 233 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 234 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 235 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 236 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 237 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 238 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 239 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 240 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 241 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 242 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 243 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 244 Names[RTLIB::OEQ_F32] = "__eqsf2"; 245 Names[RTLIB::OEQ_F64] = "__eqdf2"; 246 Names[RTLIB::UNE_F32] = "__nesf2"; 247 Names[RTLIB::UNE_F64] = "__nedf2"; 248 Names[RTLIB::OGE_F32] = "__gesf2"; 249 Names[RTLIB::OGE_F64] = "__gedf2"; 250 Names[RTLIB::OLT_F32] = "__ltsf2"; 251 Names[RTLIB::OLT_F64] = "__ltdf2"; 252 Names[RTLIB::OLE_F32] = "__lesf2"; 253 Names[RTLIB::OLE_F64] = "__ledf2"; 254 Names[RTLIB::OGT_F32] = "__gtsf2"; 255 Names[RTLIB::OGT_F64] = "__gtdf2"; 256 Names[RTLIB::UO_F32] = "__unordsf2"; 257 Names[RTLIB::UO_F64] = "__unorddf2"; 258 Names[RTLIB::O_F32] = "__unordsf2"; 259 Names[RTLIB::O_F64] = "__unorddf2"; 260 Names[RTLIB::MEMCPY] = "memcpy"; 261 Names[RTLIB::MEMMOVE] = "memmove"; 262 Names[RTLIB::MEMSET] = "memset"; 263 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 264 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 268 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 272 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 273 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 276 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 277 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 280 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 281 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 284 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 285 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 288 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 289 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 292 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 293 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 296 } 297 298 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 299 /// 300 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 301 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 302 CCs[i] = CallingConv::C; 303 } 304 } 305 306 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 307 /// UNKNOWN_LIBCALL if there is none. 308 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 309 if (OpVT == MVT::f32) { 310 if (RetVT == MVT::f64) 311 return FPEXT_F32_F64; 312 } 313 314 return UNKNOWN_LIBCALL; 315 } 316 317 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 318 /// UNKNOWN_LIBCALL if there is none. 319 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 320 if (RetVT == MVT::f32) { 321 if (OpVT == MVT::f64) 322 return FPROUND_F64_F32; 323 if (OpVT == MVT::f80) 324 return FPROUND_F80_F32; 325 if (OpVT == MVT::ppcf128) 326 return FPROUND_PPCF128_F32; 327 } else if (RetVT == MVT::f64) { 328 if (OpVT == MVT::f80) 329 return FPROUND_F80_F64; 330 if (OpVT == MVT::ppcf128) 331 return FPROUND_PPCF128_F64; 332 } 333 334 return UNKNOWN_LIBCALL; 335 } 336 337 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 338 /// UNKNOWN_LIBCALL if there is none. 339 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 340 if (OpVT == MVT::f32) { 341 if (RetVT == MVT::i8) 342 return FPTOSINT_F32_I8; 343 if (RetVT == MVT::i16) 344 return FPTOSINT_F32_I16; 345 if (RetVT == MVT::i32) 346 return FPTOSINT_F32_I32; 347 if (RetVT == MVT::i64) 348 return FPTOSINT_F32_I64; 349 if (RetVT == MVT::i128) 350 return FPTOSINT_F32_I128; 351 } else if (OpVT == MVT::f64) { 352 if (RetVT == MVT::i8) 353 return FPTOSINT_F64_I8; 354 if (RetVT == MVT::i16) 355 return FPTOSINT_F64_I16; 356 if (RetVT == MVT::i32) 357 return FPTOSINT_F64_I32; 358 if (RetVT == MVT::i64) 359 return FPTOSINT_F64_I64; 360 if (RetVT == MVT::i128) 361 return FPTOSINT_F64_I128; 362 } else if (OpVT == MVT::f80) { 363 if (RetVT == MVT::i32) 364 return FPTOSINT_F80_I32; 365 if (RetVT == MVT::i64) 366 return FPTOSINT_F80_I64; 367 if (RetVT == MVT::i128) 368 return FPTOSINT_F80_I128; 369 } else if (OpVT == MVT::ppcf128) { 370 if (RetVT == MVT::i32) 371 return FPTOSINT_PPCF128_I32; 372 if (RetVT == MVT::i64) 373 return FPTOSINT_PPCF128_I64; 374 if (RetVT == MVT::i128) 375 return FPTOSINT_PPCF128_I128; 376 } 377 return UNKNOWN_LIBCALL; 378 } 379 380 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 381 /// UNKNOWN_LIBCALL if there is none. 382 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 383 if (OpVT == MVT::f32) { 384 if (RetVT == MVT::i8) 385 return FPTOUINT_F32_I8; 386 if (RetVT == MVT::i16) 387 return FPTOUINT_F32_I16; 388 if (RetVT == MVT::i32) 389 return FPTOUINT_F32_I32; 390 if (RetVT == MVT::i64) 391 return FPTOUINT_F32_I64; 392 if (RetVT == MVT::i128) 393 return FPTOUINT_F32_I128; 394 } else if (OpVT == MVT::f64) { 395 if (RetVT == MVT::i8) 396 return FPTOUINT_F64_I8; 397 if (RetVT == MVT::i16) 398 return FPTOUINT_F64_I16; 399 if (RetVT == MVT::i32) 400 return FPTOUINT_F64_I32; 401 if (RetVT == MVT::i64) 402 return FPTOUINT_F64_I64; 403 if (RetVT == MVT::i128) 404 return FPTOUINT_F64_I128; 405 } else if (OpVT == MVT::f80) { 406 if (RetVT == MVT::i32) 407 return FPTOUINT_F80_I32; 408 if (RetVT == MVT::i64) 409 return FPTOUINT_F80_I64; 410 if (RetVT == MVT::i128) 411 return FPTOUINT_F80_I128; 412 } else if (OpVT == MVT::ppcf128) { 413 if (RetVT == MVT::i32) 414 return FPTOUINT_PPCF128_I32; 415 if (RetVT == MVT::i64) 416 return FPTOUINT_PPCF128_I64; 417 if (RetVT == MVT::i128) 418 return FPTOUINT_PPCF128_I128; 419 } 420 return UNKNOWN_LIBCALL; 421 } 422 423 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 424 /// UNKNOWN_LIBCALL if there is none. 425 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 426 if (OpVT == MVT::i32) { 427 if (RetVT == MVT::f32) 428 return SINTTOFP_I32_F32; 429 else if (RetVT == MVT::f64) 430 return SINTTOFP_I32_F64; 431 else if (RetVT == MVT::f80) 432 return SINTTOFP_I32_F80; 433 else if (RetVT == MVT::ppcf128) 434 return SINTTOFP_I32_PPCF128; 435 } else if (OpVT == MVT::i64) { 436 if (RetVT == MVT::f32) 437 return SINTTOFP_I64_F32; 438 else if (RetVT == MVT::f64) 439 return SINTTOFP_I64_F64; 440 else if (RetVT == MVT::f80) 441 return SINTTOFP_I64_F80; 442 else if (RetVT == MVT::ppcf128) 443 return SINTTOFP_I64_PPCF128; 444 } else if (OpVT == MVT::i128) { 445 if (RetVT == MVT::f32) 446 return SINTTOFP_I128_F32; 447 else if (RetVT == MVT::f64) 448 return SINTTOFP_I128_F64; 449 else if (RetVT == MVT::f80) 450 return SINTTOFP_I128_F80; 451 else if (RetVT == MVT::ppcf128) 452 return SINTTOFP_I128_PPCF128; 453 } 454 return UNKNOWN_LIBCALL; 455 } 456 457 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 458 /// UNKNOWN_LIBCALL if there is none. 459 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 460 if (OpVT == MVT::i32) { 461 if (RetVT == MVT::f32) 462 return UINTTOFP_I32_F32; 463 else if (RetVT == MVT::f64) 464 return UINTTOFP_I32_F64; 465 else if (RetVT == MVT::f80) 466 return UINTTOFP_I32_F80; 467 else if (RetVT == MVT::ppcf128) 468 return UINTTOFP_I32_PPCF128; 469 } else if (OpVT == MVT::i64) { 470 if (RetVT == MVT::f32) 471 return UINTTOFP_I64_F32; 472 else if (RetVT == MVT::f64) 473 return UINTTOFP_I64_F64; 474 else if (RetVT == MVT::f80) 475 return UINTTOFP_I64_F80; 476 else if (RetVT == MVT::ppcf128) 477 return UINTTOFP_I64_PPCF128; 478 } else if (OpVT == MVT::i128) { 479 if (RetVT == MVT::f32) 480 return UINTTOFP_I128_F32; 481 else if (RetVT == MVT::f64) 482 return UINTTOFP_I128_F64; 483 else if (RetVT == MVT::f80) 484 return UINTTOFP_I128_F80; 485 else if (RetVT == MVT::ppcf128) 486 return UINTTOFP_I128_PPCF128; 487 } 488 return UNKNOWN_LIBCALL; 489 } 490 491 /// InitCmpLibcallCCs - Set default comparison libcall CC. 492 /// 493 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 494 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 495 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 496 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 497 CCs[RTLIB::UNE_F32] = ISD::SETNE; 498 CCs[RTLIB::UNE_F64] = ISD::SETNE; 499 CCs[RTLIB::OGE_F32] = ISD::SETGE; 500 CCs[RTLIB::OGE_F64] = ISD::SETGE; 501 CCs[RTLIB::OLT_F32] = ISD::SETLT; 502 CCs[RTLIB::OLT_F64] = ISD::SETLT; 503 CCs[RTLIB::OLE_F32] = ISD::SETLE; 504 CCs[RTLIB::OLE_F64] = ISD::SETLE; 505 CCs[RTLIB::OGT_F32] = ISD::SETGT; 506 CCs[RTLIB::OGT_F64] = ISD::SETGT; 507 CCs[RTLIB::UO_F32] = ISD::SETNE; 508 CCs[RTLIB::UO_F64] = ISD::SETNE; 509 CCs[RTLIB::O_F32] = ISD::SETEQ; 510 CCs[RTLIB::O_F64] = ISD::SETEQ; 511 } 512 513 /// NOTE: The constructor takes ownership of TLOF. 514 TargetLowering::TargetLowering(const TargetMachine &tm, 515 const TargetLoweringObjectFile *tlof) 516 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 517 // All operations default to being supported. 518 memset(OpActions, 0, sizeof(OpActions)); 519 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 520 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 521 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 522 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 523 524 // Set default actions for various operations. 525 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 526 // Default all indexed load / store to expand. 527 for (unsigned IM = (unsigned)ISD::PRE_INC; 528 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 529 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 530 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 531 } 532 533 // These operations default to expand. 534 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 535 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 536 } 537 538 // Most targets ignore the @llvm.prefetch intrinsic. 539 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 540 541 // ConstantFP nodes default to expand. Targets can either change this to 542 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 543 // to optimize expansions for certain constants. 544 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 545 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 546 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 547 548 // These library functions default to expand. 549 setOperationAction(ISD::FLOG , MVT::f64, Expand); 550 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 551 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 552 setOperationAction(ISD::FEXP , MVT::f64, Expand); 553 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 554 setOperationAction(ISD::FLOG , MVT::f32, Expand); 555 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 556 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 557 setOperationAction(ISD::FEXP , MVT::f32, Expand); 558 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 559 560 // Default ISD::TRAP to expand (which turns it into abort). 561 setOperationAction(ISD::TRAP, MVT::Other, Expand); 562 563 IsLittleEndian = TD->isLittleEndian(); 564 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 565 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 566 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 567 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 568 benefitFromCodePlacementOpt = false; 569 UseUnderscoreSetJmp = false; 570 UseUnderscoreLongJmp = false; 571 SelectIsExpensive = false; 572 IntDivIsCheap = false; 573 Pow2DivIsCheap = false; 574 StackPointerRegisterToSaveRestore = 0; 575 ExceptionPointerRegister = 0; 576 ExceptionSelectorRegister = 0; 577 BooleanContents = UndefinedBooleanContent; 578 SchedPreferenceInfo = Sched::Latency; 579 JumpBufSize = 0; 580 JumpBufAlignment = 0; 581 PrefLoopAlignment = 0; 582 ShouldFoldAtomicFences = false; 583 584 InitLibcallNames(LibcallRoutineNames); 585 InitCmpLibcallCCs(CmpLibcallCCs); 586 InitLibcallCallingConvs(LibcallCallingConvs); 587 } 588 589 TargetLowering::~TargetLowering() { 590 delete &TLOF; 591 } 592 593 /// canOpTrap - Returns true if the operation can trap for the value type. 594 /// VT must be a legal type. 595 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 596 assert(isTypeLegal(VT)); 597 switch (Op) { 598 default: 599 return false; 600 case ISD::FDIV: 601 case ISD::FREM: 602 case ISD::SDIV: 603 case ISD::UDIV: 604 case ISD::SREM: 605 case ISD::UREM: 606 return true; 607 } 608 } 609 610 611 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 612 unsigned &NumIntermediates, 613 EVT &RegisterVT, 614 TargetLowering* TLI) { 615 // Figure out the right, legal destination reg to copy into. 616 unsigned NumElts = VT.getVectorNumElements(); 617 MVT EltTy = VT.getVectorElementType(); 618 619 unsigned NumVectorRegs = 1; 620 621 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 622 // could break down into LHS/RHS like LegalizeDAG does. 623 if (!isPowerOf2_32(NumElts)) { 624 NumVectorRegs = NumElts; 625 NumElts = 1; 626 } 627 628 // Divide the input until we get to a supported size. This will always 629 // end with a scalar if the target doesn't support vectors. 630 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 631 NumElts >>= 1; 632 NumVectorRegs <<= 1; 633 } 634 635 NumIntermediates = NumVectorRegs; 636 637 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 638 if (!TLI->isTypeLegal(NewVT)) 639 NewVT = EltTy; 640 IntermediateVT = NewVT; 641 642 EVT DestVT = TLI->getRegisterType(NewVT); 643 RegisterVT = DestVT; 644 if (EVT(DestVT).bitsLT(NewVT)) { 645 // Value is expanded, e.g. i64 -> i16. 646 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 647 } else { 648 // Otherwise, promotion or legal types use the same number of registers as 649 // the vector decimated to the appropriate level. 650 return NumVectorRegs; 651 } 652 653 return 1; 654 } 655 656 /// computeRegisterProperties - Once all of the register classes are added, 657 /// this allows us to compute derived properties we expose. 658 void TargetLowering::computeRegisterProperties() { 659 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 660 "Too many value types for ValueTypeActions to hold!"); 661 662 // Everything defaults to needing one register. 663 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 664 NumRegistersForVT[i] = 1; 665 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 666 } 667 // ...except isVoid, which doesn't need any registers. 668 NumRegistersForVT[MVT::isVoid] = 0; 669 670 // Find the largest integer register class. 671 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 672 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 673 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 674 675 // Every integer value type larger than this largest register takes twice as 676 // many registers to represent as the previous ValueType. 677 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 678 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 679 if (!ExpandedVT.isInteger()) 680 break; 681 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 682 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 683 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 684 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 685 } 686 687 // Inspect all of the ValueType's smaller than the largest integer 688 // register to see which ones need promotion. 689 unsigned LegalIntReg = LargestIntReg; 690 for (unsigned IntReg = LargestIntReg - 1; 691 IntReg >= (unsigned)MVT::i1; --IntReg) { 692 EVT IVT = (MVT::SimpleValueType)IntReg; 693 if (isTypeLegal(IVT)) { 694 LegalIntReg = IntReg; 695 } else { 696 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 697 (MVT::SimpleValueType)LegalIntReg; 698 ValueTypeActions.setTypeAction(IVT, Promote); 699 } 700 } 701 702 // ppcf128 type is really two f64's. 703 if (!isTypeLegal(MVT::ppcf128)) { 704 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 705 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 706 TransformToType[MVT::ppcf128] = MVT::f64; 707 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 708 } 709 710 // Decide how to handle f64. If the target does not have native f64 support, 711 // expand it to i64 and we will be generating soft float library calls. 712 if (!isTypeLegal(MVT::f64)) { 713 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 714 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 715 TransformToType[MVT::f64] = MVT::i64; 716 ValueTypeActions.setTypeAction(MVT::f64, Expand); 717 } 718 719 // Decide how to handle f32. If the target does not have native support for 720 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 721 if (!isTypeLegal(MVT::f32)) { 722 if (isTypeLegal(MVT::f64)) { 723 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 724 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 725 TransformToType[MVT::f32] = MVT::f64; 726 ValueTypeActions.setTypeAction(MVT::f32, Promote); 727 } else { 728 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 729 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 730 TransformToType[MVT::f32] = MVT::i32; 731 ValueTypeActions.setTypeAction(MVT::f32, Expand); 732 } 733 } 734 735 // Loop over all of the vector value types to see which need transformations. 736 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 737 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 738 MVT VT = (MVT::SimpleValueType)i; 739 if (!isTypeLegal(VT)) { 740 MVT IntermediateVT; 741 EVT RegisterVT; 742 unsigned NumIntermediates; 743 NumRegistersForVT[i] = 744 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 745 RegisterVT, this); 746 RegisterTypeForVT[i] = RegisterVT; 747 748 // Determine if there is a legal wider type. 749 bool IsLegalWiderType = false; 750 EVT EltVT = VT.getVectorElementType(); 751 unsigned NElts = VT.getVectorNumElements(); 752 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 753 EVT SVT = (MVT::SimpleValueType)nVT; 754 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && 755 SVT.getVectorNumElements() > NElts && NElts != 1) { 756 TransformToType[i] = SVT; 757 ValueTypeActions.setTypeAction(VT, Promote); 758 IsLegalWiderType = true; 759 break; 760 } 761 } 762 if (!IsLegalWiderType) { 763 EVT NVT = VT.getPow2VectorType(); 764 if (NVT == VT) { 765 // Type is already a power of 2. The default action is to split. 766 TransformToType[i] = MVT::Other; 767 ValueTypeActions.setTypeAction(VT, Expand); 768 } else { 769 TransformToType[i] = NVT; 770 ValueTypeActions.setTypeAction(VT, Promote); 771 } 772 } 773 } 774 } 775 } 776 777 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 778 return NULL; 779 } 780 781 782 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 783 return PointerTy.SimpleTy; 784 } 785 786 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 787 return MVT::i32; // return the default value 788 } 789 790 /// getVectorTypeBreakdown - Vector types are broken down into some number of 791 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 792 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 793 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 794 /// 795 /// This method returns the number of registers needed, and the VT for each 796 /// register. It also returns the VT and quantity of the intermediate values 797 /// before they are promoted/expanded. 798 /// 799 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 800 EVT &IntermediateVT, 801 unsigned &NumIntermediates, 802 EVT &RegisterVT) const { 803 // Figure out the right, legal destination reg to copy into. 804 unsigned NumElts = VT.getVectorNumElements(); 805 EVT EltTy = VT.getVectorElementType(); 806 807 unsigned NumVectorRegs = 1; 808 809 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 810 // could break down into LHS/RHS like LegalizeDAG does. 811 if (!isPowerOf2_32(NumElts)) { 812 NumVectorRegs = NumElts; 813 NumElts = 1; 814 } 815 816 // Divide the input until we get to a supported size. This will always 817 // end with a scalar if the target doesn't support vectors. 818 while (NumElts > 1 && !isTypeLegal( 819 EVT::getVectorVT(Context, EltTy, NumElts))) { 820 NumElts >>= 1; 821 NumVectorRegs <<= 1; 822 } 823 824 NumIntermediates = NumVectorRegs; 825 826 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 827 if (!isTypeLegal(NewVT)) 828 NewVT = EltTy; 829 IntermediateVT = NewVT; 830 831 EVT DestVT = getRegisterType(Context, NewVT); 832 RegisterVT = DestVT; 833 if (DestVT.bitsLT(NewVT)) { 834 // Value is expanded, e.g. i64 -> i16. 835 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 836 } else { 837 // Otherwise, promotion or legal types use the same number of registers as 838 // the vector decimated to the appropriate level. 839 return NumVectorRegs; 840 } 841 842 return 1; 843 } 844 845 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 846 /// function arguments in the caller parameter area. This is the actual 847 /// alignment, not its logarithm. 848 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 849 return TD->getCallFrameTypeAlignment(Ty); 850 } 851 852 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 853 /// current function. The returned value is a member of the 854 /// MachineJumpTableInfo::JTEntryKind enum. 855 unsigned TargetLowering::getJumpTableEncoding() const { 856 // In non-pic modes, just use the address of a block. 857 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 858 return MachineJumpTableInfo::EK_BlockAddress; 859 860 // In PIC mode, if the target supports a GPRel32 directive, use it. 861 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 862 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 863 864 // Otherwise, use a label difference. 865 return MachineJumpTableInfo::EK_LabelDifference32; 866 } 867 868 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 869 SelectionDAG &DAG) const { 870 // If our PIC model is GP relative, use the global offset table as the base. 871 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 872 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 873 return Table; 874 } 875 876 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 877 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 878 /// MCExpr. 879 const MCExpr * 880 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 881 unsigned JTI,MCContext &Ctx) const{ 882 // The normal PIC reloc base is the label at the start of the jump table. 883 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 884 } 885 886 bool 887 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 888 // Assume that everything is safe in static mode. 889 if (getTargetMachine().getRelocationModel() == Reloc::Static) 890 return true; 891 892 // In dynamic-no-pic mode, assume that known defined values are safe. 893 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 894 GA && 895 !GA->getGlobal()->isDeclaration() && 896 !GA->getGlobal()->isWeakForLinker()) 897 return true; 898 899 // Otherwise assume nothing is safe. 900 return false; 901 } 902 903 //===----------------------------------------------------------------------===// 904 // Optimization Methods 905 //===----------------------------------------------------------------------===// 906 907 /// ShrinkDemandedConstant - Check to see if the specified operand of the 908 /// specified instruction is a constant integer. If so, check to see if there 909 /// are any bits set in the constant that are not demanded. If so, shrink the 910 /// constant and return true. 911 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 912 const APInt &Demanded) { 913 DebugLoc dl = Op.getDebugLoc(); 914 915 // FIXME: ISD::SELECT, ISD::SELECT_CC 916 switch (Op.getOpcode()) { 917 default: break; 918 case ISD::XOR: 919 case ISD::AND: 920 case ISD::OR: { 921 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 922 if (!C) return false; 923 924 if (Op.getOpcode() == ISD::XOR && 925 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 926 return false; 927 928 // if we can expand it to have all bits set, do it 929 if (C->getAPIntValue().intersects(~Demanded)) { 930 EVT VT = Op.getValueType(); 931 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 932 DAG.getConstant(Demanded & 933 C->getAPIntValue(), 934 VT)); 935 return CombineTo(Op, New); 936 } 937 938 break; 939 } 940 } 941 942 return false; 943 } 944 945 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 946 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 947 /// cast, but it could be generalized for targets with other types of 948 /// implicit widening casts. 949 bool 950 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 951 unsigned BitWidth, 952 const APInt &Demanded, 953 DebugLoc dl) { 954 assert(Op.getNumOperands() == 2 && 955 "ShrinkDemandedOp only supports binary operators!"); 956 assert(Op.getNode()->getNumValues() == 1 && 957 "ShrinkDemandedOp only supports nodes with one result!"); 958 959 // Don't do this if the node has another user, which may require the 960 // full value. 961 if (!Op.getNode()->hasOneUse()) 962 return false; 963 964 // Search for the smallest integer type with free casts to and from 965 // Op's type. For expedience, just check power-of-2 integer types. 966 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 967 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 968 if (!isPowerOf2_32(SmallVTBits)) 969 SmallVTBits = NextPowerOf2(SmallVTBits); 970 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 971 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 972 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 973 TLI.isZExtFree(SmallVT, Op.getValueType())) { 974 // We found a type with free casts. 975 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 976 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 977 Op.getNode()->getOperand(0)), 978 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 979 Op.getNode()->getOperand(1))); 980 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 981 return CombineTo(Op, Z); 982 } 983 } 984 return false; 985 } 986 987 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 988 /// DemandedMask bits of the result of Op are ever used downstream. If we can 989 /// use this information to simplify Op, create a new simplified DAG node and 990 /// return true, returning the original and new nodes in Old and New. Otherwise, 991 /// analyze the expression and return a mask of KnownOne and KnownZero bits for 992 /// the expression (used to simplify the caller). The KnownZero/One bits may 993 /// only be accurate for those bits in the DemandedMask. 994 bool TargetLowering::SimplifyDemandedBits(SDValue Op, 995 const APInt &DemandedMask, 996 APInt &KnownZero, 997 APInt &KnownOne, 998 TargetLoweringOpt &TLO, 999 unsigned Depth) const { 1000 unsigned BitWidth = DemandedMask.getBitWidth(); 1001 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1002 "Mask size mismatches value type size!"); 1003 APInt NewMask = DemandedMask; 1004 DebugLoc dl = Op.getDebugLoc(); 1005 1006 // Don't know anything. 1007 KnownZero = KnownOne = APInt(BitWidth, 0); 1008 1009 // Other users may use these bits. 1010 if (!Op.getNode()->hasOneUse()) { 1011 if (Depth != 0) { 1012 // If not at the root, Just compute the KnownZero/KnownOne bits to 1013 // simplify things downstream. 1014 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1015 return false; 1016 } 1017 // If this is the root being simplified, allow it to have multiple uses, 1018 // just set the NewMask to all bits. 1019 NewMask = APInt::getAllOnesValue(BitWidth); 1020 } else if (DemandedMask == 0) { 1021 // Not demanding any bits from Op. 1022 if (Op.getOpcode() != ISD::UNDEF) 1023 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1024 return false; 1025 } else if (Depth == 6) { // Limit search depth. 1026 return false; 1027 } 1028 1029 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1030 switch (Op.getOpcode()) { 1031 case ISD::Constant: 1032 // We know all of the bits for a constant! 1033 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1034 KnownZero = ~KnownOne & NewMask; 1035 return false; // Don't fall through, will infinitely loop. 1036 case ISD::AND: 1037 // If the RHS is a constant, check to see if the LHS would be zero without 1038 // using the bits from the RHS. Below, we use knowledge about the RHS to 1039 // simplify the LHS, here we're using information from the LHS to simplify 1040 // the RHS. 1041 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1042 APInt LHSZero, LHSOne; 1043 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1044 LHSZero, LHSOne, Depth+1); 1045 // If the LHS already has zeros where RHSC does, this and is dead. 1046 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1047 return TLO.CombineTo(Op, Op.getOperand(0)); 1048 // If any of the set bits in the RHS are known zero on the LHS, shrink 1049 // the constant. 1050 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1051 return true; 1052 } 1053 1054 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1055 KnownOne, TLO, Depth+1)) 1056 return true; 1057 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1058 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1059 KnownZero2, KnownOne2, TLO, Depth+1)) 1060 return true; 1061 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1062 1063 // If all of the demanded bits are known one on one side, return the other. 1064 // These bits cannot contribute to the result of the 'and'. 1065 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1066 return TLO.CombineTo(Op, Op.getOperand(0)); 1067 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1068 return TLO.CombineTo(Op, Op.getOperand(1)); 1069 // If all of the demanded bits in the inputs are known zeros, return zero. 1070 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1071 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1072 // If the RHS is a constant, see if we can simplify it. 1073 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1074 return true; 1075 // If the operation can be done in a smaller type, do so. 1076 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1077 return true; 1078 1079 // Output known-1 bits are only known if set in both the LHS & RHS. 1080 KnownOne &= KnownOne2; 1081 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1082 KnownZero |= KnownZero2; 1083 break; 1084 case ISD::OR: 1085 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1086 KnownOne, TLO, Depth+1)) 1087 return true; 1088 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1089 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1090 KnownZero2, KnownOne2, TLO, Depth+1)) 1091 return true; 1092 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1093 1094 // If all of the demanded bits are known zero on one side, return the other. 1095 // These bits cannot contribute to the result of the 'or'. 1096 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1097 return TLO.CombineTo(Op, Op.getOperand(0)); 1098 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1099 return TLO.CombineTo(Op, Op.getOperand(1)); 1100 // If all of the potentially set bits on one side are known to be set on 1101 // the other side, just use the 'other' side. 1102 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1103 return TLO.CombineTo(Op, Op.getOperand(0)); 1104 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1105 return TLO.CombineTo(Op, Op.getOperand(1)); 1106 // If the RHS is a constant, see if we can simplify it. 1107 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1108 return true; 1109 // If the operation can be done in a smaller type, do so. 1110 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1111 return true; 1112 1113 // Output known-0 bits are only known if clear in both the LHS & RHS. 1114 KnownZero &= KnownZero2; 1115 // Output known-1 are known to be set if set in either the LHS | RHS. 1116 KnownOne |= KnownOne2; 1117 break; 1118 case ISD::XOR: 1119 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1120 KnownOne, TLO, Depth+1)) 1121 return true; 1122 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1123 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1124 KnownOne2, TLO, Depth+1)) 1125 return true; 1126 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1127 1128 // If all of the demanded bits are known zero on one side, return the other. 1129 // These bits cannot contribute to the result of the 'xor'. 1130 if ((KnownZero & NewMask) == NewMask) 1131 return TLO.CombineTo(Op, Op.getOperand(0)); 1132 if ((KnownZero2 & NewMask) == NewMask) 1133 return TLO.CombineTo(Op, Op.getOperand(1)); 1134 // If the operation can be done in a smaller type, do so. 1135 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1136 return true; 1137 1138 // If all of the unknown bits are known to be zero on one side or the other 1139 // (but not both) turn this into an *inclusive* or. 1140 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1141 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1142 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1143 Op.getOperand(0), 1144 Op.getOperand(1))); 1145 1146 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1147 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1148 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1149 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1150 1151 // If all of the demanded bits on one side are known, and all of the set 1152 // bits on that side are also known to be set on the other side, turn this 1153 // into an AND, as we know the bits will be cleared. 1154 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1155 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1156 if ((KnownOne & KnownOne2) == KnownOne) { 1157 EVT VT = Op.getValueType(); 1158 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1159 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1160 Op.getOperand(0), ANDC)); 1161 } 1162 } 1163 1164 // If the RHS is a constant, see if we can simplify it. 1165 // for XOR, we prefer to force bits to 1 if they will make a -1. 1166 // if we can't force bits, try to shrink constant 1167 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1168 APInt Expanded = C->getAPIntValue() | (~NewMask); 1169 // if we can expand it to have all bits set, do it 1170 if (Expanded.isAllOnesValue()) { 1171 if (Expanded != C->getAPIntValue()) { 1172 EVT VT = Op.getValueType(); 1173 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1174 TLO.DAG.getConstant(Expanded, VT)); 1175 return TLO.CombineTo(Op, New); 1176 } 1177 // if it already has all the bits set, nothing to change 1178 // but don't shrink either! 1179 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1180 return true; 1181 } 1182 } 1183 1184 KnownZero = KnownZeroOut; 1185 KnownOne = KnownOneOut; 1186 break; 1187 case ISD::SELECT: 1188 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1189 KnownOne, TLO, Depth+1)) 1190 return true; 1191 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1192 KnownOne2, TLO, Depth+1)) 1193 return true; 1194 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1195 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1196 1197 // If the operands are constants, see if we can simplify them. 1198 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1199 return true; 1200 1201 // Only known if known in both the LHS and RHS. 1202 KnownOne &= KnownOne2; 1203 KnownZero &= KnownZero2; 1204 break; 1205 case ISD::SELECT_CC: 1206 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1207 KnownOne, TLO, Depth+1)) 1208 return true; 1209 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1210 KnownOne2, TLO, Depth+1)) 1211 return true; 1212 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1213 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1214 1215 // If the operands are constants, see if we can simplify them. 1216 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1217 return true; 1218 1219 // Only known if known in both the LHS and RHS. 1220 KnownOne &= KnownOne2; 1221 KnownZero &= KnownZero2; 1222 break; 1223 case ISD::SHL: 1224 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1225 unsigned ShAmt = SA->getZExtValue(); 1226 SDValue InOp = Op.getOperand(0); 1227 1228 // If the shift count is an invalid immediate, don't do anything. 1229 if (ShAmt >= BitWidth) 1230 break; 1231 1232 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1233 // single shift. We can do this if the bottom bits (which are shifted 1234 // out) are never demanded. 1235 if (InOp.getOpcode() == ISD::SRL && 1236 isa<ConstantSDNode>(InOp.getOperand(1))) { 1237 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1238 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1239 unsigned Opc = ISD::SHL; 1240 int Diff = ShAmt-C1; 1241 if (Diff < 0) { 1242 Diff = -Diff; 1243 Opc = ISD::SRL; 1244 } 1245 1246 SDValue NewSA = 1247 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1248 EVT VT = Op.getValueType(); 1249 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1250 InOp.getOperand(0), NewSA)); 1251 } 1252 } 1253 1254 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1255 KnownZero, KnownOne, TLO, Depth+1)) 1256 return true; 1257 KnownZero <<= SA->getZExtValue(); 1258 KnownOne <<= SA->getZExtValue(); 1259 // low bits known zero. 1260 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1261 } 1262 break; 1263 case ISD::SRL: 1264 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1265 EVT VT = Op.getValueType(); 1266 unsigned ShAmt = SA->getZExtValue(); 1267 unsigned VTSize = VT.getSizeInBits(); 1268 SDValue InOp = Op.getOperand(0); 1269 1270 // If the shift count is an invalid immediate, don't do anything. 1271 if (ShAmt >= BitWidth) 1272 break; 1273 1274 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1275 // single shift. We can do this if the top bits (which are shifted out) 1276 // are never demanded. 1277 if (InOp.getOpcode() == ISD::SHL && 1278 isa<ConstantSDNode>(InOp.getOperand(1))) { 1279 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1280 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1281 unsigned Opc = ISD::SRL; 1282 int Diff = ShAmt-C1; 1283 if (Diff < 0) { 1284 Diff = -Diff; 1285 Opc = ISD::SHL; 1286 } 1287 1288 SDValue NewSA = 1289 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1290 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1291 InOp.getOperand(0), NewSA)); 1292 } 1293 } 1294 1295 // Compute the new bits that are at the top now. 1296 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1297 KnownZero, KnownOne, TLO, Depth+1)) 1298 return true; 1299 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1300 KnownZero = KnownZero.lshr(ShAmt); 1301 KnownOne = KnownOne.lshr(ShAmt); 1302 1303 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1304 KnownZero |= HighBits; // High bits known zero. 1305 } 1306 break; 1307 case ISD::SRA: 1308 // If this is an arithmetic shift right and only the low-bit is set, we can 1309 // always convert this into a logical shr, even if the shift amount is 1310 // variable. The low bit of the shift cannot be an input sign bit unless 1311 // the shift amount is >= the size of the datatype, which is undefined. 1312 if (DemandedMask == 1) 1313 return TLO.CombineTo(Op, 1314 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1315 Op.getOperand(0), Op.getOperand(1))); 1316 1317 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1318 EVT VT = Op.getValueType(); 1319 unsigned ShAmt = SA->getZExtValue(); 1320 1321 // If the shift count is an invalid immediate, don't do anything. 1322 if (ShAmt >= BitWidth) 1323 break; 1324 1325 APInt InDemandedMask = (NewMask << ShAmt); 1326 1327 // If any of the demanded bits are produced by the sign extension, we also 1328 // demand the input sign bit. 1329 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1330 if (HighBits.intersects(NewMask)) 1331 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1332 1333 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1334 KnownZero, KnownOne, TLO, Depth+1)) 1335 return true; 1336 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1337 KnownZero = KnownZero.lshr(ShAmt); 1338 KnownOne = KnownOne.lshr(ShAmt); 1339 1340 // Handle the sign bit, adjusted to where it is now in the mask. 1341 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1342 1343 // If the input sign bit is known to be zero, or if none of the top bits 1344 // are demanded, turn this into an unsigned shift right. 1345 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1346 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1347 Op.getOperand(0), 1348 Op.getOperand(1))); 1349 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1350 KnownOne |= HighBits; 1351 } 1352 } 1353 break; 1354 case ISD::SIGN_EXTEND_INREG: { 1355 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1356 1357 // Sign extension. Compute the demanded bits in the result that are not 1358 // present in the input. 1359 APInt NewBits = 1360 APInt::getHighBitsSet(BitWidth, 1361 BitWidth - EVT.getScalarType().getSizeInBits()) & 1362 NewMask; 1363 1364 // If none of the extended bits are demanded, eliminate the sextinreg. 1365 if (NewBits == 0) 1366 return TLO.CombineTo(Op, Op.getOperand(0)); 1367 1368 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1369 InSignBit.zext(BitWidth); 1370 APInt InputDemandedBits = 1371 APInt::getLowBitsSet(BitWidth, 1372 EVT.getScalarType().getSizeInBits()) & 1373 NewMask; 1374 1375 // Since the sign extended bits are demanded, we know that the sign 1376 // bit is demanded. 1377 InputDemandedBits |= InSignBit; 1378 1379 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1380 KnownZero, KnownOne, TLO, Depth+1)) 1381 return true; 1382 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1383 1384 // If the sign bit of the input is known set or clear, then we know the 1385 // top bits of the result. 1386 1387 // If the input sign bit is known zero, convert this into a zero extension. 1388 if (KnownZero.intersects(InSignBit)) 1389 return TLO.CombineTo(Op, 1390 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1391 1392 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1393 KnownOne |= NewBits; 1394 KnownZero &= ~NewBits; 1395 } else { // Input sign bit unknown 1396 KnownZero &= ~NewBits; 1397 KnownOne &= ~NewBits; 1398 } 1399 break; 1400 } 1401 case ISD::ZERO_EXTEND: { 1402 unsigned OperandBitWidth = 1403 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1404 APInt InMask = NewMask; 1405 InMask.trunc(OperandBitWidth); 1406 1407 // If none of the top bits are demanded, convert this into an any_extend. 1408 APInt NewBits = 1409 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1410 if (!NewBits.intersects(NewMask)) 1411 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1412 Op.getValueType(), 1413 Op.getOperand(0))); 1414 1415 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1416 KnownZero, KnownOne, TLO, Depth+1)) 1417 return true; 1418 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1419 KnownZero.zext(BitWidth); 1420 KnownOne.zext(BitWidth); 1421 KnownZero |= NewBits; 1422 break; 1423 } 1424 case ISD::SIGN_EXTEND: { 1425 EVT InVT = Op.getOperand(0).getValueType(); 1426 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1427 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1428 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1429 APInt NewBits = ~InMask & NewMask; 1430 1431 // If none of the top bits are demanded, convert this into an any_extend. 1432 if (NewBits == 0) 1433 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1434 Op.getValueType(), 1435 Op.getOperand(0))); 1436 1437 // Since some of the sign extended bits are demanded, we know that the sign 1438 // bit is demanded. 1439 APInt InDemandedBits = InMask & NewMask; 1440 InDemandedBits |= InSignBit; 1441 InDemandedBits.trunc(InBits); 1442 1443 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1444 KnownOne, TLO, Depth+1)) 1445 return true; 1446 KnownZero.zext(BitWidth); 1447 KnownOne.zext(BitWidth); 1448 1449 // If the sign bit is known zero, convert this to a zero extend. 1450 if (KnownZero.intersects(InSignBit)) 1451 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1452 Op.getValueType(), 1453 Op.getOperand(0))); 1454 1455 // If the sign bit is known one, the top bits match. 1456 if (KnownOne.intersects(InSignBit)) { 1457 KnownOne |= NewBits; 1458 KnownZero &= ~NewBits; 1459 } else { // Otherwise, top bits aren't known. 1460 KnownOne &= ~NewBits; 1461 KnownZero &= ~NewBits; 1462 } 1463 break; 1464 } 1465 case ISD::ANY_EXTEND: { 1466 unsigned OperandBitWidth = 1467 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1468 APInt InMask = NewMask; 1469 InMask.trunc(OperandBitWidth); 1470 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1471 KnownZero, KnownOne, TLO, Depth+1)) 1472 return true; 1473 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1474 KnownZero.zext(BitWidth); 1475 KnownOne.zext(BitWidth); 1476 break; 1477 } 1478 case ISD::TRUNCATE: { 1479 // Simplify the input, using demanded bit information, and compute the known 1480 // zero/one bits live out. 1481 unsigned OperandBitWidth = 1482 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1483 APInt TruncMask = NewMask; 1484 TruncMask.zext(OperandBitWidth); 1485 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1486 KnownZero, KnownOne, TLO, Depth+1)) 1487 return true; 1488 KnownZero.trunc(BitWidth); 1489 KnownOne.trunc(BitWidth); 1490 1491 // If the input is only used by this truncate, see if we can shrink it based 1492 // on the known demanded bits. 1493 if (Op.getOperand(0).getNode()->hasOneUse()) { 1494 SDValue In = Op.getOperand(0); 1495 switch (In.getOpcode()) { 1496 default: break; 1497 case ISD::SRL: 1498 // Shrink SRL by a constant if none of the high bits shifted in are 1499 // demanded. 1500 if (TLO.LegalTypes() && 1501 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1502 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1503 // undesirable. 1504 break; 1505 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1506 if (!ShAmt) 1507 break; 1508 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1509 OperandBitWidth - BitWidth); 1510 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1511 HighBits.trunc(BitWidth); 1512 1513 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1514 // None of the shifted in bits are needed. Add a truncate of the 1515 // shift input, then shift it. 1516 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1517 Op.getValueType(), 1518 In.getOperand(0)); 1519 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1520 Op.getValueType(), 1521 NewTrunc, 1522 In.getOperand(1))); 1523 } 1524 break; 1525 } 1526 } 1527 1528 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1529 break; 1530 } 1531 case ISD::AssertZext: { 1532 // Demand all the bits of the input that are demanded in the output. 1533 // The low bits are obvious; the high bits are demanded because we're 1534 // asserting that they're zero here. 1535 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1536 KnownZero, KnownOne, TLO, Depth+1)) 1537 return true; 1538 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1539 1540 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1541 APInt InMask = APInt::getLowBitsSet(BitWidth, 1542 VT.getSizeInBits()); 1543 KnownZero |= ~InMask & NewMask; 1544 break; 1545 } 1546 case ISD::BIT_CONVERT: 1547 #if 0 1548 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1549 // is demanded, turn this into a FGETSIGN. 1550 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1551 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1552 !MVT::isVector(Op.getOperand(0).getValueType())) { 1553 // Only do this xform if FGETSIGN is valid or if before legalize. 1554 if (!TLO.AfterLegalize || 1555 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1556 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1557 // place. We expect the SHL to be eliminated by other optimizations. 1558 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1559 Op.getOperand(0)); 1560 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1561 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1562 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1563 Sign, ShAmt)); 1564 } 1565 } 1566 #endif 1567 break; 1568 case ISD::ADD: 1569 case ISD::MUL: 1570 case ISD::SUB: { 1571 // Add, Sub, and Mul don't demand any bits in positions beyond that 1572 // of the highest bit demanded of them. 1573 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1574 BitWidth - NewMask.countLeadingZeros()); 1575 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1576 KnownOne2, TLO, Depth+1)) 1577 return true; 1578 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1579 KnownOne2, TLO, Depth+1)) 1580 return true; 1581 // See if the operation should be performed at a smaller bit width. 1582 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1583 return true; 1584 } 1585 // FALL THROUGH 1586 default: 1587 // Just use ComputeMaskedBits to compute output bits. 1588 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1589 break; 1590 } 1591 1592 // If we know the value of all of the demanded bits, return this as a 1593 // constant. 1594 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1595 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1596 1597 return false; 1598 } 1599 1600 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 1601 /// in Mask are known to be either zero or one and return them in the 1602 /// KnownZero/KnownOne bitsets. 1603 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1604 const APInt &Mask, 1605 APInt &KnownZero, 1606 APInt &KnownOne, 1607 const SelectionDAG &DAG, 1608 unsigned Depth) const { 1609 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1610 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1611 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1612 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1613 "Should use MaskedValueIsZero if you don't know whether Op" 1614 " is a target node!"); 1615 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1616 } 1617 1618 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1619 /// targets that want to expose additional information about sign bits to the 1620 /// DAG Combiner. 1621 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1622 unsigned Depth) const { 1623 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1624 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1625 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1626 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1627 "Should use ComputeNumSignBits if you don't know whether Op" 1628 " is a target node!"); 1629 return 1; 1630 } 1631 1632 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1633 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1634 /// determine which bit is set. 1635 /// 1636 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1637 // A left-shift of a constant one will have exactly one bit set, because 1638 // shifting the bit off the end is undefined. 1639 if (Val.getOpcode() == ISD::SHL) 1640 if (ConstantSDNode *C = 1641 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1642 if (C->getAPIntValue() == 1) 1643 return true; 1644 1645 // Similarly, a right-shift of a constant sign-bit will have exactly 1646 // one bit set. 1647 if (Val.getOpcode() == ISD::SRL) 1648 if (ConstantSDNode *C = 1649 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1650 if (C->getAPIntValue().isSignBit()) 1651 return true; 1652 1653 // More could be done here, though the above checks are enough 1654 // to handle some common cases. 1655 1656 // Fall back to ComputeMaskedBits to catch other known cases. 1657 EVT OpVT = Val.getValueType(); 1658 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1659 APInt Mask = APInt::getAllOnesValue(BitWidth); 1660 APInt KnownZero, KnownOne; 1661 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1662 return (KnownZero.countPopulation() == BitWidth - 1) && 1663 (KnownOne.countPopulation() == 1); 1664 } 1665 1666 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1667 /// and cc. If it is unable to simplify it, return a null SDValue. 1668 SDValue 1669 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1670 ISD::CondCode Cond, bool foldBooleans, 1671 DAGCombinerInfo &DCI, DebugLoc dl) const { 1672 SelectionDAG &DAG = DCI.DAG; 1673 LLVMContext &Context = *DAG.getContext(); 1674 1675 // These setcc operations always fold. 1676 switch (Cond) { 1677 default: break; 1678 case ISD::SETFALSE: 1679 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1680 case ISD::SETTRUE: 1681 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1682 } 1683 1684 if (isa<ConstantSDNode>(N0.getNode())) { 1685 // Ensure that the constant occurs on the RHS, and fold constant 1686 // comparisons. 1687 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1688 } 1689 1690 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1691 const APInt &C1 = N1C->getAPIntValue(); 1692 1693 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1694 // equality comparison, then we're just comparing whether X itself is 1695 // zero. 1696 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1697 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1698 N0.getOperand(1).getOpcode() == ISD::Constant) { 1699 const APInt &ShAmt 1700 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1701 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1702 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1703 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1704 // (srl (ctlz x), 5) == 0 -> X != 0 1705 // (srl (ctlz x), 5) != 1 -> X != 0 1706 Cond = ISD::SETNE; 1707 } else { 1708 // (srl (ctlz x), 5) != 0 -> X == 0 1709 // (srl (ctlz x), 5) == 1 -> X == 0 1710 Cond = ISD::SETEQ; 1711 } 1712 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1713 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1714 Zero, Cond); 1715 } 1716 } 1717 1718 // If the LHS is '(and load, const)', the RHS is 0, 1719 // the test is for equality or unsigned, and all 1 bits of the const are 1720 // in the same partial word, see if we can shorten the load. 1721 if (DCI.isBeforeLegalize() && 1722 N0.getOpcode() == ISD::AND && C1 == 0 && 1723 N0.getNode()->hasOneUse() && 1724 isa<LoadSDNode>(N0.getOperand(0)) && 1725 N0.getOperand(0).getNode()->hasOneUse() && 1726 isa<ConstantSDNode>(N0.getOperand(1))) { 1727 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1728 APInt bestMask; 1729 unsigned bestWidth = 0, bestOffset = 0; 1730 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1731 unsigned origWidth = N0.getValueType().getSizeInBits(); 1732 unsigned maskWidth = origWidth; 1733 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1734 // 8 bits, but have to be careful... 1735 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1736 origWidth = Lod->getMemoryVT().getSizeInBits(); 1737 const APInt &Mask = 1738 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1739 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1740 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1741 for (unsigned offset=0; offset<origWidth/width; offset++) { 1742 if ((newMask & Mask) == Mask) { 1743 if (!TD->isLittleEndian()) 1744 bestOffset = (origWidth/width - offset - 1) * (width/8); 1745 else 1746 bestOffset = (uint64_t)offset * (width/8); 1747 bestMask = Mask.lshr(offset * (width/8) * 8); 1748 bestWidth = width; 1749 break; 1750 } 1751 newMask = newMask << width; 1752 } 1753 } 1754 } 1755 if (bestWidth) { 1756 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1757 if (newVT.isRound()) { 1758 EVT PtrType = Lod->getOperand(1).getValueType(); 1759 SDValue Ptr = Lod->getBasePtr(); 1760 if (bestOffset != 0) 1761 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1762 DAG.getConstant(bestOffset, PtrType)); 1763 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1764 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1765 Lod->getSrcValue(), 1766 Lod->getSrcValueOffset() + bestOffset, 1767 false, false, NewAlign); 1768 return DAG.getSetCC(dl, VT, 1769 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1770 DAG.getConstant(bestMask.trunc(bestWidth), 1771 newVT)), 1772 DAG.getConstant(0LL, newVT), Cond); 1773 } 1774 } 1775 } 1776 1777 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1778 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1779 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1780 1781 // If the comparison constant has bits in the upper part, the 1782 // zero-extended value could never match. 1783 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1784 C1.getBitWidth() - InSize))) { 1785 switch (Cond) { 1786 case ISD::SETUGT: 1787 case ISD::SETUGE: 1788 case ISD::SETEQ: return DAG.getConstant(0, VT); 1789 case ISD::SETULT: 1790 case ISD::SETULE: 1791 case ISD::SETNE: return DAG.getConstant(1, VT); 1792 case ISD::SETGT: 1793 case ISD::SETGE: 1794 // True if the sign bit of C1 is set. 1795 return DAG.getConstant(C1.isNegative(), VT); 1796 case ISD::SETLT: 1797 case ISD::SETLE: 1798 // True if the sign bit of C1 isn't set. 1799 return DAG.getConstant(C1.isNonNegative(), VT); 1800 default: 1801 break; 1802 } 1803 } 1804 1805 // Otherwise, we can perform the comparison with the low bits. 1806 switch (Cond) { 1807 case ISD::SETEQ: 1808 case ISD::SETNE: 1809 case ISD::SETUGT: 1810 case ISD::SETUGE: 1811 case ISD::SETULT: 1812 case ISD::SETULE: { 1813 EVT newVT = N0.getOperand(0).getValueType(); 1814 if (DCI.isBeforeLegalizeOps() || 1815 (isOperationLegal(ISD::SETCC, newVT) && 1816 getCondCodeAction(Cond, newVT)==Legal)) 1817 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1818 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1819 Cond); 1820 break; 1821 } 1822 default: 1823 break; // todo, be more careful with signed comparisons 1824 } 1825 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1826 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1827 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1828 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1829 EVT ExtDstTy = N0.getValueType(); 1830 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1831 1832 // If the extended part has any inconsistent bits, it cannot ever 1833 // compare equal. In other words, they have to be all ones or all 1834 // zeros. 1835 APInt ExtBits = 1836 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1837 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1838 return DAG.getConstant(Cond == ISD::SETNE, VT); 1839 1840 SDValue ZextOp; 1841 EVT Op0Ty = N0.getOperand(0).getValueType(); 1842 if (Op0Ty == ExtSrcTy) { 1843 ZextOp = N0.getOperand(0); 1844 } else { 1845 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1846 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1847 DAG.getConstant(Imm, Op0Ty)); 1848 } 1849 if (!DCI.isCalledByLegalizer()) 1850 DCI.AddToWorklist(ZextOp.getNode()); 1851 // Otherwise, make this a use of a zext. 1852 return DAG.getSetCC(dl, VT, ZextOp, 1853 DAG.getConstant(C1 & APInt::getLowBitsSet( 1854 ExtDstTyBits, 1855 ExtSrcTyBits), 1856 ExtDstTy), 1857 Cond); 1858 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1859 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1860 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1861 if (N0.getOpcode() == ISD::SETCC && 1862 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1863 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1864 if (TrueWhenTrue) 1865 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1866 // Invert the condition. 1867 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1868 CC = ISD::getSetCCInverse(CC, 1869 N0.getOperand(0).getValueType().isInteger()); 1870 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1871 } 1872 1873 if ((N0.getOpcode() == ISD::XOR || 1874 (N0.getOpcode() == ISD::AND && 1875 N0.getOperand(0).getOpcode() == ISD::XOR && 1876 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1877 isa<ConstantSDNode>(N0.getOperand(1)) && 1878 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1879 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1880 // can only do this if the top bits are known zero. 1881 unsigned BitWidth = N0.getValueSizeInBits(); 1882 if (DAG.MaskedValueIsZero(N0, 1883 APInt::getHighBitsSet(BitWidth, 1884 BitWidth-1))) { 1885 // Okay, get the un-inverted input value. 1886 SDValue Val; 1887 if (N0.getOpcode() == ISD::XOR) 1888 Val = N0.getOperand(0); 1889 else { 1890 assert(N0.getOpcode() == ISD::AND && 1891 N0.getOperand(0).getOpcode() == ISD::XOR); 1892 // ((X^1)&1)^1 -> X & 1 1893 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1894 N0.getOperand(0).getOperand(0), 1895 N0.getOperand(1)); 1896 } 1897 1898 return DAG.getSetCC(dl, VT, Val, N1, 1899 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1900 } 1901 } else if (N1C->getAPIntValue() == 1 && 1902 (VT == MVT::i1 || 1903 getBooleanContents() == ZeroOrOneBooleanContent)) { 1904 SDValue Op0 = N0; 1905 if (Op0.getOpcode() == ISD::TRUNCATE) 1906 Op0 = Op0.getOperand(0); 1907 1908 if ((Op0.getOpcode() == ISD::XOR) && 1909 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1910 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1911 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1912 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1913 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1914 Cond); 1915 } else if (Op0.getOpcode() == ISD::AND && 1916 isa<ConstantSDNode>(Op0.getOperand(1)) && 1917 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1918 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1919 if (Op0.getValueType().bitsGT(VT)) 1920 Op0 = DAG.getNode(ISD::AND, dl, VT, 1921 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1922 DAG.getConstant(1, VT)); 1923 else if (Op0.getValueType().bitsLT(VT)) 1924 Op0 = DAG.getNode(ISD::AND, dl, VT, 1925 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1926 DAG.getConstant(1, VT)); 1927 1928 return DAG.getSetCC(dl, VT, Op0, 1929 DAG.getConstant(0, Op0.getValueType()), 1930 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1931 } 1932 } 1933 } 1934 1935 APInt MinVal, MaxVal; 1936 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1937 if (ISD::isSignedIntSetCC(Cond)) { 1938 MinVal = APInt::getSignedMinValue(OperandBitSize); 1939 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1940 } else { 1941 MinVal = APInt::getMinValue(OperandBitSize); 1942 MaxVal = APInt::getMaxValue(OperandBitSize); 1943 } 1944 1945 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1946 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1947 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1948 // X >= C0 --> X > (C0-1) 1949 return DAG.getSetCC(dl, VT, N0, 1950 DAG.getConstant(C1-1, N1.getValueType()), 1951 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1952 } 1953 1954 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1955 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1956 // X <= C0 --> X < (C0+1) 1957 return DAG.getSetCC(dl, VT, N0, 1958 DAG.getConstant(C1+1, N1.getValueType()), 1959 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1960 } 1961 1962 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1963 return DAG.getConstant(0, VT); // X < MIN --> false 1964 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1965 return DAG.getConstant(1, VT); // X >= MIN --> true 1966 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1967 return DAG.getConstant(0, VT); // X > MAX --> false 1968 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1969 return DAG.getConstant(1, VT); // X <= MAX --> true 1970 1971 // Canonicalize setgt X, Min --> setne X, Min 1972 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1973 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1974 // Canonicalize setlt X, Max --> setne X, Max 1975 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1976 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1977 1978 // If we have setult X, 1, turn it into seteq X, 0 1979 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1980 return DAG.getSetCC(dl, VT, N0, 1981 DAG.getConstant(MinVal, N0.getValueType()), 1982 ISD::SETEQ); 1983 // If we have setugt X, Max-1, turn it into seteq X, Max 1984 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1985 return DAG.getSetCC(dl, VT, N0, 1986 DAG.getConstant(MaxVal, N0.getValueType()), 1987 ISD::SETEQ); 1988 1989 // If we have "setcc X, C0", check to see if we can shrink the immediate 1990 // by changing cc. 1991 1992 // SETUGT X, SINTMAX -> SETLT X, 0 1993 if (Cond == ISD::SETUGT && 1994 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1995 return DAG.getSetCC(dl, VT, N0, 1996 DAG.getConstant(0, N1.getValueType()), 1997 ISD::SETLT); 1998 1999 // SETULT X, SINTMIN -> SETGT X, -1 2000 if (Cond == ISD::SETULT && 2001 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2002 SDValue ConstMinusOne = 2003 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2004 N1.getValueType()); 2005 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2006 } 2007 2008 // Fold bit comparisons when we can. 2009 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2010 (VT == N0.getValueType() || 2011 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2012 N0.getOpcode() == ISD::AND) 2013 if (ConstantSDNode *AndRHS = 2014 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2015 EVT ShiftTy = DCI.isBeforeLegalize() ? 2016 getPointerTy() : getShiftAmountTy(); 2017 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2018 // Perform the xform if the AND RHS is a single bit. 2019 if (AndRHS->getAPIntValue().isPowerOf2()) { 2020 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2021 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2022 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2023 } 2024 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2025 // (X & 8) == 8 --> (X & 8) >> 3 2026 // Perform the xform if C1 is a single bit. 2027 if (C1.isPowerOf2()) { 2028 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2029 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2030 DAG.getConstant(C1.logBase2(), ShiftTy))); 2031 } 2032 } 2033 } 2034 } 2035 2036 if (isa<ConstantFPSDNode>(N0.getNode())) { 2037 // Constant fold or commute setcc. 2038 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2039 if (O.getNode()) return O; 2040 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2041 // If the RHS of an FP comparison is a constant, simplify it away in 2042 // some cases. 2043 if (CFP->getValueAPF().isNaN()) { 2044 // If an operand is known to be a nan, we can fold it. 2045 switch (ISD::getUnorderedFlavor(Cond)) { 2046 default: llvm_unreachable("Unknown flavor!"); 2047 case 0: // Known false. 2048 return DAG.getConstant(0, VT); 2049 case 1: // Known true. 2050 return DAG.getConstant(1, VT); 2051 case 2: // Undefined. 2052 return DAG.getUNDEF(VT); 2053 } 2054 } 2055 2056 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2057 // constant if knowing that the operand is non-nan is enough. We prefer to 2058 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2059 // materialize 0.0. 2060 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2061 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2062 2063 // If the condition is not legal, see if we can find an equivalent one 2064 // which is legal. 2065 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2066 // If the comparison was an awkward floating-point == or != and one of 2067 // the comparison operands is infinity or negative infinity, convert the 2068 // condition to a less-awkward <= or >=. 2069 if (CFP->getValueAPF().isInfinity()) { 2070 if (CFP->getValueAPF().isNegative()) { 2071 if (Cond == ISD::SETOEQ && 2072 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2073 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2074 if (Cond == ISD::SETUEQ && 2075 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2076 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2077 if (Cond == ISD::SETUNE && 2078 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2079 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2080 if (Cond == ISD::SETONE && 2081 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2082 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2083 } else { 2084 if (Cond == ISD::SETOEQ && 2085 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2086 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2087 if (Cond == ISD::SETUEQ && 2088 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2089 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2090 if (Cond == ISD::SETUNE && 2091 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2092 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2093 if (Cond == ISD::SETONE && 2094 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2095 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2096 } 2097 } 2098 } 2099 } 2100 2101 if (N0 == N1) { 2102 // We can always fold X == X for integer setcc's. 2103 if (N0.getValueType().isInteger()) 2104 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2105 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2106 if (UOF == 2) // FP operators that are undefined on NaNs. 2107 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2108 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2109 return DAG.getConstant(UOF, VT); 2110 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2111 // if it is not already. 2112 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2113 if (NewCond != Cond) 2114 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2115 } 2116 2117 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2118 N0.getValueType().isInteger()) { 2119 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2120 N0.getOpcode() == ISD::XOR) { 2121 // Simplify (X+Y) == (X+Z) --> Y == Z 2122 if (N0.getOpcode() == N1.getOpcode()) { 2123 if (N0.getOperand(0) == N1.getOperand(0)) 2124 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2125 if (N0.getOperand(1) == N1.getOperand(1)) 2126 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2127 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2128 // If X op Y == Y op X, try other combinations. 2129 if (N0.getOperand(0) == N1.getOperand(1)) 2130 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2131 Cond); 2132 if (N0.getOperand(1) == N1.getOperand(0)) 2133 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2134 Cond); 2135 } 2136 } 2137 2138 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2139 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2140 // Turn (X+C1) == C2 --> X == C2-C1 2141 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2142 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2143 DAG.getConstant(RHSC->getAPIntValue()- 2144 LHSR->getAPIntValue(), 2145 N0.getValueType()), Cond); 2146 } 2147 2148 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2149 if (N0.getOpcode() == ISD::XOR) 2150 // If we know that all of the inverted bits are zero, don't bother 2151 // performing the inversion. 2152 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2153 return 2154 DAG.getSetCC(dl, VT, N0.getOperand(0), 2155 DAG.getConstant(LHSR->getAPIntValue() ^ 2156 RHSC->getAPIntValue(), 2157 N0.getValueType()), 2158 Cond); 2159 } 2160 2161 // Turn (C1-X) == C2 --> X == C1-C2 2162 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2163 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2164 return 2165 DAG.getSetCC(dl, VT, N0.getOperand(1), 2166 DAG.getConstant(SUBC->getAPIntValue() - 2167 RHSC->getAPIntValue(), 2168 N0.getValueType()), 2169 Cond); 2170 } 2171 } 2172 } 2173 2174 // Simplify (X+Z) == X --> Z == 0 2175 if (N0.getOperand(0) == N1) 2176 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2177 DAG.getConstant(0, N0.getValueType()), Cond); 2178 if (N0.getOperand(1) == N1) { 2179 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2180 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2181 DAG.getConstant(0, N0.getValueType()), Cond); 2182 else if (N0.getNode()->hasOneUse()) { 2183 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2184 // (Z-X) == X --> Z == X<<1 2185 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2186 N1, 2187 DAG.getConstant(1, getShiftAmountTy())); 2188 if (!DCI.isCalledByLegalizer()) 2189 DCI.AddToWorklist(SH.getNode()); 2190 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2191 } 2192 } 2193 } 2194 2195 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2196 N1.getOpcode() == ISD::XOR) { 2197 // Simplify X == (X+Z) --> Z == 0 2198 if (N1.getOperand(0) == N0) { 2199 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2200 DAG.getConstant(0, N1.getValueType()), Cond); 2201 } else if (N1.getOperand(1) == N0) { 2202 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2203 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2204 DAG.getConstant(0, N1.getValueType()), Cond); 2205 } else if (N1.getNode()->hasOneUse()) { 2206 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2207 // X == (Z-X) --> X<<1 == Z 2208 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2209 DAG.getConstant(1, getShiftAmountTy())); 2210 if (!DCI.isCalledByLegalizer()) 2211 DCI.AddToWorklist(SH.getNode()); 2212 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2213 } 2214 } 2215 } 2216 2217 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2218 // Note that where y is variable and is known to have at most 2219 // one bit set (for example, if it is z&1) we cannot do this; 2220 // the expressions are not equivalent when y==0. 2221 if (N0.getOpcode() == ISD::AND) 2222 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2223 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2224 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2225 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2226 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2227 } 2228 } 2229 if (N1.getOpcode() == ISD::AND) 2230 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2231 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2232 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2233 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2234 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2235 } 2236 } 2237 } 2238 2239 // Fold away ALL boolean setcc's. 2240 SDValue Temp; 2241 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2242 switch (Cond) { 2243 default: llvm_unreachable("Unknown integer setcc!"); 2244 case ISD::SETEQ: // X == Y -> ~(X^Y) 2245 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2246 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2247 if (!DCI.isCalledByLegalizer()) 2248 DCI.AddToWorklist(Temp.getNode()); 2249 break; 2250 case ISD::SETNE: // X != Y --> (X^Y) 2251 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2252 break; 2253 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2254 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2255 Temp = DAG.getNOT(dl, N0, MVT::i1); 2256 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2257 if (!DCI.isCalledByLegalizer()) 2258 DCI.AddToWorklist(Temp.getNode()); 2259 break; 2260 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2261 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2262 Temp = DAG.getNOT(dl, N1, MVT::i1); 2263 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2264 if (!DCI.isCalledByLegalizer()) 2265 DCI.AddToWorklist(Temp.getNode()); 2266 break; 2267 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2268 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2269 Temp = DAG.getNOT(dl, N0, MVT::i1); 2270 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2271 if (!DCI.isCalledByLegalizer()) 2272 DCI.AddToWorklist(Temp.getNode()); 2273 break; 2274 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2275 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2276 Temp = DAG.getNOT(dl, N1, MVT::i1); 2277 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2278 break; 2279 } 2280 if (VT != MVT::i1) { 2281 if (!DCI.isCalledByLegalizer()) 2282 DCI.AddToWorklist(N0.getNode()); 2283 // FIXME: If running after legalize, we probably can't do this. 2284 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2285 } 2286 return N0; 2287 } 2288 2289 // Could not fold it. 2290 return SDValue(); 2291 } 2292 2293 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2294 /// node is a GlobalAddress + offset. 2295 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2296 int64_t &Offset) const { 2297 if (isa<GlobalAddressSDNode>(N)) { 2298 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2299 GA = GASD->getGlobal(); 2300 Offset += GASD->getOffset(); 2301 return true; 2302 } 2303 2304 if (N->getOpcode() == ISD::ADD) { 2305 SDValue N1 = N->getOperand(0); 2306 SDValue N2 = N->getOperand(1); 2307 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2308 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2309 if (V) { 2310 Offset += V->getSExtValue(); 2311 return true; 2312 } 2313 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2314 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2315 if (V) { 2316 Offset += V->getSExtValue(); 2317 return true; 2318 } 2319 } 2320 } 2321 return false; 2322 } 2323 2324 2325 SDValue TargetLowering:: 2326 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2327 // Default implementation: no optimization. 2328 return SDValue(); 2329 } 2330 2331 //===----------------------------------------------------------------------===// 2332 // Inline Assembler Implementation Methods 2333 //===----------------------------------------------------------------------===// 2334 2335 2336 TargetLowering::ConstraintType 2337 TargetLowering::getConstraintType(const std::string &Constraint) const { 2338 // FIXME: lots more standard ones to handle. 2339 if (Constraint.size() == 1) { 2340 switch (Constraint[0]) { 2341 default: break; 2342 case 'r': return C_RegisterClass; 2343 case 'm': // memory 2344 case 'o': // offsetable 2345 case 'V': // not offsetable 2346 return C_Memory; 2347 case 'i': // Simple Integer or Relocatable Constant 2348 case 'n': // Simple Integer 2349 case 's': // Relocatable Constant 2350 case 'X': // Allow ANY value. 2351 case 'I': // Target registers. 2352 case 'J': 2353 case 'K': 2354 case 'L': 2355 case 'M': 2356 case 'N': 2357 case 'O': 2358 case 'P': 2359 return C_Other; 2360 } 2361 } 2362 2363 if (Constraint.size() > 1 && Constraint[0] == '{' && 2364 Constraint[Constraint.size()-1] == '}') 2365 return C_Register; 2366 return C_Unknown; 2367 } 2368 2369 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2370 /// with another that has more specific requirements based on the type of the 2371 /// corresponding operand. 2372 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2373 if (ConstraintVT.isInteger()) 2374 return "r"; 2375 if (ConstraintVT.isFloatingPoint()) 2376 return "f"; // works for many targets 2377 return 0; 2378 } 2379 2380 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2381 /// vector. If it is invalid, don't add anything to Ops. 2382 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2383 char ConstraintLetter, 2384 std::vector<SDValue> &Ops, 2385 SelectionDAG &DAG) const { 2386 switch (ConstraintLetter) { 2387 default: break; 2388 case 'X': // Allows any operand; labels (basic block) use this. 2389 if (Op.getOpcode() == ISD::BasicBlock) { 2390 Ops.push_back(Op); 2391 return; 2392 } 2393 // fall through 2394 case 'i': // Simple Integer or Relocatable Constant 2395 case 'n': // Simple Integer 2396 case 's': { // Relocatable Constant 2397 // These operands are interested in values of the form (GV+C), where C may 2398 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2399 // is possible and fine if either GV or C are missing. 2400 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2401 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2402 2403 // If we have "(add GV, C)", pull out GV/C 2404 if (Op.getOpcode() == ISD::ADD) { 2405 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2406 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2407 if (C == 0 || GA == 0) { 2408 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2409 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2410 } 2411 if (C == 0 || GA == 0) 2412 C = 0, GA = 0; 2413 } 2414 2415 // If we find a valid operand, map to the TargetXXX version so that the 2416 // value itself doesn't get selected. 2417 if (GA) { // Either &GV or &GV+C 2418 if (ConstraintLetter != 'n') { 2419 int64_t Offs = GA->getOffset(); 2420 if (C) Offs += C->getZExtValue(); 2421 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2422 Op.getValueType(), Offs)); 2423 return; 2424 } 2425 } 2426 if (C) { // just C, no GV. 2427 // Simple constants are not allowed for 's'. 2428 if (ConstraintLetter != 's') { 2429 // gcc prints these as sign extended. Sign extend value to 64 bits 2430 // now; without this it would get ZExt'd later in 2431 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2432 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2433 MVT::i64)); 2434 return; 2435 } 2436 } 2437 break; 2438 } 2439 } 2440 } 2441 2442 std::vector<unsigned> TargetLowering:: 2443 getRegClassForInlineAsmConstraint(const std::string &Constraint, 2444 EVT VT) const { 2445 return std::vector<unsigned>(); 2446 } 2447 2448 2449 std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2450 getRegForInlineAsmConstraint(const std::string &Constraint, 2451 EVT VT) const { 2452 if (Constraint[0] != '{') 2453 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2454 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2455 2456 // Remove the braces from around the name. 2457 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2458 2459 // Figure out which register class contains this reg. 2460 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2461 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2462 E = RI->regclass_end(); RCI != E; ++RCI) { 2463 const TargetRegisterClass *RC = *RCI; 2464 2465 // If none of the value types for this register class are valid, we 2466 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2467 bool isLegal = false; 2468 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2469 I != E; ++I) { 2470 if (isTypeLegal(*I)) { 2471 isLegal = true; 2472 break; 2473 } 2474 } 2475 2476 if (!isLegal) continue; 2477 2478 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2479 I != E; ++I) { 2480 if (RegName.equals_lower(RI->getName(*I))) 2481 return std::make_pair(*I, RC); 2482 } 2483 } 2484 2485 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2486 } 2487 2488 //===----------------------------------------------------------------------===// 2489 // Constraint Selection. 2490 2491 /// isMatchingInputConstraint - Return true of this is an input operand that is 2492 /// a matching constraint like "4". 2493 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2494 assert(!ConstraintCode.empty() && "No known constraint!"); 2495 return isdigit(ConstraintCode[0]); 2496 } 2497 2498 /// getMatchedOperand - If this is an input matching constraint, this method 2499 /// returns the output operand it matches. 2500 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2501 assert(!ConstraintCode.empty() && "No known constraint!"); 2502 return atoi(ConstraintCode.c_str()); 2503 } 2504 2505 2506 /// getConstraintGenerality - Return an integer indicating how general CT 2507 /// is. 2508 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2509 switch (CT) { 2510 default: llvm_unreachable("Unknown constraint type!"); 2511 case TargetLowering::C_Other: 2512 case TargetLowering::C_Unknown: 2513 return 0; 2514 case TargetLowering::C_Register: 2515 return 1; 2516 case TargetLowering::C_RegisterClass: 2517 return 2; 2518 case TargetLowering::C_Memory: 2519 return 3; 2520 } 2521 } 2522 2523 /// ChooseConstraint - If there are multiple different constraints that we 2524 /// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2525 /// This is somewhat tricky: constraints fall into four classes: 2526 /// Other -> immediates and magic values 2527 /// Register -> one specific register 2528 /// RegisterClass -> a group of regs 2529 /// Memory -> memory 2530 /// Ideally, we would pick the most specific constraint possible: if we have 2531 /// something that fits into a register, we would pick it. The problem here 2532 /// is that if we have something that could either be in a register or in 2533 /// memory that use of the register could cause selection of *other* 2534 /// operands to fail: they might only succeed if we pick memory. Because of 2535 /// this the heuristic we use is: 2536 /// 2537 /// 1) If there is an 'other' constraint, and if the operand is valid for 2538 /// that constraint, use it. This makes us take advantage of 'i' 2539 /// constraints when available. 2540 /// 2) Otherwise, pick the most general constraint present. This prefers 2541 /// 'm' over 'r', for example. 2542 /// 2543 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2544 const TargetLowering &TLI, 2545 SDValue Op, SelectionDAG *DAG) { 2546 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2547 unsigned BestIdx = 0; 2548 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2549 int BestGenerality = -1; 2550 2551 // Loop over the options, keeping track of the most general one. 2552 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2553 TargetLowering::ConstraintType CType = 2554 TLI.getConstraintType(OpInfo.Codes[i]); 2555 2556 // If this is an 'other' constraint, see if the operand is valid for it. 2557 // For example, on X86 we might have an 'rI' constraint. If the operand 2558 // is an integer in the range [0..31] we want to use I (saving a load 2559 // of a register), otherwise we must use 'r'. 2560 if (CType == TargetLowering::C_Other && Op.getNode()) { 2561 assert(OpInfo.Codes[i].size() == 1 && 2562 "Unhandled multi-letter 'other' constraint"); 2563 std::vector<SDValue> ResultOps; 2564 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 2565 ResultOps, *DAG); 2566 if (!ResultOps.empty()) { 2567 BestType = CType; 2568 BestIdx = i; 2569 break; 2570 } 2571 } 2572 2573 // Things with matching constraints can only be registers, per gcc 2574 // documentation. This mainly affects "g" constraints. 2575 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2576 continue; 2577 2578 // This constraint letter is more general than the previous one, use it. 2579 int Generality = getConstraintGenerality(CType); 2580 if (Generality > BestGenerality) { 2581 BestType = CType; 2582 BestIdx = i; 2583 BestGenerality = Generality; 2584 } 2585 } 2586 2587 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2588 OpInfo.ConstraintType = BestType; 2589 } 2590 2591 /// ComputeConstraintToUse - Determines the constraint code and constraint 2592 /// type to use for the specific AsmOperandInfo, setting 2593 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2594 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2595 SDValue Op, 2596 SelectionDAG *DAG) const { 2597 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2598 2599 // Single-letter constraints ('r') are very common. 2600 if (OpInfo.Codes.size() == 1) { 2601 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2602 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2603 } else { 2604 ChooseConstraint(OpInfo, *this, Op, DAG); 2605 } 2606 2607 // 'X' matches anything. 2608 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2609 // Labels and constants are handled elsewhere ('X' is the only thing 2610 // that matches labels). For Functions, the type here is the type of 2611 // the result, which is not what we want to look at; leave them alone. 2612 Value *v = OpInfo.CallOperandVal; 2613 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2614 OpInfo.CallOperandVal = v; 2615 return; 2616 } 2617 2618 // Otherwise, try to resolve it to something we know about by looking at 2619 // the actual operand type. 2620 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2621 OpInfo.ConstraintCode = Repl; 2622 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2623 } 2624 } 2625 } 2626 2627 //===----------------------------------------------------------------------===// 2628 // Loop Strength Reduction hooks 2629 //===----------------------------------------------------------------------===// 2630 2631 /// isLegalAddressingMode - Return true if the addressing mode represented 2632 /// by AM is legal for this target, for a load/store of the specified type. 2633 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2634 const Type *Ty) const { 2635 // The default implementation of this implements a conservative RISCy, r+r and 2636 // r+i addr mode. 2637 2638 // Allows a sign-extended 16-bit immediate field. 2639 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2640 return false; 2641 2642 // No global is ever allowed as a base. 2643 if (AM.BaseGV) 2644 return false; 2645 2646 // Only support r+r, 2647 switch (AM.Scale) { 2648 case 0: // "r+i" or just "i", depending on HasBaseReg. 2649 break; 2650 case 1: 2651 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2652 return false; 2653 // Otherwise we have r+r or r+i. 2654 break; 2655 case 2: 2656 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2657 return false; 2658 // Allow 2*r as r+r. 2659 break; 2660 } 2661 2662 return true; 2663 } 2664 2665 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2666 /// return a DAG expression to select that will generate the same value by 2667 /// multiplying by a magic number. See: 2668 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2669 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2670 std::vector<SDNode*>* Created) const { 2671 EVT VT = N->getValueType(0); 2672 DebugLoc dl= N->getDebugLoc(); 2673 2674 // Check to see if we can do this. 2675 // FIXME: We should be more aggressive here. 2676 if (!isTypeLegal(VT)) 2677 return SDValue(); 2678 2679 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2680 APInt::ms magics = d.magic(); 2681 2682 // Multiply the numerator (operand 0) by the magic value 2683 // FIXME: We should support doing a MUL in a wider type 2684 SDValue Q; 2685 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2686 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2687 DAG.getConstant(magics.m, VT)); 2688 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2689 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2690 N->getOperand(0), 2691 DAG.getConstant(magics.m, VT)).getNode(), 1); 2692 else 2693 return SDValue(); // No mulhs or equvialent 2694 // If d > 0 and m < 0, add the numerator 2695 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2696 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2697 if (Created) 2698 Created->push_back(Q.getNode()); 2699 } 2700 // If d < 0 and m > 0, subtract the numerator. 2701 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2702 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2703 if (Created) 2704 Created->push_back(Q.getNode()); 2705 } 2706 // Shift right algebraic if shift value is nonzero 2707 if (magics.s > 0) { 2708 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2709 DAG.getConstant(magics.s, getShiftAmountTy())); 2710 if (Created) 2711 Created->push_back(Q.getNode()); 2712 } 2713 // Extract the sign bit and add it to the quotient 2714 SDValue T = 2715 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2716 getShiftAmountTy())); 2717 if (Created) 2718 Created->push_back(T.getNode()); 2719 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2720 } 2721 2722 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2723 /// return a DAG expression to select that will generate the same value by 2724 /// multiplying by a magic number. See: 2725 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2726 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2727 std::vector<SDNode*>* Created) const { 2728 EVT VT = N->getValueType(0); 2729 DebugLoc dl = N->getDebugLoc(); 2730 2731 // Check to see if we can do this. 2732 // FIXME: We should be more aggressive here. 2733 if (!isTypeLegal(VT)) 2734 return SDValue(); 2735 2736 // FIXME: We should use a narrower constant when the upper 2737 // bits are known to be zero. 2738 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2739 APInt::mu magics = N1C->getAPIntValue().magicu(); 2740 2741 // Multiply the numerator (operand 0) by the magic value 2742 // FIXME: We should support doing a MUL in a wider type 2743 SDValue Q; 2744 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2745 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2746 DAG.getConstant(magics.m, VT)); 2747 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2748 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2749 N->getOperand(0), 2750 DAG.getConstant(magics.m, VT)).getNode(), 1); 2751 else 2752 return SDValue(); // No mulhu or equvialent 2753 if (Created) 2754 Created->push_back(Q.getNode()); 2755 2756 if (magics.a == 0) { 2757 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2758 "We shouldn't generate an undefined shift!"); 2759 return DAG.getNode(ISD::SRL, dl, VT, Q, 2760 DAG.getConstant(magics.s, getShiftAmountTy())); 2761 } else { 2762 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2763 if (Created) 2764 Created->push_back(NPQ.getNode()); 2765 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2766 DAG.getConstant(1, getShiftAmountTy())); 2767 if (Created) 2768 Created->push_back(NPQ.getNode()); 2769 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2770 if (Created) 2771 Created->push_back(NPQ.getNode()); 2772 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2773 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2774 } 2775 } 2776