1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/MC/MCAsmInfo.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/Target/TargetData.h" 18 #include "llvm/Target/TargetLoweringObjectFile.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include "llvm/Target/TargetRegisterInfo.h" 21 #include "llvm/GlobalVariable.h" 22 #include "llvm/DerivedTypes.h" 23 #include "llvm/CodeGen/Analysis.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineJumpTableInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/SelectionDAG.h" 28 #include "llvm/ADT/BitVector.h" 29 #include "llvm/ADT/STLExtras.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/MathExtras.h" 33 #include <cctype> 34 using namespace llvm; 35 36 /// We are in the process of implementing a new TypeLegalization action 37 /// - the promotion of vector elements. This feature is disabled by default 38 /// and only enabled using this flag. 39 static cl::opt<bool> 40 AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true), 41 cl::desc("Allow promotion of integer vector element types")); 42 43 /// InitLibcallNames - Set default libcall names. 44 /// 45 static void InitLibcallNames(const char **Names) { 46 Names[RTLIB::SHL_I16] = "__ashlhi3"; 47 Names[RTLIB::SHL_I32] = "__ashlsi3"; 48 Names[RTLIB::SHL_I64] = "__ashldi3"; 49 Names[RTLIB::SHL_I128] = "__ashlti3"; 50 Names[RTLIB::SRL_I16] = "__lshrhi3"; 51 Names[RTLIB::SRL_I32] = "__lshrsi3"; 52 Names[RTLIB::SRL_I64] = "__lshrdi3"; 53 Names[RTLIB::SRL_I128] = "__lshrti3"; 54 Names[RTLIB::SRA_I16] = "__ashrhi3"; 55 Names[RTLIB::SRA_I32] = "__ashrsi3"; 56 Names[RTLIB::SRA_I64] = "__ashrdi3"; 57 Names[RTLIB::SRA_I128] = "__ashrti3"; 58 Names[RTLIB::MUL_I8] = "__mulqi3"; 59 Names[RTLIB::MUL_I16] = "__mulhi3"; 60 Names[RTLIB::MUL_I32] = "__mulsi3"; 61 Names[RTLIB::MUL_I64] = "__muldi3"; 62 Names[RTLIB::MUL_I128] = "__multi3"; 63 Names[RTLIB::MULO_I32] = "__mulosi4"; 64 Names[RTLIB::MULO_I64] = "__mulodi4"; 65 Names[RTLIB::MULO_I128] = "__muloti4"; 66 Names[RTLIB::SDIV_I8] = "__divqi3"; 67 Names[RTLIB::SDIV_I16] = "__divhi3"; 68 Names[RTLIB::SDIV_I32] = "__divsi3"; 69 Names[RTLIB::SDIV_I64] = "__divdi3"; 70 Names[RTLIB::SDIV_I128] = "__divti3"; 71 Names[RTLIB::UDIV_I8] = "__udivqi3"; 72 Names[RTLIB::UDIV_I16] = "__udivhi3"; 73 Names[RTLIB::UDIV_I32] = "__udivsi3"; 74 Names[RTLIB::UDIV_I64] = "__udivdi3"; 75 Names[RTLIB::UDIV_I128] = "__udivti3"; 76 Names[RTLIB::SREM_I8] = "__modqi3"; 77 Names[RTLIB::SREM_I16] = "__modhi3"; 78 Names[RTLIB::SREM_I32] = "__modsi3"; 79 Names[RTLIB::SREM_I64] = "__moddi3"; 80 Names[RTLIB::SREM_I128] = "__modti3"; 81 Names[RTLIB::UREM_I8] = "__umodqi3"; 82 Names[RTLIB::UREM_I16] = "__umodhi3"; 83 Names[RTLIB::UREM_I32] = "__umodsi3"; 84 Names[RTLIB::UREM_I64] = "__umoddi3"; 85 Names[RTLIB::UREM_I128] = "__umodti3"; 86 87 // These are generally not available. 88 Names[RTLIB::SDIVREM_I8] = 0; 89 Names[RTLIB::SDIVREM_I16] = 0; 90 Names[RTLIB::SDIVREM_I32] = 0; 91 Names[RTLIB::SDIVREM_I64] = 0; 92 Names[RTLIB::SDIVREM_I128] = 0; 93 Names[RTLIB::UDIVREM_I8] = 0; 94 Names[RTLIB::UDIVREM_I16] = 0; 95 Names[RTLIB::UDIVREM_I32] = 0; 96 Names[RTLIB::UDIVREM_I64] = 0; 97 Names[RTLIB::UDIVREM_I128] = 0; 98 99 Names[RTLIB::NEG_I32] = "__negsi2"; 100 Names[RTLIB::NEG_I64] = "__negdi2"; 101 Names[RTLIB::ADD_F32] = "__addsf3"; 102 Names[RTLIB::ADD_F64] = "__adddf3"; 103 Names[RTLIB::ADD_F80] = "__addxf3"; 104 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 105 Names[RTLIB::SUB_F32] = "__subsf3"; 106 Names[RTLIB::SUB_F64] = "__subdf3"; 107 Names[RTLIB::SUB_F80] = "__subxf3"; 108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 109 Names[RTLIB::MUL_F32] = "__mulsf3"; 110 Names[RTLIB::MUL_F64] = "__muldf3"; 111 Names[RTLIB::MUL_F80] = "__mulxf3"; 112 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 113 Names[RTLIB::DIV_F32] = "__divsf3"; 114 Names[RTLIB::DIV_F64] = "__divdf3"; 115 Names[RTLIB::DIV_F80] = "__divxf3"; 116 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 117 Names[RTLIB::REM_F32] = "fmodf"; 118 Names[RTLIB::REM_F64] = "fmod"; 119 Names[RTLIB::REM_F80] = "fmodl"; 120 Names[RTLIB::REM_PPCF128] = "fmodl"; 121 Names[RTLIB::FMA_F32] = "fmaf"; 122 Names[RTLIB::FMA_F64] = "fma"; 123 Names[RTLIB::FMA_F80] = "fmal"; 124 Names[RTLIB::FMA_PPCF128] = "fmal"; 125 Names[RTLIB::POWI_F32] = "__powisf2"; 126 Names[RTLIB::POWI_F64] = "__powidf2"; 127 Names[RTLIB::POWI_F80] = "__powixf2"; 128 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 129 Names[RTLIB::SQRT_F32] = "sqrtf"; 130 Names[RTLIB::SQRT_F64] = "sqrt"; 131 Names[RTLIB::SQRT_F80] = "sqrtl"; 132 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 133 Names[RTLIB::LOG_F32] = "logf"; 134 Names[RTLIB::LOG_F64] = "log"; 135 Names[RTLIB::LOG_F80] = "logl"; 136 Names[RTLIB::LOG_PPCF128] = "logl"; 137 Names[RTLIB::LOG2_F32] = "log2f"; 138 Names[RTLIB::LOG2_F64] = "log2"; 139 Names[RTLIB::LOG2_F80] = "log2l"; 140 Names[RTLIB::LOG2_PPCF128] = "log2l"; 141 Names[RTLIB::LOG10_F32] = "log10f"; 142 Names[RTLIB::LOG10_F64] = "log10"; 143 Names[RTLIB::LOG10_F80] = "log10l"; 144 Names[RTLIB::LOG10_PPCF128] = "log10l"; 145 Names[RTLIB::EXP_F32] = "expf"; 146 Names[RTLIB::EXP_F64] = "exp"; 147 Names[RTLIB::EXP_F80] = "expl"; 148 Names[RTLIB::EXP_PPCF128] = "expl"; 149 Names[RTLIB::EXP2_F32] = "exp2f"; 150 Names[RTLIB::EXP2_F64] = "exp2"; 151 Names[RTLIB::EXP2_F80] = "exp2l"; 152 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 153 Names[RTLIB::SIN_F32] = "sinf"; 154 Names[RTLIB::SIN_F64] = "sin"; 155 Names[RTLIB::SIN_F80] = "sinl"; 156 Names[RTLIB::SIN_PPCF128] = "sinl"; 157 Names[RTLIB::COS_F32] = "cosf"; 158 Names[RTLIB::COS_F64] = "cos"; 159 Names[RTLIB::COS_F80] = "cosl"; 160 Names[RTLIB::COS_PPCF128] = "cosl"; 161 Names[RTLIB::POW_F32] = "powf"; 162 Names[RTLIB::POW_F64] = "pow"; 163 Names[RTLIB::POW_F80] = "powl"; 164 Names[RTLIB::POW_PPCF128] = "powl"; 165 Names[RTLIB::CEIL_F32] = "ceilf"; 166 Names[RTLIB::CEIL_F64] = "ceil"; 167 Names[RTLIB::CEIL_F80] = "ceill"; 168 Names[RTLIB::CEIL_PPCF128] = "ceill"; 169 Names[RTLIB::TRUNC_F32] = "truncf"; 170 Names[RTLIB::TRUNC_F64] = "trunc"; 171 Names[RTLIB::TRUNC_F80] = "truncl"; 172 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 173 Names[RTLIB::RINT_F32] = "rintf"; 174 Names[RTLIB::RINT_F64] = "rint"; 175 Names[RTLIB::RINT_F80] = "rintl"; 176 Names[RTLIB::RINT_PPCF128] = "rintl"; 177 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 178 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 179 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 180 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 181 Names[RTLIB::FLOOR_F32] = "floorf"; 182 Names[RTLIB::FLOOR_F64] = "floor"; 183 Names[RTLIB::FLOOR_F80] = "floorl"; 184 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 185 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 186 Names[RTLIB::COPYSIGN_F64] = "copysign"; 187 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 188 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 189 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 190 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 191 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 192 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 193 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 194 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 195 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 196 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 197 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 198 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 199 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 200 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 201 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 202 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 203 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 204 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 205 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 206 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 207 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 208 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 209 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 210 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 211 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 212 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 213 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 214 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 215 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 216 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 217 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 218 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 219 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 220 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 221 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 222 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 223 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 224 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 225 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 226 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 227 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 228 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 229 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 230 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 231 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 232 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 233 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 234 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 235 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 236 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 237 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 238 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 239 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 240 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 241 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 242 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 243 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 244 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 245 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 246 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 247 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 248 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 249 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 250 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 251 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 252 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 253 Names[RTLIB::OEQ_F32] = "__eqsf2"; 254 Names[RTLIB::OEQ_F64] = "__eqdf2"; 255 Names[RTLIB::UNE_F32] = "__nesf2"; 256 Names[RTLIB::UNE_F64] = "__nedf2"; 257 Names[RTLIB::OGE_F32] = "__gesf2"; 258 Names[RTLIB::OGE_F64] = "__gedf2"; 259 Names[RTLIB::OLT_F32] = "__ltsf2"; 260 Names[RTLIB::OLT_F64] = "__ltdf2"; 261 Names[RTLIB::OLE_F32] = "__lesf2"; 262 Names[RTLIB::OLE_F64] = "__ledf2"; 263 Names[RTLIB::OGT_F32] = "__gtsf2"; 264 Names[RTLIB::OGT_F64] = "__gtdf2"; 265 Names[RTLIB::UO_F32] = "__unordsf2"; 266 Names[RTLIB::UO_F64] = "__unorddf2"; 267 Names[RTLIB::O_F32] = "__unordsf2"; 268 Names[RTLIB::O_F64] = "__unorddf2"; 269 Names[RTLIB::MEMCPY] = "memcpy"; 270 Names[RTLIB::MEMMOVE] = "memmove"; 271 Names[RTLIB::MEMSET] = "memset"; 272 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 273 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 274 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 275 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 276 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 277 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 278 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 279 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 280 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 281 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 282 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 283 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 284 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 285 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 286 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 287 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 288 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 289 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 290 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 291 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 292 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 293 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 294 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 295 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 296 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 297 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 298 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 299 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 300 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 301 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 302 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 303 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 304 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 305 } 306 307 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 308 /// 309 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 310 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 311 CCs[i] = CallingConv::C; 312 } 313 } 314 315 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 316 /// UNKNOWN_LIBCALL if there is none. 317 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 318 if (OpVT == MVT::f32) { 319 if (RetVT == MVT::f64) 320 return FPEXT_F32_F64; 321 } 322 323 return UNKNOWN_LIBCALL; 324 } 325 326 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 327 /// UNKNOWN_LIBCALL if there is none. 328 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 329 if (RetVT == MVT::f32) { 330 if (OpVT == MVT::f64) 331 return FPROUND_F64_F32; 332 if (OpVT == MVT::f80) 333 return FPROUND_F80_F32; 334 if (OpVT == MVT::ppcf128) 335 return FPROUND_PPCF128_F32; 336 } else if (RetVT == MVT::f64) { 337 if (OpVT == MVT::f80) 338 return FPROUND_F80_F64; 339 if (OpVT == MVT::ppcf128) 340 return FPROUND_PPCF128_F64; 341 } 342 343 return UNKNOWN_LIBCALL; 344 } 345 346 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 347 /// UNKNOWN_LIBCALL if there is none. 348 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 349 if (OpVT == MVT::f32) { 350 if (RetVT == MVT::i8) 351 return FPTOSINT_F32_I8; 352 if (RetVT == MVT::i16) 353 return FPTOSINT_F32_I16; 354 if (RetVT == MVT::i32) 355 return FPTOSINT_F32_I32; 356 if (RetVT == MVT::i64) 357 return FPTOSINT_F32_I64; 358 if (RetVT == MVT::i128) 359 return FPTOSINT_F32_I128; 360 } else if (OpVT == MVT::f64) { 361 if (RetVT == MVT::i8) 362 return FPTOSINT_F64_I8; 363 if (RetVT == MVT::i16) 364 return FPTOSINT_F64_I16; 365 if (RetVT == MVT::i32) 366 return FPTOSINT_F64_I32; 367 if (RetVT == MVT::i64) 368 return FPTOSINT_F64_I64; 369 if (RetVT == MVT::i128) 370 return FPTOSINT_F64_I128; 371 } else if (OpVT == MVT::f80) { 372 if (RetVT == MVT::i32) 373 return FPTOSINT_F80_I32; 374 if (RetVT == MVT::i64) 375 return FPTOSINT_F80_I64; 376 if (RetVT == MVT::i128) 377 return FPTOSINT_F80_I128; 378 } else if (OpVT == MVT::ppcf128) { 379 if (RetVT == MVT::i32) 380 return FPTOSINT_PPCF128_I32; 381 if (RetVT == MVT::i64) 382 return FPTOSINT_PPCF128_I64; 383 if (RetVT == MVT::i128) 384 return FPTOSINT_PPCF128_I128; 385 } 386 return UNKNOWN_LIBCALL; 387 } 388 389 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 390 /// UNKNOWN_LIBCALL if there is none. 391 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 392 if (OpVT == MVT::f32) { 393 if (RetVT == MVT::i8) 394 return FPTOUINT_F32_I8; 395 if (RetVT == MVT::i16) 396 return FPTOUINT_F32_I16; 397 if (RetVT == MVT::i32) 398 return FPTOUINT_F32_I32; 399 if (RetVT == MVT::i64) 400 return FPTOUINT_F32_I64; 401 if (RetVT == MVT::i128) 402 return FPTOUINT_F32_I128; 403 } else if (OpVT == MVT::f64) { 404 if (RetVT == MVT::i8) 405 return FPTOUINT_F64_I8; 406 if (RetVT == MVT::i16) 407 return FPTOUINT_F64_I16; 408 if (RetVT == MVT::i32) 409 return FPTOUINT_F64_I32; 410 if (RetVT == MVT::i64) 411 return FPTOUINT_F64_I64; 412 if (RetVT == MVT::i128) 413 return FPTOUINT_F64_I128; 414 } else if (OpVT == MVT::f80) { 415 if (RetVT == MVT::i32) 416 return FPTOUINT_F80_I32; 417 if (RetVT == MVT::i64) 418 return FPTOUINT_F80_I64; 419 if (RetVT == MVT::i128) 420 return FPTOUINT_F80_I128; 421 } else if (OpVT == MVT::ppcf128) { 422 if (RetVT == MVT::i32) 423 return FPTOUINT_PPCF128_I32; 424 if (RetVT == MVT::i64) 425 return FPTOUINT_PPCF128_I64; 426 if (RetVT == MVT::i128) 427 return FPTOUINT_PPCF128_I128; 428 } 429 return UNKNOWN_LIBCALL; 430 } 431 432 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 433 /// UNKNOWN_LIBCALL if there is none. 434 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 435 if (OpVT == MVT::i32) { 436 if (RetVT == MVT::f32) 437 return SINTTOFP_I32_F32; 438 else if (RetVT == MVT::f64) 439 return SINTTOFP_I32_F64; 440 else if (RetVT == MVT::f80) 441 return SINTTOFP_I32_F80; 442 else if (RetVT == MVT::ppcf128) 443 return SINTTOFP_I32_PPCF128; 444 } else if (OpVT == MVT::i64) { 445 if (RetVT == MVT::f32) 446 return SINTTOFP_I64_F32; 447 else if (RetVT == MVT::f64) 448 return SINTTOFP_I64_F64; 449 else if (RetVT == MVT::f80) 450 return SINTTOFP_I64_F80; 451 else if (RetVT == MVT::ppcf128) 452 return SINTTOFP_I64_PPCF128; 453 } else if (OpVT == MVT::i128) { 454 if (RetVT == MVT::f32) 455 return SINTTOFP_I128_F32; 456 else if (RetVT == MVT::f64) 457 return SINTTOFP_I128_F64; 458 else if (RetVT == MVT::f80) 459 return SINTTOFP_I128_F80; 460 else if (RetVT == MVT::ppcf128) 461 return SINTTOFP_I128_PPCF128; 462 } 463 return UNKNOWN_LIBCALL; 464 } 465 466 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 467 /// UNKNOWN_LIBCALL if there is none. 468 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 469 if (OpVT == MVT::i32) { 470 if (RetVT == MVT::f32) 471 return UINTTOFP_I32_F32; 472 else if (RetVT == MVT::f64) 473 return UINTTOFP_I32_F64; 474 else if (RetVT == MVT::f80) 475 return UINTTOFP_I32_F80; 476 else if (RetVT == MVT::ppcf128) 477 return UINTTOFP_I32_PPCF128; 478 } else if (OpVT == MVT::i64) { 479 if (RetVT == MVT::f32) 480 return UINTTOFP_I64_F32; 481 else if (RetVT == MVT::f64) 482 return UINTTOFP_I64_F64; 483 else if (RetVT == MVT::f80) 484 return UINTTOFP_I64_F80; 485 else if (RetVT == MVT::ppcf128) 486 return UINTTOFP_I64_PPCF128; 487 } else if (OpVT == MVT::i128) { 488 if (RetVT == MVT::f32) 489 return UINTTOFP_I128_F32; 490 else if (RetVT == MVT::f64) 491 return UINTTOFP_I128_F64; 492 else if (RetVT == MVT::f80) 493 return UINTTOFP_I128_F80; 494 else if (RetVT == MVT::ppcf128) 495 return UINTTOFP_I128_PPCF128; 496 } 497 return UNKNOWN_LIBCALL; 498 } 499 500 /// InitCmpLibcallCCs - Set default comparison libcall CC. 501 /// 502 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 503 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 504 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 505 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 506 CCs[RTLIB::UNE_F32] = ISD::SETNE; 507 CCs[RTLIB::UNE_F64] = ISD::SETNE; 508 CCs[RTLIB::OGE_F32] = ISD::SETGE; 509 CCs[RTLIB::OGE_F64] = ISD::SETGE; 510 CCs[RTLIB::OLT_F32] = ISD::SETLT; 511 CCs[RTLIB::OLT_F64] = ISD::SETLT; 512 CCs[RTLIB::OLE_F32] = ISD::SETLE; 513 CCs[RTLIB::OLE_F64] = ISD::SETLE; 514 CCs[RTLIB::OGT_F32] = ISD::SETGT; 515 CCs[RTLIB::OGT_F64] = ISD::SETGT; 516 CCs[RTLIB::UO_F32] = ISD::SETNE; 517 CCs[RTLIB::UO_F64] = ISD::SETNE; 518 CCs[RTLIB::O_F32] = ISD::SETEQ; 519 CCs[RTLIB::O_F64] = ISD::SETEQ; 520 } 521 522 /// NOTE: The constructor takes ownership of TLOF. 523 TargetLowering::TargetLowering(const TargetMachine &tm, 524 const TargetLoweringObjectFile *tlof) 525 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), 526 mayPromoteElements(AllowPromoteIntElem) { 527 // All operations default to being supported. 528 memset(OpActions, 0, sizeof(OpActions)); 529 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 530 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 531 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 532 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 533 534 // Set default actions for various operations. 535 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 536 // Default all indexed load / store to expand. 537 for (unsigned IM = (unsigned)ISD::PRE_INC; 538 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 539 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 540 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 541 } 542 543 // These operations default to expand. 544 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 545 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 546 } 547 548 // Most targets ignore the @llvm.prefetch intrinsic. 549 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 550 551 // ConstantFP nodes default to expand. Targets can either change this to 552 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 553 // to optimize expansions for certain constants. 554 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 555 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 556 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 557 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 558 559 // These library functions default to expand. 560 setOperationAction(ISD::FLOG , MVT::f16, Expand); 561 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 562 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 563 setOperationAction(ISD::FEXP , MVT::f16, Expand); 564 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 565 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 566 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 567 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 568 setOperationAction(ISD::FRINT, MVT::f16, Expand); 569 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 570 setOperationAction(ISD::FLOG , MVT::f32, Expand); 571 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 572 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 573 setOperationAction(ISD::FEXP , MVT::f32, Expand); 574 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 575 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 576 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 577 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 578 setOperationAction(ISD::FRINT, MVT::f32, Expand); 579 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 580 setOperationAction(ISD::FLOG , MVT::f64, Expand); 581 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 582 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 583 setOperationAction(ISD::FEXP , MVT::f64, Expand); 584 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 585 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 586 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 587 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 588 setOperationAction(ISD::FRINT, MVT::f64, Expand); 589 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 590 591 // Default ISD::TRAP to expand (which turns it into abort). 592 setOperationAction(ISD::TRAP, MVT::Other, Expand); 593 594 IsLittleEndian = TD->isLittleEndian(); 595 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 596 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 597 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 598 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 599 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 600 = maxStoresPerMemmoveOptSize = 4; 601 benefitFromCodePlacementOpt = false; 602 UseUnderscoreSetJmp = false; 603 UseUnderscoreLongJmp = false; 604 SelectIsExpensive = false; 605 IntDivIsCheap = false; 606 Pow2DivIsCheap = false; 607 JumpIsExpensive = false; 608 predictableSelectIsExpensive = false; 609 StackPointerRegisterToSaveRestore = 0; 610 ExceptionPointerRegister = 0; 611 ExceptionSelectorRegister = 0; 612 BooleanContents = UndefinedBooleanContent; 613 BooleanVectorContents = UndefinedBooleanContent; 614 SchedPreferenceInfo = Sched::ILP; 615 JumpBufSize = 0; 616 JumpBufAlignment = 0; 617 MinFunctionAlignment = 0; 618 PrefFunctionAlignment = 0; 619 PrefLoopAlignment = 0; 620 MinStackArgumentAlignment = 1; 621 ShouldFoldAtomicFences = false; 622 InsertFencesForAtomic = false; 623 624 InitLibcallNames(LibcallRoutineNames); 625 InitCmpLibcallCCs(CmpLibcallCCs); 626 InitLibcallCallingConvs(LibcallCallingConvs); 627 } 628 629 TargetLowering::~TargetLowering() { 630 delete &TLOF; 631 } 632 633 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 634 return MVT::getIntegerVT(8*TD->getPointerSize()); 635 } 636 637 /// canOpTrap - Returns true if the operation can trap for the value type. 638 /// VT must be a legal type. 639 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 640 assert(isTypeLegal(VT)); 641 switch (Op) { 642 default: 643 return false; 644 case ISD::FDIV: 645 case ISD::FREM: 646 case ISD::SDIV: 647 case ISD::UDIV: 648 case ISD::SREM: 649 case ISD::UREM: 650 return true; 651 } 652 } 653 654 655 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 656 unsigned &NumIntermediates, 657 EVT &RegisterVT, 658 TargetLowering *TLI) { 659 // Figure out the right, legal destination reg to copy into. 660 unsigned NumElts = VT.getVectorNumElements(); 661 MVT EltTy = VT.getVectorElementType(); 662 663 unsigned NumVectorRegs = 1; 664 665 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 666 // could break down into LHS/RHS like LegalizeDAG does. 667 if (!isPowerOf2_32(NumElts)) { 668 NumVectorRegs = NumElts; 669 NumElts = 1; 670 } 671 672 // Divide the input until we get to a supported size. This will always 673 // end with a scalar if the target doesn't support vectors. 674 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 675 NumElts >>= 1; 676 NumVectorRegs <<= 1; 677 } 678 679 NumIntermediates = NumVectorRegs; 680 681 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 682 if (!TLI->isTypeLegal(NewVT)) 683 NewVT = EltTy; 684 IntermediateVT = NewVT; 685 686 unsigned NewVTSize = NewVT.getSizeInBits(); 687 688 // Convert sizes such as i33 to i64. 689 if (!isPowerOf2_32(NewVTSize)) 690 NewVTSize = NextPowerOf2(NewVTSize); 691 692 EVT DestVT = TLI->getRegisterType(NewVT); 693 RegisterVT = DestVT; 694 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 695 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 696 697 // Otherwise, promotion or legal types use the same number of registers as 698 // the vector decimated to the appropriate level. 699 return NumVectorRegs; 700 } 701 702 /// isLegalRC - Return true if the value types that can be represented by the 703 /// specified register class are all legal. 704 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 705 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 706 I != E; ++I) { 707 if (isTypeLegal(*I)) 708 return true; 709 } 710 return false; 711 } 712 713 /// findRepresentativeClass - Return the largest legal super-reg register class 714 /// of the register class for the specified type and its associated "cost". 715 std::pair<const TargetRegisterClass*, uint8_t> 716 TargetLowering::findRepresentativeClass(EVT VT) const { 717 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 718 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 719 if (!RC) 720 return std::make_pair(RC, 0); 721 722 // Compute the set of all super-register classes. 723 BitVector SuperRegRC(TRI->getNumRegClasses()); 724 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 725 SuperRegRC.setBitsInMask(RCI.getMask()); 726 727 // Find the first legal register class with the largest spill size. 728 const TargetRegisterClass *BestRC = RC; 729 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 730 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 731 // We want the largest possible spill size. 732 if (SuperRC->getSize() <= BestRC->getSize()) 733 continue; 734 if (!isLegalRC(SuperRC)) 735 continue; 736 BestRC = SuperRC; 737 } 738 return std::make_pair(BestRC, 1); 739 } 740 741 /// computeRegisterProperties - Once all of the register classes are added, 742 /// this allows us to compute derived properties we expose. 743 void TargetLowering::computeRegisterProperties() { 744 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 745 "Too many value types for ValueTypeActions to hold!"); 746 747 // Everything defaults to needing one register. 748 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 749 NumRegistersForVT[i] = 1; 750 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 751 } 752 // ...except isVoid, which doesn't need any registers. 753 NumRegistersForVT[MVT::isVoid] = 0; 754 755 // Find the largest integer register class. 756 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 757 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 758 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 759 760 // Every integer value type larger than this largest register takes twice as 761 // many registers to represent as the previous ValueType. 762 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 763 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 764 if (!ExpandedVT.isInteger()) 765 break; 766 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 767 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 768 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 769 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger); 770 } 771 772 // Inspect all of the ValueType's smaller than the largest integer 773 // register to see which ones need promotion. 774 unsigned LegalIntReg = LargestIntReg; 775 for (unsigned IntReg = LargestIntReg - 1; 776 IntReg >= (unsigned)MVT::i1; --IntReg) { 777 EVT IVT = (MVT::SimpleValueType)IntReg; 778 if (isTypeLegal(IVT)) { 779 LegalIntReg = IntReg; 780 } else { 781 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 782 (MVT::SimpleValueType)LegalIntReg; 783 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 784 } 785 } 786 787 // ppcf128 type is really two f64's. 788 if (!isTypeLegal(MVT::ppcf128)) { 789 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 790 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 791 TransformToType[MVT::ppcf128] = MVT::f64; 792 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 793 } 794 795 // Decide how to handle f64. If the target does not have native f64 support, 796 // expand it to i64 and we will be generating soft float library calls. 797 if (!isTypeLegal(MVT::f64)) { 798 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 799 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 800 TransformToType[MVT::f64] = MVT::i64; 801 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 802 } 803 804 // Decide how to handle f32. If the target does not have native support for 805 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 806 if (!isTypeLegal(MVT::f32)) { 807 if (isTypeLegal(MVT::f64)) { 808 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 809 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 810 TransformToType[MVT::f32] = MVT::f64; 811 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 812 } else { 813 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 814 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 815 TransformToType[MVT::f32] = MVT::i32; 816 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 817 } 818 } 819 820 // Loop over all of the vector value types to see which need transformations. 821 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 822 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 823 MVT VT = (MVT::SimpleValueType)i; 824 if (isTypeLegal(VT)) continue; 825 826 // Determine if there is a legal wider type. If so, we should promote to 827 // that wider vector type. 828 EVT EltVT = VT.getVectorElementType(); 829 unsigned NElts = VT.getVectorNumElements(); 830 if (NElts != 1) { 831 bool IsLegalWiderType = false; 832 // If we allow the promotion of vector elements using a flag, 833 // then return TypePromoteInteger on vector elements. 834 // First try to promote the elements of integer vectors. If no legal 835 // promotion was found, fallback to the widen-vector method. 836 if (mayPromoteElements) 837 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 838 EVT SVT = (MVT::SimpleValueType)nVT; 839 // Promote vectors of integers to vectors with the same number 840 // of elements, with a wider element type. 841 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 842 && SVT.getVectorNumElements() == NElts && 843 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 844 TransformToType[i] = SVT; 845 RegisterTypeForVT[i] = SVT; 846 NumRegistersForVT[i] = 1; 847 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 848 IsLegalWiderType = true; 849 break; 850 } 851 } 852 853 if (IsLegalWiderType) continue; 854 855 // Try to widen the vector. 856 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 857 EVT SVT = (MVT::SimpleValueType)nVT; 858 if (SVT.getVectorElementType() == EltVT && 859 SVT.getVectorNumElements() > NElts && 860 isTypeLegal(SVT)) { 861 TransformToType[i] = SVT; 862 RegisterTypeForVT[i] = SVT; 863 NumRegistersForVT[i] = 1; 864 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 865 IsLegalWiderType = true; 866 break; 867 } 868 } 869 if (IsLegalWiderType) continue; 870 } 871 872 MVT IntermediateVT; 873 EVT RegisterVT; 874 unsigned NumIntermediates; 875 NumRegistersForVT[i] = 876 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 877 RegisterVT, this); 878 RegisterTypeForVT[i] = RegisterVT; 879 880 EVT NVT = VT.getPow2VectorType(); 881 if (NVT == VT) { 882 // Type is already a power of 2. The default action is to split. 883 TransformToType[i] = MVT::Other; 884 unsigned NumElts = VT.getVectorNumElements(); 885 ValueTypeActions.setTypeAction(VT, 886 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 887 } else { 888 TransformToType[i] = NVT; 889 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 890 } 891 } 892 893 // Determine the 'representative' register class for each value type. 894 // An representative register class is the largest (meaning one which is 895 // not a sub-register class / subreg register class) legal register class for 896 // a group of value types. For example, on i386, i8, i16, and i32 897 // representative would be GR32; while on x86_64 it's GR64. 898 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 899 const TargetRegisterClass* RRC; 900 uint8_t Cost; 901 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 902 RepRegClassForVT[i] = RRC; 903 RepRegClassCostForVT[i] = Cost; 904 } 905 } 906 907 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 908 return NULL; 909 } 910 911 912 EVT TargetLowering::getSetCCResultType(EVT VT) const { 913 assert(!VT.isVector() && "No default SetCC type for vectors!"); 914 return PointerTy.SimpleTy; 915 } 916 917 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 918 return MVT::i32; // return the default value 919 } 920 921 /// getVectorTypeBreakdown - Vector types are broken down into some number of 922 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 923 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 924 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 925 /// 926 /// This method returns the number of registers needed, and the VT for each 927 /// register. It also returns the VT and quantity of the intermediate values 928 /// before they are promoted/expanded. 929 /// 930 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 931 EVT &IntermediateVT, 932 unsigned &NumIntermediates, 933 EVT &RegisterVT) const { 934 unsigned NumElts = VT.getVectorNumElements(); 935 936 // If there is a wider vector type with the same element type as this one, 937 // or a promoted vector type that has the same number of elements which 938 // are wider, then we should convert to that legal vector type. 939 // This handles things like <2 x float> -> <4 x float> and 940 // <4 x i1> -> <4 x i32>. 941 LegalizeTypeAction TA = getTypeAction(Context, VT); 942 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 943 RegisterVT = getTypeToTransformTo(Context, VT); 944 if (isTypeLegal(RegisterVT)) { 945 IntermediateVT = RegisterVT; 946 NumIntermediates = 1; 947 return 1; 948 } 949 } 950 951 // Figure out the right, legal destination reg to copy into. 952 EVT EltTy = VT.getVectorElementType(); 953 954 unsigned NumVectorRegs = 1; 955 956 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 957 // could break down into LHS/RHS like LegalizeDAG does. 958 if (!isPowerOf2_32(NumElts)) { 959 NumVectorRegs = NumElts; 960 NumElts = 1; 961 } 962 963 // Divide the input until we get to a supported size. This will always 964 // end with a scalar if the target doesn't support vectors. 965 while (NumElts > 1 && !isTypeLegal( 966 EVT::getVectorVT(Context, EltTy, NumElts))) { 967 NumElts >>= 1; 968 NumVectorRegs <<= 1; 969 } 970 971 NumIntermediates = NumVectorRegs; 972 973 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 974 if (!isTypeLegal(NewVT)) 975 NewVT = EltTy; 976 IntermediateVT = NewVT; 977 978 EVT DestVT = getRegisterType(Context, NewVT); 979 RegisterVT = DestVT; 980 unsigned NewVTSize = NewVT.getSizeInBits(); 981 982 // Convert sizes such as i33 to i64. 983 if (!isPowerOf2_32(NewVTSize)) 984 NewVTSize = NextPowerOf2(NewVTSize); 985 986 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 987 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 988 989 // Otherwise, promotion or legal types use the same number of registers as 990 // the vector decimated to the appropriate level. 991 return NumVectorRegs; 992 } 993 994 /// Get the EVTs and ArgFlags collections that represent the legalized return 995 /// type of the given function. This does not require a DAG or a return value, 996 /// and is suitable for use before any DAGs for the function are constructed. 997 /// TODO: Move this out of TargetLowering.cpp. 998 void llvm::GetReturnInfo(Type* ReturnType, Attributes attr, 999 SmallVectorImpl<ISD::OutputArg> &Outs, 1000 const TargetLowering &TLI) { 1001 SmallVector<EVT, 4> ValueVTs; 1002 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1003 unsigned NumValues = ValueVTs.size(); 1004 if (NumValues == 0) return; 1005 1006 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1007 EVT VT = ValueVTs[j]; 1008 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1009 1010 if (attr & Attribute::SExt) 1011 ExtendKind = ISD::SIGN_EXTEND; 1012 else if (attr & Attribute::ZExt) 1013 ExtendKind = ISD::ZERO_EXTEND; 1014 1015 // FIXME: C calling convention requires the return type to be promoted to 1016 // at least 32-bit. But this is not necessary for non-C calling 1017 // conventions. The frontend should mark functions whose return values 1018 // require promoting with signext or zeroext attributes. 1019 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1020 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1021 if (VT.bitsLT(MinVT)) 1022 VT = MinVT; 1023 } 1024 1025 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1026 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1027 1028 // 'inreg' on function refers to return value 1029 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1030 if (attr & Attribute::InReg) 1031 Flags.setInReg(); 1032 1033 // Propagate extension type if any 1034 if (attr & Attribute::SExt) 1035 Flags.setSExt(); 1036 else if (attr & Attribute::ZExt) 1037 Flags.setZExt(); 1038 1039 for (unsigned i = 0; i < NumParts; ++i) { 1040 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 1041 } 1042 } 1043 } 1044 1045 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1046 /// function arguments in the caller parameter area. This is the actual 1047 /// alignment, not its logarithm. 1048 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const { 1049 return TD->getCallFrameTypeAlignment(Ty); 1050 } 1051 1052 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 1053 /// current function. The returned value is a member of the 1054 /// MachineJumpTableInfo::JTEntryKind enum. 1055 unsigned TargetLowering::getJumpTableEncoding() const { 1056 // In non-pic modes, just use the address of a block. 1057 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1058 return MachineJumpTableInfo::EK_BlockAddress; 1059 1060 // In PIC mode, if the target supports a GPRel32 directive, use it. 1061 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1062 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1063 1064 // Otherwise, use a label difference. 1065 return MachineJumpTableInfo::EK_LabelDifference32; 1066 } 1067 1068 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1069 SelectionDAG &DAG) const { 1070 // If our PIC model is GP relative, use the global offset table as the base. 1071 unsigned JTEncoding = getJumpTableEncoding(); 1072 1073 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 1074 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 1075 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1076 1077 return Table; 1078 } 1079 1080 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1081 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1082 /// MCExpr. 1083 const MCExpr * 1084 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1085 unsigned JTI,MCContext &Ctx) const{ 1086 // The normal PIC reloc base is the label at the start of the jump table. 1087 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1088 } 1089 1090 bool 1091 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1092 // Assume that everything is safe in static mode. 1093 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1094 return true; 1095 1096 // In dynamic-no-pic mode, assume that known defined values are safe. 1097 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1098 GA && 1099 !GA->getGlobal()->isDeclaration() && 1100 !GA->getGlobal()->isWeakForLinker()) 1101 return true; 1102 1103 // Otherwise assume nothing is safe. 1104 return false; 1105 } 1106 1107 //===----------------------------------------------------------------------===// 1108 // Optimization Methods 1109 //===----------------------------------------------------------------------===// 1110 1111 /// ShrinkDemandedConstant - Check to see if the specified operand of the 1112 /// specified instruction is a constant integer. If so, check to see if there 1113 /// are any bits set in the constant that are not demanded. If so, shrink the 1114 /// constant and return true. 1115 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1116 const APInt &Demanded) { 1117 DebugLoc dl = Op.getDebugLoc(); 1118 1119 // FIXME: ISD::SELECT, ISD::SELECT_CC 1120 switch (Op.getOpcode()) { 1121 default: break; 1122 case ISD::XOR: 1123 case ISD::AND: 1124 case ISD::OR: { 1125 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1126 if (!C) return false; 1127 1128 if (Op.getOpcode() == ISD::XOR && 1129 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1130 return false; 1131 1132 // if we can expand it to have all bits set, do it 1133 if (C->getAPIntValue().intersects(~Demanded)) { 1134 EVT VT = Op.getValueType(); 1135 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1136 DAG.getConstant(Demanded & 1137 C->getAPIntValue(), 1138 VT)); 1139 return CombineTo(Op, New); 1140 } 1141 1142 break; 1143 } 1144 } 1145 1146 return false; 1147 } 1148 1149 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1150 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1151 /// cast, but it could be generalized for targets with other types of 1152 /// implicit widening casts. 1153 bool 1154 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1155 unsigned BitWidth, 1156 const APInt &Demanded, 1157 DebugLoc dl) { 1158 assert(Op.getNumOperands() == 2 && 1159 "ShrinkDemandedOp only supports binary operators!"); 1160 assert(Op.getNode()->getNumValues() == 1 && 1161 "ShrinkDemandedOp only supports nodes with one result!"); 1162 1163 // Don't do this if the node has another user, which may require the 1164 // full value. 1165 if (!Op.getNode()->hasOneUse()) 1166 return false; 1167 1168 // Search for the smallest integer type with free casts to and from 1169 // Op's type. For expedience, just check power-of-2 integer types. 1170 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1171 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1172 if (!isPowerOf2_32(SmallVTBits)) 1173 SmallVTBits = NextPowerOf2(SmallVTBits); 1174 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1175 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1176 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1177 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1178 // We found a type with free casts. 1179 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1180 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1181 Op.getNode()->getOperand(0)), 1182 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1183 Op.getNode()->getOperand(1))); 1184 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1185 return CombineTo(Op, Z); 1186 } 1187 } 1188 return false; 1189 } 1190 1191 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1192 /// DemandedMask bits of the result of Op are ever used downstream. If we can 1193 /// use this information to simplify Op, create a new simplified DAG node and 1194 /// return true, returning the original and new nodes in Old and New. Otherwise, 1195 /// analyze the expression and return a mask of KnownOne and KnownZero bits for 1196 /// the expression (used to simplify the caller). The KnownZero/One bits may 1197 /// only be accurate for those bits in the DemandedMask. 1198 bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1199 const APInt &DemandedMask, 1200 APInt &KnownZero, 1201 APInt &KnownOne, 1202 TargetLoweringOpt &TLO, 1203 unsigned Depth) const { 1204 unsigned BitWidth = DemandedMask.getBitWidth(); 1205 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1206 "Mask size mismatches value type size!"); 1207 APInt NewMask = DemandedMask; 1208 DebugLoc dl = Op.getDebugLoc(); 1209 1210 // Don't know anything. 1211 KnownZero = KnownOne = APInt(BitWidth, 0); 1212 1213 // Other users may use these bits. 1214 if (!Op.getNode()->hasOneUse()) { 1215 if (Depth != 0) { 1216 // If not at the root, Just compute the KnownZero/KnownOne bits to 1217 // simplify things downstream. 1218 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1219 return false; 1220 } 1221 // If this is the root being simplified, allow it to have multiple uses, 1222 // just set the NewMask to all bits. 1223 NewMask = APInt::getAllOnesValue(BitWidth); 1224 } else if (DemandedMask == 0) { 1225 // Not demanding any bits from Op. 1226 if (Op.getOpcode() != ISD::UNDEF) 1227 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1228 return false; 1229 } else if (Depth == 6) { // Limit search depth. 1230 return false; 1231 } 1232 1233 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1234 switch (Op.getOpcode()) { 1235 case ISD::Constant: 1236 // We know all of the bits for a constant! 1237 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 1238 KnownZero = ~KnownOne; 1239 return false; // Don't fall through, will infinitely loop. 1240 case ISD::AND: 1241 // If the RHS is a constant, check to see if the LHS would be zero without 1242 // using the bits from the RHS. Below, we use knowledge about the RHS to 1243 // simplify the LHS, here we're using information from the LHS to simplify 1244 // the RHS. 1245 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1246 APInt LHSZero, LHSOne; 1247 // Do not increment Depth here; that can cause an infinite loop. 1248 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 1249 // If the LHS already has zeros where RHSC does, this and is dead. 1250 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1251 return TLO.CombineTo(Op, Op.getOperand(0)); 1252 // If any of the set bits in the RHS are known zero on the LHS, shrink 1253 // the constant. 1254 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1255 return true; 1256 } 1257 1258 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1259 KnownOne, TLO, Depth+1)) 1260 return true; 1261 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1262 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1263 KnownZero2, KnownOne2, TLO, Depth+1)) 1264 return true; 1265 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1266 1267 // If all of the demanded bits are known one on one side, return the other. 1268 // These bits cannot contribute to the result of the 'and'. 1269 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1270 return TLO.CombineTo(Op, Op.getOperand(0)); 1271 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1272 return TLO.CombineTo(Op, Op.getOperand(1)); 1273 // If all of the demanded bits in the inputs are known zeros, return zero. 1274 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1275 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1276 // If the RHS is a constant, see if we can simplify it. 1277 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1278 return true; 1279 // If the operation can be done in a smaller type, do so. 1280 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1281 return true; 1282 1283 // Output known-1 bits are only known if set in both the LHS & RHS. 1284 KnownOne &= KnownOne2; 1285 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1286 KnownZero |= KnownZero2; 1287 break; 1288 case ISD::OR: 1289 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1290 KnownOne, TLO, Depth+1)) 1291 return true; 1292 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1293 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1294 KnownZero2, KnownOne2, TLO, Depth+1)) 1295 return true; 1296 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1297 1298 // If all of the demanded bits are known zero on one side, return the other. 1299 // These bits cannot contribute to the result of the 'or'. 1300 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1301 return TLO.CombineTo(Op, Op.getOperand(0)); 1302 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1303 return TLO.CombineTo(Op, Op.getOperand(1)); 1304 // If all of the potentially set bits on one side are known to be set on 1305 // the other side, just use the 'other' side. 1306 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1307 return TLO.CombineTo(Op, Op.getOperand(0)); 1308 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1309 return TLO.CombineTo(Op, Op.getOperand(1)); 1310 // If the RHS is a constant, see if we can simplify it. 1311 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1312 return true; 1313 // If the operation can be done in a smaller type, do so. 1314 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1315 return true; 1316 1317 // Output known-0 bits are only known if clear in both the LHS & RHS. 1318 KnownZero &= KnownZero2; 1319 // Output known-1 are known to be set if set in either the LHS | RHS. 1320 KnownOne |= KnownOne2; 1321 break; 1322 case ISD::XOR: 1323 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1324 KnownOne, TLO, Depth+1)) 1325 return true; 1326 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1327 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1328 KnownOne2, TLO, Depth+1)) 1329 return true; 1330 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1331 1332 // If all of the demanded bits are known zero on one side, return the other. 1333 // These bits cannot contribute to the result of the 'xor'. 1334 if ((KnownZero & NewMask) == NewMask) 1335 return TLO.CombineTo(Op, Op.getOperand(0)); 1336 if ((KnownZero2 & NewMask) == NewMask) 1337 return TLO.CombineTo(Op, Op.getOperand(1)); 1338 // If the operation can be done in a smaller type, do so. 1339 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1340 return true; 1341 1342 // If all of the unknown bits are known to be zero on one side or the other 1343 // (but not both) turn this into an *inclusive* or. 1344 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1345 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1346 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1347 Op.getOperand(0), 1348 Op.getOperand(1))); 1349 1350 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1351 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1352 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1353 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1354 1355 // If all of the demanded bits on one side are known, and all of the set 1356 // bits on that side are also known to be set on the other side, turn this 1357 // into an AND, as we know the bits will be cleared. 1358 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1359 // NB: it is okay if more bits are known than are requested 1360 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 1361 if (KnownOne == KnownOne2) { // set bits are the same on both sides 1362 EVT VT = Op.getValueType(); 1363 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1364 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1365 Op.getOperand(0), ANDC)); 1366 } 1367 } 1368 1369 // If the RHS is a constant, see if we can simplify it. 1370 // for XOR, we prefer to force bits to 1 if they will make a -1. 1371 // if we can't force bits, try to shrink constant 1372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1373 APInt Expanded = C->getAPIntValue() | (~NewMask); 1374 // if we can expand it to have all bits set, do it 1375 if (Expanded.isAllOnesValue()) { 1376 if (Expanded != C->getAPIntValue()) { 1377 EVT VT = Op.getValueType(); 1378 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1379 TLO.DAG.getConstant(Expanded, VT)); 1380 return TLO.CombineTo(Op, New); 1381 } 1382 // if it already has all the bits set, nothing to change 1383 // but don't shrink either! 1384 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1385 return true; 1386 } 1387 } 1388 1389 KnownZero = KnownZeroOut; 1390 KnownOne = KnownOneOut; 1391 break; 1392 case ISD::SELECT: 1393 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1394 KnownOne, TLO, Depth+1)) 1395 return true; 1396 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1397 KnownOne2, TLO, Depth+1)) 1398 return true; 1399 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1400 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1401 1402 // If the operands are constants, see if we can simplify them. 1403 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1404 return true; 1405 1406 // Only known if known in both the LHS and RHS. 1407 KnownOne &= KnownOne2; 1408 KnownZero &= KnownZero2; 1409 break; 1410 case ISD::SELECT_CC: 1411 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1412 KnownOne, TLO, Depth+1)) 1413 return true; 1414 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1415 KnownOne2, TLO, Depth+1)) 1416 return true; 1417 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1418 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1419 1420 // If the operands are constants, see if we can simplify them. 1421 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1422 return true; 1423 1424 // Only known if known in both the LHS and RHS. 1425 KnownOne &= KnownOne2; 1426 KnownZero &= KnownZero2; 1427 break; 1428 case ISD::SHL: 1429 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1430 unsigned ShAmt = SA->getZExtValue(); 1431 SDValue InOp = Op.getOperand(0); 1432 1433 // If the shift count is an invalid immediate, don't do anything. 1434 if (ShAmt >= BitWidth) 1435 break; 1436 1437 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1438 // single shift. We can do this if the bottom bits (which are shifted 1439 // out) are never demanded. 1440 if (InOp.getOpcode() == ISD::SRL && 1441 isa<ConstantSDNode>(InOp.getOperand(1))) { 1442 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1443 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1444 unsigned Opc = ISD::SHL; 1445 int Diff = ShAmt-C1; 1446 if (Diff < 0) { 1447 Diff = -Diff; 1448 Opc = ISD::SRL; 1449 } 1450 1451 SDValue NewSA = 1452 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1453 EVT VT = Op.getValueType(); 1454 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1455 InOp.getOperand(0), NewSA)); 1456 } 1457 } 1458 1459 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1460 KnownZero, KnownOne, TLO, Depth+1)) 1461 return true; 1462 1463 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1464 // are not demanded. This will likely allow the anyext to be folded away. 1465 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1466 SDValue InnerOp = InOp.getNode()->getOperand(0); 1467 EVT InnerVT = InnerOp.getValueType(); 1468 unsigned InnerBits = InnerVT.getSizeInBits(); 1469 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 1470 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1471 EVT ShTy = getShiftAmountTy(InnerVT); 1472 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1473 ShTy = InnerVT; 1474 SDValue NarrowShl = 1475 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1476 TLO.DAG.getConstant(ShAmt, ShTy)); 1477 return 1478 TLO.CombineTo(Op, 1479 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1480 NarrowShl)); 1481 } 1482 } 1483 1484 KnownZero <<= SA->getZExtValue(); 1485 KnownOne <<= SA->getZExtValue(); 1486 // low bits known zero. 1487 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1488 } 1489 break; 1490 case ISD::SRL: 1491 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1492 EVT VT = Op.getValueType(); 1493 unsigned ShAmt = SA->getZExtValue(); 1494 unsigned VTSize = VT.getSizeInBits(); 1495 SDValue InOp = Op.getOperand(0); 1496 1497 // If the shift count is an invalid immediate, don't do anything. 1498 if (ShAmt >= BitWidth) 1499 break; 1500 1501 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1502 // single shift. We can do this if the top bits (which are shifted out) 1503 // are never demanded. 1504 if (InOp.getOpcode() == ISD::SHL && 1505 isa<ConstantSDNode>(InOp.getOperand(1))) { 1506 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1507 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1508 unsigned Opc = ISD::SRL; 1509 int Diff = ShAmt-C1; 1510 if (Diff < 0) { 1511 Diff = -Diff; 1512 Opc = ISD::SHL; 1513 } 1514 1515 SDValue NewSA = 1516 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1517 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1518 InOp.getOperand(0), NewSA)); 1519 } 1520 } 1521 1522 // Compute the new bits that are at the top now. 1523 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1524 KnownZero, KnownOne, TLO, Depth+1)) 1525 return true; 1526 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1527 KnownZero = KnownZero.lshr(ShAmt); 1528 KnownOne = KnownOne.lshr(ShAmt); 1529 1530 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1531 KnownZero |= HighBits; // High bits known zero. 1532 } 1533 break; 1534 case ISD::SRA: 1535 // If this is an arithmetic shift right and only the low-bit is set, we can 1536 // always convert this into a logical shr, even if the shift amount is 1537 // variable. The low bit of the shift cannot be an input sign bit unless 1538 // the shift amount is >= the size of the datatype, which is undefined. 1539 if (NewMask == 1) 1540 return TLO.CombineTo(Op, 1541 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1542 Op.getOperand(0), Op.getOperand(1))); 1543 1544 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1545 EVT VT = Op.getValueType(); 1546 unsigned ShAmt = SA->getZExtValue(); 1547 1548 // If the shift count is an invalid immediate, don't do anything. 1549 if (ShAmt >= BitWidth) 1550 break; 1551 1552 APInt InDemandedMask = (NewMask << ShAmt); 1553 1554 // If any of the demanded bits are produced by the sign extension, we also 1555 // demand the input sign bit. 1556 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1557 if (HighBits.intersects(NewMask)) 1558 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1559 1560 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1561 KnownZero, KnownOne, TLO, Depth+1)) 1562 return true; 1563 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1564 KnownZero = KnownZero.lshr(ShAmt); 1565 KnownOne = KnownOne.lshr(ShAmt); 1566 1567 // Handle the sign bit, adjusted to where it is now in the mask. 1568 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1569 1570 // If the input sign bit is known to be zero, or if none of the top bits 1571 // are demanded, turn this into an unsigned shift right. 1572 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1573 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1574 Op.getOperand(0), 1575 Op.getOperand(1))); 1576 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1577 KnownOne |= HighBits; 1578 } 1579 } 1580 break; 1581 case ISD::SIGN_EXTEND_INREG: { 1582 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1583 1584 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 1585 // If we only care about the highest bit, don't bother shifting right. 1586 if (MsbMask == DemandedMask) { 1587 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 1588 SDValue InOp = Op.getOperand(0); 1589 1590 // Compute the correct shift amount type, which must be getShiftAmountTy 1591 // for scalar types after legalization. 1592 EVT ShiftAmtTy = Op.getValueType(); 1593 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 1594 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 1595 1596 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 1597 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1598 Op.getValueType(), InOp, ShiftAmt)); 1599 } 1600 1601 // Sign extension. Compute the demanded bits in the result that are not 1602 // present in the input. 1603 APInt NewBits = 1604 APInt::getHighBitsSet(BitWidth, 1605 BitWidth - ExVT.getScalarType().getSizeInBits()); 1606 1607 // If none of the extended bits are demanded, eliminate the sextinreg. 1608 if ((NewBits & NewMask) == 0) 1609 return TLO.CombineTo(Op, Op.getOperand(0)); 1610 1611 APInt InSignBit = 1612 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 1613 APInt InputDemandedBits = 1614 APInt::getLowBitsSet(BitWidth, 1615 ExVT.getScalarType().getSizeInBits()) & 1616 NewMask; 1617 1618 // Since the sign extended bits are demanded, we know that the sign 1619 // bit is demanded. 1620 InputDemandedBits |= InSignBit; 1621 1622 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1623 KnownZero, KnownOne, TLO, Depth+1)) 1624 return true; 1625 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1626 1627 // If the sign bit of the input is known set or clear, then we know the 1628 // top bits of the result. 1629 1630 // If the input sign bit is known zero, convert this into a zero extension. 1631 if (KnownZero.intersects(InSignBit)) 1632 return TLO.CombineTo(Op, 1633 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 1634 1635 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1636 KnownOne |= NewBits; 1637 KnownZero &= ~NewBits; 1638 } else { // Input sign bit unknown 1639 KnownZero &= ~NewBits; 1640 KnownOne &= ~NewBits; 1641 } 1642 break; 1643 } 1644 case ISD::ZERO_EXTEND: { 1645 unsigned OperandBitWidth = 1646 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1647 APInt InMask = NewMask.trunc(OperandBitWidth); 1648 1649 // If none of the top bits are demanded, convert this into an any_extend. 1650 APInt NewBits = 1651 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1652 if (!NewBits.intersects(NewMask)) 1653 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1654 Op.getValueType(), 1655 Op.getOperand(0))); 1656 1657 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1658 KnownZero, KnownOne, TLO, Depth+1)) 1659 return true; 1660 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1661 KnownZero = KnownZero.zext(BitWidth); 1662 KnownOne = KnownOne.zext(BitWidth); 1663 KnownZero |= NewBits; 1664 break; 1665 } 1666 case ISD::SIGN_EXTEND: { 1667 EVT InVT = Op.getOperand(0).getValueType(); 1668 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1669 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1670 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1671 APInt NewBits = ~InMask & NewMask; 1672 1673 // If none of the top bits are demanded, convert this into an any_extend. 1674 if (NewBits == 0) 1675 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1676 Op.getValueType(), 1677 Op.getOperand(0))); 1678 1679 // Since some of the sign extended bits are demanded, we know that the sign 1680 // bit is demanded. 1681 APInt InDemandedBits = InMask & NewMask; 1682 InDemandedBits |= InSignBit; 1683 InDemandedBits = InDemandedBits.trunc(InBits); 1684 1685 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1686 KnownOne, TLO, Depth+1)) 1687 return true; 1688 KnownZero = KnownZero.zext(BitWidth); 1689 KnownOne = KnownOne.zext(BitWidth); 1690 1691 // If the sign bit is known zero, convert this to a zero extend. 1692 if (KnownZero.intersects(InSignBit)) 1693 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1694 Op.getValueType(), 1695 Op.getOperand(0))); 1696 1697 // If the sign bit is known one, the top bits match. 1698 if (KnownOne.intersects(InSignBit)) { 1699 KnownOne |= NewBits; 1700 assert((KnownZero & NewBits) == 0); 1701 } else { // Otherwise, top bits aren't known. 1702 assert((KnownOne & NewBits) == 0); 1703 assert((KnownZero & NewBits) == 0); 1704 } 1705 break; 1706 } 1707 case ISD::ANY_EXTEND: { 1708 unsigned OperandBitWidth = 1709 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1710 APInt InMask = NewMask.trunc(OperandBitWidth); 1711 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1712 KnownZero, KnownOne, TLO, Depth+1)) 1713 return true; 1714 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1715 KnownZero = KnownZero.zext(BitWidth); 1716 KnownOne = KnownOne.zext(BitWidth); 1717 break; 1718 } 1719 case ISD::TRUNCATE: { 1720 // Simplify the input, using demanded bit information, and compute the known 1721 // zero/one bits live out. 1722 unsigned OperandBitWidth = 1723 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1724 APInt TruncMask = NewMask.zext(OperandBitWidth); 1725 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1726 KnownZero, KnownOne, TLO, Depth+1)) 1727 return true; 1728 KnownZero = KnownZero.trunc(BitWidth); 1729 KnownOne = KnownOne.trunc(BitWidth); 1730 1731 // If the input is only used by this truncate, see if we can shrink it based 1732 // on the known demanded bits. 1733 if (Op.getOperand(0).getNode()->hasOneUse()) { 1734 SDValue In = Op.getOperand(0); 1735 switch (In.getOpcode()) { 1736 default: break; 1737 case ISD::SRL: 1738 // Shrink SRL by a constant if none of the high bits shifted in are 1739 // demanded. 1740 if (TLO.LegalTypes() && 1741 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1742 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1743 // undesirable. 1744 break; 1745 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1746 if (!ShAmt) 1747 break; 1748 SDValue Shift = In.getOperand(1); 1749 if (TLO.LegalTypes()) { 1750 uint64_t ShVal = ShAmt->getZExtValue(); 1751 Shift = 1752 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1753 } 1754 1755 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1756 OperandBitWidth - BitWidth); 1757 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1758 1759 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1760 // None of the shifted in bits are needed. Add a truncate of the 1761 // shift input, then shift it. 1762 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1763 Op.getValueType(), 1764 In.getOperand(0)); 1765 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1766 Op.getValueType(), 1767 NewTrunc, 1768 Shift)); 1769 } 1770 break; 1771 } 1772 } 1773 1774 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1775 break; 1776 } 1777 case ISD::AssertZext: { 1778 // AssertZext demands all of the high bits, plus any of the low bits 1779 // demanded by its users. 1780 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1781 APInt InMask = APInt::getLowBitsSet(BitWidth, 1782 VT.getSizeInBits()); 1783 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 1784 KnownZero, KnownOne, TLO, Depth+1)) 1785 return true; 1786 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1787 1788 KnownZero |= ~InMask & NewMask; 1789 break; 1790 } 1791 case ISD::BITCAST: 1792 // If this is an FP->Int bitcast and if the sign bit is the only 1793 // thing demanded, turn this into a FGETSIGN. 1794 if (!TLO.LegalOperations() && 1795 !Op.getValueType().isVector() && 1796 !Op.getOperand(0).getValueType().isVector() && 1797 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1798 Op.getOperand(0).getValueType().isFloatingPoint()) { 1799 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1800 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1801 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1802 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1803 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1804 // place. We expect the SHL to be eliminated by other optimizations. 1805 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1806 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1807 if (!OpVTLegal && OpVTSizeInBits > 32) 1808 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1809 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1810 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1811 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1812 Op.getValueType(), 1813 Sign, ShAmt)); 1814 } 1815 } 1816 break; 1817 case ISD::ADD: 1818 case ISD::MUL: 1819 case ISD::SUB: { 1820 // Add, Sub, and Mul don't demand any bits in positions beyond that 1821 // of the highest bit demanded of them. 1822 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1823 BitWidth - NewMask.countLeadingZeros()); 1824 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1825 KnownOne2, TLO, Depth+1)) 1826 return true; 1827 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1828 KnownOne2, TLO, Depth+1)) 1829 return true; 1830 // See if the operation should be performed at a smaller bit width. 1831 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1832 return true; 1833 } 1834 // FALL THROUGH 1835 default: 1836 // Just use ComputeMaskedBits to compute output bits. 1837 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1838 break; 1839 } 1840 1841 // If we know the value of all of the demanded bits, return this as a 1842 // constant. 1843 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1844 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1845 1846 return false; 1847 } 1848 1849 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 1850 /// in Mask are known to be either zero or one and return them in the 1851 /// KnownZero/KnownOne bitsets. 1852 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1853 APInt &KnownZero, 1854 APInt &KnownOne, 1855 const SelectionDAG &DAG, 1856 unsigned Depth) const { 1857 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1858 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1859 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1860 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1861 "Should use MaskedValueIsZero if you don't know whether Op" 1862 " is a target node!"); 1863 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1864 } 1865 1866 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1867 /// targets that want to expose additional information about sign bits to the 1868 /// DAG Combiner. 1869 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1870 unsigned Depth) const { 1871 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1872 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1873 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1874 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1875 "Should use ComputeNumSignBits if you don't know whether Op" 1876 " is a target node!"); 1877 return 1; 1878 } 1879 1880 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1881 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1882 /// determine which bit is set. 1883 /// 1884 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1885 // A left-shift of a constant one will have exactly one bit set, because 1886 // shifting the bit off the end is undefined. 1887 if (Val.getOpcode() == ISD::SHL) 1888 if (ConstantSDNode *C = 1889 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1890 if (C->getAPIntValue() == 1) 1891 return true; 1892 1893 // Similarly, a right-shift of a constant sign-bit will have exactly 1894 // one bit set. 1895 if (Val.getOpcode() == ISD::SRL) 1896 if (ConstantSDNode *C = 1897 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1898 if (C->getAPIntValue().isSignBit()) 1899 return true; 1900 1901 // More could be done here, though the above checks are enough 1902 // to handle some common cases. 1903 1904 // Fall back to ComputeMaskedBits to catch other known cases. 1905 EVT OpVT = Val.getValueType(); 1906 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1907 APInt KnownZero, KnownOne; 1908 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 1909 return (KnownZero.countPopulation() == BitWidth - 1) && 1910 (KnownOne.countPopulation() == 1); 1911 } 1912 1913 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1914 /// and cc. If it is unable to simplify it, return a null SDValue. 1915 SDValue 1916 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1917 ISD::CondCode Cond, bool foldBooleans, 1918 DAGCombinerInfo &DCI, DebugLoc dl) const { 1919 SelectionDAG &DAG = DCI.DAG; 1920 1921 // These setcc operations always fold. 1922 switch (Cond) { 1923 default: break; 1924 case ISD::SETFALSE: 1925 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1926 case ISD::SETTRUE: 1927 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1928 } 1929 1930 // Ensure that the constant occurs on the RHS, and fold constant 1931 // comparisons. 1932 if (isa<ConstantSDNode>(N0.getNode())) 1933 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1934 1935 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1936 const APInt &C1 = N1C->getAPIntValue(); 1937 1938 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1939 // equality comparison, then we're just comparing whether X itself is 1940 // zero. 1941 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1942 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1943 N0.getOperand(1).getOpcode() == ISD::Constant) { 1944 const APInt &ShAmt 1945 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1946 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1947 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1948 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1949 // (srl (ctlz x), 5) == 0 -> X != 0 1950 // (srl (ctlz x), 5) != 1 -> X != 0 1951 Cond = ISD::SETNE; 1952 } else { 1953 // (srl (ctlz x), 5) != 0 -> X == 0 1954 // (srl (ctlz x), 5) == 1 -> X == 0 1955 Cond = ISD::SETEQ; 1956 } 1957 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1958 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1959 Zero, Cond); 1960 } 1961 } 1962 1963 SDValue CTPOP = N0; 1964 // Look through truncs that don't change the value of a ctpop. 1965 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1966 CTPOP = N0.getOperand(0); 1967 1968 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1969 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1970 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1971 EVT CTVT = CTPOP.getValueType(); 1972 SDValue CTOp = CTPOP.getOperand(0); 1973 1974 // (ctpop x) u< 2 -> (x & x-1) == 0 1975 // (ctpop x) u> 1 -> (x & x-1) != 0 1976 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1977 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1978 DAG.getConstant(1, CTVT)); 1979 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1980 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1981 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1982 } 1983 1984 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1985 } 1986 1987 // (zext x) == C --> x == (trunc C) 1988 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1989 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1990 unsigned MinBits = N0.getValueSizeInBits(); 1991 SDValue PreZExt; 1992 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1993 // ZExt 1994 MinBits = N0->getOperand(0).getValueSizeInBits(); 1995 PreZExt = N0->getOperand(0); 1996 } else if (N0->getOpcode() == ISD::AND) { 1997 // DAGCombine turns costly ZExts into ANDs 1998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1999 if ((C->getAPIntValue()+1).isPowerOf2()) { 2000 MinBits = C->getAPIntValue().countTrailingOnes(); 2001 PreZExt = N0->getOperand(0); 2002 } 2003 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 2004 // ZEXTLOAD 2005 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 2006 MinBits = LN0->getMemoryVT().getSizeInBits(); 2007 PreZExt = N0; 2008 } 2009 } 2010 2011 // Make sure we're not loosing bits from the constant. 2012 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 2013 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 2014 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 2015 // Will get folded away. 2016 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 2017 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 2018 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 2019 } 2020 } 2021 } 2022 2023 // If the LHS is '(and load, const)', the RHS is 0, 2024 // the test is for equality or unsigned, and all 1 bits of the const are 2025 // in the same partial word, see if we can shorten the load. 2026 if (DCI.isBeforeLegalize() && 2027 N0.getOpcode() == ISD::AND && C1 == 0 && 2028 N0.getNode()->hasOneUse() && 2029 isa<LoadSDNode>(N0.getOperand(0)) && 2030 N0.getOperand(0).getNode()->hasOneUse() && 2031 isa<ConstantSDNode>(N0.getOperand(1))) { 2032 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 2033 APInt bestMask; 2034 unsigned bestWidth = 0, bestOffset = 0; 2035 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2036 unsigned origWidth = N0.getValueType().getSizeInBits(); 2037 unsigned maskWidth = origWidth; 2038 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2039 // 8 bits, but have to be careful... 2040 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2041 origWidth = Lod->getMemoryVT().getSizeInBits(); 2042 const APInt &Mask = 2043 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2044 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2045 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2046 for (unsigned offset=0; offset<origWidth/width; offset++) { 2047 if ((newMask & Mask) == Mask) { 2048 if (!TD->isLittleEndian()) 2049 bestOffset = (origWidth/width - offset - 1) * (width/8); 2050 else 2051 bestOffset = (uint64_t)offset * (width/8); 2052 bestMask = Mask.lshr(offset * (width/8) * 8); 2053 bestWidth = width; 2054 break; 2055 } 2056 newMask = newMask << width; 2057 } 2058 } 2059 } 2060 if (bestWidth) { 2061 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2062 if (newVT.isRound()) { 2063 EVT PtrType = Lod->getOperand(1).getValueType(); 2064 SDValue Ptr = Lod->getBasePtr(); 2065 if (bestOffset != 0) 2066 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2067 DAG.getConstant(bestOffset, PtrType)); 2068 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2069 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2070 Lod->getPointerInfo().getWithOffset(bestOffset), 2071 false, false, false, NewAlign); 2072 return DAG.getSetCC(dl, VT, 2073 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2074 DAG.getConstant(bestMask.trunc(bestWidth), 2075 newVT)), 2076 DAG.getConstant(0LL, newVT), Cond); 2077 } 2078 } 2079 } 2080 2081 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2082 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2083 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2084 2085 // If the comparison constant has bits in the upper part, the 2086 // zero-extended value could never match. 2087 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2088 C1.getBitWidth() - InSize))) { 2089 switch (Cond) { 2090 case ISD::SETUGT: 2091 case ISD::SETUGE: 2092 case ISD::SETEQ: return DAG.getConstant(0, VT); 2093 case ISD::SETULT: 2094 case ISD::SETULE: 2095 case ISD::SETNE: return DAG.getConstant(1, VT); 2096 case ISD::SETGT: 2097 case ISD::SETGE: 2098 // True if the sign bit of C1 is set. 2099 return DAG.getConstant(C1.isNegative(), VT); 2100 case ISD::SETLT: 2101 case ISD::SETLE: 2102 // True if the sign bit of C1 isn't set. 2103 return DAG.getConstant(C1.isNonNegative(), VT); 2104 default: 2105 break; 2106 } 2107 } 2108 2109 // Otherwise, we can perform the comparison with the low bits. 2110 switch (Cond) { 2111 case ISD::SETEQ: 2112 case ISD::SETNE: 2113 case ISD::SETUGT: 2114 case ISD::SETUGE: 2115 case ISD::SETULT: 2116 case ISD::SETULE: { 2117 EVT newVT = N0.getOperand(0).getValueType(); 2118 if (DCI.isBeforeLegalizeOps() || 2119 (isOperationLegal(ISD::SETCC, newVT) && 2120 getCondCodeAction(Cond, newVT)==Legal)) 2121 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2122 DAG.getConstant(C1.trunc(InSize), newVT), 2123 Cond); 2124 break; 2125 } 2126 default: 2127 break; // todo, be more careful with signed comparisons 2128 } 2129 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2130 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2131 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2132 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2133 EVT ExtDstTy = N0.getValueType(); 2134 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2135 2136 // If the constant doesn't fit into the number of bits for the source of 2137 // the sign extension, it is impossible for both sides to be equal. 2138 if (C1.getMinSignedBits() > ExtSrcTyBits) 2139 return DAG.getConstant(Cond == ISD::SETNE, VT); 2140 2141 SDValue ZextOp; 2142 EVT Op0Ty = N0.getOperand(0).getValueType(); 2143 if (Op0Ty == ExtSrcTy) { 2144 ZextOp = N0.getOperand(0); 2145 } else { 2146 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2147 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2148 DAG.getConstant(Imm, Op0Ty)); 2149 } 2150 if (!DCI.isCalledByLegalizer()) 2151 DCI.AddToWorklist(ZextOp.getNode()); 2152 // Otherwise, make this a use of a zext. 2153 return DAG.getSetCC(dl, VT, ZextOp, 2154 DAG.getConstant(C1 & APInt::getLowBitsSet( 2155 ExtDstTyBits, 2156 ExtSrcTyBits), 2157 ExtDstTy), 2158 Cond); 2159 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2160 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2161 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2162 if (N0.getOpcode() == ISD::SETCC && 2163 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2164 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2165 if (TrueWhenTrue) 2166 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2167 // Invert the condition. 2168 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2169 CC = ISD::getSetCCInverse(CC, 2170 N0.getOperand(0).getValueType().isInteger()); 2171 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2172 } 2173 2174 if ((N0.getOpcode() == ISD::XOR || 2175 (N0.getOpcode() == ISD::AND && 2176 N0.getOperand(0).getOpcode() == ISD::XOR && 2177 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2178 isa<ConstantSDNode>(N0.getOperand(1)) && 2179 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2180 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2181 // can only do this if the top bits are known zero. 2182 unsigned BitWidth = N0.getValueSizeInBits(); 2183 if (DAG.MaskedValueIsZero(N0, 2184 APInt::getHighBitsSet(BitWidth, 2185 BitWidth-1))) { 2186 // Okay, get the un-inverted input value. 2187 SDValue Val; 2188 if (N0.getOpcode() == ISD::XOR) 2189 Val = N0.getOperand(0); 2190 else { 2191 assert(N0.getOpcode() == ISD::AND && 2192 N0.getOperand(0).getOpcode() == ISD::XOR); 2193 // ((X^1)&1)^1 -> X & 1 2194 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2195 N0.getOperand(0).getOperand(0), 2196 N0.getOperand(1)); 2197 } 2198 2199 return DAG.getSetCC(dl, VT, Val, N1, 2200 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2201 } 2202 } else if (N1C->getAPIntValue() == 1 && 2203 (VT == MVT::i1 || 2204 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 2205 SDValue Op0 = N0; 2206 if (Op0.getOpcode() == ISD::TRUNCATE) 2207 Op0 = Op0.getOperand(0); 2208 2209 if ((Op0.getOpcode() == ISD::XOR) && 2210 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2211 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2212 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2213 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2214 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2215 Cond); 2216 } else if (Op0.getOpcode() == ISD::AND && 2217 isa<ConstantSDNode>(Op0.getOperand(1)) && 2218 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2219 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2220 if (Op0.getValueType().bitsGT(VT)) 2221 Op0 = DAG.getNode(ISD::AND, dl, VT, 2222 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2223 DAG.getConstant(1, VT)); 2224 else if (Op0.getValueType().bitsLT(VT)) 2225 Op0 = DAG.getNode(ISD::AND, dl, VT, 2226 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2227 DAG.getConstant(1, VT)); 2228 2229 return DAG.getSetCC(dl, VT, Op0, 2230 DAG.getConstant(0, Op0.getValueType()), 2231 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2232 } 2233 } 2234 } 2235 2236 APInt MinVal, MaxVal; 2237 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2238 if (ISD::isSignedIntSetCC(Cond)) { 2239 MinVal = APInt::getSignedMinValue(OperandBitSize); 2240 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2241 } else { 2242 MinVal = APInt::getMinValue(OperandBitSize); 2243 MaxVal = APInt::getMaxValue(OperandBitSize); 2244 } 2245 2246 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2247 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2248 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2249 // X >= C0 --> X > (C0-1) 2250 return DAG.getSetCC(dl, VT, N0, 2251 DAG.getConstant(C1-1, N1.getValueType()), 2252 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2253 } 2254 2255 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2256 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2257 // X <= C0 --> X < (C0+1) 2258 return DAG.getSetCC(dl, VT, N0, 2259 DAG.getConstant(C1+1, N1.getValueType()), 2260 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2261 } 2262 2263 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2264 return DAG.getConstant(0, VT); // X < MIN --> false 2265 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2266 return DAG.getConstant(1, VT); // X >= MIN --> true 2267 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2268 return DAG.getConstant(0, VT); // X > MAX --> false 2269 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2270 return DAG.getConstant(1, VT); // X <= MAX --> true 2271 2272 // Canonicalize setgt X, Min --> setne X, Min 2273 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2274 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2275 // Canonicalize setlt X, Max --> setne X, Max 2276 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2277 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2278 2279 // If we have setult X, 1, turn it into seteq X, 0 2280 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2281 return DAG.getSetCC(dl, VT, N0, 2282 DAG.getConstant(MinVal, N0.getValueType()), 2283 ISD::SETEQ); 2284 // If we have setugt X, Max-1, turn it into seteq X, Max 2285 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2286 return DAG.getSetCC(dl, VT, N0, 2287 DAG.getConstant(MaxVal, N0.getValueType()), 2288 ISD::SETEQ); 2289 2290 // If we have "setcc X, C0", check to see if we can shrink the immediate 2291 // by changing cc. 2292 2293 // SETUGT X, SINTMAX -> SETLT X, 0 2294 if (Cond == ISD::SETUGT && 2295 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2296 return DAG.getSetCC(dl, VT, N0, 2297 DAG.getConstant(0, N1.getValueType()), 2298 ISD::SETLT); 2299 2300 // SETULT X, SINTMIN -> SETGT X, -1 2301 if (Cond == ISD::SETULT && 2302 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2303 SDValue ConstMinusOne = 2304 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2305 N1.getValueType()); 2306 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2307 } 2308 2309 // Fold bit comparisons when we can. 2310 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2311 (VT == N0.getValueType() || 2312 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2313 N0.getOpcode() == ISD::AND) 2314 if (ConstantSDNode *AndRHS = 2315 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2316 EVT ShiftTy = DCI.isBeforeLegalize() ? 2317 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2318 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2319 // Perform the xform if the AND RHS is a single bit. 2320 if (AndRHS->getAPIntValue().isPowerOf2()) { 2321 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2322 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2323 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2324 } 2325 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2326 // (X & 8) == 8 --> (X & 8) >> 3 2327 // Perform the xform if C1 is a single bit. 2328 if (C1.isPowerOf2()) { 2329 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2330 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2331 DAG.getConstant(C1.logBase2(), ShiftTy))); 2332 } 2333 } 2334 } 2335 } 2336 2337 if (isa<ConstantFPSDNode>(N0.getNode())) { 2338 // Constant fold or commute setcc. 2339 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2340 if (O.getNode()) return O; 2341 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2342 // If the RHS of an FP comparison is a constant, simplify it away in 2343 // some cases. 2344 if (CFP->getValueAPF().isNaN()) { 2345 // If an operand is known to be a nan, we can fold it. 2346 switch (ISD::getUnorderedFlavor(Cond)) { 2347 default: llvm_unreachable("Unknown flavor!"); 2348 case 0: // Known false. 2349 return DAG.getConstant(0, VT); 2350 case 1: // Known true. 2351 return DAG.getConstant(1, VT); 2352 case 2: // Undefined. 2353 return DAG.getUNDEF(VT); 2354 } 2355 } 2356 2357 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2358 // constant if knowing that the operand is non-nan is enough. We prefer to 2359 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2360 // materialize 0.0. 2361 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2362 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2363 2364 // If the condition is not legal, see if we can find an equivalent one 2365 // which is legal. 2366 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2367 // If the comparison was an awkward floating-point == or != and one of 2368 // the comparison operands is infinity or negative infinity, convert the 2369 // condition to a less-awkward <= or >=. 2370 if (CFP->getValueAPF().isInfinity()) { 2371 if (CFP->getValueAPF().isNegative()) { 2372 if (Cond == ISD::SETOEQ && 2373 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2374 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2375 if (Cond == ISD::SETUEQ && 2376 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2377 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2378 if (Cond == ISD::SETUNE && 2379 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2380 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2381 if (Cond == ISD::SETONE && 2382 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2383 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2384 } else { 2385 if (Cond == ISD::SETOEQ && 2386 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2387 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2388 if (Cond == ISD::SETUEQ && 2389 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2390 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2391 if (Cond == ISD::SETUNE && 2392 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2393 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2394 if (Cond == ISD::SETONE && 2395 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2396 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2397 } 2398 } 2399 } 2400 } 2401 2402 if (N0 == N1) { 2403 // We can always fold X == X for integer setcc's. 2404 if (N0.getValueType().isInteger()) { 2405 switch (getBooleanContents(N0.getValueType().isVector())) { 2406 case UndefinedBooleanContent: 2407 case ZeroOrOneBooleanContent: 2408 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2409 case ZeroOrNegativeOneBooleanContent: 2410 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT); 2411 } 2412 } 2413 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2414 if (UOF == 2) // FP operators that are undefined on NaNs. 2415 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2416 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2417 return DAG.getConstant(UOF, VT); 2418 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2419 // if it is not already. 2420 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2421 if (NewCond != Cond) 2422 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2423 } 2424 2425 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2426 N0.getValueType().isInteger()) { 2427 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2428 N0.getOpcode() == ISD::XOR) { 2429 // Simplify (X+Y) == (X+Z) --> Y == Z 2430 if (N0.getOpcode() == N1.getOpcode()) { 2431 if (N0.getOperand(0) == N1.getOperand(0)) 2432 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2433 if (N0.getOperand(1) == N1.getOperand(1)) 2434 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2435 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2436 // If X op Y == Y op X, try other combinations. 2437 if (N0.getOperand(0) == N1.getOperand(1)) 2438 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2439 Cond); 2440 if (N0.getOperand(1) == N1.getOperand(0)) 2441 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2442 Cond); 2443 } 2444 } 2445 2446 // If RHS is a legal immediate value for a compare instruction, we need 2447 // to be careful about increasing register pressure needlessly. 2448 bool LegalRHSImm = false; 2449 2450 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2451 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2452 // Turn (X+C1) == C2 --> X == C2-C1 2453 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2454 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2455 DAG.getConstant(RHSC->getAPIntValue()- 2456 LHSR->getAPIntValue(), 2457 N0.getValueType()), Cond); 2458 } 2459 2460 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2461 if (N0.getOpcode() == ISD::XOR) 2462 // If we know that all of the inverted bits are zero, don't bother 2463 // performing the inversion. 2464 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2465 return 2466 DAG.getSetCC(dl, VT, N0.getOperand(0), 2467 DAG.getConstant(LHSR->getAPIntValue() ^ 2468 RHSC->getAPIntValue(), 2469 N0.getValueType()), 2470 Cond); 2471 } 2472 2473 // Turn (C1-X) == C2 --> X == C1-C2 2474 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2475 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2476 return 2477 DAG.getSetCC(dl, VT, N0.getOperand(1), 2478 DAG.getConstant(SUBC->getAPIntValue() - 2479 RHSC->getAPIntValue(), 2480 N0.getValueType()), 2481 Cond); 2482 } 2483 } 2484 2485 // Could RHSC fold directly into a compare? 2486 if (RHSC->getValueType(0).getSizeInBits() <= 64) 2487 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 2488 } 2489 2490 // Simplify (X+Z) == X --> Z == 0 2491 // Don't do this if X is an immediate that can fold into a cmp 2492 // instruction and X+Z has other uses. It could be an induction variable 2493 // chain, and the transform would increase register pressure. 2494 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 2495 if (N0.getOperand(0) == N1) 2496 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2497 DAG.getConstant(0, N0.getValueType()), Cond); 2498 if (N0.getOperand(1) == N1) { 2499 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2500 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2501 DAG.getConstant(0, N0.getValueType()), Cond); 2502 else if (N0.getNode()->hasOneUse()) { 2503 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2504 // (Z-X) == X --> Z == X<<1 2505 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 2506 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2507 if (!DCI.isCalledByLegalizer()) 2508 DCI.AddToWorklist(SH.getNode()); 2509 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2510 } 2511 } 2512 } 2513 } 2514 2515 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2516 N1.getOpcode() == ISD::XOR) { 2517 // Simplify X == (X+Z) --> Z == 0 2518 if (N1.getOperand(0) == N0) { 2519 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2520 DAG.getConstant(0, N1.getValueType()), Cond); 2521 } else if (N1.getOperand(1) == N0) { 2522 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2523 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2524 DAG.getConstant(0, N1.getValueType()), Cond); 2525 } else if (N1.getNode()->hasOneUse()) { 2526 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2527 // X == (Z-X) --> X<<1 == Z 2528 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2529 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2530 if (!DCI.isCalledByLegalizer()) 2531 DCI.AddToWorklist(SH.getNode()); 2532 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2533 } 2534 } 2535 } 2536 2537 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2538 // Note that where y is variable and is known to have at most 2539 // one bit set (for example, if it is z&1) we cannot do this; 2540 // the expressions are not equivalent when y==0. 2541 if (N0.getOpcode() == ISD::AND) 2542 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2543 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2544 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2545 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2546 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2547 } 2548 } 2549 if (N1.getOpcode() == ISD::AND) 2550 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2551 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2552 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2553 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2554 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2555 } 2556 } 2557 } 2558 2559 // Fold away ALL boolean setcc's. 2560 SDValue Temp; 2561 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2562 switch (Cond) { 2563 default: llvm_unreachable("Unknown integer setcc!"); 2564 case ISD::SETEQ: // X == Y -> ~(X^Y) 2565 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2566 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2567 if (!DCI.isCalledByLegalizer()) 2568 DCI.AddToWorklist(Temp.getNode()); 2569 break; 2570 case ISD::SETNE: // X != Y --> (X^Y) 2571 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2572 break; 2573 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2574 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2575 Temp = DAG.getNOT(dl, N0, MVT::i1); 2576 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2577 if (!DCI.isCalledByLegalizer()) 2578 DCI.AddToWorklist(Temp.getNode()); 2579 break; 2580 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2581 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2582 Temp = DAG.getNOT(dl, N1, MVT::i1); 2583 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2584 if (!DCI.isCalledByLegalizer()) 2585 DCI.AddToWorklist(Temp.getNode()); 2586 break; 2587 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2588 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2589 Temp = DAG.getNOT(dl, N0, MVT::i1); 2590 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2591 if (!DCI.isCalledByLegalizer()) 2592 DCI.AddToWorklist(Temp.getNode()); 2593 break; 2594 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2595 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2596 Temp = DAG.getNOT(dl, N1, MVT::i1); 2597 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2598 break; 2599 } 2600 if (VT != MVT::i1) { 2601 if (!DCI.isCalledByLegalizer()) 2602 DCI.AddToWorklist(N0.getNode()); 2603 // FIXME: If running after legalize, we probably can't do this. 2604 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2605 } 2606 return N0; 2607 } 2608 2609 // Could not fold it. 2610 return SDValue(); 2611 } 2612 2613 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2614 /// node is a GlobalAddress + offset. 2615 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2616 int64_t &Offset) const { 2617 if (isa<GlobalAddressSDNode>(N)) { 2618 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2619 GA = GASD->getGlobal(); 2620 Offset += GASD->getOffset(); 2621 return true; 2622 } 2623 2624 if (N->getOpcode() == ISD::ADD) { 2625 SDValue N1 = N->getOperand(0); 2626 SDValue N2 = N->getOperand(1); 2627 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2628 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2629 if (V) { 2630 Offset += V->getSExtValue(); 2631 return true; 2632 } 2633 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2634 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2635 if (V) { 2636 Offset += V->getSExtValue(); 2637 return true; 2638 } 2639 } 2640 } 2641 2642 return false; 2643 } 2644 2645 2646 SDValue TargetLowering:: 2647 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2648 // Default implementation: no optimization. 2649 return SDValue(); 2650 } 2651 2652 //===----------------------------------------------------------------------===// 2653 // Inline Assembler Implementation Methods 2654 //===----------------------------------------------------------------------===// 2655 2656 2657 TargetLowering::ConstraintType 2658 TargetLowering::getConstraintType(const std::string &Constraint) const { 2659 if (Constraint.size() == 1) { 2660 switch (Constraint[0]) { 2661 default: break; 2662 case 'r': return C_RegisterClass; 2663 case 'm': // memory 2664 case 'o': // offsetable 2665 case 'V': // not offsetable 2666 return C_Memory; 2667 case 'i': // Simple Integer or Relocatable Constant 2668 case 'n': // Simple Integer 2669 case 'E': // Floating Point Constant 2670 case 'F': // Floating Point Constant 2671 case 's': // Relocatable Constant 2672 case 'p': // Address. 2673 case 'X': // Allow ANY value. 2674 case 'I': // Target registers. 2675 case 'J': 2676 case 'K': 2677 case 'L': 2678 case 'M': 2679 case 'N': 2680 case 'O': 2681 case 'P': 2682 case '<': 2683 case '>': 2684 return C_Other; 2685 } 2686 } 2687 2688 if (Constraint.size() > 1 && Constraint[0] == '{' && 2689 Constraint[Constraint.size()-1] == '}') 2690 return C_Register; 2691 return C_Unknown; 2692 } 2693 2694 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2695 /// with another that has more specific requirements based on the type of the 2696 /// corresponding operand. 2697 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2698 if (ConstraintVT.isInteger()) 2699 return "r"; 2700 if (ConstraintVT.isFloatingPoint()) 2701 return "f"; // works for many targets 2702 return 0; 2703 } 2704 2705 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2706 /// vector. If it is invalid, don't add anything to Ops. 2707 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2708 std::string &Constraint, 2709 std::vector<SDValue> &Ops, 2710 SelectionDAG &DAG) const { 2711 2712 if (Constraint.length() > 1) return; 2713 2714 char ConstraintLetter = Constraint[0]; 2715 switch (ConstraintLetter) { 2716 default: break; 2717 case 'X': // Allows any operand; labels (basic block) use this. 2718 if (Op.getOpcode() == ISD::BasicBlock) { 2719 Ops.push_back(Op); 2720 return; 2721 } 2722 // fall through 2723 case 'i': // Simple Integer or Relocatable Constant 2724 case 'n': // Simple Integer 2725 case 's': { // Relocatable Constant 2726 // These operands are interested in values of the form (GV+C), where C may 2727 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2728 // is possible and fine if either GV or C are missing. 2729 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2730 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2731 2732 // If we have "(add GV, C)", pull out GV/C 2733 if (Op.getOpcode() == ISD::ADD) { 2734 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2735 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2736 if (C == 0 || GA == 0) { 2737 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2738 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2739 } 2740 if (C == 0 || GA == 0) 2741 C = 0, GA = 0; 2742 } 2743 2744 // If we find a valid operand, map to the TargetXXX version so that the 2745 // value itself doesn't get selected. 2746 if (GA) { // Either &GV or &GV+C 2747 if (ConstraintLetter != 'n') { 2748 int64_t Offs = GA->getOffset(); 2749 if (C) Offs += C->getZExtValue(); 2750 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2751 C ? C->getDebugLoc() : DebugLoc(), 2752 Op.getValueType(), Offs)); 2753 return; 2754 } 2755 } 2756 if (C) { // just C, no GV. 2757 // Simple constants are not allowed for 's'. 2758 if (ConstraintLetter != 's') { 2759 // gcc prints these as sign extended. Sign extend value to 64 bits 2760 // now; without this it would get ZExt'd later in 2761 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2762 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2763 MVT::i64)); 2764 return; 2765 } 2766 } 2767 break; 2768 } 2769 } 2770 } 2771 2772 std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2773 getRegForInlineAsmConstraint(const std::string &Constraint, 2774 EVT VT) const { 2775 if (Constraint[0] != '{') 2776 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2777 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2778 2779 // Remove the braces from around the name. 2780 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2781 2782 // Figure out which register class contains this reg. 2783 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2784 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2785 E = RI->regclass_end(); RCI != E; ++RCI) { 2786 const TargetRegisterClass *RC = *RCI; 2787 2788 // If none of the value types for this register class are valid, we 2789 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2790 if (!isLegalRC(RC)) 2791 continue; 2792 2793 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2794 I != E; ++I) { 2795 if (RegName.equals_lower(RI->getName(*I))) 2796 return std::make_pair(*I, RC); 2797 } 2798 } 2799 2800 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2801 } 2802 2803 //===----------------------------------------------------------------------===// 2804 // Constraint Selection. 2805 2806 /// isMatchingInputConstraint - Return true of this is an input operand that is 2807 /// a matching constraint like "4". 2808 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2809 assert(!ConstraintCode.empty() && "No known constraint!"); 2810 return isdigit(ConstraintCode[0]); 2811 } 2812 2813 /// getMatchedOperand - If this is an input matching constraint, this method 2814 /// returns the output operand it matches. 2815 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2816 assert(!ConstraintCode.empty() && "No known constraint!"); 2817 return atoi(ConstraintCode.c_str()); 2818 } 2819 2820 2821 /// ParseConstraints - Split up the constraint string from the inline 2822 /// assembly value into the specific constraints and their prefixes, 2823 /// and also tie in the associated operand values. 2824 /// If this returns an empty vector, and if the constraint string itself 2825 /// isn't empty, there was an error parsing. 2826 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2827 ImmutableCallSite CS) const { 2828 /// ConstraintOperands - Information about all of the constraints. 2829 AsmOperandInfoVector ConstraintOperands; 2830 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2831 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2832 2833 // Do a prepass over the constraints, canonicalizing them, and building up the 2834 // ConstraintOperands list. 2835 InlineAsm::ConstraintInfoVector 2836 ConstraintInfos = IA->ParseConstraints(); 2837 2838 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2839 unsigned ResNo = 0; // ResNo - The result number of the next output. 2840 2841 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2842 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2843 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2844 2845 // Update multiple alternative constraint count. 2846 if (OpInfo.multipleAlternatives.size() > maCount) 2847 maCount = OpInfo.multipleAlternatives.size(); 2848 2849 OpInfo.ConstraintVT = MVT::Other; 2850 2851 // Compute the value type for each operand. 2852 switch (OpInfo.Type) { 2853 case InlineAsm::isOutput: 2854 // Indirect outputs just consume an argument. 2855 if (OpInfo.isIndirect) { 2856 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2857 break; 2858 } 2859 2860 // The return value of the call is this value. As such, there is no 2861 // corresponding argument. 2862 assert(!CS.getType()->isVoidTy() && 2863 "Bad inline asm!"); 2864 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2865 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2866 } else { 2867 assert(ResNo == 0 && "Asm only has one result!"); 2868 OpInfo.ConstraintVT = getValueType(CS.getType()); 2869 } 2870 ++ResNo; 2871 break; 2872 case InlineAsm::isInput: 2873 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2874 break; 2875 case InlineAsm::isClobber: 2876 // Nothing to do. 2877 break; 2878 } 2879 2880 if (OpInfo.CallOperandVal) { 2881 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2882 if (OpInfo.isIndirect) { 2883 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2884 if (!PtrTy) 2885 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2886 OpTy = PtrTy->getElementType(); 2887 } 2888 2889 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2890 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2891 if (STy->getNumElements() == 1) 2892 OpTy = STy->getElementType(0); 2893 2894 // If OpTy is not a single value, it may be a struct/union that we 2895 // can tile with integers. 2896 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2897 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2898 switch (BitSize) { 2899 default: break; 2900 case 1: 2901 case 8: 2902 case 16: 2903 case 32: 2904 case 64: 2905 case 128: 2906 OpInfo.ConstraintVT = 2907 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2908 break; 2909 } 2910 } else if (dyn_cast<PointerType>(OpTy)) { 2911 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2912 } else { 2913 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2914 } 2915 } 2916 } 2917 2918 // If we have multiple alternative constraints, select the best alternative. 2919 if (ConstraintInfos.size()) { 2920 if (maCount) { 2921 unsigned bestMAIndex = 0; 2922 int bestWeight = -1; 2923 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2924 int weight = -1; 2925 unsigned maIndex; 2926 // Compute the sums of the weights for each alternative, keeping track 2927 // of the best (highest weight) one so far. 2928 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2929 int weightSum = 0; 2930 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2931 cIndex != eIndex; ++cIndex) { 2932 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2933 if (OpInfo.Type == InlineAsm::isClobber) 2934 continue; 2935 2936 // If this is an output operand with a matching input operand, 2937 // look up the matching input. If their types mismatch, e.g. one 2938 // is an integer, the other is floating point, or their sizes are 2939 // different, flag it as an maCantMatch. 2940 if (OpInfo.hasMatchingInput()) { 2941 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2942 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2943 if ((OpInfo.ConstraintVT.isInteger() != 2944 Input.ConstraintVT.isInteger()) || 2945 (OpInfo.ConstraintVT.getSizeInBits() != 2946 Input.ConstraintVT.getSizeInBits())) { 2947 weightSum = -1; // Can't match. 2948 break; 2949 } 2950 } 2951 } 2952 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2953 if (weight == -1) { 2954 weightSum = -1; 2955 break; 2956 } 2957 weightSum += weight; 2958 } 2959 // Update best. 2960 if (weightSum > bestWeight) { 2961 bestWeight = weightSum; 2962 bestMAIndex = maIndex; 2963 } 2964 } 2965 2966 // Now select chosen alternative in each constraint. 2967 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2968 cIndex != eIndex; ++cIndex) { 2969 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2970 if (cInfo.Type == InlineAsm::isClobber) 2971 continue; 2972 cInfo.selectAlternative(bestMAIndex); 2973 } 2974 } 2975 } 2976 2977 // Check and hook up tied operands, choose constraint code to use. 2978 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2979 cIndex != eIndex; ++cIndex) { 2980 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2981 2982 // If this is an output operand with a matching input operand, look up the 2983 // matching input. If their types mismatch, e.g. one is an integer, the 2984 // other is floating point, or their sizes are different, flag it as an 2985 // error. 2986 if (OpInfo.hasMatchingInput()) { 2987 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2988 2989 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2990 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 2991 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 2992 std::pair<unsigned, const TargetRegisterClass*> InputRC = 2993 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 2994 if ((OpInfo.ConstraintVT.isInteger() != 2995 Input.ConstraintVT.isInteger()) || 2996 (MatchRC.second != InputRC.second)) { 2997 report_fatal_error("Unsupported asm: input constraint" 2998 " with a matching output constraint of" 2999 " incompatible type!"); 3000 } 3001 } 3002 3003 } 3004 } 3005 3006 return ConstraintOperands; 3007 } 3008 3009 3010 /// getConstraintGenerality - Return an integer indicating how general CT 3011 /// is. 3012 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3013 switch (CT) { 3014 case TargetLowering::C_Other: 3015 case TargetLowering::C_Unknown: 3016 return 0; 3017 case TargetLowering::C_Register: 3018 return 1; 3019 case TargetLowering::C_RegisterClass: 3020 return 2; 3021 case TargetLowering::C_Memory: 3022 return 3; 3023 } 3024 llvm_unreachable("Invalid constraint type"); 3025 } 3026 3027 /// Examine constraint type and operand type and determine a weight value. 3028 /// This object must already have been set up with the operand type 3029 /// and the current alternative constraint selected. 3030 TargetLowering::ConstraintWeight 3031 TargetLowering::getMultipleConstraintMatchWeight( 3032 AsmOperandInfo &info, int maIndex) const { 3033 InlineAsm::ConstraintCodeVector *rCodes; 3034 if (maIndex >= (int)info.multipleAlternatives.size()) 3035 rCodes = &info.Codes; 3036 else 3037 rCodes = &info.multipleAlternatives[maIndex].Codes; 3038 ConstraintWeight BestWeight = CW_Invalid; 3039 3040 // Loop over the options, keeping track of the most general one. 3041 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 3042 ConstraintWeight weight = 3043 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 3044 if (weight > BestWeight) 3045 BestWeight = weight; 3046 } 3047 3048 return BestWeight; 3049 } 3050 3051 /// Examine constraint type and operand type and determine a weight value. 3052 /// This object must already have been set up with the operand type 3053 /// and the current alternative constraint selected. 3054 TargetLowering::ConstraintWeight 3055 TargetLowering::getSingleConstraintMatchWeight( 3056 AsmOperandInfo &info, const char *constraint) const { 3057 ConstraintWeight weight = CW_Invalid; 3058 Value *CallOperandVal = info.CallOperandVal; 3059 // If we don't have a value, we can't do a match, 3060 // but allow it at the lowest weight. 3061 if (CallOperandVal == NULL) 3062 return CW_Default; 3063 // Look at the constraint type. 3064 switch (*constraint) { 3065 case 'i': // immediate integer. 3066 case 'n': // immediate integer with a known value. 3067 if (isa<ConstantInt>(CallOperandVal)) 3068 weight = CW_Constant; 3069 break; 3070 case 's': // non-explicit intregal immediate. 3071 if (isa<GlobalValue>(CallOperandVal)) 3072 weight = CW_Constant; 3073 break; 3074 case 'E': // immediate float if host format. 3075 case 'F': // immediate float. 3076 if (isa<ConstantFP>(CallOperandVal)) 3077 weight = CW_Constant; 3078 break; 3079 case '<': // memory operand with autodecrement. 3080 case '>': // memory operand with autoincrement. 3081 case 'm': // memory operand. 3082 case 'o': // offsettable memory operand 3083 case 'V': // non-offsettable memory operand 3084 weight = CW_Memory; 3085 break; 3086 case 'r': // general register. 3087 case 'g': // general register, memory operand or immediate integer. 3088 // note: Clang converts "g" to "imr". 3089 if (CallOperandVal->getType()->isIntegerTy()) 3090 weight = CW_Register; 3091 break; 3092 case 'X': // any operand. 3093 default: 3094 weight = CW_Default; 3095 break; 3096 } 3097 return weight; 3098 } 3099 3100 /// ChooseConstraint - If there are multiple different constraints that we 3101 /// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3102 /// This is somewhat tricky: constraints fall into four classes: 3103 /// Other -> immediates and magic values 3104 /// Register -> one specific register 3105 /// RegisterClass -> a group of regs 3106 /// Memory -> memory 3107 /// Ideally, we would pick the most specific constraint possible: if we have 3108 /// something that fits into a register, we would pick it. The problem here 3109 /// is that if we have something that could either be in a register or in 3110 /// memory that use of the register could cause selection of *other* 3111 /// operands to fail: they might only succeed if we pick memory. Because of 3112 /// this the heuristic we use is: 3113 /// 3114 /// 1) If there is an 'other' constraint, and if the operand is valid for 3115 /// that constraint, use it. This makes us take advantage of 'i' 3116 /// constraints when available. 3117 /// 2) Otherwise, pick the most general constraint present. This prefers 3118 /// 'm' over 'r', for example. 3119 /// 3120 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3121 const TargetLowering &TLI, 3122 SDValue Op, SelectionDAG *DAG) { 3123 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3124 unsigned BestIdx = 0; 3125 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3126 int BestGenerality = -1; 3127 3128 // Loop over the options, keeping track of the most general one. 3129 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3130 TargetLowering::ConstraintType CType = 3131 TLI.getConstraintType(OpInfo.Codes[i]); 3132 3133 // If this is an 'other' constraint, see if the operand is valid for it. 3134 // For example, on X86 we might have an 'rI' constraint. If the operand 3135 // is an integer in the range [0..31] we want to use I (saving a load 3136 // of a register), otherwise we must use 'r'. 3137 if (CType == TargetLowering::C_Other && Op.getNode()) { 3138 assert(OpInfo.Codes[i].size() == 1 && 3139 "Unhandled multi-letter 'other' constraint"); 3140 std::vector<SDValue> ResultOps; 3141 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 3142 ResultOps, *DAG); 3143 if (!ResultOps.empty()) { 3144 BestType = CType; 3145 BestIdx = i; 3146 break; 3147 } 3148 } 3149 3150 // Things with matching constraints can only be registers, per gcc 3151 // documentation. This mainly affects "g" constraints. 3152 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3153 continue; 3154 3155 // This constraint letter is more general than the previous one, use it. 3156 int Generality = getConstraintGenerality(CType); 3157 if (Generality > BestGenerality) { 3158 BestType = CType; 3159 BestIdx = i; 3160 BestGenerality = Generality; 3161 } 3162 } 3163 3164 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3165 OpInfo.ConstraintType = BestType; 3166 } 3167 3168 /// ComputeConstraintToUse - Determines the constraint code and constraint 3169 /// type to use for the specific AsmOperandInfo, setting 3170 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3171 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3172 SDValue Op, 3173 SelectionDAG *DAG) const { 3174 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3175 3176 // Single-letter constraints ('r') are very common. 3177 if (OpInfo.Codes.size() == 1) { 3178 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3179 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3180 } else { 3181 ChooseConstraint(OpInfo, *this, Op, DAG); 3182 } 3183 3184 // 'X' matches anything. 3185 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3186 // Labels and constants are handled elsewhere ('X' is the only thing 3187 // that matches labels). For Functions, the type here is the type of 3188 // the result, which is not what we want to look at; leave them alone. 3189 Value *v = OpInfo.CallOperandVal; 3190 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3191 OpInfo.CallOperandVal = v; 3192 return; 3193 } 3194 3195 // Otherwise, try to resolve it to something we know about by looking at 3196 // the actual operand type. 3197 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3198 OpInfo.ConstraintCode = Repl; 3199 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3200 } 3201 } 3202 } 3203 3204 //===----------------------------------------------------------------------===// 3205 // Loop Strength Reduction hooks 3206 //===----------------------------------------------------------------------===// 3207 3208 /// isLegalAddressingMode - Return true if the addressing mode represented 3209 /// by AM is legal for this target, for a load/store of the specified type. 3210 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3211 Type *Ty) const { 3212 // The default implementation of this implements a conservative RISCy, r+r and 3213 // r+i addr mode. 3214 3215 // Allows a sign-extended 16-bit immediate field. 3216 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3217 return false; 3218 3219 // No global is ever allowed as a base. 3220 if (AM.BaseGV) 3221 return false; 3222 3223 // Only support r+r, 3224 switch (AM.Scale) { 3225 case 0: // "r+i" or just "i", depending on HasBaseReg. 3226 break; 3227 case 1: 3228 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3229 return false; 3230 // Otherwise we have r+r or r+i. 3231 break; 3232 case 2: 3233 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3234 return false; 3235 // Allow 2*r as r+r. 3236 break; 3237 } 3238 3239 return true; 3240 } 3241 3242 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication 3243 /// with the multiplicative inverse of the constant. 3244 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 3245 SelectionDAG &DAG) const { 3246 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 3247 APInt d = C->getAPIntValue(); 3248 assert(d != 0 && "Division by zero!"); 3249 3250 // Shift the value upfront if it is even, so the LSB is one. 3251 unsigned ShAmt = d.countTrailingZeros(); 3252 if (ShAmt) { 3253 // TODO: For UDIV use SRL instead of SRA. 3254 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 3255 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 3256 d = d.ashr(ShAmt); 3257 } 3258 3259 // Calculate the multiplicative inverse, using Newton's method. 3260 APInt t, xn = d; 3261 while ((t = d*xn) != 1) 3262 xn *= APInt(d.getBitWidth(), 2) - t; 3263 3264 Op2 = DAG.getConstant(xn, Op1.getValueType()); 3265 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 3266 } 3267 3268 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3269 /// return a DAG expression to select that will generate the same value by 3270 /// multiplying by a magic number. See: 3271 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3272 SDValue TargetLowering:: 3273 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3274 std::vector<SDNode*>* Created) const { 3275 EVT VT = N->getValueType(0); 3276 DebugLoc dl= N->getDebugLoc(); 3277 3278 // Check to see if we can do this. 3279 // FIXME: We should be more aggressive here. 3280 if (!isTypeLegal(VT)) 3281 return SDValue(); 3282 3283 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3284 APInt::ms magics = d.magic(); 3285 3286 // Multiply the numerator (operand 0) by the magic value 3287 // FIXME: We should support doing a MUL in a wider type 3288 SDValue Q; 3289 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 3290 isOperationLegalOrCustom(ISD::MULHS, VT)) 3291 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3292 DAG.getConstant(magics.m, VT)); 3293 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 3294 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3295 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3296 N->getOperand(0), 3297 DAG.getConstant(magics.m, VT)).getNode(), 1); 3298 else 3299 return SDValue(); // No mulhs or equvialent 3300 // If d > 0 and m < 0, add the numerator 3301 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3302 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3303 if (Created) 3304 Created->push_back(Q.getNode()); 3305 } 3306 // If d < 0 and m > 0, subtract the numerator. 3307 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3308 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3309 if (Created) 3310 Created->push_back(Q.getNode()); 3311 } 3312 // Shift right algebraic if shift value is nonzero 3313 if (magics.s > 0) { 3314 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3315 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3316 if (Created) 3317 Created->push_back(Q.getNode()); 3318 } 3319 // Extract the sign bit and add it to the quotient 3320 SDValue T = 3321 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3322 getShiftAmountTy(Q.getValueType()))); 3323 if (Created) 3324 Created->push_back(T.getNode()); 3325 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3326 } 3327 3328 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3329 /// return a DAG expression to select that will generate the same value by 3330 /// multiplying by a magic number. See: 3331 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3332 SDValue TargetLowering:: 3333 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3334 std::vector<SDNode*>* Created) const { 3335 EVT VT = N->getValueType(0); 3336 DebugLoc dl = N->getDebugLoc(); 3337 3338 // Check to see if we can do this. 3339 // FIXME: We should be more aggressive here. 3340 if (!isTypeLegal(VT)) 3341 return SDValue(); 3342 3343 // FIXME: We should use a narrower constant when the upper 3344 // bits are known to be zero. 3345 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3346 APInt::mu magics = N1C.magicu(); 3347 3348 SDValue Q = N->getOperand(0); 3349 3350 // If the divisor is even, we can avoid using the expensive fixup by shifting 3351 // the divided value upfront. 3352 if (magics.a != 0 && !N1C[0]) { 3353 unsigned Shift = N1C.countTrailingZeros(); 3354 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3355 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3356 if (Created) 3357 Created->push_back(Q.getNode()); 3358 3359 // Get magic number for the shifted divisor. 3360 magics = N1C.lshr(Shift).magicu(Shift); 3361 assert(magics.a == 0 && "Should use cheap fixup now"); 3362 } 3363 3364 // Multiply the numerator (operand 0) by the magic value 3365 // FIXME: We should support doing a MUL in a wider type 3366 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 3367 isOperationLegalOrCustom(ISD::MULHU, VT)) 3368 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3369 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 3370 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3371 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3372 DAG.getConstant(magics.m, VT)).getNode(), 1); 3373 else 3374 return SDValue(); // No mulhu or equvialent 3375 if (Created) 3376 Created->push_back(Q.getNode()); 3377 3378 if (magics.a == 0) { 3379 assert(magics.s < N1C.getBitWidth() && 3380 "We shouldn't generate an undefined shift!"); 3381 return DAG.getNode(ISD::SRL, dl, VT, Q, 3382 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3383 } else { 3384 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3385 if (Created) 3386 Created->push_back(NPQ.getNode()); 3387 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3388 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3389 if (Created) 3390 Created->push_back(NPQ.getNode()); 3391 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3392 if (Created) 3393 Created->push_back(NPQ.getNode()); 3394 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3395 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3396 } 3397 } 3398