1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/CodeGen/Analysis.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineJumpTableInfo.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/IR/DerivedTypes.h" 24 #include "llvm/IR/GlobalVariable.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/Target/TargetLoweringObjectFile.h" 31 #include "llvm/Target/TargetMachine.h" 32 #include "llvm/Target/TargetRegisterInfo.h" 33 #include <cctype> 34 using namespace llvm; 35 36 /// InitLibcallNames - Set default libcall names. 37 /// 38 static void InitLibcallNames(const char **Names) { 39 Names[RTLIB::SHL_I16] = "__ashlhi3"; 40 Names[RTLIB::SHL_I32] = "__ashlsi3"; 41 Names[RTLIB::SHL_I64] = "__ashldi3"; 42 Names[RTLIB::SHL_I128] = "__ashlti3"; 43 Names[RTLIB::SRL_I16] = "__lshrhi3"; 44 Names[RTLIB::SRL_I32] = "__lshrsi3"; 45 Names[RTLIB::SRL_I64] = "__lshrdi3"; 46 Names[RTLIB::SRL_I128] = "__lshrti3"; 47 Names[RTLIB::SRA_I16] = "__ashrhi3"; 48 Names[RTLIB::SRA_I32] = "__ashrsi3"; 49 Names[RTLIB::SRA_I64] = "__ashrdi3"; 50 Names[RTLIB::SRA_I128] = "__ashrti3"; 51 Names[RTLIB::MUL_I8] = "__mulqi3"; 52 Names[RTLIB::MUL_I16] = "__mulhi3"; 53 Names[RTLIB::MUL_I32] = "__mulsi3"; 54 Names[RTLIB::MUL_I64] = "__muldi3"; 55 Names[RTLIB::MUL_I128] = "__multi3"; 56 Names[RTLIB::MULO_I32] = "__mulosi4"; 57 Names[RTLIB::MULO_I64] = "__mulodi4"; 58 Names[RTLIB::MULO_I128] = "__muloti4"; 59 Names[RTLIB::SDIV_I8] = "__divqi3"; 60 Names[RTLIB::SDIV_I16] = "__divhi3"; 61 Names[RTLIB::SDIV_I32] = "__divsi3"; 62 Names[RTLIB::SDIV_I64] = "__divdi3"; 63 Names[RTLIB::SDIV_I128] = "__divti3"; 64 Names[RTLIB::UDIV_I8] = "__udivqi3"; 65 Names[RTLIB::UDIV_I16] = "__udivhi3"; 66 Names[RTLIB::UDIV_I32] = "__udivsi3"; 67 Names[RTLIB::UDIV_I64] = "__udivdi3"; 68 Names[RTLIB::UDIV_I128] = "__udivti3"; 69 Names[RTLIB::SREM_I8] = "__modqi3"; 70 Names[RTLIB::SREM_I16] = "__modhi3"; 71 Names[RTLIB::SREM_I32] = "__modsi3"; 72 Names[RTLIB::SREM_I64] = "__moddi3"; 73 Names[RTLIB::SREM_I128] = "__modti3"; 74 Names[RTLIB::UREM_I8] = "__umodqi3"; 75 Names[RTLIB::UREM_I16] = "__umodhi3"; 76 Names[RTLIB::UREM_I32] = "__umodsi3"; 77 Names[RTLIB::UREM_I64] = "__umoddi3"; 78 Names[RTLIB::UREM_I128] = "__umodti3"; 79 80 // These are generally not available. 81 Names[RTLIB::SDIVREM_I8] = 0; 82 Names[RTLIB::SDIVREM_I16] = 0; 83 Names[RTLIB::SDIVREM_I32] = 0; 84 Names[RTLIB::SDIVREM_I64] = 0; 85 Names[RTLIB::SDIVREM_I128] = 0; 86 Names[RTLIB::UDIVREM_I8] = 0; 87 Names[RTLIB::UDIVREM_I16] = 0; 88 Names[RTLIB::UDIVREM_I32] = 0; 89 Names[RTLIB::UDIVREM_I64] = 0; 90 Names[RTLIB::UDIVREM_I128] = 0; 91 92 Names[RTLIB::NEG_I32] = "__negsi2"; 93 Names[RTLIB::NEG_I64] = "__negdi2"; 94 Names[RTLIB::ADD_F32] = "__addsf3"; 95 Names[RTLIB::ADD_F64] = "__adddf3"; 96 Names[RTLIB::ADD_F80] = "__addxf3"; 97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 98 Names[RTLIB::SUB_F32] = "__subsf3"; 99 Names[RTLIB::SUB_F64] = "__subdf3"; 100 Names[RTLIB::SUB_F80] = "__subxf3"; 101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 102 Names[RTLIB::MUL_F32] = "__mulsf3"; 103 Names[RTLIB::MUL_F64] = "__muldf3"; 104 Names[RTLIB::MUL_F80] = "__mulxf3"; 105 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 106 Names[RTLIB::DIV_F32] = "__divsf3"; 107 Names[RTLIB::DIV_F64] = "__divdf3"; 108 Names[RTLIB::DIV_F80] = "__divxf3"; 109 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 110 Names[RTLIB::REM_F32] = "fmodf"; 111 Names[RTLIB::REM_F64] = "fmod"; 112 Names[RTLIB::REM_F80] = "fmodl"; 113 Names[RTLIB::REM_PPCF128] = "fmodl"; 114 Names[RTLIB::FMA_F32] = "fmaf"; 115 Names[RTLIB::FMA_F64] = "fma"; 116 Names[RTLIB::FMA_F80] = "fmal"; 117 Names[RTLIB::FMA_PPCF128] = "fmal"; 118 Names[RTLIB::POWI_F32] = "__powisf2"; 119 Names[RTLIB::POWI_F64] = "__powidf2"; 120 Names[RTLIB::POWI_F80] = "__powixf2"; 121 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 122 Names[RTLIB::SQRT_F32] = "sqrtf"; 123 Names[RTLIB::SQRT_F64] = "sqrt"; 124 Names[RTLIB::SQRT_F80] = "sqrtl"; 125 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 126 Names[RTLIB::LOG_F32] = "logf"; 127 Names[RTLIB::LOG_F64] = "log"; 128 Names[RTLIB::LOG_F80] = "logl"; 129 Names[RTLIB::LOG_PPCF128] = "logl"; 130 Names[RTLIB::LOG2_F32] = "log2f"; 131 Names[RTLIB::LOG2_F64] = "log2"; 132 Names[RTLIB::LOG2_F80] = "log2l"; 133 Names[RTLIB::LOG2_PPCF128] = "log2l"; 134 Names[RTLIB::LOG10_F32] = "log10f"; 135 Names[RTLIB::LOG10_F64] = "log10"; 136 Names[RTLIB::LOG10_F80] = "log10l"; 137 Names[RTLIB::LOG10_PPCF128] = "log10l"; 138 Names[RTLIB::EXP_F32] = "expf"; 139 Names[RTLIB::EXP_F64] = "exp"; 140 Names[RTLIB::EXP_F80] = "expl"; 141 Names[RTLIB::EXP_PPCF128] = "expl"; 142 Names[RTLIB::EXP2_F32] = "exp2f"; 143 Names[RTLIB::EXP2_F64] = "exp2"; 144 Names[RTLIB::EXP2_F80] = "exp2l"; 145 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 146 Names[RTLIB::SIN_F32] = "sinf"; 147 Names[RTLIB::SIN_F64] = "sin"; 148 Names[RTLIB::SIN_F80] = "sinl"; 149 Names[RTLIB::SIN_PPCF128] = "sinl"; 150 Names[RTLIB::COS_F32] = "cosf"; 151 Names[RTLIB::COS_F64] = "cos"; 152 Names[RTLIB::COS_F80] = "cosl"; 153 Names[RTLIB::COS_PPCF128] = "cosl"; 154 Names[RTLIB::POW_F32] = "powf"; 155 Names[RTLIB::POW_F64] = "pow"; 156 Names[RTLIB::POW_F80] = "powl"; 157 Names[RTLIB::POW_PPCF128] = "powl"; 158 Names[RTLIB::CEIL_F32] = "ceilf"; 159 Names[RTLIB::CEIL_F64] = "ceil"; 160 Names[RTLIB::CEIL_F80] = "ceill"; 161 Names[RTLIB::CEIL_PPCF128] = "ceill"; 162 Names[RTLIB::TRUNC_F32] = "truncf"; 163 Names[RTLIB::TRUNC_F64] = "trunc"; 164 Names[RTLIB::TRUNC_F80] = "truncl"; 165 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 166 Names[RTLIB::RINT_F32] = "rintf"; 167 Names[RTLIB::RINT_F64] = "rint"; 168 Names[RTLIB::RINT_F80] = "rintl"; 169 Names[RTLIB::RINT_PPCF128] = "rintl"; 170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 171 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 174 Names[RTLIB::FLOOR_F32] = "floorf"; 175 Names[RTLIB::FLOOR_F64] = "floor"; 176 Names[RTLIB::FLOOR_F80] = "floorl"; 177 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 178 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 179 Names[RTLIB::COPYSIGN_F64] = "copysign"; 180 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 246 Names[RTLIB::OEQ_F32] = "__eqsf2"; 247 Names[RTLIB::OEQ_F64] = "__eqdf2"; 248 Names[RTLIB::UNE_F32] = "__nesf2"; 249 Names[RTLIB::UNE_F64] = "__nedf2"; 250 Names[RTLIB::OGE_F32] = "__gesf2"; 251 Names[RTLIB::OGE_F64] = "__gedf2"; 252 Names[RTLIB::OLT_F32] = "__ltsf2"; 253 Names[RTLIB::OLT_F64] = "__ltdf2"; 254 Names[RTLIB::OLE_F32] = "__lesf2"; 255 Names[RTLIB::OLE_F64] = "__ledf2"; 256 Names[RTLIB::OGT_F32] = "__gtsf2"; 257 Names[RTLIB::OGT_F64] = "__gtdf2"; 258 Names[RTLIB::UO_F32] = "__unordsf2"; 259 Names[RTLIB::UO_F64] = "__unorddf2"; 260 Names[RTLIB::O_F32] = "__unordsf2"; 261 Names[RTLIB::O_F64] = "__unorddf2"; 262 Names[RTLIB::MEMCPY] = "memcpy"; 263 Names[RTLIB::MEMMOVE] = "memmove"; 264 Names[RTLIB::MEMSET] = "memset"; 265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 298 } 299 300 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 301 /// 302 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 304 CCs[i] = CallingConv::C; 305 } 306 } 307 308 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 309 /// UNKNOWN_LIBCALL if there is none. 310 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 311 if (OpVT == MVT::f32) { 312 if (RetVT == MVT::f64) 313 return FPEXT_F32_F64; 314 } 315 316 return UNKNOWN_LIBCALL; 317 } 318 319 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 320 /// UNKNOWN_LIBCALL if there is none. 321 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 322 if (RetVT == MVT::f32) { 323 if (OpVT == MVT::f64) 324 return FPROUND_F64_F32; 325 if (OpVT == MVT::f80) 326 return FPROUND_F80_F32; 327 if (OpVT == MVT::ppcf128) 328 return FPROUND_PPCF128_F32; 329 } else if (RetVT == MVT::f64) { 330 if (OpVT == MVT::f80) 331 return FPROUND_F80_F64; 332 if (OpVT == MVT::ppcf128) 333 return FPROUND_PPCF128_F64; 334 } 335 336 return UNKNOWN_LIBCALL; 337 } 338 339 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 340 /// UNKNOWN_LIBCALL if there is none. 341 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 342 if (OpVT == MVT::f32) { 343 if (RetVT == MVT::i8) 344 return FPTOSINT_F32_I8; 345 if (RetVT == MVT::i16) 346 return FPTOSINT_F32_I16; 347 if (RetVT == MVT::i32) 348 return FPTOSINT_F32_I32; 349 if (RetVT == MVT::i64) 350 return FPTOSINT_F32_I64; 351 if (RetVT == MVT::i128) 352 return FPTOSINT_F32_I128; 353 } else if (OpVT == MVT::f64) { 354 if (RetVT == MVT::i8) 355 return FPTOSINT_F64_I8; 356 if (RetVT == MVT::i16) 357 return FPTOSINT_F64_I16; 358 if (RetVT == MVT::i32) 359 return FPTOSINT_F64_I32; 360 if (RetVT == MVT::i64) 361 return FPTOSINT_F64_I64; 362 if (RetVT == MVT::i128) 363 return FPTOSINT_F64_I128; 364 } else if (OpVT == MVT::f80) { 365 if (RetVT == MVT::i32) 366 return FPTOSINT_F80_I32; 367 if (RetVT == MVT::i64) 368 return FPTOSINT_F80_I64; 369 if (RetVT == MVT::i128) 370 return FPTOSINT_F80_I128; 371 } else if (OpVT == MVT::ppcf128) { 372 if (RetVT == MVT::i32) 373 return FPTOSINT_PPCF128_I32; 374 if (RetVT == MVT::i64) 375 return FPTOSINT_PPCF128_I64; 376 if (RetVT == MVT::i128) 377 return FPTOSINT_PPCF128_I128; 378 } 379 return UNKNOWN_LIBCALL; 380 } 381 382 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 383 /// UNKNOWN_LIBCALL if there is none. 384 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 385 if (OpVT == MVT::f32) { 386 if (RetVT == MVT::i8) 387 return FPTOUINT_F32_I8; 388 if (RetVT == MVT::i16) 389 return FPTOUINT_F32_I16; 390 if (RetVT == MVT::i32) 391 return FPTOUINT_F32_I32; 392 if (RetVT == MVT::i64) 393 return FPTOUINT_F32_I64; 394 if (RetVT == MVT::i128) 395 return FPTOUINT_F32_I128; 396 } else if (OpVT == MVT::f64) { 397 if (RetVT == MVT::i8) 398 return FPTOUINT_F64_I8; 399 if (RetVT == MVT::i16) 400 return FPTOUINT_F64_I16; 401 if (RetVT == MVT::i32) 402 return FPTOUINT_F64_I32; 403 if (RetVT == MVT::i64) 404 return FPTOUINT_F64_I64; 405 if (RetVT == MVT::i128) 406 return FPTOUINT_F64_I128; 407 } else if (OpVT == MVT::f80) { 408 if (RetVT == MVT::i32) 409 return FPTOUINT_F80_I32; 410 if (RetVT == MVT::i64) 411 return FPTOUINT_F80_I64; 412 if (RetVT == MVT::i128) 413 return FPTOUINT_F80_I128; 414 } else if (OpVT == MVT::ppcf128) { 415 if (RetVT == MVT::i32) 416 return FPTOUINT_PPCF128_I32; 417 if (RetVT == MVT::i64) 418 return FPTOUINT_PPCF128_I64; 419 if (RetVT == MVT::i128) 420 return FPTOUINT_PPCF128_I128; 421 } 422 return UNKNOWN_LIBCALL; 423 } 424 425 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 426 /// UNKNOWN_LIBCALL if there is none. 427 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 428 if (OpVT == MVT::i32) { 429 if (RetVT == MVT::f32) 430 return SINTTOFP_I32_F32; 431 if (RetVT == MVT::f64) 432 return SINTTOFP_I32_F64; 433 if (RetVT == MVT::f80) 434 return SINTTOFP_I32_F80; 435 if (RetVT == MVT::ppcf128) 436 return SINTTOFP_I32_PPCF128; 437 } else if (OpVT == MVT::i64) { 438 if (RetVT == MVT::f32) 439 return SINTTOFP_I64_F32; 440 if (RetVT == MVT::f64) 441 return SINTTOFP_I64_F64; 442 if (RetVT == MVT::f80) 443 return SINTTOFP_I64_F80; 444 if (RetVT == MVT::ppcf128) 445 return SINTTOFP_I64_PPCF128; 446 } else if (OpVT == MVT::i128) { 447 if (RetVT == MVT::f32) 448 return SINTTOFP_I128_F32; 449 if (RetVT == MVT::f64) 450 return SINTTOFP_I128_F64; 451 if (RetVT == MVT::f80) 452 return SINTTOFP_I128_F80; 453 if (RetVT == MVT::ppcf128) 454 return SINTTOFP_I128_PPCF128; 455 } 456 return UNKNOWN_LIBCALL; 457 } 458 459 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 460 /// UNKNOWN_LIBCALL if there is none. 461 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 462 if (OpVT == MVT::i32) { 463 if (RetVT == MVT::f32) 464 return UINTTOFP_I32_F32; 465 if (RetVT == MVT::f64) 466 return UINTTOFP_I32_F64; 467 if (RetVT == MVT::f80) 468 return UINTTOFP_I32_F80; 469 if (RetVT == MVT::ppcf128) 470 return UINTTOFP_I32_PPCF128; 471 } else if (OpVT == MVT::i64) { 472 if (RetVT == MVT::f32) 473 return UINTTOFP_I64_F32; 474 if (RetVT == MVT::f64) 475 return UINTTOFP_I64_F64; 476 if (RetVT == MVT::f80) 477 return UINTTOFP_I64_F80; 478 if (RetVT == MVT::ppcf128) 479 return UINTTOFP_I64_PPCF128; 480 } else if (OpVT == MVT::i128) { 481 if (RetVT == MVT::f32) 482 return UINTTOFP_I128_F32; 483 if (RetVT == MVT::f64) 484 return UINTTOFP_I128_F64; 485 if (RetVT == MVT::f80) 486 return UINTTOFP_I128_F80; 487 if (RetVT == MVT::ppcf128) 488 return UINTTOFP_I128_PPCF128; 489 } 490 return UNKNOWN_LIBCALL; 491 } 492 493 /// InitCmpLibcallCCs - Set default comparison libcall CC. 494 /// 495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 499 CCs[RTLIB::UNE_F32] = ISD::SETNE; 500 CCs[RTLIB::UNE_F64] = ISD::SETNE; 501 CCs[RTLIB::OGE_F32] = ISD::SETGE; 502 CCs[RTLIB::OGE_F64] = ISD::SETGE; 503 CCs[RTLIB::OLT_F32] = ISD::SETLT; 504 CCs[RTLIB::OLT_F64] = ISD::SETLT; 505 CCs[RTLIB::OLE_F32] = ISD::SETLE; 506 CCs[RTLIB::OLE_F64] = ISD::SETLE; 507 CCs[RTLIB::OGT_F32] = ISD::SETGT; 508 CCs[RTLIB::OGT_F64] = ISD::SETGT; 509 CCs[RTLIB::UO_F32] = ISD::SETNE; 510 CCs[RTLIB::UO_F64] = ISD::SETNE; 511 CCs[RTLIB::O_F32] = ISD::SETEQ; 512 CCs[RTLIB::O_F64] = ISD::SETEQ; 513 } 514 515 /// NOTE: The constructor takes ownership of TLOF. 516 TargetLowering::TargetLowering(const TargetMachine &tm, 517 const TargetLoweringObjectFile *tlof) 518 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) { 519 // All operations default to being supported. 520 memset(OpActions, 0, sizeof(OpActions)); 521 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 524 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 525 526 // Set default actions for various operations. 527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 528 // Default all indexed load / store to expand. 529 for (unsigned IM = (unsigned)ISD::PRE_INC; 530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 533 } 534 535 // These operations default to expand. 536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 538 } 539 540 // Most targets ignore the @llvm.prefetch intrinsic. 541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 542 543 // ConstantFP nodes default to expand. Targets can either change this to 544 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 545 // to optimize expansions for certain constants. 546 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 548 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 549 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 550 551 // These library functions default to expand. 552 setOperationAction(ISD::FLOG , MVT::f16, Expand); 553 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 554 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 555 setOperationAction(ISD::FEXP , MVT::f16, Expand); 556 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 557 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 558 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 559 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 560 setOperationAction(ISD::FRINT, MVT::f16, Expand); 561 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 562 setOperationAction(ISD::FLOG , MVT::f32, Expand); 563 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 564 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 565 setOperationAction(ISD::FEXP , MVT::f32, Expand); 566 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 567 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 568 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 569 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 570 setOperationAction(ISD::FRINT, MVT::f32, Expand); 571 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 572 setOperationAction(ISD::FLOG , MVT::f64, Expand); 573 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 574 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 575 setOperationAction(ISD::FEXP , MVT::f64, Expand); 576 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 577 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 578 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 579 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 580 setOperationAction(ISD::FRINT, MVT::f64, Expand); 581 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 582 583 // Default ISD::TRAP to expand (which turns it into abort). 584 setOperationAction(ISD::TRAP, MVT::Other, Expand); 585 586 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 587 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 588 // 589 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 590 591 IsLittleEndian = TD->isLittleEndian(); 592 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0)); 593 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 594 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 595 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 596 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 597 = maxStoresPerMemmoveOptSize = 4; 598 benefitFromCodePlacementOpt = false; 599 UseUnderscoreSetJmp = false; 600 UseUnderscoreLongJmp = false; 601 SelectIsExpensive = false; 602 IntDivIsCheap = false; 603 Pow2DivIsCheap = false; 604 JumpIsExpensive = false; 605 predictableSelectIsExpensive = false; 606 StackPointerRegisterToSaveRestore = 0; 607 ExceptionPointerRegister = 0; 608 ExceptionSelectorRegister = 0; 609 BooleanContents = UndefinedBooleanContent; 610 BooleanVectorContents = UndefinedBooleanContent; 611 SchedPreferenceInfo = Sched::ILP; 612 JumpBufSize = 0; 613 JumpBufAlignment = 0; 614 MinFunctionAlignment = 0; 615 PrefFunctionAlignment = 0; 616 PrefLoopAlignment = 0; 617 MinStackArgumentAlignment = 1; 618 ShouldFoldAtomicFences = false; 619 InsertFencesForAtomic = false; 620 SupportJumpTables = true; 621 MinimumJumpTableEntries = 4; 622 623 InitLibcallNames(LibcallRoutineNames); 624 InitCmpLibcallCCs(CmpLibcallCCs); 625 InitLibcallCallingConvs(LibcallCallingConvs); 626 } 627 628 TargetLowering::~TargetLowering() { 629 delete &TLOF; 630 } 631 632 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 633 return MVT::getIntegerVT(8*TD->getPointerSize(0)); 634 } 635 636 /// canOpTrap - Returns true if the operation can trap for the value type. 637 /// VT must be a legal type. 638 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 639 assert(isTypeLegal(VT)); 640 switch (Op) { 641 default: 642 return false; 643 case ISD::FDIV: 644 case ISD::FREM: 645 case ISD::SDIV: 646 case ISD::UDIV: 647 case ISD::SREM: 648 case ISD::UREM: 649 return true; 650 } 651 } 652 653 654 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 655 unsigned &NumIntermediates, 656 MVT &RegisterVT, 657 TargetLowering *TLI) { 658 // Figure out the right, legal destination reg to copy into. 659 unsigned NumElts = VT.getVectorNumElements(); 660 MVT EltTy = VT.getVectorElementType(); 661 662 unsigned NumVectorRegs = 1; 663 664 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 665 // could break down into LHS/RHS like LegalizeDAG does. 666 if (!isPowerOf2_32(NumElts)) { 667 NumVectorRegs = NumElts; 668 NumElts = 1; 669 } 670 671 // Divide the input until we get to a supported size. This will always 672 // end with a scalar if the target doesn't support vectors. 673 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 674 NumElts >>= 1; 675 NumVectorRegs <<= 1; 676 } 677 678 NumIntermediates = NumVectorRegs; 679 680 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 681 if (!TLI->isTypeLegal(NewVT)) 682 NewVT = EltTy; 683 IntermediateVT = NewVT; 684 685 unsigned NewVTSize = NewVT.getSizeInBits(); 686 687 // Convert sizes such as i33 to i64. 688 if (!isPowerOf2_32(NewVTSize)) 689 NewVTSize = NextPowerOf2(NewVTSize); 690 691 MVT DestVT = TLI->getRegisterType(NewVT); 692 RegisterVT = DestVT; 693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 694 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 695 696 // Otherwise, promotion or legal types use the same number of registers as 697 // the vector decimated to the appropriate level. 698 return NumVectorRegs; 699 } 700 701 /// isLegalRC - Return true if the value types that can be represented by the 702 /// specified register class are all legal. 703 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 704 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 705 I != E; ++I) { 706 if (isTypeLegal(*I)) 707 return true; 708 } 709 return false; 710 } 711 712 /// findRepresentativeClass - Return the largest legal super-reg register class 713 /// of the register class for the specified type and its associated "cost". 714 std::pair<const TargetRegisterClass*, uint8_t> 715 TargetLowering::findRepresentativeClass(MVT VT) const { 716 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 717 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 718 if (!RC) 719 return std::make_pair(RC, 0); 720 721 // Compute the set of all super-register classes. 722 BitVector SuperRegRC(TRI->getNumRegClasses()); 723 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 724 SuperRegRC.setBitsInMask(RCI.getMask()); 725 726 // Find the first legal register class with the largest spill size. 727 const TargetRegisterClass *BestRC = RC; 728 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 729 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 730 // We want the largest possible spill size. 731 if (SuperRC->getSize() <= BestRC->getSize()) 732 continue; 733 if (!isLegalRC(SuperRC)) 734 continue; 735 BestRC = SuperRC; 736 } 737 return std::make_pair(BestRC, 1); 738 } 739 740 /// computeRegisterProperties - Once all of the register classes are added, 741 /// this allows us to compute derived properties we expose. 742 void TargetLowering::computeRegisterProperties() { 743 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 744 "Too many value types for ValueTypeActions to hold!"); 745 746 // Everything defaults to needing one register. 747 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 748 NumRegistersForVT[i] = 1; 749 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 750 } 751 // ...except isVoid, which doesn't need any registers. 752 NumRegistersForVT[MVT::isVoid] = 0; 753 754 // Find the largest integer register class. 755 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 756 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 757 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 758 759 // Every integer value type larger than this largest register takes twice as 760 // many registers to represent as the previous ValueType. 761 for (unsigned ExpandedReg = LargestIntReg + 1; 762 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 763 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 764 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 765 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 766 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 767 TypeExpandInteger); 768 } 769 770 // Inspect all of the ValueType's smaller than the largest integer 771 // register to see which ones need promotion. 772 unsigned LegalIntReg = LargestIntReg; 773 for (unsigned IntReg = LargestIntReg - 1; 774 IntReg >= (unsigned)MVT::i1; --IntReg) { 775 MVT IVT = (MVT::SimpleValueType)IntReg; 776 if (isTypeLegal(IVT)) { 777 LegalIntReg = IntReg; 778 } else { 779 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 780 (const MVT::SimpleValueType)LegalIntReg; 781 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 782 } 783 } 784 785 // ppcf128 type is really two f64's. 786 if (!isTypeLegal(MVT::ppcf128)) { 787 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 788 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 789 TransformToType[MVT::ppcf128] = MVT::f64; 790 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 791 } 792 793 // Decide how to handle f64. If the target does not have native f64 support, 794 // expand it to i64 and we will be generating soft float library calls. 795 if (!isTypeLegal(MVT::f64)) { 796 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 797 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 798 TransformToType[MVT::f64] = MVT::i64; 799 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 800 } 801 802 // Decide how to handle f32. If the target does not have native support for 803 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 804 if (!isTypeLegal(MVT::f32)) { 805 if (isTypeLegal(MVT::f64)) { 806 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 807 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 808 TransformToType[MVT::f32] = MVT::f64; 809 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 810 } else { 811 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 812 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 813 TransformToType[MVT::f32] = MVT::i32; 814 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 815 } 816 } 817 818 // Loop over all of the vector value types to see which need transformations. 819 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 820 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 821 MVT VT = (MVT::SimpleValueType)i; 822 if (isTypeLegal(VT)) continue; 823 824 // Determine if there is a legal wider type. If so, we should promote to 825 // that wider vector type. 826 MVT EltVT = VT.getVectorElementType(); 827 unsigned NElts = VT.getVectorNumElements(); 828 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) { 829 bool IsLegalWiderType = false; 830 // First try to promote the elements of integer vectors. If no legal 831 // promotion was found, fallback to the widen-vector method. 832 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 833 MVT SVT = (MVT::SimpleValueType)nVT; 834 // Promote vectors of integers to vectors with the same number 835 // of elements, with a wider element type. 836 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 837 && SVT.getVectorNumElements() == NElts && 838 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 839 TransformToType[i] = SVT; 840 RegisterTypeForVT[i] = SVT; 841 NumRegistersForVT[i] = 1; 842 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 843 IsLegalWiderType = true; 844 break; 845 } 846 } 847 848 if (IsLegalWiderType) continue; 849 850 // Try to widen the vector. 851 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 852 MVT SVT = (MVT::SimpleValueType)nVT; 853 if (SVT.getVectorElementType() == EltVT && 854 SVT.getVectorNumElements() > NElts && 855 isTypeLegal(SVT)) { 856 TransformToType[i] = SVT; 857 RegisterTypeForVT[i] = SVT; 858 NumRegistersForVT[i] = 1; 859 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 860 IsLegalWiderType = true; 861 break; 862 } 863 } 864 if (IsLegalWiderType) continue; 865 } 866 867 MVT IntermediateVT; 868 MVT RegisterVT; 869 unsigned NumIntermediates; 870 NumRegistersForVT[i] = 871 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 872 RegisterVT, this); 873 RegisterTypeForVT[i] = RegisterVT; 874 875 MVT NVT = VT.getPow2VectorType(); 876 if (NVT == VT) { 877 // Type is already a power of 2. The default action is to split. 878 TransformToType[i] = MVT::Other; 879 unsigned NumElts = VT.getVectorNumElements(); 880 ValueTypeActions.setTypeAction(VT, 881 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 882 } else { 883 TransformToType[i] = NVT; 884 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 885 } 886 } 887 888 // Determine the 'representative' register class for each value type. 889 // An representative register class is the largest (meaning one which is 890 // not a sub-register class / subreg register class) legal register class for 891 // a group of value types. For example, on i386, i8, i16, and i32 892 // representative would be GR32; while on x86_64 it's GR64. 893 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 894 const TargetRegisterClass* RRC; 895 uint8_t Cost; 896 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 897 RepRegClassForVT[i] = RRC; 898 RepRegClassCostForVT[i] = Cost; 899 } 900 } 901 902 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 903 return NULL; 904 } 905 906 EVT TargetLowering::getSetCCResultType(EVT VT) const { 907 assert(!VT.isVector() && "No default SetCC type for vectors!"); 908 return getPointerTy(0).SimpleTy; 909 } 910 911 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 912 return MVT::i32; // return the default value 913 } 914 915 /// getVectorTypeBreakdown - Vector types are broken down into some number of 916 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 917 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 918 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 919 /// 920 /// This method returns the number of registers needed, and the VT for each 921 /// register. It also returns the VT and quantity of the intermediate values 922 /// before they are promoted/expanded. 923 /// 924 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 925 EVT &IntermediateVT, 926 unsigned &NumIntermediates, 927 MVT &RegisterVT) const { 928 unsigned NumElts = VT.getVectorNumElements(); 929 930 // If there is a wider vector type with the same element type as this one, 931 // or a promoted vector type that has the same number of elements which 932 // are wider, then we should convert to that legal vector type. 933 // This handles things like <2 x float> -> <4 x float> and 934 // <4 x i1> -> <4 x i32>. 935 LegalizeTypeAction TA = getTypeAction(Context, VT); 936 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 937 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 938 if (isTypeLegal(RegisterEVT)) { 939 IntermediateVT = RegisterEVT; 940 RegisterVT = RegisterEVT.getSimpleVT(); 941 NumIntermediates = 1; 942 return 1; 943 } 944 } 945 946 // Figure out the right, legal destination reg to copy into. 947 EVT EltTy = VT.getVectorElementType(); 948 949 unsigned NumVectorRegs = 1; 950 951 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 952 // could break down into LHS/RHS like LegalizeDAG does. 953 if (!isPowerOf2_32(NumElts)) { 954 NumVectorRegs = NumElts; 955 NumElts = 1; 956 } 957 958 // Divide the input until we get to a supported size. This will always 959 // end with a scalar if the target doesn't support vectors. 960 while (NumElts > 1 && !isTypeLegal( 961 EVT::getVectorVT(Context, EltTy, NumElts))) { 962 NumElts >>= 1; 963 NumVectorRegs <<= 1; 964 } 965 966 NumIntermediates = NumVectorRegs; 967 968 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 969 if (!isTypeLegal(NewVT)) 970 NewVT = EltTy; 971 IntermediateVT = NewVT; 972 973 MVT DestVT = getRegisterType(Context, NewVT); 974 RegisterVT = DestVT; 975 unsigned NewVTSize = NewVT.getSizeInBits(); 976 977 // Convert sizes such as i33 to i64. 978 if (!isPowerOf2_32(NewVTSize)) 979 NewVTSize = NextPowerOf2(NewVTSize); 980 981 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 982 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 983 984 // Otherwise, promotion or legal types use the same number of registers as 985 // the vector decimated to the appropriate level. 986 return NumVectorRegs; 987 } 988 989 /// Get the EVTs and ArgFlags collections that represent the legalized return 990 /// type of the given function. This does not require a DAG or a return value, 991 /// and is suitable for use before any DAGs for the function are constructed. 992 /// TODO: Move this out of TargetLowering.cpp. 993 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 994 SmallVectorImpl<ISD::OutputArg> &Outs, 995 const TargetLowering &TLI) { 996 SmallVector<EVT, 4> ValueVTs; 997 ComputeValueVTs(TLI, ReturnType, ValueVTs); 998 unsigned NumValues = ValueVTs.size(); 999 if (NumValues == 0) return; 1000 1001 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1002 EVT VT = ValueVTs[j]; 1003 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1004 1005 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1006 ExtendKind = ISD::SIGN_EXTEND; 1007 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1008 ExtendKind = ISD::ZERO_EXTEND; 1009 1010 // FIXME: C calling convention requires the return type to be promoted to 1011 // at least 32-bit. But this is not necessary for non-C calling 1012 // conventions. The frontend should mark functions whose return values 1013 // require promoting with signext or zeroext attributes. 1014 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1015 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1016 if (VT.bitsLT(MinVT)) 1017 VT = MinVT; 1018 } 1019 1020 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1021 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1022 1023 // 'inreg' on function refers to return value 1024 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1025 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1026 Flags.setInReg(); 1027 1028 // Propagate extension type if any 1029 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1030 Flags.setSExt(); 1031 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1032 Flags.setZExt(); 1033 1034 for (unsigned i = 0; i < NumParts; ++i) 1035 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0)); 1036 } 1037 } 1038 1039 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1040 /// function arguments in the caller parameter area. This is the actual 1041 /// alignment, not its logarithm. 1042 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const { 1043 return TD->getCallFrameTypeAlignment(Ty); 1044 } 1045 1046 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 1047 /// current function. The returned value is a member of the 1048 /// MachineJumpTableInfo::JTEntryKind enum. 1049 unsigned TargetLowering::getJumpTableEncoding() const { 1050 // In non-pic modes, just use the address of a block. 1051 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1052 return MachineJumpTableInfo::EK_BlockAddress; 1053 1054 // In PIC mode, if the target supports a GPRel32 directive, use it. 1055 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1056 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1057 1058 // Otherwise, use a label difference. 1059 return MachineJumpTableInfo::EK_LabelDifference32; 1060 } 1061 1062 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1063 SelectionDAG &DAG) const { 1064 // If our PIC model is GP relative, use the global offset table as the base. 1065 unsigned JTEncoding = getJumpTableEncoding(); 1066 1067 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 1068 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 1069 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0)); 1070 1071 return Table; 1072 } 1073 1074 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1075 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1076 /// MCExpr. 1077 const MCExpr * 1078 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1079 unsigned JTI,MCContext &Ctx) const{ 1080 // The normal PIC reloc base is the label at the start of the jump table. 1081 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1082 } 1083 1084 bool 1085 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1086 // Assume that everything is safe in static mode. 1087 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1088 return true; 1089 1090 // In dynamic-no-pic mode, assume that known defined values are safe. 1091 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1092 GA && 1093 !GA->getGlobal()->isDeclaration() && 1094 !GA->getGlobal()->isWeakForLinker()) 1095 return true; 1096 1097 // Otherwise assume nothing is safe. 1098 return false; 1099 } 1100 1101 //===----------------------------------------------------------------------===// 1102 // TargetTransformInfo Helpers 1103 //===----------------------------------------------------------------------===// 1104 1105 int TargetLowering::InstructionOpcodeToISD(unsigned Opcode) const { 1106 enum InstructionOpcodes { 1107 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1108 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1109 #include "llvm/IR/Instruction.def" 1110 }; 1111 switch (static_cast<InstructionOpcodes>(Opcode)) { 1112 case Ret: return 0; 1113 case Br: return 0; 1114 case Switch: return 0; 1115 case IndirectBr: return 0; 1116 case Invoke: return 0; 1117 case Resume: return 0; 1118 case Unreachable: return 0; 1119 case Add: return ISD::ADD; 1120 case FAdd: return ISD::FADD; 1121 case Sub: return ISD::SUB; 1122 case FSub: return ISD::FSUB; 1123 case Mul: return ISD::MUL; 1124 case FMul: return ISD::FMUL; 1125 case UDiv: return ISD::UDIV; 1126 case SDiv: return ISD::UDIV; 1127 case FDiv: return ISD::FDIV; 1128 case URem: return ISD::UREM; 1129 case SRem: return ISD::SREM; 1130 case FRem: return ISD::FREM; 1131 case Shl: return ISD::SHL; 1132 case LShr: return ISD::SRL; 1133 case AShr: return ISD::SRA; 1134 case And: return ISD::AND; 1135 case Or: return ISD::OR; 1136 case Xor: return ISD::XOR; 1137 case Alloca: return 0; 1138 case Load: return ISD::LOAD; 1139 case Store: return ISD::STORE; 1140 case GetElementPtr: return 0; 1141 case Fence: return 0; 1142 case AtomicCmpXchg: return 0; 1143 case AtomicRMW: return 0; 1144 case Trunc: return ISD::TRUNCATE; 1145 case ZExt: return ISD::ZERO_EXTEND; 1146 case SExt: return ISD::SIGN_EXTEND; 1147 case FPToUI: return ISD::FP_TO_UINT; 1148 case FPToSI: return ISD::FP_TO_SINT; 1149 case UIToFP: return ISD::UINT_TO_FP; 1150 case SIToFP: return ISD::SINT_TO_FP; 1151 case FPTrunc: return ISD::FP_ROUND; 1152 case FPExt: return ISD::FP_EXTEND; 1153 case PtrToInt: return ISD::BITCAST; 1154 case IntToPtr: return ISD::BITCAST; 1155 case BitCast: return ISD::BITCAST; 1156 case ICmp: return ISD::SETCC; 1157 case FCmp: return ISD::SETCC; 1158 case PHI: return 0; 1159 case Call: return 0; 1160 case Select: return ISD::SELECT; 1161 case UserOp1: return 0; 1162 case UserOp2: return 0; 1163 case VAArg: return 0; 1164 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1165 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1166 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1167 case ExtractValue: return ISD::MERGE_VALUES; 1168 case InsertValue: return ISD::MERGE_VALUES; 1169 case LandingPad: return 0; 1170 } 1171 1172 llvm_unreachable("Unknown instruction type encountered!"); 1173 } 1174 1175 std::pair<unsigned, MVT> 1176 TargetLowering::getTypeLegalizationCost(Type *Ty) const { 1177 LLVMContext &C = Ty->getContext(); 1178 EVT MTy = getValueType(Ty); 1179 1180 unsigned Cost = 1; 1181 // We keep legalizing the type until we find a legal kind. We assume that 1182 // the only operation that costs anything is the split. After splitting 1183 // we need to handle two types. 1184 while (true) { 1185 LegalizeKind LK = getTypeConversion(C, MTy); 1186 1187 if (LK.first == TypeLegal) 1188 return std::make_pair(Cost, MTy.getSimpleVT()); 1189 1190 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1191 Cost *= 2; 1192 1193 // Keep legalizing the type. 1194 MTy = LK.second; 1195 } 1196 } 1197 1198 //===----------------------------------------------------------------------===// 1199 // Optimization Methods 1200 //===----------------------------------------------------------------------===// 1201 1202 /// ShrinkDemandedConstant - Check to see if the specified operand of the 1203 /// specified instruction is a constant integer. If so, check to see if there 1204 /// are any bits set in the constant that are not demanded. If so, shrink the 1205 /// constant and return true. 1206 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1207 const APInt &Demanded) { 1208 DebugLoc dl = Op.getDebugLoc(); 1209 1210 // FIXME: ISD::SELECT, ISD::SELECT_CC 1211 switch (Op.getOpcode()) { 1212 default: break; 1213 case ISD::XOR: 1214 case ISD::AND: 1215 case ISD::OR: { 1216 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1217 if (!C) return false; 1218 1219 if (Op.getOpcode() == ISD::XOR && 1220 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1221 return false; 1222 1223 // if we can expand it to have all bits set, do it 1224 if (C->getAPIntValue().intersects(~Demanded)) { 1225 EVT VT = Op.getValueType(); 1226 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1227 DAG.getConstant(Demanded & 1228 C->getAPIntValue(), 1229 VT)); 1230 return CombineTo(Op, New); 1231 } 1232 1233 break; 1234 } 1235 } 1236 1237 return false; 1238 } 1239 1240 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1241 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1242 /// cast, but it could be generalized for targets with other types of 1243 /// implicit widening casts. 1244 bool 1245 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1246 unsigned BitWidth, 1247 const APInt &Demanded, 1248 DebugLoc dl) { 1249 assert(Op.getNumOperands() == 2 && 1250 "ShrinkDemandedOp only supports binary operators!"); 1251 assert(Op.getNode()->getNumValues() == 1 && 1252 "ShrinkDemandedOp only supports nodes with one result!"); 1253 1254 // Don't do this if the node has another user, which may require the 1255 // full value. 1256 if (!Op.getNode()->hasOneUse()) 1257 return false; 1258 1259 // Search for the smallest integer type with free casts to and from 1260 // Op's type. For expedience, just check power-of-2 integer types. 1261 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1262 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros(); 1263 unsigned SmallVTBits = DemandedSize; 1264 if (!isPowerOf2_32(SmallVTBits)) 1265 SmallVTBits = NextPowerOf2(SmallVTBits); 1266 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1267 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1268 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1269 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1270 // We found a type with free casts. 1271 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1272 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1273 Op.getNode()->getOperand(0)), 1274 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1275 Op.getNode()->getOperand(1))); 1276 bool NeedZext = DemandedSize > SmallVTBits; 1277 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, 1278 dl, Op.getValueType(), X); 1279 return CombineTo(Op, Z); 1280 } 1281 } 1282 return false; 1283 } 1284 1285 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1286 /// DemandedMask bits of the result of Op are ever used downstream. If we can 1287 /// use this information to simplify Op, create a new simplified DAG node and 1288 /// return true, returning the original and new nodes in Old and New. Otherwise, 1289 /// analyze the expression and return a mask of KnownOne and KnownZero bits for 1290 /// the expression (used to simplify the caller). The KnownZero/One bits may 1291 /// only be accurate for those bits in the DemandedMask. 1292 bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1293 const APInt &DemandedMask, 1294 APInt &KnownZero, 1295 APInt &KnownOne, 1296 TargetLoweringOpt &TLO, 1297 unsigned Depth) const { 1298 unsigned BitWidth = DemandedMask.getBitWidth(); 1299 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1300 "Mask size mismatches value type size!"); 1301 APInt NewMask = DemandedMask; 1302 DebugLoc dl = Op.getDebugLoc(); 1303 1304 // Don't know anything. 1305 KnownZero = KnownOne = APInt(BitWidth, 0); 1306 1307 // Other users may use these bits. 1308 if (!Op.getNode()->hasOneUse()) { 1309 if (Depth != 0) { 1310 // If not at the root, Just compute the KnownZero/KnownOne bits to 1311 // simplify things downstream. 1312 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1313 return false; 1314 } 1315 // If this is the root being simplified, allow it to have multiple uses, 1316 // just set the NewMask to all bits. 1317 NewMask = APInt::getAllOnesValue(BitWidth); 1318 } else if (DemandedMask == 0) { 1319 // Not demanding any bits from Op. 1320 if (Op.getOpcode() != ISD::UNDEF) 1321 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1322 return false; 1323 } else if (Depth == 6) { // Limit search depth. 1324 return false; 1325 } 1326 1327 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1328 switch (Op.getOpcode()) { 1329 case ISD::Constant: 1330 // We know all of the bits for a constant! 1331 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 1332 KnownZero = ~KnownOne; 1333 return false; // Don't fall through, will infinitely loop. 1334 case ISD::AND: 1335 // If the RHS is a constant, check to see if the LHS would be zero without 1336 // using the bits from the RHS. Below, we use knowledge about the RHS to 1337 // simplify the LHS, here we're using information from the LHS to simplify 1338 // the RHS. 1339 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1340 APInt LHSZero, LHSOne; 1341 // Do not increment Depth here; that can cause an infinite loop. 1342 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 1343 // If the LHS already has zeros where RHSC does, this and is dead. 1344 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1345 return TLO.CombineTo(Op, Op.getOperand(0)); 1346 // If any of the set bits in the RHS are known zero on the LHS, shrink 1347 // the constant. 1348 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1349 return true; 1350 } 1351 1352 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1353 KnownOne, TLO, Depth+1)) 1354 return true; 1355 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1356 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1357 KnownZero2, KnownOne2, TLO, Depth+1)) 1358 return true; 1359 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1360 1361 // If all of the demanded bits are known one on one side, return the other. 1362 // These bits cannot contribute to the result of the 'and'. 1363 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1364 return TLO.CombineTo(Op, Op.getOperand(0)); 1365 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1366 return TLO.CombineTo(Op, Op.getOperand(1)); 1367 // If all of the demanded bits in the inputs are known zeros, return zero. 1368 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1369 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1370 // If the RHS is a constant, see if we can simplify it. 1371 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1372 return true; 1373 // If the operation can be done in a smaller type, do so. 1374 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1375 return true; 1376 1377 // Output known-1 bits are only known if set in both the LHS & RHS. 1378 KnownOne &= KnownOne2; 1379 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1380 KnownZero |= KnownZero2; 1381 break; 1382 case ISD::OR: 1383 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1384 KnownOne, TLO, Depth+1)) 1385 return true; 1386 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1387 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1388 KnownZero2, KnownOne2, TLO, Depth+1)) 1389 return true; 1390 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1391 1392 // If all of the demanded bits are known zero on one side, return the other. 1393 // These bits cannot contribute to the result of the 'or'. 1394 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1395 return TLO.CombineTo(Op, Op.getOperand(0)); 1396 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1397 return TLO.CombineTo(Op, Op.getOperand(1)); 1398 // If all of the potentially set bits on one side are known to be set on 1399 // the other side, just use the 'other' side. 1400 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1401 return TLO.CombineTo(Op, Op.getOperand(0)); 1402 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1403 return TLO.CombineTo(Op, Op.getOperand(1)); 1404 // If the RHS is a constant, see if we can simplify it. 1405 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1406 return true; 1407 // If the operation can be done in a smaller type, do so. 1408 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1409 return true; 1410 1411 // Output known-0 bits are only known if clear in both the LHS & RHS. 1412 KnownZero &= KnownZero2; 1413 // Output known-1 are known to be set if set in either the LHS | RHS. 1414 KnownOne |= KnownOne2; 1415 break; 1416 case ISD::XOR: 1417 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1418 KnownOne, TLO, Depth+1)) 1419 return true; 1420 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1421 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1422 KnownOne2, TLO, Depth+1)) 1423 return true; 1424 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1425 1426 // If all of the demanded bits are known zero on one side, return the other. 1427 // These bits cannot contribute to the result of the 'xor'. 1428 if ((KnownZero & NewMask) == NewMask) 1429 return TLO.CombineTo(Op, Op.getOperand(0)); 1430 if ((KnownZero2 & NewMask) == NewMask) 1431 return TLO.CombineTo(Op, Op.getOperand(1)); 1432 // If the operation can be done in a smaller type, do so. 1433 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1434 return true; 1435 1436 // If all of the unknown bits are known to be zero on one side or the other 1437 // (but not both) turn this into an *inclusive* or. 1438 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1439 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1440 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1441 Op.getOperand(0), 1442 Op.getOperand(1))); 1443 1444 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1445 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1446 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1447 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1448 1449 // If all of the demanded bits on one side are known, and all of the set 1450 // bits on that side are also known to be set on the other side, turn this 1451 // into an AND, as we know the bits will be cleared. 1452 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1453 // NB: it is okay if more bits are known than are requested 1454 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 1455 if (KnownOne == KnownOne2) { // set bits are the same on both sides 1456 EVT VT = Op.getValueType(); 1457 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1458 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1459 Op.getOperand(0), ANDC)); 1460 } 1461 } 1462 1463 // If the RHS is a constant, see if we can simplify it. 1464 // for XOR, we prefer to force bits to 1 if they will make a -1. 1465 // if we can't force bits, try to shrink constant 1466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1467 APInt Expanded = C->getAPIntValue() | (~NewMask); 1468 // if we can expand it to have all bits set, do it 1469 if (Expanded.isAllOnesValue()) { 1470 if (Expanded != C->getAPIntValue()) { 1471 EVT VT = Op.getValueType(); 1472 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1473 TLO.DAG.getConstant(Expanded, VT)); 1474 return TLO.CombineTo(Op, New); 1475 } 1476 // if it already has all the bits set, nothing to change 1477 // but don't shrink either! 1478 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1479 return true; 1480 } 1481 } 1482 1483 KnownZero = KnownZeroOut; 1484 KnownOne = KnownOneOut; 1485 break; 1486 case ISD::SELECT: 1487 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1488 KnownOne, TLO, Depth+1)) 1489 return true; 1490 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1491 KnownOne2, TLO, Depth+1)) 1492 return true; 1493 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1494 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1495 1496 // If the operands are constants, see if we can simplify them. 1497 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1498 return true; 1499 1500 // Only known if known in both the LHS and RHS. 1501 KnownOne &= KnownOne2; 1502 KnownZero &= KnownZero2; 1503 break; 1504 case ISD::SELECT_CC: 1505 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1506 KnownOne, TLO, Depth+1)) 1507 return true; 1508 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1509 KnownOne2, TLO, Depth+1)) 1510 return true; 1511 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1512 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1513 1514 // If the operands are constants, see if we can simplify them. 1515 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1516 return true; 1517 1518 // Only known if known in both the LHS and RHS. 1519 KnownOne &= KnownOne2; 1520 KnownZero &= KnownZero2; 1521 break; 1522 case ISD::SHL: 1523 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1524 unsigned ShAmt = SA->getZExtValue(); 1525 SDValue InOp = Op.getOperand(0); 1526 1527 // If the shift count is an invalid immediate, don't do anything. 1528 if (ShAmt >= BitWidth) 1529 break; 1530 1531 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1532 // single shift. We can do this if the bottom bits (which are shifted 1533 // out) are never demanded. 1534 if (InOp.getOpcode() == ISD::SRL && 1535 isa<ConstantSDNode>(InOp.getOperand(1))) { 1536 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1537 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1538 unsigned Opc = ISD::SHL; 1539 int Diff = ShAmt-C1; 1540 if (Diff < 0) { 1541 Diff = -Diff; 1542 Opc = ISD::SRL; 1543 } 1544 1545 SDValue NewSA = 1546 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1547 EVT VT = Op.getValueType(); 1548 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1549 InOp.getOperand(0), NewSA)); 1550 } 1551 } 1552 1553 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1554 KnownZero, KnownOne, TLO, Depth+1)) 1555 return true; 1556 1557 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1558 // are not demanded. This will likely allow the anyext to be folded away. 1559 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1560 SDValue InnerOp = InOp.getNode()->getOperand(0); 1561 EVT InnerVT = InnerOp.getValueType(); 1562 unsigned InnerBits = InnerVT.getSizeInBits(); 1563 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 1564 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1565 EVT ShTy = getShiftAmountTy(InnerVT); 1566 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1567 ShTy = InnerVT; 1568 SDValue NarrowShl = 1569 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1570 TLO.DAG.getConstant(ShAmt, ShTy)); 1571 return 1572 TLO.CombineTo(Op, 1573 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1574 NarrowShl)); 1575 } 1576 } 1577 1578 KnownZero <<= SA->getZExtValue(); 1579 KnownOne <<= SA->getZExtValue(); 1580 // low bits known zero. 1581 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1582 } 1583 break; 1584 case ISD::SRL: 1585 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1586 EVT VT = Op.getValueType(); 1587 unsigned ShAmt = SA->getZExtValue(); 1588 unsigned VTSize = VT.getSizeInBits(); 1589 SDValue InOp = Op.getOperand(0); 1590 1591 // If the shift count is an invalid immediate, don't do anything. 1592 if (ShAmt >= BitWidth) 1593 break; 1594 1595 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1596 // single shift. We can do this if the top bits (which are shifted out) 1597 // are never demanded. 1598 if (InOp.getOpcode() == ISD::SHL && 1599 isa<ConstantSDNode>(InOp.getOperand(1))) { 1600 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1601 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1602 unsigned Opc = ISD::SRL; 1603 int Diff = ShAmt-C1; 1604 if (Diff < 0) { 1605 Diff = -Diff; 1606 Opc = ISD::SHL; 1607 } 1608 1609 SDValue NewSA = 1610 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1611 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1612 InOp.getOperand(0), NewSA)); 1613 } 1614 } 1615 1616 // Compute the new bits that are at the top now. 1617 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1618 KnownZero, KnownOne, TLO, Depth+1)) 1619 return true; 1620 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1621 KnownZero = KnownZero.lshr(ShAmt); 1622 KnownOne = KnownOne.lshr(ShAmt); 1623 1624 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1625 KnownZero |= HighBits; // High bits known zero. 1626 } 1627 break; 1628 case ISD::SRA: 1629 // If this is an arithmetic shift right and only the low-bit is set, we can 1630 // always convert this into a logical shr, even if the shift amount is 1631 // variable. The low bit of the shift cannot be an input sign bit unless 1632 // the shift amount is >= the size of the datatype, which is undefined. 1633 if (NewMask == 1) 1634 return TLO.CombineTo(Op, 1635 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1636 Op.getOperand(0), Op.getOperand(1))); 1637 1638 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1639 EVT VT = Op.getValueType(); 1640 unsigned ShAmt = SA->getZExtValue(); 1641 1642 // If the shift count is an invalid immediate, don't do anything. 1643 if (ShAmt >= BitWidth) 1644 break; 1645 1646 APInt InDemandedMask = (NewMask << ShAmt); 1647 1648 // If any of the demanded bits are produced by the sign extension, we also 1649 // demand the input sign bit. 1650 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1651 if (HighBits.intersects(NewMask)) 1652 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1653 1654 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1655 KnownZero, KnownOne, TLO, Depth+1)) 1656 return true; 1657 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1658 KnownZero = KnownZero.lshr(ShAmt); 1659 KnownOne = KnownOne.lshr(ShAmt); 1660 1661 // Handle the sign bit, adjusted to where it is now in the mask. 1662 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1663 1664 // If the input sign bit is known to be zero, or if none of the top bits 1665 // are demanded, turn this into an unsigned shift right. 1666 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1667 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1668 Op.getOperand(0), 1669 Op.getOperand(1))); 1670 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1671 KnownOne |= HighBits; 1672 } 1673 } 1674 break; 1675 case ISD::SIGN_EXTEND_INREG: { 1676 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1677 1678 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 1679 // If we only care about the highest bit, don't bother shifting right. 1680 if (MsbMask == DemandedMask) { 1681 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 1682 SDValue InOp = Op.getOperand(0); 1683 1684 // Compute the correct shift amount type, which must be getShiftAmountTy 1685 // for scalar types after legalization. 1686 EVT ShiftAmtTy = Op.getValueType(); 1687 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 1688 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 1689 1690 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 1691 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1692 Op.getValueType(), InOp, ShiftAmt)); 1693 } 1694 1695 // Sign extension. Compute the demanded bits in the result that are not 1696 // present in the input. 1697 APInt NewBits = 1698 APInt::getHighBitsSet(BitWidth, 1699 BitWidth - ExVT.getScalarType().getSizeInBits()); 1700 1701 // If none of the extended bits are demanded, eliminate the sextinreg. 1702 if ((NewBits & NewMask) == 0) 1703 return TLO.CombineTo(Op, Op.getOperand(0)); 1704 1705 APInt InSignBit = 1706 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 1707 APInt InputDemandedBits = 1708 APInt::getLowBitsSet(BitWidth, 1709 ExVT.getScalarType().getSizeInBits()) & 1710 NewMask; 1711 1712 // Since the sign extended bits are demanded, we know that the sign 1713 // bit is demanded. 1714 InputDemandedBits |= InSignBit; 1715 1716 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1717 KnownZero, KnownOne, TLO, Depth+1)) 1718 return true; 1719 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1720 1721 // If the sign bit of the input is known set or clear, then we know the 1722 // top bits of the result. 1723 1724 // If the input sign bit is known zero, convert this into a zero extension. 1725 if (KnownZero.intersects(InSignBit)) 1726 return TLO.CombineTo(Op, 1727 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 1728 1729 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1730 KnownOne |= NewBits; 1731 KnownZero &= ~NewBits; 1732 } else { // Input sign bit unknown 1733 KnownZero &= ~NewBits; 1734 KnownOne &= ~NewBits; 1735 } 1736 break; 1737 } 1738 case ISD::ZERO_EXTEND: { 1739 unsigned OperandBitWidth = 1740 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1741 APInt InMask = NewMask.trunc(OperandBitWidth); 1742 1743 // If none of the top bits are demanded, convert this into an any_extend. 1744 APInt NewBits = 1745 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1746 if (!NewBits.intersects(NewMask)) 1747 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1748 Op.getValueType(), 1749 Op.getOperand(0))); 1750 1751 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1752 KnownZero, KnownOne, TLO, Depth+1)) 1753 return true; 1754 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1755 KnownZero = KnownZero.zext(BitWidth); 1756 KnownOne = KnownOne.zext(BitWidth); 1757 KnownZero |= NewBits; 1758 break; 1759 } 1760 case ISD::SIGN_EXTEND: { 1761 EVT InVT = Op.getOperand(0).getValueType(); 1762 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1763 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1764 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1765 APInt NewBits = ~InMask & NewMask; 1766 1767 // If none of the top bits are demanded, convert this into an any_extend. 1768 if (NewBits == 0) 1769 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1770 Op.getValueType(), 1771 Op.getOperand(0))); 1772 1773 // Since some of the sign extended bits are demanded, we know that the sign 1774 // bit is demanded. 1775 APInt InDemandedBits = InMask & NewMask; 1776 InDemandedBits |= InSignBit; 1777 InDemandedBits = InDemandedBits.trunc(InBits); 1778 1779 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1780 KnownOne, TLO, Depth+1)) 1781 return true; 1782 KnownZero = KnownZero.zext(BitWidth); 1783 KnownOne = KnownOne.zext(BitWidth); 1784 1785 // If the sign bit is known zero, convert this to a zero extend. 1786 if (KnownZero.intersects(InSignBit)) 1787 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1788 Op.getValueType(), 1789 Op.getOperand(0))); 1790 1791 // If the sign bit is known one, the top bits match. 1792 if (KnownOne.intersects(InSignBit)) { 1793 KnownOne |= NewBits; 1794 assert((KnownZero & NewBits) == 0); 1795 } else { // Otherwise, top bits aren't known. 1796 assert((KnownOne & NewBits) == 0); 1797 assert((KnownZero & NewBits) == 0); 1798 } 1799 break; 1800 } 1801 case ISD::ANY_EXTEND: { 1802 unsigned OperandBitWidth = 1803 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1804 APInt InMask = NewMask.trunc(OperandBitWidth); 1805 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1806 KnownZero, KnownOne, TLO, Depth+1)) 1807 return true; 1808 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1809 KnownZero = KnownZero.zext(BitWidth); 1810 KnownOne = KnownOne.zext(BitWidth); 1811 break; 1812 } 1813 case ISD::TRUNCATE: { 1814 // Simplify the input, using demanded bit information, and compute the known 1815 // zero/one bits live out. 1816 unsigned OperandBitWidth = 1817 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1818 APInt TruncMask = NewMask.zext(OperandBitWidth); 1819 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1820 KnownZero, KnownOne, TLO, Depth+1)) 1821 return true; 1822 KnownZero = KnownZero.trunc(BitWidth); 1823 KnownOne = KnownOne.trunc(BitWidth); 1824 1825 // If the input is only used by this truncate, see if we can shrink it based 1826 // on the known demanded bits. 1827 if (Op.getOperand(0).getNode()->hasOneUse()) { 1828 SDValue In = Op.getOperand(0); 1829 switch (In.getOpcode()) { 1830 default: break; 1831 case ISD::SRL: 1832 // Shrink SRL by a constant if none of the high bits shifted in are 1833 // demanded. 1834 if (TLO.LegalTypes() && 1835 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1836 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1837 // undesirable. 1838 break; 1839 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1840 if (!ShAmt) 1841 break; 1842 SDValue Shift = In.getOperand(1); 1843 if (TLO.LegalTypes()) { 1844 uint64_t ShVal = ShAmt->getZExtValue(); 1845 Shift = 1846 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1847 } 1848 1849 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1850 OperandBitWidth - BitWidth); 1851 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1852 1853 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1854 // None of the shifted in bits are needed. Add a truncate of the 1855 // shift input, then shift it. 1856 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1857 Op.getValueType(), 1858 In.getOperand(0)); 1859 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1860 Op.getValueType(), 1861 NewTrunc, 1862 Shift)); 1863 } 1864 break; 1865 } 1866 } 1867 1868 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1869 break; 1870 } 1871 case ISD::AssertZext: { 1872 // AssertZext demands all of the high bits, plus any of the low bits 1873 // demanded by its users. 1874 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1875 APInt InMask = APInt::getLowBitsSet(BitWidth, 1876 VT.getSizeInBits()); 1877 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 1878 KnownZero, KnownOne, TLO, Depth+1)) 1879 return true; 1880 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1881 1882 KnownZero |= ~InMask & NewMask; 1883 break; 1884 } 1885 case ISD::BITCAST: 1886 // If this is an FP->Int bitcast and if the sign bit is the only 1887 // thing demanded, turn this into a FGETSIGN. 1888 if (!TLO.LegalOperations() && 1889 !Op.getValueType().isVector() && 1890 !Op.getOperand(0).getValueType().isVector() && 1891 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1892 Op.getOperand(0).getValueType().isFloatingPoint()) { 1893 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1894 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1895 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1896 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1897 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1898 // place. We expect the SHL to be eliminated by other optimizations. 1899 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1900 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1901 if (!OpVTLegal && OpVTSizeInBits > 32) 1902 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1903 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1904 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1905 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1906 Op.getValueType(), 1907 Sign, ShAmt)); 1908 } 1909 } 1910 break; 1911 case ISD::ADD: 1912 case ISD::MUL: 1913 case ISD::SUB: { 1914 // Add, Sub, and Mul don't demand any bits in positions beyond that 1915 // of the highest bit demanded of them. 1916 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1917 BitWidth - NewMask.countLeadingZeros()); 1918 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1919 KnownOne2, TLO, Depth+1)) 1920 return true; 1921 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1922 KnownOne2, TLO, Depth+1)) 1923 return true; 1924 // See if the operation should be performed at a smaller bit width. 1925 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1926 return true; 1927 } 1928 // FALL THROUGH 1929 default: 1930 // Just use ComputeMaskedBits to compute output bits. 1931 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1932 break; 1933 } 1934 1935 // If we know the value of all of the demanded bits, return this as a 1936 // constant. 1937 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1938 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1939 1940 return false; 1941 } 1942 1943 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 1944 /// in Mask are known to be either zero or one and return them in the 1945 /// KnownZero/KnownOne bitsets. 1946 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1947 APInt &KnownZero, 1948 APInt &KnownOne, 1949 const SelectionDAG &DAG, 1950 unsigned Depth) const { 1951 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1952 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1953 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1954 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1955 "Should use MaskedValueIsZero if you don't know whether Op" 1956 " is a target node!"); 1957 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1958 } 1959 1960 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1961 /// targets that want to expose additional information about sign bits to the 1962 /// DAG Combiner. 1963 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1964 unsigned Depth) const { 1965 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1966 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1967 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1968 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1969 "Should use ComputeNumSignBits if you don't know whether Op" 1970 " is a target node!"); 1971 return 1; 1972 } 1973 1974 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1975 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1976 /// determine which bit is set. 1977 /// 1978 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1979 // A left-shift of a constant one will have exactly one bit set, because 1980 // shifting the bit off the end is undefined. 1981 if (Val.getOpcode() == ISD::SHL) 1982 if (ConstantSDNode *C = 1983 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1984 if (C->getAPIntValue() == 1) 1985 return true; 1986 1987 // Similarly, a right-shift of a constant sign-bit will have exactly 1988 // one bit set. 1989 if (Val.getOpcode() == ISD::SRL) 1990 if (ConstantSDNode *C = 1991 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1992 if (C->getAPIntValue().isSignBit()) 1993 return true; 1994 1995 // More could be done here, though the above checks are enough 1996 // to handle some common cases. 1997 1998 // Fall back to ComputeMaskedBits to catch other known cases. 1999 EVT OpVT = Val.getValueType(); 2000 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 2001 APInt KnownZero, KnownOne; 2002 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 2003 return (KnownZero.countPopulation() == BitWidth - 1) && 2004 (KnownOne.countPopulation() == 1); 2005 } 2006 2007 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 2008 /// and cc. If it is unable to simplify it, return a null SDValue. 2009 SDValue 2010 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 2011 ISD::CondCode Cond, bool foldBooleans, 2012 DAGCombinerInfo &DCI, DebugLoc dl) const { 2013 SelectionDAG &DAG = DCI.DAG; 2014 2015 // These setcc operations always fold. 2016 switch (Cond) { 2017 default: break; 2018 case ISD::SETFALSE: 2019 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2020 case ISD::SETTRUE: 2021 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2022 } 2023 2024 // Ensure that the constant occurs on the RHS, and fold constant 2025 // comparisons. 2026 if (isa<ConstantSDNode>(N0.getNode())) 2027 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2028 2029 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 2030 const APInt &C1 = N1C->getAPIntValue(); 2031 2032 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 2033 // equality comparison, then we're just comparing whether X itself is 2034 // zero. 2035 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 2036 N0.getOperand(0).getOpcode() == ISD::CTLZ && 2037 N0.getOperand(1).getOpcode() == ISD::Constant) { 2038 const APInt &ShAmt 2039 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2040 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2041 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 2042 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 2043 // (srl (ctlz x), 5) == 0 -> X != 0 2044 // (srl (ctlz x), 5) != 1 -> X != 0 2045 Cond = ISD::SETNE; 2046 } else { 2047 // (srl (ctlz x), 5) != 0 -> X == 0 2048 // (srl (ctlz x), 5) == 1 -> X == 0 2049 Cond = ISD::SETEQ; 2050 } 2051 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2052 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 2053 Zero, Cond); 2054 } 2055 } 2056 2057 SDValue CTPOP = N0; 2058 // Look through truncs that don't change the value of a ctpop. 2059 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 2060 CTPOP = N0.getOperand(0); 2061 2062 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 2063 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 2064 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 2065 EVT CTVT = CTPOP.getValueType(); 2066 SDValue CTOp = CTPOP.getOperand(0); 2067 2068 // (ctpop x) u< 2 -> (x & x-1) == 0 2069 // (ctpop x) u> 1 -> (x & x-1) != 0 2070 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 2071 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 2072 DAG.getConstant(1, CTVT)); 2073 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 2074 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 2075 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 2076 } 2077 2078 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 2079 } 2080 2081 // (zext x) == C --> x == (trunc C) 2082 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 2083 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2084 unsigned MinBits = N0.getValueSizeInBits(); 2085 SDValue PreZExt; 2086 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 2087 // ZExt 2088 MinBits = N0->getOperand(0).getValueSizeInBits(); 2089 PreZExt = N0->getOperand(0); 2090 } else if (N0->getOpcode() == ISD::AND) { 2091 // DAGCombine turns costly ZExts into ANDs 2092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 2093 if ((C->getAPIntValue()+1).isPowerOf2()) { 2094 MinBits = C->getAPIntValue().countTrailingOnes(); 2095 PreZExt = N0->getOperand(0); 2096 } 2097 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 2098 // ZEXTLOAD 2099 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 2100 MinBits = LN0->getMemoryVT().getSizeInBits(); 2101 PreZExt = N0; 2102 } 2103 } 2104 2105 // Make sure we're not losing bits from the constant. 2106 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 2107 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 2108 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 2109 // Will get folded away. 2110 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 2111 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 2112 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 2113 } 2114 } 2115 } 2116 2117 // If the LHS is '(and load, const)', the RHS is 0, 2118 // the test is for equality or unsigned, and all 1 bits of the const are 2119 // in the same partial word, see if we can shorten the load. 2120 if (DCI.isBeforeLegalize() && 2121 N0.getOpcode() == ISD::AND && C1 == 0 && 2122 N0.getNode()->hasOneUse() && 2123 isa<LoadSDNode>(N0.getOperand(0)) && 2124 N0.getOperand(0).getNode()->hasOneUse() && 2125 isa<ConstantSDNode>(N0.getOperand(1))) { 2126 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 2127 APInt bestMask; 2128 unsigned bestWidth = 0, bestOffset = 0; 2129 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2130 unsigned origWidth = N0.getValueType().getSizeInBits(); 2131 unsigned maskWidth = origWidth; 2132 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2133 // 8 bits, but have to be careful... 2134 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2135 origWidth = Lod->getMemoryVT().getSizeInBits(); 2136 const APInt &Mask = 2137 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2138 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2139 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2140 for (unsigned offset=0; offset<origWidth/width; offset++) { 2141 if ((newMask & Mask) == Mask) { 2142 if (!TD->isLittleEndian()) 2143 bestOffset = (origWidth/width - offset - 1) * (width/8); 2144 else 2145 bestOffset = (uint64_t)offset * (width/8); 2146 bestMask = Mask.lshr(offset * (width/8) * 8); 2147 bestWidth = width; 2148 break; 2149 } 2150 newMask = newMask << width; 2151 } 2152 } 2153 } 2154 if (bestWidth) { 2155 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2156 if (newVT.isRound()) { 2157 EVT PtrType = Lod->getOperand(1).getValueType(); 2158 SDValue Ptr = Lod->getBasePtr(); 2159 if (bestOffset != 0) 2160 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2161 DAG.getConstant(bestOffset, PtrType)); 2162 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2163 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2164 Lod->getPointerInfo().getWithOffset(bestOffset), 2165 false, false, false, NewAlign); 2166 return DAG.getSetCC(dl, VT, 2167 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2168 DAG.getConstant(bestMask.trunc(bestWidth), 2169 newVT)), 2170 DAG.getConstant(0LL, newVT), Cond); 2171 } 2172 } 2173 } 2174 2175 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2176 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2177 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2178 2179 // If the comparison constant has bits in the upper part, the 2180 // zero-extended value could never match. 2181 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2182 C1.getBitWidth() - InSize))) { 2183 switch (Cond) { 2184 case ISD::SETUGT: 2185 case ISD::SETUGE: 2186 case ISD::SETEQ: return DAG.getConstant(0, VT); 2187 case ISD::SETULT: 2188 case ISD::SETULE: 2189 case ISD::SETNE: return DAG.getConstant(1, VT); 2190 case ISD::SETGT: 2191 case ISD::SETGE: 2192 // True if the sign bit of C1 is set. 2193 return DAG.getConstant(C1.isNegative(), VT); 2194 case ISD::SETLT: 2195 case ISD::SETLE: 2196 // True if the sign bit of C1 isn't set. 2197 return DAG.getConstant(C1.isNonNegative(), VT); 2198 default: 2199 break; 2200 } 2201 } 2202 2203 // Otherwise, we can perform the comparison with the low bits. 2204 switch (Cond) { 2205 case ISD::SETEQ: 2206 case ISD::SETNE: 2207 case ISD::SETUGT: 2208 case ISD::SETUGE: 2209 case ISD::SETULT: 2210 case ISD::SETULE: { 2211 EVT newVT = N0.getOperand(0).getValueType(); 2212 if (DCI.isBeforeLegalizeOps() || 2213 (isOperationLegal(ISD::SETCC, newVT) && 2214 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal)) 2215 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2216 DAG.getConstant(C1.trunc(InSize), newVT), 2217 Cond); 2218 break; 2219 } 2220 default: 2221 break; // todo, be more careful with signed comparisons 2222 } 2223 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2224 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2225 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2226 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2227 EVT ExtDstTy = N0.getValueType(); 2228 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2229 2230 // If the constant doesn't fit into the number of bits for the source of 2231 // the sign extension, it is impossible for both sides to be equal. 2232 if (C1.getMinSignedBits() > ExtSrcTyBits) 2233 return DAG.getConstant(Cond == ISD::SETNE, VT); 2234 2235 SDValue ZextOp; 2236 EVT Op0Ty = N0.getOperand(0).getValueType(); 2237 if (Op0Ty == ExtSrcTy) { 2238 ZextOp = N0.getOperand(0); 2239 } else { 2240 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2241 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2242 DAG.getConstant(Imm, Op0Ty)); 2243 } 2244 if (!DCI.isCalledByLegalizer()) 2245 DCI.AddToWorklist(ZextOp.getNode()); 2246 // Otherwise, make this a use of a zext. 2247 return DAG.getSetCC(dl, VT, ZextOp, 2248 DAG.getConstant(C1 & APInt::getLowBitsSet( 2249 ExtDstTyBits, 2250 ExtSrcTyBits), 2251 ExtDstTy), 2252 Cond); 2253 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2254 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2255 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2256 if (N0.getOpcode() == ISD::SETCC && 2257 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2258 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2259 if (TrueWhenTrue) 2260 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2261 // Invert the condition. 2262 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2263 CC = ISD::getSetCCInverse(CC, 2264 N0.getOperand(0).getValueType().isInteger()); 2265 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2266 } 2267 2268 if ((N0.getOpcode() == ISD::XOR || 2269 (N0.getOpcode() == ISD::AND && 2270 N0.getOperand(0).getOpcode() == ISD::XOR && 2271 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2272 isa<ConstantSDNode>(N0.getOperand(1)) && 2273 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2274 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2275 // can only do this if the top bits are known zero. 2276 unsigned BitWidth = N0.getValueSizeInBits(); 2277 if (DAG.MaskedValueIsZero(N0, 2278 APInt::getHighBitsSet(BitWidth, 2279 BitWidth-1))) { 2280 // Okay, get the un-inverted input value. 2281 SDValue Val; 2282 if (N0.getOpcode() == ISD::XOR) 2283 Val = N0.getOperand(0); 2284 else { 2285 assert(N0.getOpcode() == ISD::AND && 2286 N0.getOperand(0).getOpcode() == ISD::XOR); 2287 // ((X^1)&1)^1 -> X & 1 2288 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2289 N0.getOperand(0).getOperand(0), 2290 N0.getOperand(1)); 2291 } 2292 2293 return DAG.getSetCC(dl, VT, Val, N1, 2294 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2295 } 2296 } else if (N1C->getAPIntValue() == 1 && 2297 (VT == MVT::i1 || 2298 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 2299 SDValue Op0 = N0; 2300 if (Op0.getOpcode() == ISD::TRUNCATE) 2301 Op0 = Op0.getOperand(0); 2302 2303 if ((Op0.getOpcode() == ISD::XOR) && 2304 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2305 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2306 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2307 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2308 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2309 Cond); 2310 } 2311 if (Op0.getOpcode() == ISD::AND && 2312 isa<ConstantSDNode>(Op0.getOperand(1)) && 2313 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2314 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2315 if (Op0.getValueType().bitsGT(VT)) 2316 Op0 = DAG.getNode(ISD::AND, dl, VT, 2317 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2318 DAG.getConstant(1, VT)); 2319 else if (Op0.getValueType().bitsLT(VT)) 2320 Op0 = DAG.getNode(ISD::AND, dl, VT, 2321 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2322 DAG.getConstant(1, VT)); 2323 2324 return DAG.getSetCC(dl, VT, Op0, 2325 DAG.getConstant(0, Op0.getValueType()), 2326 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2327 } 2328 if (Op0.getOpcode() == ISD::AssertZext && 2329 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) 2330 return DAG.getSetCC(dl, VT, Op0, 2331 DAG.getConstant(0, Op0.getValueType()), 2332 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2333 } 2334 } 2335 2336 APInt MinVal, MaxVal; 2337 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2338 if (ISD::isSignedIntSetCC(Cond)) { 2339 MinVal = APInt::getSignedMinValue(OperandBitSize); 2340 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2341 } else { 2342 MinVal = APInt::getMinValue(OperandBitSize); 2343 MaxVal = APInt::getMaxValue(OperandBitSize); 2344 } 2345 2346 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2347 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2348 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2349 // X >= C0 --> X > (C0-1) 2350 return DAG.getSetCC(dl, VT, N0, 2351 DAG.getConstant(C1-1, N1.getValueType()), 2352 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2353 } 2354 2355 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2356 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2357 // X <= C0 --> X < (C0+1) 2358 return DAG.getSetCC(dl, VT, N0, 2359 DAG.getConstant(C1+1, N1.getValueType()), 2360 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2361 } 2362 2363 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2364 return DAG.getConstant(0, VT); // X < MIN --> false 2365 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2366 return DAG.getConstant(1, VT); // X >= MIN --> true 2367 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2368 return DAG.getConstant(0, VT); // X > MAX --> false 2369 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2370 return DAG.getConstant(1, VT); // X <= MAX --> true 2371 2372 // Canonicalize setgt X, Min --> setne X, Min 2373 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2374 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2375 // Canonicalize setlt X, Max --> setne X, Max 2376 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2377 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2378 2379 // If we have setult X, 1, turn it into seteq X, 0 2380 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2381 return DAG.getSetCC(dl, VT, N0, 2382 DAG.getConstant(MinVal, N0.getValueType()), 2383 ISD::SETEQ); 2384 // If we have setugt X, Max-1, turn it into seteq X, Max 2385 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2386 return DAG.getSetCC(dl, VT, N0, 2387 DAG.getConstant(MaxVal, N0.getValueType()), 2388 ISD::SETEQ); 2389 2390 // If we have "setcc X, C0", check to see if we can shrink the immediate 2391 // by changing cc. 2392 2393 // SETUGT X, SINTMAX -> SETLT X, 0 2394 if (Cond == ISD::SETUGT && 2395 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2396 return DAG.getSetCC(dl, VT, N0, 2397 DAG.getConstant(0, N1.getValueType()), 2398 ISD::SETLT); 2399 2400 // SETULT X, SINTMIN -> SETGT X, -1 2401 if (Cond == ISD::SETULT && 2402 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2403 SDValue ConstMinusOne = 2404 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2405 N1.getValueType()); 2406 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2407 } 2408 2409 // Fold bit comparisons when we can. 2410 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2411 (VT == N0.getValueType() || 2412 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2413 N0.getOpcode() == ISD::AND) 2414 if (ConstantSDNode *AndRHS = 2415 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2416 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 2417 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2418 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2419 // Perform the xform if the AND RHS is a single bit. 2420 if (AndRHS->getAPIntValue().isPowerOf2()) { 2421 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2422 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2423 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2424 } 2425 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2426 // (X & 8) == 8 --> (X & 8) >> 3 2427 // Perform the xform if C1 is a single bit. 2428 if (C1.isPowerOf2()) { 2429 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2430 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2431 DAG.getConstant(C1.logBase2(), ShiftTy))); 2432 } 2433 } 2434 } 2435 2436 if (C1.getMinSignedBits() <= 64 && 2437 !isLegalICmpImmediate(C1.getSExtValue())) { 2438 // (X & -256) == 256 -> (X >> 8) == 1 2439 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2440 N0.getOpcode() == ISD::AND && N0.hasOneUse()) { 2441 if (ConstantSDNode *AndRHS = 2442 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2443 const APInt &AndRHSC = AndRHS->getAPIntValue(); 2444 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { 2445 unsigned ShiftBits = AndRHSC.countTrailingZeros(); 2446 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 2447 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2448 EVT CmpTy = N0.getValueType(); 2449 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), 2450 DAG.getConstant(ShiftBits, ShiftTy)); 2451 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy); 2452 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 2453 } 2454 } 2455 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || 2456 Cond == ISD::SETULE || Cond == ISD::SETUGT) { 2457 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); 2458 // X < 0x100000000 -> (X >> 32) < 1 2459 // X >= 0x100000000 -> (X >> 32) >= 1 2460 // X <= 0x0ffffffff -> (X >> 32) < 1 2461 // X > 0x0ffffffff -> (X >> 32) >= 1 2462 unsigned ShiftBits; 2463 APInt NewC = C1; 2464 ISD::CondCode NewCond = Cond; 2465 if (AdjOne) { 2466 ShiftBits = C1.countTrailingOnes(); 2467 NewC = NewC + 1; 2468 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2469 } else { 2470 ShiftBits = C1.countTrailingZeros(); 2471 } 2472 NewC = NewC.lshr(ShiftBits); 2473 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { 2474 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 2475 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2476 EVT CmpTy = N0.getValueType(); 2477 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, 2478 DAG.getConstant(ShiftBits, ShiftTy)); 2479 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy); 2480 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 2481 } 2482 } 2483 } 2484 } 2485 2486 if (isa<ConstantFPSDNode>(N0.getNode())) { 2487 // Constant fold or commute setcc. 2488 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2489 if (O.getNode()) return O; 2490 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2491 // If the RHS of an FP comparison is a constant, simplify it away in 2492 // some cases. 2493 if (CFP->getValueAPF().isNaN()) { 2494 // If an operand is known to be a nan, we can fold it. 2495 switch (ISD::getUnorderedFlavor(Cond)) { 2496 default: llvm_unreachable("Unknown flavor!"); 2497 case 0: // Known false. 2498 return DAG.getConstant(0, VT); 2499 case 1: // Known true. 2500 return DAG.getConstant(1, VT); 2501 case 2: // Undefined. 2502 return DAG.getUNDEF(VT); 2503 } 2504 } 2505 2506 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2507 // constant if knowing that the operand is non-nan is enough. We prefer to 2508 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2509 // materialize 0.0. 2510 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2511 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2512 2513 // If the condition is not legal, see if we can find an equivalent one 2514 // which is legal. 2515 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { 2516 // If the comparison was an awkward floating-point == or != and one of 2517 // the comparison operands is infinity or negative infinity, convert the 2518 // condition to a less-awkward <= or >=. 2519 if (CFP->getValueAPF().isInfinity()) { 2520 if (CFP->getValueAPF().isNegative()) { 2521 if (Cond == ISD::SETOEQ && 2522 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 2523 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2524 if (Cond == ISD::SETUEQ && 2525 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 2526 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2527 if (Cond == ISD::SETUNE && 2528 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 2529 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2530 if (Cond == ISD::SETONE && 2531 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 2532 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2533 } else { 2534 if (Cond == ISD::SETOEQ && 2535 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 2536 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2537 if (Cond == ISD::SETUEQ && 2538 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 2539 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2540 if (Cond == ISD::SETUNE && 2541 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 2542 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2543 if (Cond == ISD::SETONE && 2544 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 2545 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2546 } 2547 } 2548 } 2549 } 2550 2551 if (N0 == N1) { 2552 // The sext(setcc()) => setcc() optimization relies on the appropriate 2553 // constant being emitted. 2554 uint64_t EqVal = 0; 2555 switch (getBooleanContents(N0.getValueType().isVector())) { 2556 case UndefinedBooleanContent: 2557 case ZeroOrOneBooleanContent: 2558 EqVal = ISD::isTrueWhenEqual(Cond); 2559 break; 2560 case ZeroOrNegativeOneBooleanContent: 2561 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0; 2562 break; 2563 } 2564 2565 // We can always fold X == X for integer setcc's. 2566 if (N0.getValueType().isInteger()) { 2567 return DAG.getConstant(EqVal, VT); 2568 } 2569 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2570 if (UOF == 2) // FP operators that are undefined on NaNs. 2571 return DAG.getConstant(EqVal, VT); 2572 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2573 return DAG.getConstant(EqVal, VT); 2574 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2575 // if it is not already. 2576 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2577 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || 2578 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) 2579 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2580 } 2581 2582 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2583 N0.getValueType().isInteger()) { 2584 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2585 N0.getOpcode() == ISD::XOR) { 2586 // Simplify (X+Y) == (X+Z) --> Y == Z 2587 if (N0.getOpcode() == N1.getOpcode()) { 2588 if (N0.getOperand(0) == N1.getOperand(0)) 2589 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2590 if (N0.getOperand(1) == N1.getOperand(1)) 2591 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2592 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2593 // If X op Y == Y op X, try other combinations. 2594 if (N0.getOperand(0) == N1.getOperand(1)) 2595 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2596 Cond); 2597 if (N0.getOperand(1) == N1.getOperand(0)) 2598 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2599 Cond); 2600 } 2601 } 2602 2603 // If RHS is a legal immediate value for a compare instruction, we need 2604 // to be careful about increasing register pressure needlessly. 2605 bool LegalRHSImm = false; 2606 2607 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2608 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2609 // Turn (X+C1) == C2 --> X == C2-C1 2610 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2611 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2612 DAG.getConstant(RHSC->getAPIntValue()- 2613 LHSR->getAPIntValue(), 2614 N0.getValueType()), Cond); 2615 } 2616 2617 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2618 if (N0.getOpcode() == ISD::XOR) 2619 // If we know that all of the inverted bits are zero, don't bother 2620 // performing the inversion. 2621 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2622 return 2623 DAG.getSetCC(dl, VT, N0.getOperand(0), 2624 DAG.getConstant(LHSR->getAPIntValue() ^ 2625 RHSC->getAPIntValue(), 2626 N0.getValueType()), 2627 Cond); 2628 } 2629 2630 // Turn (C1-X) == C2 --> X == C1-C2 2631 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2632 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2633 return 2634 DAG.getSetCC(dl, VT, N0.getOperand(1), 2635 DAG.getConstant(SUBC->getAPIntValue() - 2636 RHSC->getAPIntValue(), 2637 N0.getValueType()), 2638 Cond); 2639 } 2640 } 2641 2642 // Could RHSC fold directly into a compare? 2643 if (RHSC->getValueType(0).getSizeInBits() <= 64) 2644 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 2645 } 2646 2647 // Simplify (X+Z) == X --> Z == 0 2648 // Don't do this if X is an immediate that can fold into a cmp 2649 // instruction and X+Z has other uses. It could be an induction variable 2650 // chain, and the transform would increase register pressure. 2651 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 2652 if (N0.getOperand(0) == N1) 2653 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2654 DAG.getConstant(0, N0.getValueType()), Cond); 2655 if (N0.getOperand(1) == N1) { 2656 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2657 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2658 DAG.getConstant(0, N0.getValueType()), Cond); 2659 if (N0.getNode()->hasOneUse()) { 2660 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2661 // (Z-X) == X --> Z == X<<1 2662 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 2663 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2664 if (!DCI.isCalledByLegalizer()) 2665 DCI.AddToWorklist(SH.getNode()); 2666 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2667 } 2668 } 2669 } 2670 } 2671 2672 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2673 N1.getOpcode() == ISD::XOR) { 2674 // Simplify X == (X+Z) --> Z == 0 2675 if (N1.getOperand(0) == N0) 2676 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2677 DAG.getConstant(0, N1.getValueType()), Cond); 2678 if (N1.getOperand(1) == N0) { 2679 if (DAG.isCommutativeBinOp(N1.getOpcode())) 2680 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2681 DAG.getConstant(0, N1.getValueType()), Cond); 2682 if (N1.getNode()->hasOneUse()) { 2683 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2684 // X == (Z-X) --> X<<1 == Z 2685 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2686 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2687 if (!DCI.isCalledByLegalizer()) 2688 DCI.AddToWorklist(SH.getNode()); 2689 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2690 } 2691 } 2692 } 2693 2694 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2695 // Note that where y is variable and is known to have at most 2696 // one bit set (for example, if it is z&1) we cannot do this; 2697 // the expressions are not equivalent when y==0. 2698 if (N0.getOpcode() == ISD::AND) 2699 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2700 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2701 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2702 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2703 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2704 } 2705 } 2706 if (N1.getOpcode() == ISD::AND) 2707 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2708 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2709 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2710 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2711 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2712 } 2713 } 2714 } 2715 2716 // Fold away ALL boolean setcc's. 2717 SDValue Temp; 2718 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2719 switch (Cond) { 2720 default: llvm_unreachable("Unknown integer setcc!"); 2721 case ISD::SETEQ: // X == Y -> ~(X^Y) 2722 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2723 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2724 if (!DCI.isCalledByLegalizer()) 2725 DCI.AddToWorklist(Temp.getNode()); 2726 break; 2727 case ISD::SETNE: // X != Y --> (X^Y) 2728 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2729 break; 2730 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2731 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2732 Temp = DAG.getNOT(dl, N0, MVT::i1); 2733 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2734 if (!DCI.isCalledByLegalizer()) 2735 DCI.AddToWorklist(Temp.getNode()); 2736 break; 2737 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2738 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2739 Temp = DAG.getNOT(dl, N1, MVT::i1); 2740 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2741 if (!DCI.isCalledByLegalizer()) 2742 DCI.AddToWorklist(Temp.getNode()); 2743 break; 2744 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2745 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2746 Temp = DAG.getNOT(dl, N0, MVT::i1); 2747 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2748 if (!DCI.isCalledByLegalizer()) 2749 DCI.AddToWorklist(Temp.getNode()); 2750 break; 2751 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2752 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2753 Temp = DAG.getNOT(dl, N1, MVT::i1); 2754 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2755 break; 2756 } 2757 if (VT != MVT::i1) { 2758 if (!DCI.isCalledByLegalizer()) 2759 DCI.AddToWorklist(N0.getNode()); 2760 // FIXME: If running after legalize, we probably can't do this. 2761 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2762 } 2763 return N0; 2764 } 2765 2766 // Could not fold it. 2767 return SDValue(); 2768 } 2769 2770 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2771 /// node is a GlobalAddress + offset. 2772 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2773 int64_t &Offset) const { 2774 if (isa<GlobalAddressSDNode>(N)) { 2775 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2776 GA = GASD->getGlobal(); 2777 Offset += GASD->getOffset(); 2778 return true; 2779 } 2780 2781 if (N->getOpcode() == ISD::ADD) { 2782 SDValue N1 = N->getOperand(0); 2783 SDValue N2 = N->getOperand(1); 2784 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2785 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2786 if (V) { 2787 Offset += V->getSExtValue(); 2788 return true; 2789 } 2790 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2791 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2792 if (V) { 2793 Offset += V->getSExtValue(); 2794 return true; 2795 } 2796 } 2797 } 2798 2799 return false; 2800 } 2801 2802 2803 SDValue TargetLowering:: 2804 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2805 // Default implementation: no optimization. 2806 return SDValue(); 2807 } 2808 2809 //===----------------------------------------------------------------------===// 2810 // Inline Assembler Implementation Methods 2811 //===----------------------------------------------------------------------===// 2812 2813 2814 TargetLowering::ConstraintType 2815 TargetLowering::getConstraintType(const std::string &Constraint) const { 2816 if (Constraint.size() == 1) { 2817 switch (Constraint[0]) { 2818 default: break; 2819 case 'r': return C_RegisterClass; 2820 case 'm': // memory 2821 case 'o': // offsetable 2822 case 'V': // not offsetable 2823 return C_Memory; 2824 case 'i': // Simple Integer or Relocatable Constant 2825 case 'n': // Simple Integer 2826 case 'E': // Floating Point Constant 2827 case 'F': // Floating Point Constant 2828 case 's': // Relocatable Constant 2829 case 'p': // Address. 2830 case 'X': // Allow ANY value. 2831 case 'I': // Target registers. 2832 case 'J': 2833 case 'K': 2834 case 'L': 2835 case 'M': 2836 case 'N': 2837 case 'O': 2838 case 'P': 2839 case '<': 2840 case '>': 2841 return C_Other; 2842 } 2843 } 2844 2845 if (Constraint.size() > 1 && Constraint[0] == '{' && 2846 Constraint[Constraint.size()-1] == '}') 2847 return C_Register; 2848 return C_Unknown; 2849 } 2850 2851 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2852 /// with another that has more specific requirements based on the type of the 2853 /// corresponding operand. 2854 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2855 if (ConstraintVT.isInteger()) 2856 return "r"; 2857 if (ConstraintVT.isFloatingPoint()) 2858 return "f"; // works for many targets 2859 return 0; 2860 } 2861 2862 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2863 /// vector. If it is invalid, don't add anything to Ops. 2864 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2865 std::string &Constraint, 2866 std::vector<SDValue> &Ops, 2867 SelectionDAG &DAG) const { 2868 2869 if (Constraint.length() > 1) return; 2870 2871 char ConstraintLetter = Constraint[0]; 2872 switch (ConstraintLetter) { 2873 default: break; 2874 case 'X': // Allows any operand; labels (basic block) use this. 2875 if (Op.getOpcode() == ISD::BasicBlock) { 2876 Ops.push_back(Op); 2877 return; 2878 } 2879 // fall through 2880 case 'i': // Simple Integer or Relocatable Constant 2881 case 'n': // Simple Integer 2882 case 's': { // Relocatable Constant 2883 // These operands are interested in values of the form (GV+C), where C may 2884 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2885 // is possible and fine if either GV or C are missing. 2886 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2887 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2888 2889 // If we have "(add GV, C)", pull out GV/C 2890 if (Op.getOpcode() == ISD::ADD) { 2891 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2892 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2893 if (C == 0 || GA == 0) { 2894 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2895 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2896 } 2897 if (C == 0 || GA == 0) 2898 C = 0, GA = 0; 2899 } 2900 2901 // If we find a valid operand, map to the TargetXXX version so that the 2902 // value itself doesn't get selected. 2903 if (GA) { // Either &GV or &GV+C 2904 if (ConstraintLetter != 'n') { 2905 int64_t Offs = GA->getOffset(); 2906 if (C) Offs += C->getZExtValue(); 2907 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2908 C ? C->getDebugLoc() : DebugLoc(), 2909 Op.getValueType(), Offs)); 2910 return; 2911 } 2912 } 2913 if (C) { // just C, no GV. 2914 // Simple constants are not allowed for 's'. 2915 if (ConstraintLetter != 's') { 2916 // gcc prints these as sign extended. Sign extend value to 64 bits 2917 // now; without this it would get ZExt'd later in 2918 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2919 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2920 MVT::i64)); 2921 return; 2922 } 2923 } 2924 break; 2925 } 2926 } 2927 } 2928 2929 std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2930 getRegForInlineAsmConstraint(const std::string &Constraint, 2931 EVT VT) const { 2932 if (Constraint[0] != '{') 2933 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2934 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2935 2936 // Remove the braces from around the name. 2937 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2938 2939 std::pair<unsigned, const TargetRegisterClass*> R = 2940 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2941 2942 // Figure out which register class contains this reg. 2943 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2944 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2945 E = RI->regclass_end(); RCI != E; ++RCI) { 2946 const TargetRegisterClass *RC = *RCI; 2947 2948 // If none of the value types for this register class are valid, we 2949 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2950 if (!isLegalRC(RC)) 2951 continue; 2952 2953 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2954 I != E; ++I) { 2955 if (RegName.equals_lower(RI->getName(*I))) { 2956 std::pair<unsigned, const TargetRegisterClass*> S = 2957 std::make_pair(*I, RC); 2958 2959 // If this register class has the requested value type, return it, 2960 // otherwise keep searching and return the first class found 2961 // if no other is found which explicitly has the requested type. 2962 if (RC->hasType(VT)) 2963 return S; 2964 else if (!R.second) 2965 R = S; 2966 } 2967 } 2968 } 2969 2970 return R; 2971 } 2972 2973 //===----------------------------------------------------------------------===// 2974 // Constraint Selection. 2975 2976 /// isMatchingInputConstraint - Return true of this is an input operand that is 2977 /// a matching constraint like "4". 2978 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2979 assert(!ConstraintCode.empty() && "No known constraint!"); 2980 return isdigit(ConstraintCode[0]); 2981 } 2982 2983 /// getMatchedOperand - If this is an input matching constraint, this method 2984 /// returns the output operand it matches. 2985 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2986 assert(!ConstraintCode.empty() && "No known constraint!"); 2987 return atoi(ConstraintCode.c_str()); 2988 } 2989 2990 2991 /// ParseConstraints - Split up the constraint string from the inline 2992 /// assembly value into the specific constraints and their prefixes, 2993 /// and also tie in the associated operand values. 2994 /// If this returns an empty vector, and if the constraint string itself 2995 /// isn't empty, there was an error parsing. 2996 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2997 ImmutableCallSite CS) const { 2998 /// ConstraintOperands - Information about all of the constraints. 2999 AsmOperandInfoVector ConstraintOperands; 3000 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 3001 unsigned maCount = 0; // Largest number of multiple alternative constraints. 3002 3003 // Do a prepass over the constraints, canonicalizing them, and building up the 3004 // ConstraintOperands list. 3005 InlineAsm::ConstraintInfoVector 3006 ConstraintInfos = IA->ParseConstraints(); 3007 3008 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 3009 unsigned ResNo = 0; // ResNo - The result number of the next output. 3010 3011 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 3012 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 3013 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 3014 3015 // Update multiple alternative constraint count. 3016 if (OpInfo.multipleAlternatives.size() > maCount) 3017 maCount = OpInfo.multipleAlternatives.size(); 3018 3019 OpInfo.ConstraintVT = MVT::Other; 3020 3021 // Compute the value type for each operand. 3022 switch (OpInfo.Type) { 3023 case InlineAsm::isOutput: 3024 // Indirect outputs just consume an argument. 3025 if (OpInfo.isIndirect) { 3026 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 3027 break; 3028 } 3029 3030 // The return value of the call is this value. As such, there is no 3031 // corresponding argument. 3032 assert(!CS.getType()->isVoidTy() && 3033 "Bad inline asm!"); 3034 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 3035 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo)); 3036 } else { 3037 assert(ResNo == 0 && "Asm only has one result!"); 3038 OpInfo.ConstraintVT = getSimpleValueType(CS.getType()); 3039 } 3040 ++ResNo; 3041 break; 3042 case InlineAsm::isInput: 3043 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 3044 break; 3045 case InlineAsm::isClobber: 3046 // Nothing to do. 3047 break; 3048 } 3049 3050 if (OpInfo.CallOperandVal) { 3051 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 3052 if (OpInfo.isIndirect) { 3053 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 3054 if (!PtrTy) 3055 report_fatal_error("Indirect operand for inline asm not a pointer!"); 3056 OpTy = PtrTy->getElementType(); 3057 } 3058 3059 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 3060 if (StructType *STy = dyn_cast<StructType>(OpTy)) 3061 if (STy->getNumElements() == 1) 3062 OpTy = STy->getElementType(0); 3063 3064 // If OpTy is not a single value, it may be a struct/union that we 3065 // can tile with integers. 3066 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 3067 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 3068 switch (BitSize) { 3069 default: break; 3070 case 1: 3071 case 8: 3072 case 16: 3073 case 32: 3074 case 64: 3075 case 128: 3076 OpInfo.ConstraintVT = 3077 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); 3078 break; 3079 } 3080 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { 3081 OpInfo.ConstraintVT = MVT::getIntegerVT( 3082 8*TD->getPointerSize(PT->getAddressSpace())); 3083 } else { 3084 OpInfo.ConstraintVT = MVT::getVT(OpTy, true); 3085 } 3086 } 3087 } 3088 3089 // If we have multiple alternative constraints, select the best alternative. 3090 if (ConstraintInfos.size()) { 3091 if (maCount) { 3092 unsigned bestMAIndex = 0; 3093 int bestWeight = -1; 3094 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 3095 int weight = -1; 3096 unsigned maIndex; 3097 // Compute the sums of the weights for each alternative, keeping track 3098 // of the best (highest weight) one so far. 3099 for (maIndex = 0; maIndex < maCount; ++maIndex) { 3100 int weightSum = 0; 3101 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 3102 cIndex != eIndex; ++cIndex) { 3103 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 3104 if (OpInfo.Type == InlineAsm::isClobber) 3105 continue; 3106 3107 // If this is an output operand with a matching input operand, 3108 // look up the matching input. If their types mismatch, e.g. one 3109 // is an integer, the other is floating point, or their sizes are 3110 // different, flag it as an maCantMatch. 3111 if (OpInfo.hasMatchingInput()) { 3112 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 3113 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 3114 if ((OpInfo.ConstraintVT.isInteger() != 3115 Input.ConstraintVT.isInteger()) || 3116 (OpInfo.ConstraintVT.getSizeInBits() != 3117 Input.ConstraintVT.getSizeInBits())) { 3118 weightSum = -1; // Can't match. 3119 break; 3120 } 3121 } 3122 } 3123 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 3124 if (weight == -1) { 3125 weightSum = -1; 3126 break; 3127 } 3128 weightSum += weight; 3129 } 3130 // Update best. 3131 if (weightSum > bestWeight) { 3132 bestWeight = weightSum; 3133 bestMAIndex = maIndex; 3134 } 3135 } 3136 3137 // Now select chosen alternative in each constraint. 3138 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 3139 cIndex != eIndex; ++cIndex) { 3140 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 3141 if (cInfo.Type == InlineAsm::isClobber) 3142 continue; 3143 cInfo.selectAlternative(bestMAIndex); 3144 } 3145 } 3146 } 3147 3148 // Check and hook up tied operands, choose constraint code to use. 3149 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 3150 cIndex != eIndex; ++cIndex) { 3151 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 3152 3153 // If this is an output operand with a matching input operand, look up the 3154 // matching input. If their types mismatch, e.g. one is an integer, the 3155 // other is floating point, or their sizes are different, flag it as an 3156 // error. 3157 if (OpInfo.hasMatchingInput()) { 3158 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 3159 3160 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 3161 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 3162 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 3163 OpInfo.ConstraintVT); 3164 std::pair<unsigned, const TargetRegisterClass*> InputRC = 3165 getRegForInlineAsmConstraint(Input.ConstraintCode, 3166 Input.ConstraintVT); 3167 if ((OpInfo.ConstraintVT.isInteger() != 3168 Input.ConstraintVT.isInteger()) || 3169 (MatchRC.second != InputRC.second)) { 3170 report_fatal_error("Unsupported asm: input constraint" 3171 " with a matching output constraint of" 3172 " incompatible type!"); 3173 } 3174 } 3175 3176 } 3177 } 3178 3179 return ConstraintOperands; 3180 } 3181 3182 3183 /// getConstraintGenerality - Return an integer indicating how general CT 3184 /// is. 3185 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 3186 switch (CT) { 3187 case TargetLowering::C_Other: 3188 case TargetLowering::C_Unknown: 3189 return 0; 3190 case TargetLowering::C_Register: 3191 return 1; 3192 case TargetLowering::C_RegisterClass: 3193 return 2; 3194 case TargetLowering::C_Memory: 3195 return 3; 3196 } 3197 llvm_unreachable("Invalid constraint type"); 3198 } 3199 3200 /// Examine constraint type and operand type and determine a weight value. 3201 /// This object must already have been set up with the operand type 3202 /// and the current alternative constraint selected. 3203 TargetLowering::ConstraintWeight 3204 TargetLowering::getMultipleConstraintMatchWeight( 3205 AsmOperandInfo &info, int maIndex) const { 3206 InlineAsm::ConstraintCodeVector *rCodes; 3207 if (maIndex >= (int)info.multipleAlternatives.size()) 3208 rCodes = &info.Codes; 3209 else 3210 rCodes = &info.multipleAlternatives[maIndex].Codes; 3211 ConstraintWeight BestWeight = CW_Invalid; 3212 3213 // Loop over the options, keeping track of the most general one. 3214 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 3215 ConstraintWeight weight = 3216 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 3217 if (weight > BestWeight) 3218 BestWeight = weight; 3219 } 3220 3221 return BestWeight; 3222 } 3223 3224 /// Examine constraint type and operand type and determine a weight value. 3225 /// This object must already have been set up with the operand type 3226 /// and the current alternative constraint selected. 3227 TargetLowering::ConstraintWeight 3228 TargetLowering::getSingleConstraintMatchWeight( 3229 AsmOperandInfo &info, const char *constraint) const { 3230 ConstraintWeight weight = CW_Invalid; 3231 Value *CallOperandVal = info.CallOperandVal; 3232 // If we don't have a value, we can't do a match, 3233 // but allow it at the lowest weight. 3234 if (CallOperandVal == NULL) 3235 return CW_Default; 3236 // Look at the constraint type. 3237 switch (*constraint) { 3238 case 'i': // immediate integer. 3239 case 'n': // immediate integer with a known value. 3240 if (isa<ConstantInt>(CallOperandVal)) 3241 weight = CW_Constant; 3242 break; 3243 case 's': // non-explicit intregal immediate. 3244 if (isa<GlobalValue>(CallOperandVal)) 3245 weight = CW_Constant; 3246 break; 3247 case 'E': // immediate float if host format. 3248 case 'F': // immediate float. 3249 if (isa<ConstantFP>(CallOperandVal)) 3250 weight = CW_Constant; 3251 break; 3252 case '<': // memory operand with autodecrement. 3253 case '>': // memory operand with autoincrement. 3254 case 'm': // memory operand. 3255 case 'o': // offsettable memory operand 3256 case 'V': // non-offsettable memory operand 3257 weight = CW_Memory; 3258 break; 3259 case 'r': // general register. 3260 case 'g': // general register, memory operand or immediate integer. 3261 // note: Clang converts "g" to "imr". 3262 if (CallOperandVal->getType()->isIntegerTy()) 3263 weight = CW_Register; 3264 break; 3265 case 'X': // any operand. 3266 default: 3267 weight = CW_Default; 3268 break; 3269 } 3270 return weight; 3271 } 3272 3273 /// ChooseConstraint - If there are multiple different constraints that we 3274 /// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3275 /// This is somewhat tricky: constraints fall into four classes: 3276 /// Other -> immediates and magic values 3277 /// Register -> one specific register 3278 /// RegisterClass -> a group of regs 3279 /// Memory -> memory 3280 /// Ideally, we would pick the most specific constraint possible: if we have 3281 /// something that fits into a register, we would pick it. The problem here 3282 /// is that if we have something that could either be in a register or in 3283 /// memory that use of the register could cause selection of *other* 3284 /// operands to fail: they might only succeed if we pick memory. Because of 3285 /// this the heuristic we use is: 3286 /// 3287 /// 1) If there is an 'other' constraint, and if the operand is valid for 3288 /// that constraint, use it. This makes us take advantage of 'i' 3289 /// constraints when available. 3290 /// 2) Otherwise, pick the most general constraint present. This prefers 3291 /// 'm' over 'r', for example. 3292 /// 3293 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3294 const TargetLowering &TLI, 3295 SDValue Op, SelectionDAG *DAG) { 3296 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3297 unsigned BestIdx = 0; 3298 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3299 int BestGenerality = -1; 3300 3301 // Loop over the options, keeping track of the most general one. 3302 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3303 TargetLowering::ConstraintType CType = 3304 TLI.getConstraintType(OpInfo.Codes[i]); 3305 3306 // If this is an 'other' constraint, see if the operand is valid for it. 3307 // For example, on X86 we might have an 'rI' constraint. If the operand 3308 // is an integer in the range [0..31] we want to use I (saving a load 3309 // of a register), otherwise we must use 'r'. 3310 if (CType == TargetLowering::C_Other && Op.getNode()) { 3311 assert(OpInfo.Codes[i].size() == 1 && 3312 "Unhandled multi-letter 'other' constraint"); 3313 std::vector<SDValue> ResultOps; 3314 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 3315 ResultOps, *DAG); 3316 if (!ResultOps.empty()) { 3317 BestType = CType; 3318 BestIdx = i; 3319 break; 3320 } 3321 } 3322 3323 // Things with matching constraints can only be registers, per gcc 3324 // documentation. This mainly affects "g" constraints. 3325 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3326 continue; 3327 3328 // This constraint letter is more general than the previous one, use it. 3329 int Generality = getConstraintGenerality(CType); 3330 if (Generality > BestGenerality) { 3331 BestType = CType; 3332 BestIdx = i; 3333 BestGenerality = Generality; 3334 } 3335 } 3336 3337 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3338 OpInfo.ConstraintType = BestType; 3339 } 3340 3341 /// ComputeConstraintToUse - Determines the constraint code and constraint 3342 /// type to use for the specific AsmOperandInfo, setting 3343 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3344 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3345 SDValue Op, 3346 SelectionDAG *DAG) const { 3347 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3348 3349 // Single-letter constraints ('r') are very common. 3350 if (OpInfo.Codes.size() == 1) { 3351 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3352 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3353 } else { 3354 ChooseConstraint(OpInfo, *this, Op, DAG); 3355 } 3356 3357 // 'X' matches anything. 3358 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3359 // Labels and constants are handled elsewhere ('X' is the only thing 3360 // that matches labels). For Functions, the type here is the type of 3361 // the result, which is not what we want to look at; leave them alone. 3362 Value *v = OpInfo.CallOperandVal; 3363 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3364 OpInfo.CallOperandVal = v; 3365 return; 3366 } 3367 3368 // Otherwise, try to resolve it to something we know about by looking at 3369 // the actual operand type. 3370 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3371 OpInfo.ConstraintCode = Repl; 3372 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3373 } 3374 } 3375 } 3376 3377 //===----------------------------------------------------------------------===// 3378 // Loop Strength Reduction hooks 3379 //===----------------------------------------------------------------------===// 3380 3381 /// isLegalAddressingMode - Return true if the addressing mode represented 3382 /// by AM is legal for this target, for a load/store of the specified type. 3383 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3384 Type *Ty) const { 3385 // The default implementation of this implements a conservative RISCy, r+r and 3386 // r+i addr mode. 3387 3388 // Allows a sign-extended 16-bit immediate field. 3389 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3390 return false; 3391 3392 // No global is ever allowed as a base. 3393 if (AM.BaseGV) 3394 return false; 3395 3396 // Only support r+r, 3397 switch (AM.Scale) { 3398 case 0: // "r+i" or just "i", depending on HasBaseReg. 3399 break; 3400 case 1: 3401 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3402 return false; 3403 // Otherwise we have r+r or r+i. 3404 break; 3405 case 2: 3406 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3407 return false; 3408 // Allow 2*r as r+r. 3409 break; 3410 } 3411 3412 return true; 3413 } 3414 3415 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication 3416 /// with the multiplicative inverse of the constant. 3417 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 3418 SelectionDAG &DAG) const { 3419 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 3420 APInt d = C->getAPIntValue(); 3421 assert(d != 0 && "Division by zero!"); 3422 3423 // Shift the value upfront if it is even, so the LSB is one. 3424 unsigned ShAmt = d.countTrailingZeros(); 3425 if (ShAmt) { 3426 // TODO: For UDIV use SRL instead of SRA. 3427 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 3428 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 3429 d = d.ashr(ShAmt); 3430 } 3431 3432 // Calculate the multiplicative inverse, using Newton's method. 3433 APInt t, xn = d; 3434 while ((t = d*xn) != 1) 3435 xn *= APInt(d.getBitWidth(), 2) - t; 3436 3437 Op2 = DAG.getConstant(xn, Op1.getValueType()); 3438 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 3439 } 3440 3441 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3442 /// return a DAG expression to select that will generate the same value by 3443 /// multiplying by a magic number. See: 3444 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3445 SDValue TargetLowering:: 3446 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3447 std::vector<SDNode*> *Created) const { 3448 EVT VT = N->getValueType(0); 3449 DebugLoc dl= N->getDebugLoc(); 3450 3451 // Check to see if we can do this. 3452 // FIXME: We should be more aggressive here. 3453 if (!isTypeLegal(VT)) 3454 return SDValue(); 3455 3456 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3457 APInt::ms magics = d.magic(); 3458 3459 // Multiply the numerator (operand 0) by the magic value 3460 // FIXME: We should support doing a MUL in a wider type 3461 SDValue Q; 3462 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 3463 isOperationLegalOrCustom(ISD::MULHS, VT)) 3464 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3465 DAG.getConstant(magics.m, VT)); 3466 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 3467 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3468 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3469 N->getOperand(0), 3470 DAG.getConstant(magics.m, VT)).getNode(), 1); 3471 else 3472 return SDValue(); // No mulhs or equvialent 3473 // If d > 0 and m < 0, add the numerator 3474 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3475 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3476 if (Created) 3477 Created->push_back(Q.getNode()); 3478 } 3479 // If d < 0 and m > 0, subtract the numerator. 3480 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3481 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3482 if (Created) 3483 Created->push_back(Q.getNode()); 3484 } 3485 // Shift right algebraic if shift value is nonzero 3486 if (magics.s > 0) { 3487 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3488 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3489 if (Created) 3490 Created->push_back(Q.getNode()); 3491 } 3492 // Extract the sign bit and add it to the quotient 3493 SDValue T = 3494 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3495 getShiftAmountTy(Q.getValueType()))); 3496 if (Created) 3497 Created->push_back(T.getNode()); 3498 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3499 } 3500 3501 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3502 /// return a DAG expression to select that will generate the same value by 3503 /// multiplying by a magic number. See: 3504 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3505 SDValue TargetLowering:: 3506 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3507 std::vector<SDNode*> *Created) const { 3508 EVT VT = N->getValueType(0); 3509 DebugLoc dl = N->getDebugLoc(); 3510 3511 // Check to see if we can do this. 3512 // FIXME: We should be more aggressive here. 3513 if (!isTypeLegal(VT)) 3514 return SDValue(); 3515 3516 // FIXME: We should use a narrower constant when the upper 3517 // bits are known to be zero. 3518 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3519 APInt::mu magics = N1C.magicu(); 3520 3521 SDValue Q = N->getOperand(0); 3522 3523 // If the divisor is even, we can avoid using the expensive fixup by shifting 3524 // the divided value upfront. 3525 if (magics.a != 0 && !N1C[0]) { 3526 unsigned Shift = N1C.countTrailingZeros(); 3527 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3528 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3529 if (Created) 3530 Created->push_back(Q.getNode()); 3531 3532 // Get magic number for the shifted divisor. 3533 magics = N1C.lshr(Shift).magicu(Shift); 3534 assert(magics.a == 0 && "Should use cheap fixup now"); 3535 } 3536 3537 // Multiply the numerator (operand 0) by the magic value 3538 // FIXME: We should support doing a MUL in a wider type 3539 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 3540 isOperationLegalOrCustom(ISD::MULHU, VT)) 3541 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3542 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 3543 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3544 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3545 DAG.getConstant(magics.m, VT)).getNode(), 1); 3546 else 3547 return SDValue(); // No mulhu or equvialent 3548 if (Created) 3549 Created->push_back(Q.getNode()); 3550 3551 if (magics.a == 0) { 3552 assert(magics.s < N1C.getBitWidth() && 3553 "We shouldn't generate an undefined shift!"); 3554 return DAG.getNode(ISD::SRL, dl, VT, Q, 3555 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3556 } else { 3557 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3558 if (Created) 3559 Created->push_back(NPQ.getNode()); 3560 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3561 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3562 if (Created) 3563 Created->push_back(NPQ.getNode()); 3564 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3565 if (Created) 3566 Created->push_back(NPQ.getNode()); 3567 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3568 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3569 } 3570 } 3571