1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating functions from LLVM IR into
10 // Machine IR.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/FunctionLoweringInfo.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetFrameLowering.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/CodeGen/TargetLowering.h"
25 #include "llvm/CodeGen/TargetRegisterInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/CodeGen/WasmEHFuncInfo.h"
28 #include "llvm/CodeGen/WinEHFuncInfo.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Instructions.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/LLVMContext.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include <algorithm>
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "function-lowering-info"
45 
46 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
47 /// PHI nodes or outside of the basic block that defines it, or used by a
48 /// switch or atomic instruction, which may expand to multiple basic blocks.
49 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
50   if (I->use_empty()) return false;
51   if (isa<PHINode>(I)) return true;
52   const BasicBlock *BB = I->getParent();
53   for (const User *U : I->users())
54     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
55       return true;
56 
57   return false;
58 }
59 
60 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
61                                SelectionDAG *DAG) {
62   Fn = &fn;
63   MF = &mf;
64   TLI = MF->getSubtarget().getTargetLowering();
65   RegInfo = &MF->getRegInfo();
66   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
67   DA = DAG->getDivergenceAnalysis();
68 
69   // Check whether the function can return without sret-demotion.
70   SmallVector<ISD::OutputArg, 4> Outs;
71   CallingConv::ID CC = Fn->getCallingConv();
72 
73   GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
74                 mf.getDataLayout());
75   CanLowerReturn =
76       TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
77 
78   // If this personality uses funclets, we need to do a bit more work.
79   DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
80   EHPersonality Personality = classifyEHPersonality(
81       Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
82   if (isFuncletEHPersonality(Personality)) {
83     // Calculate state numbers if we haven't already.
84     WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
85     if (Personality == EHPersonality::MSVC_CXX)
86       calculateWinCXXEHStateNumbers(&fn, EHInfo);
87     else if (isAsynchronousEHPersonality(Personality))
88       calculateSEHStateNumbers(&fn, EHInfo);
89     else if (Personality == EHPersonality::CoreCLR)
90       calculateClrEHStateNumbers(&fn, EHInfo);
91 
92     // Map all BB references in the WinEH data to MBBs.
93     for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
94       for (WinEHHandlerType &H : TBME.HandlerArray) {
95         if (const AllocaInst *AI = H.CatchObj.Alloca)
96           CatchObjects.insert({AI, {}}).first->second.push_back(
97               &H.CatchObj.FrameIndex);
98         else
99           H.CatchObj.FrameIndex = INT_MAX;
100       }
101     }
102   }
103   if (Personality == EHPersonality::Wasm_CXX) {
104     WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
105     calculateWasmEHInfo(&fn, EHInfo);
106   }
107 
108   // Initialize the mapping of values to registers.  This is only set up for
109   // instruction values that are used outside of the block that defines
110   // them.
111   const Align StackAlign = TFI->getStackAlign();
112   for (const BasicBlock &BB : *Fn) {
113     for (const Instruction &I : BB) {
114       if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
115         Type *Ty = AI->getAllocatedType();
116         Align TyPrefAlign = MF->getDataLayout().getPrefTypeAlign(Ty);
117         // The "specified" alignment is the alignment written on the alloca,
118         // or the preferred alignment of the type if none is specified.
119         //
120         // (Unspecified alignment on allocas will be going away soon.)
121         Align SpecifiedAlign = AI->getAlign();
122 
123         // If the preferred alignment of the type is higher than the specified
124         // alignment of the alloca, promote the alignment, as long as it doesn't
125         // require realigning the stack.
126         //
127         // FIXME: Do we really want to second-guess the IR in isel?
128         Align Alignment =
129             std::max(std::min(TyPrefAlign, StackAlign), SpecifiedAlign);
130 
131         // Static allocas can be folded into the initial stack frame
132         // adjustment. For targets that don't realign the stack, don't
133         // do this if there is an extra alignment requirement.
134         if (AI->isStaticAlloca() &&
135             (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
136           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
137           uint64_t TySize =
138               MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinSize();
139 
140           TySize *= CUI->getZExtValue();   // Get total allocated size.
141           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
142           int FrameIndex = INT_MAX;
143           auto Iter = CatchObjects.find(AI);
144           if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
145             FrameIndex = MF->getFrameInfo().CreateFixedObject(
146                 TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true);
147             MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment);
148           } else {
149             FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment,
150                                                               false, AI);
151           }
152 
153           // Scalable vectors may need a special StackID to distinguish
154           // them from other (fixed size) stack objects.
155           if (isa<ScalableVectorType>(Ty))
156             MF->getFrameInfo().setStackID(FrameIndex,
157                                           TFI->getStackIDForScalableVectors());
158 
159           StaticAllocaMap[AI] = FrameIndex;
160           // Update the catch handler information.
161           if (Iter != CatchObjects.end()) {
162             for (int *CatchObjPtr : Iter->second)
163               *CatchObjPtr = FrameIndex;
164           }
165         } else {
166           // FIXME: Overaligned static allocas should be grouped into
167           // a single dynamic allocation instead of using a separate
168           // stack allocation for each one.
169           // Inform the Frame Information that we have variable-sized objects.
170           MF->getFrameInfo().CreateVariableSizedObject(
171               Alignment <= StackAlign ? Align(1) : Alignment, AI);
172         }
173       } else if (auto *Call = dyn_cast<CallBase>(&I)) {
174         // Look for inline asm that clobbers the SP register.
175         if (Call->isInlineAsm()) {
176           Register SP = TLI->getStackPointerRegisterToSaveRestore();
177           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
178           std::vector<TargetLowering::AsmOperandInfo> Ops =
179               TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI,
180                                     *Call);
181           for (TargetLowering::AsmOperandInfo &Op : Ops) {
182             if (Op.Type == InlineAsm::isClobber) {
183               // Clobbers don't have SDValue operands, hence SDValue().
184               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
185               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
186                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
187                                                     Op.ConstraintVT);
188               if (PhysReg.first == SP)
189                 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
190             }
191           }
192         }
193         // Look for calls to the @llvm.va_start intrinsic. We can omit some
194         // prologue boilerplate for variadic functions that don't examine their
195         // arguments.
196         if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
197           if (II->getIntrinsicID() == Intrinsic::vastart)
198             MF->getFrameInfo().setHasVAStart(true);
199         }
200 
201         // If we have a musttail call in a variadic function, we need to ensure
202         // we forward implicit register parameters.
203         if (const auto *CI = dyn_cast<CallInst>(&I)) {
204           if (CI->isMustTailCall() && Fn->isVarArg())
205             MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
206         }
207       }
208 
209       // Mark values used outside their block as exported, by allocating
210       // a virtual register for them.
211       if (isUsedOutsideOfDefiningBlock(&I))
212         if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I)))
213           InitializeRegForValue(&I);
214     }
215   }
216 
217   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
218   // also creates the initial PHI MachineInstrs, though none of the input
219   // operands are populated.
220   for (const BasicBlock &BB : *Fn) {
221     // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
222     // are really data, and no instructions can live here.
223     if (BB.isEHPad()) {
224       const Instruction *PadInst = BB.getFirstNonPHI();
225       // If this is a non-landingpad EH pad, mark this function as using
226       // funclets.
227       // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
228       // setting this in such cases in order to improve frame layout.
229       if (!isa<LandingPadInst>(PadInst)) {
230         MF->setHasEHScopes(true);
231         MF->setHasEHFunclets(true);
232         MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
233       }
234       if (isa<CatchSwitchInst>(PadInst)) {
235         assert(&*BB.begin() == PadInst &&
236                "WinEHPrepare failed to remove PHIs from imaginary BBs");
237         continue;
238       }
239       if (isa<FuncletPadInst>(PadInst))
240         assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
241     }
242 
243     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
244     MBBMap[&BB] = MBB;
245     MF->push_back(MBB);
246 
247     // Transfer the address-taken flag. This is necessary because there could
248     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
249     // the first one should be marked.
250     if (BB.hasAddressTaken())
251       MBB->setHasAddressTaken();
252 
253     // Mark landing pad blocks.
254     if (BB.isEHPad())
255       MBB->setIsEHPad();
256 
257     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
258     // appropriate.
259     for (const PHINode &PN : BB.phis()) {
260       if (PN.use_empty())
261         continue;
262 
263       // Skip empty types
264       if (PN.getType()->isEmptyTy())
265         continue;
266 
267       DebugLoc DL = PN.getDebugLoc();
268       unsigned PHIReg = ValueMap[&PN];
269       assert(PHIReg && "PHI node does not have an assigned virtual register!");
270 
271       SmallVector<EVT, 4> ValueVTs;
272       ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
273       for (EVT VT : ValueVTs) {
274         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
275         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
276         for (unsigned i = 0; i != NumRegisters; ++i)
277           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
278         PHIReg += NumRegisters;
279       }
280     }
281   }
282 
283   if (isFuncletEHPersonality(Personality)) {
284     WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
285 
286     // Map all BB references in the WinEH data to MBBs.
287     for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
288       for (WinEHHandlerType &H : TBME.HandlerArray) {
289         if (H.Handler)
290           H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()];
291       }
292     }
293     for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
294       if (UME.Cleanup)
295         UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()];
296     for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
297       const auto *BB = UME.Handler.get<const BasicBlock *>();
298       UME.Handler = MBBMap[BB];
299     }
300     for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
301       const auto *BB = CME.Handler.get<const BasicBlock *>();
302       CME.Handler = MBBMap[BB];
303     }
304   }
305 
306   else if (Personality == EHPersonality::Wasm_CXX) {
307     WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
308     // Map all BB references in the Wasm EH data to MBBs.
309     DenseMap<BBOrMBB, BBOrMBB> SrcToUnwindDest;
310     for (auto &KV : EHInfo.SrcToUnwindDest) {
311       const auto *Src = KV.first.get<const BasicBlock *>();
312       const auto *Dest = KV.second.get<const BasicBlock *>();
313       SrcToUnwindDest[MBBMap[Src]] = MBBMap[Dest];
314     }
315     EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest);
316     DenseMap<BBOrMBB, SmallPtrSet<BBOrMBB, 4>> UnwindDestToSrcs;
317     for (auto &KV : EHInfo.UnwindDestToSrcs) {
318       const auto *Dest = KV.first.get<const BasicBlock *>();
319       UnwindDestToSrcs[MBBMap[Dest]] = SmallPtrSet<BBOrMBB, 4>();
320       for (const auto P : KV.second)
321         UnwindDestToSrcs[MBBMap[Dest]].insert(
322             MBBMap[P.get<const BasicBlock *>()]);
323     }
324     EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs);
325   }
326 }
327 
328 /// clear - Clear out all the function-specific state. This returns this
329 /// FunctionLoweringInfo to an empty state, ready to be used for a
330 /// different function.
331 void FunctionLoweringInfo::clear() {
332   MBBMap.clear();
333   ValueMap.clear();
334   VirtReg2Value.clear();
335   StaticAllocaMap.clear();
336   LiveOutRegInfo.clear();
337   VisitedBBs.clear();
338   ArgDbgValues.clear();
339   DescribedArgs.clear();
340   ByValArgFrameIndexMap.clear();
341   RegFixups.clear();
342   RegsWithFixups.clear();
343   StatepointStackSlots.clear();
344   StatepointRelocationMaps.clear();
345   PreferredExtendType.clear();
346 }
347 
348 /// CreateReg - Allocate a single virtual register for the given type.
349 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
350   return RegInfo->createVirtualRegister(
351       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
352 }
353 
354 /// CreateRegs - Allocate the appropriate number of virtual registers of
355 /// the correctly promoted or expanded types.  Assign these registers
356 /// consecutive vreg numbers and return the first assigned number.
357 ///
358 /// In the case that the given value has struct or array type, this function
359 /// will assign registers for each member or element.
360 ///
361 Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
362   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
363 
364   SmallVector<EVT, 4> ValueVTs;
365   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
366 
367   Register FirstReg;
368   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
369     EVT ValueVT = ValueVTs[Value];
370     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
371 
372     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
373     for (unsigned i = 0; i != NumRegs; ++i) {
374       Register R = CreateReg(RegisterVT, isDivergent);
375       if (!FirstReg) FirstReg = R;
376     }
377   }
378   return FirstReg;
379 }
380 
381 Register FunctionLoweringInfo::CreateRegs(const Value *V) {
382   return CreateRegs(V->getType(), DA && DA->isDivergent(V) &&
383                     !TLI->requiresUniformRegister(*MF, V));
384 }
385 
386 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
387 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
388 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
389 /// the larger bit width by zero extension. The bit width must be no smaller
390 /// than the LiveOutInfo's existing bit width.
391 const FunctionLoweringInfo::LiveOutInfo *
392 FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) {
393   if (!LiveOutRegInfo.inBounds(Reg))
394     return nullptr;
395 
396   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
397   if (!LOI->IsValid)
398     return nullptr;
399 
400   if (BitWidth > LOI->Known.getBitWidth()) {
401     LOI->NumSignBits = 1;
402     LOI->Known = LOI->Known.anyext(BitWidth);
403   }
404 
405   return LOI;
406 }
407 
408 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
409 /// register based on the LiveOutInfo of its operands.
410 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
411   Type *Ty = PN->getType();
412   if (!Ty->isIntegerTy() || Ty->isVectorTy())
413     return;
414 
415   SmallVector<EVT, 1> ValueVTs;
416   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
417   assert(ValueVTs.size() == 1 &&
418          "PHIs with non-vector integer types should have a single VT.");
419   EVT IntVT = ValueVTs[0];
420 
421   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
422     return;
423   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
424   unsigned BitWidth = IntVT.getSizeInBits();
425 
426   Register DestReg = ValueMap[PN];
427   if (!Register::isVirtualRegister(DestReg))
428     return;
429   LiveOutRegInfo.grow(DestReg);
430   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
431 
432   Value *V = PN->getIncomingValue(0);
433   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
434     DestLOI.NumSignBits = 1;
435     DestLOI.Known = KnownBits(BitWidth);
436     return;
437   }
438 
439   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
440     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
441     DestLOI.NumSignBits = Val.getNumSignBits();
442     DestLOI.Known = KnownBits::makeConstant(Val);
443   } else {
444     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
445                                 "CopyToReg node was created.");
446     Register SrcReg = ValueMap[V];
447     if (!Register::isVirtualRegister(SrcReg)) {
448       DestLOI.IsValid = false;
449       return;
450     }
451     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
452     if (!SrcLOI) {
453       DestLOI.IsValid = false;
454       return;
455     }
456     DestLOI = *SrcLOI;
457   }
458 
459   assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
460          DestLOI.Known.One.getBitWidth() == BitWidth &&
461          "Masks should have the same bit width as the type.");
462 
463   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
464     Value *V = PN->getIncomingValue(i);
465     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
466       DestLOI.NumSignBits = 1;
467       DestLOI.Known = KnownBits(BitWidth);
468       return;
469     }
470 
471     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
472       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
473       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
474       DestLOI.Known.Zero &= ~Val;
475       DestLOI.Known.One &= Val;
476       continue;
477     }
478 
479     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
480                                 "its CopyToReg node was created.");
481     Register SrcReg = ValueMap[V];
482     if (!SrcReg.isVirtual()) {
483       DestLOI.IsValid = false;
484       return;
485     }
486     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
487     if (!SrcLOI) {
488       DestLOI.IsValid = false;
489       return;
490     }
491     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
492     DestLOI.Known = KnownBits::commonBits(DestLOI.Known, SrcLOI->Known);
493   }
494 }
495 
496 /// setArgumentFrameIndex - Record frame index for the byval
497 /// argument. This overrides previous frame index entry for this argument,
498 /// if any.
499 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
500                                                  int FI) {
501   ByValArgFrameIndexMap[A] = FI;
502 }
503 
504 /// getArgumentFrameIndex - Get frame index for the byval argument.
505 /// If the argument does not have any assigned frame index then 0 is
506 /// returned.
507 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
508   auto I = ByValArgFrameIndexMap.find(A);
509   if (I != ByValArgFrameIndexMap.end())
510     return I->second;
511   LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
512   return INT_MAX;
513 }
514 
515 Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
516     const Value *CPI, const TargetRegisterClass *RC) {
517   MachineRegisterInfo &MRI = MF->getRegInfo();
518   auto I = CatchPadExceptionPointers.insert({CPI, 0});
519   Register &VReg = I.first->second;
520   if (I.second)
521     VReg = MRI.createVirtualRegister(RC);
522   assert(VReg && "null vreg in exception pointer table!");
523   return VReg;
524 }
525 
526 const Value *
527 FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
528   if (VirtReg2Value.empty()) {
529     SmallVector<EVT, 4> ValueVTs;
530     for (auto &P : ValueMap) {
531       ValueVTs.clear();
532       ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(),
533                       P.first->getType(), ValueVTs);
534       unsigned Reg = P.second;
535       for (EVT VT : ValueVTs) {
536         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
537         for (unsigned i = 0, e = NumRegisters; i != e; ++i)
538           VirtReg2Value[Reg++] = P.first;
539       }
540     }
541   }
542   return VirtReg2Value.lookup(Vreg);
543 }
544