1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating functions from LLVM IR into
11 // Machine IR.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define DEBUG_TYPE "function-lowering-info"
16 #include "llvm/CodeGen/FunctionLoweringInfo.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Instructions.h"
20 #include "llvm/IntrinsicInst.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/Module.h"
23 #include "llvm/Analysis/DebugInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include <algorithm>
39 using namespace llvm;
40 
41 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
42 /// PHI nodes or outside of the basic block that defines it, or used by a
43 /// switch or atomic instruction, which may expand to multiple basic blocks.
44 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
45   if (I->use_empty()) return false;
46   if (isa<PHINode>(I)) return true;
47   const BasicBlock *BB = I->getParent();
48   for (Value::const_use_iterator UI = I->use_begin(), E = I->use_end();
49         UI != E; ++UI) {
50     const User *U = *UI;
51     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
52       return true;
53   }
54   return false;
55 }
56 
57 FunctionLoweringInfo::FunctionLoweringInfo(const TargetLowering &tli)
58   : TLI(tli) {
59 }
60 
61 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
62   Fn = &fn;
63   MF = &mf;
64   RegInfo = &MF->getRegInfo();
65 
66   // Check whether the function can return without sret-demotion.
67   SmallVector<ISD::OutputArg, 4> Outs;
68   GetReturnInfo(Fn->getReturnType(),
69                 Fn->getAttributes().getRetAttributes(), Outs, TLI);
70   CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), Fn->isVarArg(),
71                                       Outs, Fn->getContext());
72 
73   // Initialize the mapping of values to registers.  This is only set up for
74   // instruction values that are used outside of the block that defines
75   // them.
76   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
77   for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
78     if (const AllocaInst *AI = dyn_cast<AllocaInst>(I))
79       if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
80         const Type *Ty = AI->getAllocatedType();
81         uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
82         unsigned Align =
83           std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
84                    AI->getAlignment());
85 
86         TySize *= CUI->getZExtValue();   // Get total allocated size.
87         if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
88 
89         // The object may need to be placed onto the stack near the stack
90         // protector if one exists. Determine here if this object is a suitable
91         // candidate. I.e., it would trigger the creation of a stack protector.
92         bool MayNeedSP =
93           (AI->isArrayAllocation() ||
94            (TySize > 8 && isa<ArrayType>(Ty) &&
95             cast<ArrayType>(Ty)->getElementType()->isIntegerTy(8)));
96         StaticAllocaMap[AI] =
97           MF->getFrameInfo()->CreateStackObject(TySize, Align, false, MayNeedSP);
98       }
99 
100   for (; BB != EB; ++BB)
101     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
102       // Mark values used outside their block as exported, by allocating
103       // a virtual register for them.
104       if (isUsedOutsideOfDefiningBlock(I))
105         if (!isa<AllocaInst>(I) ||
106             !StaticAllocaMap.count(cast<AllocaInst>(I)))
107           InitializeRegForValue(I);
108 
109       // Collect llvm.dbg.declare information. This is done now instead of
110       // during the initial isel pass through the IR so that it is done
111       // in a predictable order.
112       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
113         MachineModuleInfo &MMI = MF->getMMI();
114         if (MMI.hasDebugInfo() &&
115             DIVariable(DI->getVariable()).Verify() &&
116             !DI->getDebugLoc().isUnknown()) {
117           // Don't handle byval struct arguments or VLAs, for example.
118           // Non-byval arguments are handled here (they refer to the stack
119           // temporary alloca at this point).
120           const Value *Address = DI->getAddress();
121           if (Address) {
122             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
123               Address = BCI->getOperand(0);
124             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
125               DenseMap<const AllocaInst *, int>::iterator SI =
126                 StaticAllocaMap.find(AI);
127               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
128                 int FI = SI->second;
129                 MMI.setVariableDbgInfo(DI->getVariable(),
130                                        FI, DI->getDebugLoc());
131               }
132             }
133           }
134         }
135       }
136     }
137 
138   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
139   // also creates the initial PHI MachineInstrs, though none of the input
140   // operands are populated.
141   for (BB = Fn->begin(); BB != EB; ++BB) {
142     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
143     MBBMap[BB] = MBB;
144     MF->push_back(MBB);
145 
146     // Transfer the address-taken flag. This is necessary because there could
147     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
148     // the first one should be marked.
149     if (BB->hasAddressTaken())
150       MBB->setHasAddressTaken();
151 
152     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
153     // appropriate.
154     for (BasicBlock::const_iterator I = BB->begin();
155          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
156       if (PN->use_empty()) continue;
157 
158       // Skip empty types
159       if (PN->getType()->isEmptyTy())
160         continue;
161 
162       DebugLoc DL = PN->getDebugLoc();
163       unsigned PHIReg = ValueMap[PN];
164       assert(PHIReg && "PHI node does not have an assigned virtual register!");
165 
166       SmallVector<EVT, 4> ValueVTs;
167       ComputeValueVTs(TLI, PN->getType(), ValueVTs);
168       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
169         EVT VT = ValueVTs[vti];
170         unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT);
171         const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
172         for (unsigned i = 0; i != NumRegisters; ++i)
173           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
174         PHIReg += NumRegisters;
175       }
176     }
177   }
178 
179   // Mark landing pad blocks.
180   for (BB = Fn->begin(); BB != EB; ++BB)
181     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
182       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
183 }
184 
185 /// clear - Clear out all the function-specific state. This returns this
186 /// FunctionLoweringInfo to an empty state, ready to be used for a
187 /// different function.
188 void FunctionLoweringInfo::clear() {
189   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
190          "Not all catch info was assigned to a landing pad!");
191 
192   MBBMap.clear();
193   ValueMap.clear();
194   StaticAllocaMap.clear();
195 #ifndef NDEBUG
196   CatchInfoLost.clear();
197   CatchInfoFound.clear();
198 #endif
199   LiveOutRegInfo.clear();
200   VisitedBBs.clear();
201   ArgDbgValues.clear();
202   ByValArgFrameIndexMap.clear();
203   RegFixups.clear();
204 }
205 
206 /// CreateReg - Allocate a single virtual register for the given type.
207 unsigned FunctionLoweringInfo::CreateReg(EVT VT) {
208   return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
209 }
210 
211 /// CreateRegs - Allocate the appropriate number of virtual registers of
212 /// the correctly promoted or expanded types.  Assign these registers
213 /// consecutive vreg numbers and return the first assigned number.
214 ///
215 /// In the case that the given value has struct or array type, this function
216 /// will assign registers for each member or element.
217 ///
218 unsigned FunctionLoweringInfo::CreateRegs(const Type *Ty) {
219   SmallVector<EVT, 4> ValueVTs;
220   ComputeValueVTs(TLI, Ty, ValueVTs);
221 
222   unsigned FirstReg = 0;
223   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
224     EVT ValueVT = ValueVTs[Value];
225     EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
226 
227     unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
228     for (unsigned i = 0; i != NumRegs; ++i) {
229       unsigned R = CreateReg(RegisterVT);
230       if (!FirstReg) FirstReg = R;
231     }
232   }
233   return FirstReg;
234 }
235 
236 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
237 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
238 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
239 /// the larger bit width by zero extension. The bit width must be no smaller
240 /// than the LiveOutInfo's existing bit width.
241 const FunctionLoweringInfo::LiveOutInfo *
242 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
243   if (!LiveOutRegInfo.inBounds(Reg))
244     return NULL;
245 
246   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
247   if (!LOI->IsValid)
248     return NULL;
249 
250   if (BitWidth > LOI->KnownZero.getBitWidth()) {
251     LOI->NumSignBits = 1;
252     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
253     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
254   }
255 
256   return LOI;
257 }
258 
259 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
260 /// register based on the LiveOutInfo of its operands.
261 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
262   const Type *Ty = PN->getType();
263   if (!Ty->isIntegerTy() || Ty->isVectorTy())
264     return;
265 
266   SmallVector<EVT, 1> ValueVTs;
267   ComputeValueVTs(TLI, Ty, ValueVTs);
268   assert(ValueVTs.size() == 1 &&
269          "PHIs with non-vector integer types should have a single VT.");
270   EVT IntVT = ValueVTs[0];
271 
272   if (TLI.getNumRegisters(PN->getContext(), IntVT) != 1)
273     return;
274   IntVT = TLI.getTypeToTransformTo(PN->getContext(), IntVT);
275   unsigned BitWidth = IntVT.getSizeInBits();
276 
277   unsigned DestReg = ValueMap[PN];
278   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
279     return;
280   LiveOutRegInfo.grow(DestReg);
281   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
282 
283   Value *V = PN->getIncomingValue(0);
284   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
285     DestLOI.NumSignBits = 1;
286     APInt Zero(BitWidth, 0);
287     DestLOI.KnownZero = Zero;
288     DestLOI.KnownOne = Zero;
289     return;
290   }
291 
292   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
293     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
294     DestLOI.NumSignBits = Val.getNumSignBits();
295     DestLOI.KnownZero = ~Val;
296     DestLOI.KnownOne = Val;
297   } else {
298     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
299                                 "CopyToReg node was created.");
300     unsigned SrcReg = ValueMap[V];
301     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
302       DestLOI.IsValid = false;
303       return;
304     }
305     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
306     if (!SrcLOI) {
307       DestLOI.IsValid = false;
308       return;
309     }
310     DestLOI = *SrcLOI;
311   }
312 
313   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
314          DestLOI.KnownOne.getBitWidth() == BitWidth &&
315          "Masks should have the same bit width as the type.");
316 
317   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
318     Value *V = PN->getIncomingValue(i);
319     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
320       DestLOI.NumSignBits = 1;
321       APInt Zero(BitWidth, 0);
322       DestLOI.KnownZero = Zero;
323       DestLOI.KnownOne = Zero;
324       return;
325     }
326 
327     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
328       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
329       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
330       DestLOI.KnownZero &= ~Val;
331       DestLOI.KnownOne &= Val;
332       continue;
333     }
334 
335     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
336                                 "its CopyToReg node was created.");
337     unsigned SrcReg = ValueMap[V];
338     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
339       DestLOI.IsValid = false;
340       return;
341     }
342     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
343     if (!SrcLOI) {
344       DestLOI.IsValid = false;
345       return;
346     }
347     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
348     DestLOI.KnownZero &= SrcLOI->KnownZero;
349     DestLOI.KnownOne &= SrcLOI->KnownOne;
350   }
351 }
352 
353 /// setByValArgumentFrameIndex - Record frame index for the byval
354 /// argument. This overrides previous frame index entry for this argument,
355 /// if any.
356 void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A,
357                                                       int FI) {
358   assert (A->hasByValAttr() && "Argument does not have byval attribute!");
359   ByValArgFrameIndexMap[A] = FI;
360 }
361 
362 /// getByValArgumentFrameIndex - Get frame index for the byval argument.
363 /// If the argument does not have any assigned frame index then 0 is
364 /// returned.
365 int FunctionLoweringInfo::getByValArgumentFrameIndex(const Argument *A) {
366   assert (A->hasByValAttr() && "Argument does not have byval attribute!");
367   DenseMap<const Argument *, int>::iterator I =
368     ByValArgFrameIndexMap.find(A);
369   if (I != ByValArgFrameIndexMap.end())
370     return I->second;
371   DEBUG(dbgs() << "Argument does not have assigned frame index!");
372   return 0;
373 }
374 
375 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
376 /// call, and add them to the specified machine basic block.
377 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
378                         MachineBasicBlock *MBB) {
379   // Inform the MachineModuleInfo of the personality for this landing pad.
380   const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
381   assert(CE->getOpcode() == Instruction::BitCast &&
382          isa<Function>(CE->getOperand(0)) &&
383          "Personality should be a function");
384   MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
385 
386   // Gather all the type infos for this landing pad and pass them along to
387   // MachineModuleInfo.
388   std::vector<const GlobalVariable *> TyInfo;
389   unsigned N = I.getNumArgOperands();
390 
391   for (unsigned i = N - 1; i > 1; --i) {
392     if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
393       unsigned FilterLength = CI->getZExtValue();
394       unsigned FirstCatch = i + FilterLength + !FilterLength;
395       assert(FirstCatch <= N && "Invalid filter length");
396 
397       if (FirstCatch < N) {
398         TyInfo.reserve(N - FirstCatch);
399         for (unsigned j = FirstCatch; j < N; ++j)
400           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
401         MMI->addCatchTypeInfo(MBB, TyInfo);
402         TyInfo.clear();
403       }
404 
405       if (!FilterLength) {
406         // Cleanup.
407         MMI->addCleanup(MBB);
408       } else {
409         // Filter.
410         TyInfo.reserve(FilterLength - 1);
411         for (unsigned j = i + 1; j < FirstCatch; ++j)
412           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
413         MMI->addFilterTypeInfo(MBB, TyInfo);
414         TyInfo.clear();
415       }
416 
417       N = i;
418     }
419   }
420 
421   if (N > 2) {
422     TyInfo.reserve(N - 2);
423     for (unsigned j = 2; j < N; ++j)
424       TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
425     MMI->addCatchTypeInfo(MBB, TyInfo);
426   }
427 }
428 
429 void llvm::CopyCatchInfo(const BasicBlock *SuccBB, const BasicBlock *LPad,
430                          MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
431   SmallPtrSet<const BasicBlock*, 4> Visited;
432 
433   // The 'eh.selector' call may not be in the direct successor of a basic block,
434   // but could be several successors deeper. If we don't find it, try going one
435   // level further. <rdar://problem/8824861>
436   while (Visited.insert(SuccBB)) {
437     for (BasicBlock::const_iterator I = SuccBB->begin(), E = --SuccBB->end();
438          I != E; ++I)
439       if (const EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
440         // Apply the catch info to LPad.
441         AddCatchInfo(*EHSel, MMI, FLI.MBBMap[LPad]);
442 #ifndef NDEBUG
443         if (!FLI.MBBMap[SuccBB]->isLandingPad())
444           FLI.CatchInfoFound.insert(EHSel);
445 #endif
446         return;
447       }
448 
449     const BranchInst *Br = dyn_cast<BranchInst>(SuccBB->getTerminator());
450     if (Br && Br->isUnconditional())
451       SuccBB = Br->getSuccessor(0);
452     else
453       break;
454   }
455 }
456