168ac7b17SMircea Trofin //===- MLRegAllocEvictAdvisor.cpp - ML eviction advisor -------------------===// 268ac7b17SMircea Trofin // 368ac7b17SMircea Trofin // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 468ac7b17SMircea Trofin // See https://llvm.org/LICENSE.txt for license information. 568ac7b17SMircea Trofin // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 668ac7b17SMircea Trofin // 768ac7b17SMircea Trofin //===----------------------------------------------------------------------===// 868ac7b17SMircea Trofin // 968ac7b17SMircea Trofin // Implementation of the ML eviction advisor and reward injection pass 1068ac7b17SMircea Trofin // 1168ac7b17SMircea Trofin //===----------------------------------------------------------------------===// 1268ac7b17SMircea Trofin 13989f1c72Sserge-sans-paille #include "AllocationOrder.h" 1468ac7b17SMircea Trofin #include "RegAllocEvictionAdvisor.h" 15e67430ccSMircea Trofin #include "RegAllocGreedy.h" 16e67430ccSMircea Trofin #include "llvm/Analysis/AliasAnalysis.h" 1768ac7b17SMircea Trofin #include "llvm/Analysis/MLModelRunner.h" 18*f658ca1aSMircea Trofin #if defined(LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL) || defined(LLVM_HAVE_TF_API) 19*f658ca1aSMircea Trofin #include "llvm/Analysis/ModelUnderTrainingRunner.h" 20*f658ca1aSMircea Trofin #include "llvm/Analysis/NoInferenceModelRunner.h" 21*f658ca1aSMircea Trofin #endif 22e67430ccSMircea Trofin #include "llvm/Analysis/ReleaseModeModelRunner.h" 2368ac7b17SMircea Trofin #include "llvm/CodeGen/CalcSpillWeights.h" 24989f1c72Sserge-sans-paille #include "llvm/CodeGen/LiveRegMatrix.h" 2568ac7b17SMircea Trofin #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 2668ac7b17SMircea Trofin #include "llvm/CodeGen/MachineFunction.h" 2768ac7b17SMircea Trofin #include "llvm/CodeGen/MachineLoopInfo.h" 28e67430ccSMircea Trofin #include "llvm/CodeGen/MachineRegisterInfo.h" 29e67430ccSMircea Trofin #include "llvm/CodeGen/Passes.h" 3068ac7b17SMircea Trofin #include "llvm/CodeGen/RegisterClassInfo.h" 3168ac7b17SMircea Trofin #include "llvm/CodeGen/VirtRegMap.h" 3268ac7b17SMircea Trofin #include "llvm/InitializePasses.h" 3368ac7b17SMircea Trofin #include "llvm/Pass.h" 3468ac7b17SMircea Trofin #include "llvm/PassRegistry.h" 3568ac7b17SMircea Trofin #include "llvm/Support/CommandLine.h" 3668ac7b17SMircea Trofin #include "llvm/Support/ErrorHandling.h" 3768ac7b17SMircea Trofin 38e67430ccSMircea Trofin #include <array> 3968ac7b17SMircea Trofin #include <memory> 4068ac7b17SMircea Trofin 4168ac7b17SMircea Trofin using namespace llvm; 4268ac7b17SMircea Trofin 4368ac7b17SMircea Trofin #define DEBUG_TYPE "ml-regalloc" 44b1af01feSMircea Trofin 45e67430ccSMircea Trofin // Generated header in release (AOT) mode 46b1af01feSMircea Trofin #if defined(LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL) 47e67430ccSMircea Trofin #include "RegallocEvictModel.h" 485a50ab4dSMircea Trofin using CompiledModelType = RegallocEvictModel; 495a50ab4dSMircea Trofin #else 505a50ab4dSMircea Trofin using CompiledModelType = NoopSavedModelImpl; 51e67430ccSMircea Trofin #endif 52e67430ccSMircea Trofin 53e67430ccSMircea Trofin // Options that only make sense in development mode 54e67430ccSMircea Trofin #ifdef LLVM_HAVE_TF_API 55*f658ca1aSMircea Trofin #include "RegAllocScore.h" 56*f658ca1aSMircea Trofin #include "llvm/Analysis/Utils/TFUtils.h" 57*f658ca1aSMircea Trofin 58e67430ccSMircea Trofin static cl::opt<std::string> TrainingLog( 59e67430ccSMircea Trofin "regalloc-training-log", cl::Hidden, 60e67430ccSMircea Trofin cl::desc("Training log for the register allocator eviction model")); 61e67430ccSMircea Trofin 62e67430ccSMircea Trofin static cl::opt<std::string> ModelUnderTraining( 63e67430ccSMircea Trofin "regalloc-model", cl::Hidden, 64e67430ccSMircea Trofin cl::desc("The model being trained for register allocation eviction")); 65e67430ccSMircea Trofin 66e67430ccSMircea Trofin #endif // #ifdef LLVM_HAVE_TF_API 67e67430ccSMircea Trofin 68660ff655SMircea Trofin extern cl::opt<unsigned> EvictInterferenceCutoff; 69660ff655SMircea Trofin 70e67430ccSMircea Trofin /// The score injection pass. 71e67430ccSMircea Trofin /// This pass calculates the score for a function and inserts it in the log, but 72e67430ccSMircea Trofin /// this happens only in development mode. It's a no-op otherwise. 73e67430ccSMircea Trofin namespace llvm { 74e67430ccSMircea Trofin class RegAllocScoring : public MachineFunctionPass { 75e67430ccSMircea Trofin public: 76e67430ccSMircea Trofin static char ID; 77e67430ccSMircea Trofin 78e67430ccSMircea Trofin RegAllocScoring() : MachineFunctionPass(ID) { 79e67430ccSMircea Trofin initializeRegAllocScoringPass(*PassRegistry::getPassRegistry()); 80e67430ccSMircea Trofin } 81e67430ccSMircea Trofin 82e67430ccSMircea Trofin ~RegAllocScoring() override = default; 83e67430ccSMircea Trofin 84e67430ccSMircea Trofin StringRef getPassName() const override { 85e67430ccSMircea Trofin return "Register Allocation Pass Scoring"; 86e67430ccSMircea Trofin } 87e67430ccSMircea Trofin 88e67430ccSMircea Trofin /// RegAllocReward analysis usage. 89e67430ccSMircea Trofin void getAnalysisUsage(AnalysisUsage &AU) const override { 90e67430ccSMircea Trofin AU.setPreservesAll(); 91e67430ccSMircea Trofin AU.addRequired<RegAllocEvictionAdvisorAnalysis>(); 92e67430ccSMircea Trofin AU.addRequired<MachineBlockFrequencyInfo>(); 93e67430ccSMircea Trofin AU.addRequired<AAResultsWrapperPass>(); 94e67430ccSMircea Trofin MachineFunctionPass::getAnalysisUsage(AU); 95e67430ccSMircea Trofin } 96e67430ccSMircea Trofin 97e67430ccSMircea Trofin /// Performs this pass 98e67430ccSMircea Trofin bool runOnMachineFunction(MachineFunction &) override; 99e67430ccSMircea Trofin }; 100e67430ccSMircea Trofin 101e67430ccSMircea Trofin char RegAllocScoring::ID = 0; 102073e0968SMircea Trofin FunctionPass *createRegAllocScoringPass() { return new RegAllocScoring(); } 103073e0968SMircea Trofin 104073e0968SMircea Trofin } // namespace llvm 105e67430ccSMircea Trofin 106e67430ccSMircea Trofin INITIALIZE_PASS(RegAllocScoring, "regallocscoringpass", 107e67430ccSMircea Trofin "Register Allocation Scoring Pass", false, false) 108e67430ccSMircea Trofin 109e67430ccSMircea Trofin // =================================== 110e67430ccSMircea Trofin // Common ML Advisor declarations 111e67430ccSMircea Trofin // =================================== 11268ac7b17SMircea Trofin namespace { 11368ac7b17SMircea Trofin // This is the maximum number of interfererring ranges. That's the number of 11468ac7b17SMircea Trofin // distinct AllocationOrder values, which comes from MCRegisterClass::RegsSize. 11568ac7b17SMircea Trofin // For X86, that's 32. 11668ac7b17SMircea Trofin // TODO: find a way to get this, statically, in a programmatic way. 11768ac7b17SMircea Trofin static const int64_t MaxInterferences = 32; 11868ac7b17SMircea Trofin 11968ac7b17SMircea Trofin // Logically, we can think of the feature set given to the evaluator as a 2D 12068ac7b17SMircea Trofin // matrix. The rows are the features (see next). The columns correspond to the 12168ac7b17SMircea Trofin // interferences. We treat the candidate virt reg as an 'interference', too, as 12268ac7b17SMircea Trofin // its feature set is the same as that of the interferring ranges. So we'll have 12368ac7b17SMircea Trofin // MaxInterferences + 1 columns and by convention, we will use the last column 12468ac7b17SMircea Trofin // for the virt reg seeking allocation. 12568ac7b17SMircea Trofin static const int64_t CandidateVirtRegPos = MaxInterferences; 12668ac7b17SMircea Trofin static const int64_t NumberOfInterferences = CandidateVirtRegPos + 1; 12768ac7b17SMircea Trofin 12868ac7b17SMircea Trofin // Most features are as described above, so we'll reuse this vector in defining 12968ac7b17SMircea Trofin // them. 13068ac7b17SMircea Trofin static const std::vector<int64_t> PerLiveRangeShape{1, NumberOfInterferences}; 13168ac7b17SMircea Trofin 13268ac7b17SMircea Trofin // -------------- 13368ac7b17SMircea Trofin // Features table 13468ac7b17SMircea Trofin // -------------- 13568ac7b17SMircea Trofin // For each interfering live range (incl. the candidate) we collect a number of 13668ac7b17SMircea Trofin // features. However, because the features are of different types (and because 13768ac7b17SMircea Trofin // of ML best practices), we organize the tensors per feature, not per 13868ac7b17SMircea Trofin // candidate. Each such tensor has a scalar value corresponding to the 13968ac7b17SMircea Trofin // interferring live range at that position, in the order in AllocationOrder. 14068ac7b17SMircea Trofin // The last position corresponds to the virt reg seeking allocation. 14168ac7b17SMircea Trofin // Exception to all that is the progression feature, which is just a scalar (see 14268ac7b17SMircea Trofin // its documentation for details). 14368ac7b17SMircea Trofin // Note on naming: the "_by_max" are normalized using the largest value of that 14468ac7b17SMircea Trofin // tensor, as observed in the current decision making stage (i.e. for the 14568ac7b17SMircea Trofin // current call to the advisor's tryFindEvictionCandidate) 14668ac7b17SMircea Trofin // 14768ac7b17SMircea Trofin // The feature list format: type, name, shape, documentation. 14868ac7b17SMircea Trofin // Note: we can really just use int64 and float, hence the modeling of some 14968ac7b17SMircea Trofin // bools as int64 values. 15068ac7b17SMircea Trofin #define RA_EVICT_FEATURES_LIST(M) \ 15168ac7b17SMircea Trofin M(int64_t, mask, PerLiveRangeShape, \ 15268ac7b17SMircea Trofin "boolean values, 0 for unavailable candidates (i.e. if a position is 0, " \ 15368ac7b17SMircea Trofin "it " \ 15468ac7b17SMircea Trofin "can't be evicted)") \ 15568ac7b17SMircea Trofin M(int64_t, is_free, PerLiveRangeShape, \ 15668ac7b17SMircea Trofin "boolean values, 1 if this phys reg is actually free (no interferences)") \ 15768ac7b17SMircea Trofin M(float, nr_urgent, PerLiveRangeShape, \ 15868ac7b17SMircea Trofin "number of 'urgent' intervals, normalized. Urgent are those that are OK " \ 15968ac7b17SMircea Trofin "to break cascades") \ 16068ac7b17SMircea Trofin M(float, nr_broken_hints, PerLiveRangeShape, \ 16168ac7b17SMircea Trofin "if this position were evicted, how many broken hints would there be") \ 16268ac7b17SMircea Trofin M(int64_t, is_hint, PerLiveRangeShape, \ 16368ac7b17SMircea Trofin "is this a preferred phys reg for the candidate") \ 16468ac7b17SMircea Trofin M(int64_t, is_local, PerLiveRangeShape, \ 16568ac7b17SMircea Trofin "is this live range local to a basic block") \ 16668ac7b17SMircea Trofin M(float, nr_rematerializable, PerLiveRangeShape, \ 16768ac7b17SMircea Trofin "nr rematerializable ranges") \ 16868ac7b17SMircea Trofin M(float, nr_defs_and_uses, PerLiveRangeShape, \ 16968ac7b17SMircea Trofin "bb freq - weighed nr defs and uses") \ 17068ac7b17SMircea Trofin M(float, weighed_reads_by_max, PerLiveRangeShape, \ 17168ac7b17SMircea Trofin "bb freq - weighed nr of reads, normalized") \ 17268ac7b17SMircea Trofin M(float, weighed_writes_by_max, PerLiveRangeShape, \ 17368ac7b17SMircea Trofin "bb feq - weighed nr of writes, normalized") \ 17468ac7b17SMircea Trofin M(float, weighed_read_writes_by_max, PerLiveRangeShape, \ 17568ac7b17SMircea Trofin "bb freq - weighed nr of uses that are both read and writes, normalized") \ 17668ac7b17SMircea Trofin M(float, weighed_indvars_by_max, PerLiveRangeShape, \ 17768ac7b17SMircea Trofin "bb freq - weighed nr of uses that are indvars, normalized") \ 17868ac7b17SMircea Trofin M(float, hint_weights_by_max, PerLiveRangeShape, \ 17968ac7b17SMircea Trofin "bb freq - weighed nr of uses that are hints, normalized") \ 18068ac7b17SMircea Trofin M(float, start_bb_freq_by_max, PerLiveRangeShape, \ 18168ac7b17SMircea Trofin "the freq in the start block, normalized") \ 18268ac7b17SMircea Trofin M(float, end_bb_freq_by_max, PerLiveRangeShape, \ 18368ac7b17SMircea Trofin "freq of end block, normalized") \ 18468ac7b17SMircea Trofin M(float, hottest_bb_freq_by_max, PerLiveRangeShape, \ 18568ac7b17SMircea Trofin "hottest BB freq, normalized") \ 18668ac7b17SMircea Trofin M(float, liverange_size, PerLiveRangeShape, \ 18768ac7b17SMircea Trofin "size (instr index diff) of the LR") \ 18868ac7b17SMircea Trofin M(float, use_def_density, PerLiveRangeShape, \ 18968ac7b17SMircea Trofin "the max weight, as computed by the manual heuristic") \ 19068ac7b17SMircea Trofin M(int64_t, max_stage, PerLiveRangeShape, \ 19168ac7b17SMircea Trofin "largest stage of an interval in this LR") \ 19268ac7b17SMircea Trofin M(int64_t, min_stage, PerLiveRangeShape, \ 19368ac7b17SMircea Trofin "lowest stage of an interval in this LR") \ 19468ac7b17SMircea Trofin M(float, progress, {1}, "ratio of current queue size to initial size") 19568ac7b17SMircea Trofin 19668ac7b17SMircea Trofin // The model learns to pick one of the mask == 1 interferences. This is the name 19768ac7b17SMircea Trofin // of the output tensor. 19868ac7b17SMircea Trofin // The contract with the model is that the output will be guaranteed to be to a 19968ac7b17SMircea Trofin // mask == 1 position. 200b1af01feSMircea Trofin // Using a macro here to avoid 'not used' warnings (and keep cond compilation to 201b1af01feSMircea Trofin // a minimum) 202b1af01feSMircea Trofin #define DecisionName "index_to_evict" 20368ac7b17SMircea Trofin 20468ac7b17SMircea Trofin // Named features index. 20568ac7b17SMircea Trofin enum FeatureIDs { 20668ac7b17SMircea Trofin #define _FEATURE_IDX(_, name, __, ___) name, 20768ac7b17SMircea Trofin RA_EVICT_FEATURES_LIST(_FEATURE_IDX) 20868ac7b17SMircea Trofin #undef _FEATURE_IDX 20968ac7b17SMircea Trofin FeatureCount 21068ac7b17SMircea Trofin }; 21168ac7b17SMircea Trofin 21268ac7b17SMircea Trofin // The ML advisor will typically have a sparse input to the evaluator, because 21368ac7b17SMircea Trofin // various phys regs won't be available. It's easier (maintenance-wise) to 21468ac7b17SMircea Trofin // bulk-reset the state of the evaluator each time we are about to use it again. 21568ac7b17SMircea Trofin template <typename T> size_t getTotalSize(const std::vector<int64_t> &Shape) { 21668ac7b17SMircea Trofin size_t Ret = sizeof(T); 21768ac7b17SMircea Trofin for (const auto V : Shape) 21868ac7b17SMircea Trofin Ret *= V; 21968ac7b17SMircea Trofin return Ret; 22068ac7b17SMircea Trofin } 22168ac7b17SMircea Trofin 22268ac7b17SMircea Trofin void resetInputs(MLModelRunner &Runner) { 22368ac7b17SMircea Trofin #define _RESET(TYPE, NAME, SHAPE, __) \ 22468ac7b17SMircea Trofin std::memset(Runner.getTensorUntyped(FeatureIDs::NAME), 0, \ 22568ac7b17SMircea Trofin getTotalSize<TYPE>(SHAPE)); 22668ac7b17SMircea Trofin RA_EVICT_FEATURES_LIST(_RESET) 22768ac7b17SMircea Trofin #undef _RESET 22868ac7b17SMircea Trofin } 22968ac7b17SMircea Trofin 2309aa2c914SMircea Trofin // Per-live interval components that get aggregated into the feature values that 2319aa2c914SMircea Trofin // will be passed to the evaluator. 2329aa2c914SMircea Trofin struct LIFeatureComponents { 2339aa2c914SMircea Trofin double R = 0; 2349aa2c914SMircea Trofin double W = 0; 2359aa2c914SMircea Trofin double RW = 0; 2369aa2c914SMircea Trofin double IndVarUpdates = 0; 2379aa2c914SMircea Trofin double HintWeights = 0.0; 2389aa2c914SMircea Trofin int64_t NrDefsAndUses = 0; 2399aa2c914SMircea Trofin float HottestBlockFreq = 0.0; 2409aa2c914SMircea Trofin bool IsRemat = false; 2419aa2c914SMircea Trofin }; 2429aa2c914SMircea Trofin 243e67430ccSMircea Trofin using CandidateRegList = 244e67430ccSMircea Trofin std::array<std::pair<MCRegister, bool>, NumberOfInterferences>; 245e67430ccSMircea Trofin using FeaturesListNormalizer = std::array<float, FeatureIDs::FeatureCount>; 246e67430ccSMircea Trofin 247e67430ccSMircea Trofin /// The ML evictor (commonalities between release and development mode) 248e67430ccSMircea Trofin class MLEvictAdvisor : public RegAllocEvictionAdvisor { 249e67430ccSMircea Trofin public: 25079b98f0aSMircea Trofin MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA, 25179b98f0aSMircea Trofin MLModelRunner *Runner, const MachineBlockFrequencyInfo &MBFI, 252e67430ccSMircea Trofin const MachineLoopInfo &Loops); 253e67430ccSMircea Trofin 254e67430ccSMircea Trofin protected: 255e67430ccSMircea Trofin const RegAllocEvictionAdvisor &getDefaultAdvisor() const { 256e67430ccSMircea Trofin return static_cast<const RegAllocEvictionAdvisor &>(DefaultAdvisor); 257e67430ccSMircea Trofin } 258e67430ccSMircea Trofin 259e67430ccSMircea Trofin // The assumption is that if the Runner could not be constructed, we emit-ed 260e67430ccSMircea Trofin // error, and we shouldn't be asking for it here. 261e67430ccSMircea Trofin const MLModelRunner &getRunner() const { return *Runner; } 262e67430ccSMircea Trofin 263e67430ccSMircea Trofin /// This just calls Evaluate on the Runner, but in the development mode case, 264e67430ccSMircea Trofin /// if we're just capturing the log of the default advisor, it needs to call 265e67430ccSMircea Trofin /// the latter instead, so we need to pass all the necessary parameters for 266e67430ccSMircea Trofin /// it. In the development case, it will also log. 267592f52deSMircea Trofin virtual int64_t 268592f52deSMircea Trofin tryFindEvictionCandidatePosition(const LiveInterval &VirtReg, 269592f52deSMircea Trofin const AllocationOrder &Order, 270592f52deSMircea Trofin unsigned OrderLimit, uint8_t CostPerUseLimit, 271592f52deSMircea Trofin const SmallVirtRegSet &FixedRegisters) const; 272e67430ccSMircea Trofin 273e67430ccSMircea Trofin /// Load the features of the given VirtReg (allocated or not) at column Pos, 274e67430ccSMircea Trofin /// but if that can't be evicted, return false instead. 275e67430ccSMircea Trofin bool 276592f52deSMircea Trofin loadInterferenceFeatures(const LiveInterval &VirtReg, MCRegister PhysReg, 277e67430ccSMircea Trofin bool IsHint, const SmallVirtRegSet &FixedRegisters, 278e67430ccSMircea Trofin std::array<float, FeatureIDs::FeatureCount> &Largest, 279e67430ccSMircea Trofin size_t Pos) const; 280e67430ccSMircea Trofin 281e67430ccSMircea Trofin private: 282e67430ccSMircea Trofin static float getInitialQueueSize(const MachineFunction &MF); 283e67430ccSMircea Trofin 284e67430ccSMircea Trofin MCRegister tryFindEvictionCandidate( 285592f52deSMircea Trofin const LiveInterval &VirtReg, const AllocationOrder &Order, 286e67430ccSMircea Trofin uint8_t CostPerUseLimit, 287e67430ccSMircea Trofin const SmallVirtRegSet &FixedRegisters) const override; 288e67430ccSMircea Trofin 289592f52deSMircea Trofin void extractFeatures(const SmallVectorImpl<const LiveInterval *> &Intervals, 290e67430ccSMircea Trofin std::array<float, FeatureIDs::FeatureCount> &Largest, 291e67430ccSMircea Trofin size_t Pos, int64_t IsHint, int64_t LocalIntfsCount, 292e67430ccSMircea Trofin float NrUrgent) const; 293e67430ccSMircea Trofin 294e67430ccSMircea Trofin // Point-in-time: we didn't learn this, so we always delegate to the default. 295e67430ccSMircea Trofin bool canEvictHintInterference( 296592f52deSMircea Trofin const LiveInterval &VirtReg, MCRegister PhysReg, 297e67430ccSMircea Trofin const SmallVirtRegSet &FixedRegisters) const override { 298e67430ccSMircea Trofin return getDefaultAdvisor().canEvictHintInterference(VirtReg, PhysReg, 299e67430ccSMircea Trofin FixedRegisters); 300e67430ccSMircea Trofin } 301e67430ccSMircea Trofin 30291a33ad3SMircea Trofin const LIFeatureComponents & 3039aa2c914SMircea Trofin getLIFeatureComponents(const LiveInterval &LI) const; 3049aa2c914SMircea Trofin 305e67430ccSMircea Trofin // Hold on to a default advisor for: 306e67430ccSMircea Trofin // 1) the implementation of canEvictHintInterference, because we didn't learn 307e67430ccSMircea Trofin // that nuance yet; 308e67430ccSMircea Trofin // 2) for bootstrapping (logging) in the development mode case. 309e67430ccSMircea Trofin const DefaultEvictionAdvisor DefaultAdvisor; 310e67430ccSMircea Trofin MLModelRunner *const Runner; 311e67430ccSMircea Trofin const MachineBlockFrequencyInfo &MBFI; 312e67430ccSMircea Trofin const MachineLoopInfo &Loops; 313e67430ccSMircea Trofin 314e67430ccSMircea Trofin // Indices of those features we don't want to normalize. 315e67430ccSMircea Trofin // This could be static and shared, but its initialization is non-trivial. 316e67430ccSMircea Trofin std::bitset<FeatureIDs::FeatureCount> DoNotNormalize; 317e67430ccSMircea Trofin const float InitialQSize; 31891a33ad3SMircea Trofin 31991a33ad3SMircea Trofin using RegID = unsigned; 32091a33ad3SMircea Trofin mutable DenseMap<RegID, LIFeatureComponents> CachedFeatures; 321e67430ccSMircea Trofin }; 322e67430ccSMircea Trofin 323e67430ccSMircea Trofin // =================================== 324e67430ccSMircea Trofin // Release (AOT) - specifics 325e67430ccSMircea Trofin // =================================== 326e67430ccSMircea Trofin const std::array<std::string, FeatureIDs::FeatureCount> FeatureNames{ 327e67430ccSMircea Trofin #define _GETNAME(_, NAME, __, ___) #NAME, 328e67430ccSMircea Trofin RA_EVICT_FEATURES_LIST(_GETNAME) 329e67430ccSMircea Trofin #undef _GETNAME 330e67430ccSMircea Trofin }; 331e67430ccSMircea Trofin class ReleaseModeEvictionAdvisorAnalysis final 332e67430ccSMircea Trofin : public RegAllocEvictionAdvisorAnalysis { 333e67430ccSMircea Trofin public: 334e67430ccSMircea Trofin ReleaseModeEvictionAdvisorAnalysis() 335e67430ccSMircea Trofin : RegAllocEvictionAdvisorAnalysis(AdvisorMode::Release) {} 336e67430ccSMircea Trofin // support for isa<> and dyn_cast. 337e67430ccSMircea Trofin static bool classof(const RegAllocEvictionAdvisorAnalysis *R) { 338e67430ccSMircea Trofin return R->getAdvisorMode() == AdvisorMode::Release; 339e67430ccSMircea Trofin } 340e67430ccSMircea Trofin 341e67430ccSMircea Trofin private: 342e67430ccSMircea Trofin void getAnalysisUsage(AnalysisUsage &AU) const override { 343e67430ccSMircea Trofin AU.addRequired<MachineBlockFrequencyInfo>(); 344e67430ccSMircea Trofin AU.addRequired<MachineLoopInfo>(); 345e67430ccSMircea Trofin RegAllocEvictionAdvisorAnalysis::getAnalysisUsage(AU); 346e67430ccSMircea Trofin } 347e67430ccSMircea Trofin 348e67430ccSMircea Trofin std::unique_ptr<RegAllocEvictionAdvisor> 34979b98f0aSMircea Trofin getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { 350e67430ccSMircea Trofin if (!Runner) 3515a50ab4dSMircea Trofin Runner = std::make_unique<ReleaseModeModelRunner<CompiledModelType>>( 352e67430ccSMircea Trofin MF.getFunction().getContext(), FeatureNames, DecisionName); 353e67430ccSMircea Trofin return std::make_unique<MLEvictAdvisor>( 354e67430ccSMircea Trofin MF, RA, Runner.get(), getAnalysis<MachineBlockFrequencyInfo>(), 355e67430ccSMircea Trofin getAnalysis<MachineLoopInfo>()); 356e67430ccSMircea Trofin } 3575a50ab4dSMircea Trofin std::unique_ptr<ReleaseModeModelRunner<CompiledModelType>> Runner; 358e67430ccSMircea Trofin }; 359e67430ccSMircea Trofin 360e67430ccSMircea Trofin // =================================== 36168ac7b17SMircea Trofin // Development mode-specifics 362e67430ccSMircea Trofin // =================================== 363e67430ccSMircea Trofin // 364e67430ccSMircea Trofin // Features we log 36568ac7b17SMircea Trofin #ifdef LLVM_HAVE_TF_API 36668ac7b17SMircea Trofin #define _DECL_FEATURES(type, name, shape, _) \ 36768ac7b17SMircea Trofin TensorSpec::createSpec<type>(#name, shape), 36868ac7b17SMircea Trofin 36968ac7b17SMircea Trofin static const std::vector<TensorSpec> InputFeatures{ 370e67430ccSMircea Trofin {RA_EVICT_FEATURES_LIST(_DECL_FEATURES)}, 371e67430ccSMircea Trofin }; 37268ac7b17SMircea Trofin #undef _DECL_FEATURES 37368ac7b17SMircea Trofin static const TensorSpec Output = 37468ac7b17SMircea Trofin TensorSpec::createSpec<int64_t>(DecisionName, {1}); 375b2d2e931SMircea Trofin static const TensorSpec Reward = TensorSpec::createSpec<float>("reward", {1}); 37668ac7b17SMircea Trofin 377e67430ccSMircea Trofin // Features we bind on the model. The tensor names have a prefix, and we also 378e67430ccSMircea Trofin // need to include some tensors that are expected to be present by the training 379e67430ccSMircea Trofin // algo. 380e67430ccSMircea Trofin // TODO: can we just get rid of these? 381e67430ccSMircea Trofin #define _DECL_TRAIN_FEATURES(type, name, shape, _) \ 382e67430ccSMircea Trofin TensorSpec::createSpec<type>(std::string("action_") + #name, shape), 383e67430ccSMircea Trofin 384e67430ccSMircea Trofin static const std::vector<TensorSpec> TrainingInputFeatures{ 385e67430ccSMircea Trofin {RA_EVICT_FEATURES_LIST(_DECL_TRAIN_FEATURES) 386e67430ccSMircea Trofin TensorSpec::createSpec<float>("action_discount", {1}), 387e67430ccSMircea Trofin TensorSpec::createSpec<int32_t>("action_step_type", {1}), 388e67430ccSMircea Trofin TensorSpec::createSpec<float>("action_reward", {1})}}; 389e67430ccSMircea Trofin #undef _DECL_TRAIN_FEATURES 390e67430ccSMircea Trofin 391e67430ccSMircea Trofin class DevelopmentModeEvictAdvisor : public MLEvictAdvisor { 392e67430ccSMircea Trofin public: 39379b98f0aSMircea Trofin DevelopmentModeEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA, 394e67430ccSMircea Trofin MLModelRunner *Runner, 395e67430ccSMircea Trofin const MachineBlockFrequencyInfo &MBFI, 396e67430ccSMircea Trofin const MachineLoopInfo &Loops, Logger *Log) 397e67430ccSMircea Trofin : MLEvictAdvisor(MF, RA, Runner, MBFI, Loops), Log(Log) {} 398e67430ccSMircea Trofin 399e67430ccSMircea Trofin private: 400e67430ccSMircea Trofin int64_t tryFindEvictionCandidatePosition( 401592f52deSMircea Trofin const LiveInterval &VirtReg, const AllocationOrder &Order, 402592f52deSMircea Trofin unsigned OrderLimit, uint8_t CostPerUseLimit, 403e67430ccSMircea Trofin const SmallVirtRegSet &FixedRegisters) const override; 404e67430ccSMircea Trofin 405e67430ccSMircea Trofin Logger *const Log; 406e67430ccSMircea Trofin }; 407e67430ccSMircea Trofin 408e67430ccSMircea Trofin class DevelopmentModeEvictionAdvisorAnalysis final 409e67430ccSMircea Trofin : public RegAllocEvictionAdvisorAnalysis { 410e67430ccSMircea Trofin public: 411e67430ccSMircea Trofin DevelopmentModeEvictionAdvisorAnalysis() 412e67430ccSMircea Trofin : RegAllocEvictionAdvisorAnalysis(AdvisorMode::Development) {} 413e67430ccSMircea Trofin // support for isa<> and dyn_cast. 414e67430ccSMircea Trofin static bool classof(const RegAllocEvictionAdvisorAnalysis *R) { 415e67430ccSMircea Trofin return R->getAdvisorMode() == AdvisorMode::Development; 416e67430ccSMircea Trofin } 417e67430ccSMircea Trofin 418e67430ccSMircea Trofin /// get the logger for the given function, or nullptr if we didn't collect 419e67430ccSMircea Trofin /// one. This is used to inject the score by the RegAllocScoring pass. 420e67430ccSMircea Trofin Logger *getLogger(const MachineFunction &MF) const { 421e67430ccSMircea Trofin auto I = LogMap.find(MF.getName()); 422e67430ccSMircea Trofin if (I == LogMap.end()) 423e67430ccSMircea Trofin return nullptr; 424e67430ccSMircea Trofin return I->second.get(); 425e67430ccSMircea Trofin } 426e67430ccSMircea Trofin 427e67430ccSMircea Trofin private: 428e67430ccSMircea Trofin void getAnalysisUsage(AnalysisUsage &AU) const override { 429e67430ccSMircea Trofin AU.addRequired<MachineBlockFrequencyInfo>(); 430e67430ccSMircea Trofin AU.addRequired<MachineLoopInfo>(); 431e67430ccSMircea Trofin RegAllocEvictionAdvisorAnalysis::getAnalysisUsage(AU); 432e67430ccSMircea Trofin } 433e67430ccSMircea Trofin 434e67430ccSMircea Trofin // Save all the logs (when requested). 435e67430ccSMircea Trofin bool doFinalization(Module &M) override { 436e67430ccSMircea Trofin if (TrainingLog.empty()) 437e67430ccSMircea Trofin return false; 438e67430ccSMircea Trofin std::error_code EC; 439e67430ccSMircea Trofin auto OS = std::make_unique<raw_fd_ostream>(TrainingLog, EC); 440e67430ccSMircea Trofin if (EC) { 441e67430ccSMircea Trofin M.getContext().emitError(EC.message() + ":" + TrainingLog); 442e67430ccSMircea Trofin return false; 443e67430ccSMircea Trofin } 444e67430ccSMircea Trofin Logger::flushLogs(*OS, LogMap); 445e67430ccSMircea Trofin return false; 446e67430ccSMircea Trofin } 447e67430ccSMircea Trofin 448e67430ccSMircea Trofin std::unique_ptr<RegAllocEvictionAdvisor> 44979b98f0aSMircea Trofin getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { 450e67430ccSMircea Trofin LLVMContext &Ctx = MF.getFunction().getContext(); 451e67430ccSMircea Trofin if (ModelUnderTraining.empty() && TrainingLog.empty()) { 452e67430ccSMircea Trofin Ctx.emitError("Regalloc development mode should be requested with at " 453e67430ccSMircea Trofin "least logging enabled and/or a training model"); 454e67430ccSMircea Trofin return nullptr; 455e67430ccSMircea Trofin } 456e67430ccSMircea Trofin if (!Runner) { 457e67430ccSMircea Trofin if (ModelUnderTraining.empty()) 458e67430ccSMircea Trofin Runner = std::make_unique<NoInferenceModelRunner>(Ctx, InputFeatures); 459e67430ccSMircea Trofin else 460e67430ccSMircea Trofin Runner = ModelUnderTrainingRunner::createAndEnsureValid( 461e67430ccSMircea Trofin Ctx, ModelUnderTraining, DecisionName, TrainingInputFeatures); 462e67430ccSMircea Trofin if (!Runner) { 463e67430ccSMircea Trofin Ctx.emitError("Regalloc: could not set up the model runner"); 464e67430ccSMircea Trofin return nullptr; 465e67430ccSMircea Trofin } 466e67430ccSMircea Trofin } 467e67430ccSMircea Trofin 468e67430ccSMircea Trofin Logger *Log = nullptr; 469e67430ccSMircea Trofin if (!TrainingLog.empty()) { 470e67430ccSMircea Trofin std::vector<LoggedFeatureSpec> LFS; 471e67430ccSMircea Trofin for (const auto &FS : InputFeatures) 472e67430ccSMircea Trofin LFS.push_back({FS, None}); 473e67430ccSMircea Trofin if (auto *MUTR = dyn_cast<ModelUnderTrainingRunner>(Runner.get())) 474e67430ccSMircea Trofin if (MUTR->outputLoggedFeatureSpecs().size() > 1) 475e67430ccSMircea Trofin append_range(LFS, drop_begin(MUTR->outputLoggedFeatureSpecs())); 476e67430ccSMircea Trofin // We always log the output; in particular, if we're not evaluating, we 477e67430ccSMircea Trofin // don't have an output spec json file. That's why we handle the 478e67430ccSMircea Trofin // 'normal' output separately. 479e67430ccSMircea Trofin LFS.push_back({Output, None}); 480e67430ccSMircea Trofin auto I = LogMap.insert(std::make_pair( 481e67430ccSMircea Trofin MF.getFunction().getName(), 482e67430ccSMircea Trofin std::make_unique<Logger>(LFS, Reward, /*IncludeReward*/ true))); 483e67430ccSMircea Trofin assert(I.second); 484e67430ccSMircea Trofin Log = I.first->second.get(); 485e67430ccSMircea Trofin } 486e67430ccSMircea Trofin return std::make_unique<DevelopmentModeEvictAdvisor>( 487e67430ccSMircea Trofin MF, RA, Runner.get(), getAnalysis<MachineBlockFrequencyInfo>(), 488e67430ccSMircea Trofin getAnalysis<MachineLoopInfo>(), Log); 489e67430ccSMircea Trofin } 490e67430ccSMircea Trofin 491e67430ccSMircea Trofin std::unique_ptr<MLModelRunner> Runner; 492e67430ccSMircea Trofin StringMap<std::unique_ptr<Logger>> LogMap; 493e67430ccSMircea Trofin }; 49468ac7b17SMircea Trofin #endif //#ifdef LLVM_HAVE_TF_API 49568ac7b17SMircea Trofin } // namespace 496e67430ccSMircea Trofin 497e67430ccSMircea Trofin float MLEvictAdvisor::getInitialQueueSize(const MachineFunction &MF) { 498e67430ccSMircea Trofin auto &MRI = MF.getRegInfo(); 499e67430ccSMircea Trofin float Ret = 0.0; 500e67430ccSMircea Trofin for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { 501e67430ccSMircea Trofin Register Reg = Register::index2VirtReg(I); 502e67430ccSMircea Trofin if (MRI.reg_nodbg_empty(Reg)) 503e67430ccSMircea Trofin continue; 504e67430ccSMircea Trofin ++Ret; 505e67430ccSMircea Trofin } 506e67430ccSMircea Trofin return Ret; 507e67430ccSMircea Trofin } 508e67430ccSMircea Trofin 50979b98f0aSMircea Trofin MLEvictAdvisor::MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA, 510e67430ccSMircea Trofin MLModelRunner *Runner, 511e67430ccSMircea Trofin const MachineBlockFrequencyInfo &MBFI, 512e67430ccSMircea Trofin const MachineLoopInfo &Loops) 513e67430ccSMircea Trofin : RegAllocEvictionAdvisor(MF, RA), DefaultAdvisor(MF, RA), 514e67430ccSMircea Trofin Runner(std::move(Runner)), MBFI(MBFI), Loops(Loops), 515e67430ccSMircea Trofin InitialQSize(MLEvictAdvisor::getInitialQueueSize(MF)) { 516e67430ccSMircea Trofin assert(this->Runner); 517e67430ccSMircea Trofin DoNotNormalize.set(FeatureIDs::mask); 518e67430ccSMircea Trofin DoNotNormalize.set(FeatureIDs::is_free); 519e67430ccSMircea Trofin DoNotNormalize.set(FeatureIDs::is_hint); 520e67430ccSMircea Trofin DoNotNormalize.set(FeatureIDs::is_local); 521e67430ccSMircea Trofin DoNotNormalize.set(FeatureIDs::min_stage); 522e67430ccSMircea Trofin DoNotNormalize.set(FeatureIDs::max_stage); 523e67430ccSMircea Trofin DoNotNormalize.set(FeatureIDs::progress); 524e67430ccSMircea Trofin } 525e67430ccSMircea Trofin 526e67430ccSMircea Trofin int64_t MLEvictAdvisor::tryFindEvictionCandidatePosition( 527592f52deSMircea Trofin const LiveInterval &, const AllocationOrder &, unsigned, uint8_t, 528e67430ccSMircea Trofin const SmallVirtRegSet &) const { 529e67430ccSMircea Trofin int64_t Ret = Runner->evaluate<int64_t>(); 530e67430ccSMircea Trofin assert(Ret >= 0); 531e67430ccSMircea Trofin assert(Ret <= CandidateVirtRegPos); 532e67430ccSMircea Trofin return Ret; 533e67430ccSMircea Trofin } 534e67430ccSMircea Trofin 535e67430ccSMircea Trofin bool MLEvictAdvisor::loadInterferenceFeatures( 536592f52deSMircea Trofin const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, 537e67430ccSMircea Trofin const SmallVirtRegSet &FixedRegisters, FeaturesListNormalizer &Largest, 538e67430ccSMircea Trofin size_t Pos) const { 539e67430ccSMircea Trofin // It is only possible to evict virtual register interference. 540e67430ccSMircea Trofin if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) { 541e67430ccSMircea Trofin // leave unavailable 542e67430ccSMircea Trofin return false; 543e67430ccSMircea Trofin } 544e67430ccSMircea Trofin 545e67430ccSMircea Trofin const bool IsLocal = LIS->intervalIsInOneMBB(VirtReg); 546e67430ccSMircea Trofin int64_t LocalIntfs = 0; 547e67430ccSMircea Trofin float NrUrgent = 0.0f; 548e67430ccSMircea Trofin 549e67430ccSMircea Trofin // The cascade tracking is the same as in the default advisor 550e67430ccSMircea Trofin unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); 551e67430ccSMircea Trofin 552592f52deSMircea Trofin SmallVector<const LiveInterval *, MaxInterferences> InterferingIntervals; 553e67430ccSMircea Trofin for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 554e67430ccSMircea Trofin LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); 555e67430ccSMircea Trofin // Different from the default heuristic, we don't make any assumptions about 556e67430ccSMircea Trofin // what having more than 10 results in the query may mean. 557ed2deab5SMircea Trofin const auto &IFIntervals = Q.interferingVRegs(EvictInterferenceCutoff); 558e67430ccSMircea Trofin if (IFIntervals.empty() && InterferingIntervals.empty()) 559e67430ccSMircea Trofin continue; 560ed2deab5SMircea Trofin if (IFIntervals.size() >= EvictInterferenceCutoff) 561ed2deab5SMircea Trofin return false; 562e67430ccSMircea Trofin InterferingIntervals.append(IFIntervals.begin(), IFIntervals.end()); 563592f52deSMircea Trofin for (const LiveInterval *Intf : reverse(IFIntervals)) { 564e67430ccSMircea Trofin assert(Register::isVirtualRegister(Intf->reg()) && 565e67430ccSMircea Trofin "Only expecting virtual register interference from query"); 566e67430ccSMircea Trofin // This is the same set of legality checks as in the default case: don't 567e67430ccSMircea Trofin // try to evict fixed regs or 'done' ones. Also don't break cascades, 568e67430ccSMircea Trofin // except in the urgent case, with the same nuances used in the default 569e67430ccSMircea Trofin // heuristic. 570e67430ccSMircea Trofin // We could try sharing this between the advisors, but it may end up 571e67430ccSMircea Trofin // more complex than it is right now. 572e67430ccSMircea Trofin if (FixedRegisters.count(Intf->reg())) 573e67430ccSMircea Trofin return false; 574e67430ccSMircea Trofin if (RA.getExtraInfo().getStage(*Intf) == RS_Done) 575e67430ccSMircea Trofin return false; 576e67430ccSMircea Trofin bool Urgent = 577e67430ccSMircea Trofin !VirtReg.isSpillable() && 578e67430ccSMircea Trofin (Intf->isSpillable() || 579e67430ccSMircea Trofin RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < 580e67430ccSMircea Trofin RegClassInfo.getNumAllocatableRegs( 581e67430ccSMircea Trofin MRI->getRegClass(Intf->reg()))); 582e67430ccSMircea Trofin // Only evict older cascades or live ranges without a cascade. 583e67430ccSMircea Trofin unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg()); 584e67430ccSMircea Trofin if (Cascade <= IntfCascade) { 585e67430ccSMircea Trofin if (!Urgent) 586e67430ccSMircea Trofin return false; 587e67430ccSMircea Trofin ++NrUrgent; 588e67430ccSMircea Trofin } 589e67430ccSMircea Trofin 590e67430ccSMircea Trofin LocalIntfs += (IsLocal && LIS->intervalIsInOneMBB(*Intf) && 591e67430ccSMircea Trofin (!EnableLocalReassign || !canReassign(*Intf, PhysReg))); 592e67430ccSMircea Trofin } 593e67430ccSMircea Trofin } 594e67430ccSMircea Trofin // OK, so if we made it this far, this LR is an eviction candidate, load its 595e67430ccSMircea Trofin // features. 596e67430ccSMircea Trofin extractFeatures(InterferingIntervals, Largest, Pos, IsHint, LocalIntfs, 597e67430ccSMircea Trofin NrUrgent); 598e67430ccSMircea Trofin return true; 599e67430ccSMircea Trofin } 600e67430ccSMircea Trofin 601e67430ccSMircea Trofin MCRegister MLEvictAdvisor::tryFindEvictionCandidate( 602592f52deSMircea Trofin const LiveInterval &VirtReg, const AllocationOrder &Order, 603e67430ccSMircea Trofin uint8_t CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) const { 604e67430ccSMircea Trofin auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); 605e67430ccSMircea Trofin if (!MaybeOrderLimit) 606e67430ccSMircea Trofin return MCRegister::NoRegister; 607e67430ccSMircea Trofin unsigned OrderLimit = *MaybeOrderLimit; 608e67430ccSMircea Trofin 609e67430ccSMircea Trofin // The heuristic sets initial costs such as, if CostPerUseLimit is 610e67430ccSMircea Trofin // max<uint8_t>, then any of the costs of the legally-evictable intervals 611e67430ccSMircea Trofin // would be lower. When that happens, one of those will be selected. 612e67430ccSMircea Trofin // Therefore, we allow the candidate be selected, unless the candidate is 613e67430ccSMircea Trofin // unspillable, in which case it would be incorrect to not find a register for 614e67430ccSMircea Trofin // it. 615e67430ccSMircea Trofin const bool MustFindEviction = 616e67430ccSMircea Trofin (!VirtReg.isSpillable() && CostPerUseLimit == static_cast<uint8_t>(~0u)); 617e67430ccSMircea Trofin // Number of available candidates - if 0, no need to continue. 618e67430ccSMircea Trofin size_t Available = 0; 619e67430ccSMircea Trofin // Make sure we don't have leftover partial state from an attempt where we had 620e67430ccSMircea Trofin // no available candidates and bailed out early. 621e67430ccSMircea Trofin resetInputs(*Runner); 622e67430ccSMircea Trofin 623e67430ccSMircea Trofin // Track the index->register mapping because AllocationOrder doesn't do that 624e67430ccSMircea Trofin // and we'd have to scan it. 625e67430ccSMircea Trofin // Also track their mask, to write asserts/debug. 626e67430ccSMircea Trofin CandidateRegList Regs; 627e67430ccSMircea Trofin Regs.fill({0, false}); 628e67430ccSMircea Trofin 629e67430ccSMircea Trofin // Track the largest value of features seen during this eviction session. We 630e67430ccSMircea Trofin // only normalize (some of) the float features, but it's just simpler to 631e67430ccSMircea Trofin // dimension 'Largest' to all the features, especially since we have the 632e67430ccSMircea Trofin // 'DoNotNormalize' list. 633e67430ccSMircea Trofin FeaturesListNormalizer Largest; 634e67430ccSMircea Trofin Largest.fill(0.0); 635e67430ccSMircea Trofin 636e67430ccSMircea Trofin // Same overal idea as in the default eviction policy - we visit the values of 637e67430ccSMircea Trofin // AllocationOrder one at a time. If it's not legally available, we mask off 638e67430ccSMircea Trofin // the corresponding feature column (==do nothing because we already reset all 639e67430ccSMircea Trofin // the features to 0) 640e67430ccSMircea Trofin // Use Pos to capture the column we load features at - in AllocationOrder 641e67430ccSMircea Trofin // order. 642e67430ccSMircea Trofin size_t Pos = 0; 643e67430ccSMircea Trofin for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; 644e67430ccSMircea Trofin ++I, ++Pos) { 645e67430ccSMircea Trofin MCRegister PhysReg = *I; 646a8a7bf92SMircea Trofin assert(!Regs[Pos].second); 647e67430ccSMircea Trofin assert(PhysReg); 648e67430ccSMircea Trofin if (!canAllocatePhysReg(CostPerUseLimit, PhysReg)) { 649e67430ccSMircea Trofin continue; 650e67430ccSMircea Trofin } 651e67430ccSMircea Trofin if (loadInterferenceFeatures(VirtReg, PhysReg, I.isHint(), FixedRegisters, 652e67430ccSMircea Trofin Largest, Pos)) { 653e67430ccSMircea Trofin ++Available; 654a8a7bf92SMircea Trofin Regs[Pos] = std::make_pair(PhysReg, true); 655e67430ccSMircea Trofin } 656e67430ccSMircea Trofin } 657e67430ccSMircea Trofin if (Available == 0) { 658e67430ccSMircea Trofin // Nothing to decide, nothing to learn. 659e67430ccSMircea Trofin assert(!MustFindEviction); 660e67430ccSMircea Trofin return MCRegister::NoRegister; 661e67430ccSMircea Trofin } 662a8a7bf92SMircea Trofin const size_t ValidPosLimit = Pos; 663e67430ccSMircea Trofin // If we must find eviction, the candidate should be masked out of the 664e67430ccSMircea Trofin // decision making process. 665e67430ccSMircea Trofin Regs[CandidateVirtRegPos].second = !MustFindEviction; 666e67430ccSMircea Trofin if (!MustFindEviction) 667592f52deSMircea Trofin extractFeatures(SmallVector<const LiveInterval *, 1>(1, &VirtReg), Largest, 668e67430ccSMircea Trofin CandidateVirtRegPos, /*IsHint*/ 0, /*LocalIntfsCount*/ 0, 669e67430ccSMircea Trofin /*NrUrgent*/ 0.0); 670e67430ccSMircea Trofin assert(InitialQSize > 0.0 && "We couldn't have gotten here if we had " 671e67430ccSMircea Trofin "nothing to allocate initially."); 672e67430ccSMircea Trofin // Normalize the features. 673e67430ccSMircea Trofin for (auto &V : Largest) 674e67430ccSMircea Trofin V = V ? V : 1.0; 675e67430ccSMircea Trofin for (size_t FeatureIndex = 0; FeatureIndex < FeatureIDs::FeatureCount; 676e67430ccSMircea Trofin ++FeatureIndex) { 677e67430ccSMircea Trofin if (DoNotNormalize.test(FeatureIndex)) 678e67430ccSMircea Trofin continue; 679e67430ccSMircea Trofin for (size_t Pos = 0; Pos < NumberOfInterferences; ++Pos) { 680e67430ccSMircea Trofin Runner->getTensor<float>(FeatureIndex)[Pos] /= Largest[FeatureIndex]; 681e67430ccSMircea Trofin } 682e67430ccSMircea Trofin } 683e67430ccSMircea Trofin *Runner->getTensor<float>(FeatureIDs::progress) = 684e67430ccSMircea Trofin static_cast<float>(RA.getQueueSize()) / InitialQSize; 685e67430ccSMircea Trofin 686e67430ccSMircea Trofin // Get a decision. 687e67430ccSMircea Trofin size_t CandidatePos = tryFindEvictionCandidatePosition( 688e67430ccSMircea Trofin VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); 689e67430ccSMircea Trofin // The contract with the ML side is that CandidatePos is mask == 1 (i.e. 690e67430ccSMircea Trofin // Regs[CandidatePos].second) 691e67430ccSMircea Trofin assert(Regs[CandidatePos].second); 692e67430ccSMircea Trofin if (CandidatePos == CandidateVirtRegPos) { 693e67430ccSMircea Trofin assert(!MustFindEviction); 694e67430ccSMircea Trofin return MCRegister::NoRegister; 695e67430ccSMircea Trofin } 696a8a7bf92SMircea Trofin assert(CandidatePos < ValidPosLimit); 6970e691aedSFangrui Song (void)ValidPosLimit; 698e67430ccSMircea Trofin return Regs[CandidatePos].first; 699e67430ccSMircea Trofin } 700e67430ccSMircea Trofin 70191a33ad3SMircea Trofin const LIFeatureComponents & 7029aa2c914SMircea Trofin MLEvictAdvisor::getLIFeatureComponents(const LiveInterval &LI) const { 70391a33ad3SMircea Trofin RegID ID = LI.reg().id(); 70491a33ad3SMircea Trofin LIFeatureComponents Empty; 70591a33ad3SMircea Trofin auto I = CachedFeatures.insert(std::make_pair(ID, Empty)); 70691a33ad3SMircea Trofin LIFeatureComponents &Ret = I.first->getSecond(); 70791a33ad3SMircea Trofin if (!I.second) 70891a33ad3SMircea Trofin return Ret; 70991a33ad3SMircea Trofin 7109aa2c914SMircea Trofin SmallPtrSet<MachineInstr *, 8> Visited; 7119aa2c914SMircea Trofin const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 7129aa2c914SMircea Trofin 7139aa2c914SMircea Trofin for (MachineRegisterInfo::reg_instr_nodbg_iterator 7149aa2c914SMircea Trofin I = MRI->reg_instr_nodbg_begin(LI.reg()), 7159aa2c914SMircea Trofin E = MRI->reg_instr_nodbg_end(); 7169aa2c914SMircea Trofin I != E;) { 7179aa2c914SMircea Trofin MachineInstr *MI = &*(I++); 7189aa2c914SMircea Trofin 7199aa2c914SMircea Trofin ++Ret.NrDefsAndUses; 7209aa2c914SMircea Trofin if (!Visited.insert(MI).second) 7219aa2c914SMircea Trofin continue; 7229aa2c914SMircea Trofin 7239aa2c914SMircea Trofin if (MI->isIdentityCopy() || MI->isImplicitDef()) 7249aa2c914SMircea Trofin continue; 7259aa2c914SMircea Trofin 7269aa2c914SMircea Trofin bool Reads, Writes; 7279aa2c914SMircea Trofin std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); 7289aa2c914SMircea Trofin 7299aa2c914SMircea Trofin float Freq = MBFI.getBlockFreqRelativeToEntryBlock(MI->getParent()); 7309aa2c914SMircea Trofin Ret.HottestBlockFreq = std::max(Freq, Ret.HottestBlockFreq); 7319aa2c914SMircea Trofin 7329aa2c914SMircea Trofin Ret.R += (Reads && !Writes) * Freq; 7339aa2c914SMircea Trofin Ret.W += (!Reads && Writes) * Freq; 7349aa2c914SMircea Trofin Ret.RW += (Reads && Writes) * Freq; 7359aa2c914SMircea Trofin 7369aa2c914SMircea Trofin auto *MBB = MI->getParent(); 7379aa2c914SMircea Trofin auto *Loop = Loops.getLoopFor(MBB); 7389aa2c914SMircea Trofin bool IsExiting = Loop ? Loop->isLoopExiting(MBB) : false; 7399aa2c914SMircea Trofin 7409aa2c914SMircea Trofin if (Writes && IsExiting && LIS->isLiveOutOfMBB(LI, MBB)) 7419aa2c914SMircea Trofin Ret.IndVarUpdates += Freq; 7429aa2c914SMircea Trofin 7439aa2c914SMircea Trofin if (MI->isCopy() && VirtRegAuxInfo::copyHint(MI, LI.reg(), TRI, *MRI)) 7449aa2c914SMircea Trofin Ret.HintWeights += Freq; 7459aa2c914SMircea Trofin } 7469aa2c914SMircea Trofin Ret.IsRemat = VirtRegAuxInfo::isRematerializable( 7479aa2c914SMircea Trofin LI, *LIS, *VRM, *MF.getSubtarget().getInstrInfo()); 7489aa2c914SMircea Trofin return Ret; 7499aa2c914SMircea Trofin } 7509aa2c914SMircea Trofin 751e67430ccSMircea Trofin // Overall, this currently mimics what we do for weight calculation, but instead 752e67430ccSMircea Trofin // of accummulating the various features, we keep them separate. 753e67430ccSMircea Trofin void MLEvictAdvisor::extractFeatures( 754592f52deSMircea Trofin const SmallVectorImpl<const LiveInterval *> &Intervals, 755e67430ccSMircea Trofin std::array<float, FeatureIDs::FeatureCount> &Largest, size_t Pos, 756e67430ccSMircea Trofin int64_t IsHint, int64_t LocalIntfsCount, float NrUrgent) const { 757e67430ccSMircea Trofin int64_t NrDefsAndUses = 0; 758e67430ccSMircea Trofin int64_t NrBrokenHints = 0; 7599aa2c914SMircea Trofin double R = 0.0; 7609aa2c914SMircea Trofin double W = 0.0; 7619aa2c914SMircea Trofin double RW = 0.0; 7629aa2c914SMircea Trofin double IndVarUpdates = 0.0; 7639aa2c914SMircea Trofin double HintWeights = 0.0; 764e67430ccSMircea Trofin float StartBBFreq = 0.0; 765e67430ccSMircea Trofin float EndBBFreq = 0.0; 766e67430ccSMircea Trofin float HottestBlockFreq = 0.0; 767e67430ccSMircea Trofin int32_t NrRematerializable = 0; 768e67430ccSMircea Trofin float TotalWeight = 0.0; 769e67430ccSMircea Trofin 770e67430ccSMircea Trofin SlotIndex EndSI = LIS->getSlotIndexes()->getZeroIndex(); 771e67430ccSMircea Trofin SlotIndex StartSI = LIS->getSlotIndexes()->getLastIndex(); 772e67430ccSMircea Trofin int64_t MaxStage = 0; 773e67430ccSMircea Trofin int64_t MinStage = 774e67430ccSMircea Trofin Intervals.empty() ? 0 : std::numeric_limits<int64_t>::max(); 775e67430ccSMircea Trofin 776e67430ccSMircea Trofin for (const auto *L : Intervals) { 777e67430ccSMircea Trofin const LiveInterval &LI = *L; 778e67430ccSMircea Trofin MaxStage = std::max<int64_t>( 779e67430ccSMircea Trofin MaxStage, static_cast<int64_t>(RA.getExtraInfo().getStage(LI))); 780e67430ccSMircea Trofin MinStage = std::min<int64_t>( 781e67430ccSMircea Trofin MinStage, static_cast<int64_t>(RA.getExtraInfo().getStage(LI))); 782e67430ccSMircea Trofin 783e67430ccSMircea Trofin TotalWeight = std::max(TotalWeight, LI.weight()); 784e67430ccSMircea Trofin 785e67430ccSMircea Trofin if (LI.beginIndex() < StartSI) 786e67430ccSMircea Trofin StartSI = LI.beginIndex(); 787e67430ccSMircea Trofin 788e67430ccSMircea Trofin if (LI.endIndex() > EndSI) 789e67430ccSMircea Trofin EndSI = LI.endIndex(); 79091a33ad3SMircea Trofin const LIFeatureComponents &LIFC = getLIFeatureComponents(LI); 791a3f14918SMircea Trofin NrBrokenHints += VRM->hasPreferredPhys(LI.reg()); 792e67430ccSMircea Trofin 7939aa2c914SMircea Trofin NrDefsAndUses += LIFC.NrDefsAndUses; 7949aa2c914SMircea Trofin HottestBlockFreq = std::max(HottestBlockFreq, LIFC.HottestBlockFreq); 7959aa2c914SMircea Trofin R += LIFC.R; 7969aa2c914SMircea Trofin W += LIFC.W; 7979aa2c914SMircea Trofin RW += LIFC.RW; 798e67430ccSMircea Trofin 7999aa2c914SMircea Trofin IndVarUpdates += LIFC.IndVarUpdates; 800e67430ccSMircea Trofin 8019aa2c914SMircea Trofin HintWeights += LIFC.HintWeights; 8029aa2c914SMircea Trofin NrRematerializable += LIFC.IsRemat; 803e67430ccSMircea Trofin } 804e67430ccSMircea Trofin size_t Size = 0; 805e67430ccSMircea Trofin if (!Intervals.empty()) { 806e67430ccSMircea Trofin StartBBFreq = 807e67430ccSMircea Trofin MBFI.getBlockFreqRelativeToEntryBlock(LIS->getMBBFromIndex(StartSI)); 808e67430ccSMircea Trofin if (EndSI >= LIS->getSlotIndexes()->getLastIndex()) 809e67430ccSMircea Trofin EndSI = LIS->getSlotIndexes()->getLastIndex().getPrevIndex(); 810e67430ccSMircea Trofin EndBBFreq = 811e67430ccSMircea Trofin MBFI.getBlockFreqRelativeToEntryBlock(LIS->getMBBFromIndex(EndSI)); 812e67430ccSMircea Trofin Size = StartSI.distance(EndSI); 813e67430ccSMircea Trofin } 814e67430ccSMircea Trofin // Set the features at the column 'Pos'. 815e67430ccSMircea Trofin #define SET(ID, TYPE, VAL) \ 816e67430ccSMircea Trofin do { \ 817e67430ccSMircea Trofin Runner->getTensor<TYPE>(FeatureIDs::ID)[Pos] = static_cast<TYPE>(VAL); \ 818e67430ccSMircea Trofin if (!DoNotNormalize.test(FeatureIDs::ID)) \ 819e67430ccSMircea Trofin Largest[FeatureIDs::ID] = \ 820e67430ccSMircea Trofin std::max(Largest[FeatureIDs::ID], static_cast<float>(VAL)); \ 821e67430ccSMircea Trofin } while (false) 822e67430ccSMircea Trofin SET(mask, int64_t, 1); 823e67430ccSMircea Trofin SET(is_free, int64_t, Intervals.empty()); 824e67430ccSMircea Trofin SET(nr_urgent, float, NrUrgent); 825e67430ccSMircea Trofin SET(nr_broken_hints, float, NrBrokenHints); 826e67430ccSMircea Trofin SET(is_hint, int64_t, IsHint); 827e67430ccSMircea Trofin SET(is_local, int64_t, LocalIntfsCount); 828e67430ccSMircea Trofin SET(nr_rematerializable, float, NrRematerializable); 829e67430ccSMircea Trofin SET(nr_defs_and_uses, float, NrDefsAndUses); 830e67430ccSMircea Trofin SET(weighed_reads_by_max, float, R); 831e67430ccSMircea Trofin SET(weighed_writes_by_max, float, W); 832e67430ccSMircea Trofin SET(weighed_read_writes_by_max, float, RW); 833e67430ccSMircea Trofin SET(weighed_indvars_by_max, float, IndVarUpdates); 834e67430ccSMircea Trofin SET(hint_weights_by_max, float, HintWeights); 835e67430ccSMircea Trofin SET(start_bb_freq_by_max, float, StartBBFreq); 836e67430ccSMircea Trofin SET(end_bb_freq_by_max, float, EndBBFreq); 837e67430ccSMircea Trofin SET(hottest_bb_freq_by_max, float, HottestBlockFreq); 838e67430ccSMircea Trofin SET(liverange_size, float, Size); 839e67430ccSMircea Trofin SET(use_def_density, float, TotalWeight); 840e67430ccSMircea Trofin SET(max_stage, int64_t, MaxStage); 841e67430ccSMircea Trofin SET(min_stage, int64_t, MinStage); 842e67430ccSMircea Trofin #undef SET 843e67430ccSMircea Trofin } 844e67430ccSMircea Trofin 845e67430ccSMircea Trofin // Development mode-specific implementations 846e67430ccSMircea Trofin #ifdef LLVM_HAVE_TF_API 847e67430ccSMircea Trofin RegAllocEvictionAdvisorAnalysis *llvm::createDevelopmentModeAdvisor() { 848e67430ccSMircea Trofin return new DevelopmentModeEvictionAdvisorAnalysis(); 849e67430ccSMircea Trofin } 850e67430ccSMircea Trofin 851e67430ccSMircea Trofin int64_t DevelopmentModeEvictAdvisor::tryFindEvictionCandidatePosition( 852592f52deSMircea Trofin const LiveInterval &VirtReg, const AllocationOrder &Order, 853592f52deSMircea Trofin unsigned OrderLimit, uint8_t CostPerUseLimit, 854592f52deSMircea Trofin const SmallVirtRegSet &FixedRegisters) const { 855e67430ccSMircea Trofin int64_t Ret = 0; 856e67430ccSMircea Trofin if (isa<ModelUnderTrainingRunner>(getRunner())) { 857e67430ccSMircea Trofin Ret = MLEvictAdvisor::tryFindEvictionCandidatePosition( 858e67430ccSMircea Trofin VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); 859e67430ccSMircea Trofin } else { 860e67430ccSMircea Trofin MCRegister PhysReg = getDefaultAdvisor().tryFindEvictionCandidate( 861e67430ccSMircea Trofin VirtReg, Order, CostPerUseLimit, FixedRegisters); 862e67430ccSMircea Trofin // Find the index of the selected PhysReg. We need it for logging, otherwise 863e67430ccSMircea Trofin // this is wasted cycles (but so would starting development mode without a 864e67430ccSMircea Trofin // model nor logging) 865e67430ccSMircea Trofin if (!PhysReg) 866e67430ccSMircea Trofin Ret = CandidateVirtRegPos; 867e67430ccSMircea Trofin else 868e67430ccSMircea Trofin for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); 869e67430ccSMircea Trofin I != E; ++I, ++Ret) 870e67430ccSMircea Trofin if (*I == PhysReg) 871e67430ccSMircea Trofin break; 872e67430ccSMircea Trofin } 873e67430ccSMircea Trofin if (TrainingLog.empty()) 874e67430ccSMircea Trofin return Ret; 875e67430ccSMircea Trofin size_t CurrentFeature = 0; 876e67430ccSMircea Trofin for (; CurrentFeature < FeatureIDs::FeatureCount; ++CurrentFeature) { 877e67430ccSMircea Trofin Log->logSpecifiedTensorValue( 878e67430ccSMircea Trofin CurrentFeature, reinterpret_cast<const char *>( 879e67430ccSMircea Trofin getRunner().getTensorUntyped(CurrentFeature))); 880e67430ccSMircea Trofin } 881e67430ccSMircea Trofin if (auto *MUTR = dyn_cast<ModelUnderTrainingRunner>(&getRunner())) 882e67430ccSMircea Trofin for (size_t I = 1; I < MUTR->outputLoggedFeatureSpecs().size(); 883e67430ccSMircea Trofin ++I, ++CurrentFeature) 884e67430ccSMircea Trofin Log->logSpecifiedTensorValue( 885e67430ccSMircea Trofin CurrentFeature, 886e67430ccSMircea Trofin reinterpret_cast<const char *>( 887e67430ccSMircea Trofin MUTR->lastEvaluationResult()->getUntypedTensorValue(I))); 888e67430ccSMircea Trofin // The output is right after the features and the extra outputs 889e67430ccSMircea Trofin Log->logInt64Value(CurrentFeature, &Ret); 890e67430ccSMircea Trofin return Ret; 891e67430ccSMircea Trofin } 892e67430ccSMircea Trofin 893e67430ccSMircea Trofin bool RegAllocScoring::runOnMachineFunction(MachineFunction &MF) { 894e67430ccSMircea Trofin if (auto *DevModeAnalysis = dyn_cast<DevelopmentModeEvictionAdvisorAnalysis>( 895e67430ccSMircea Trofin &getAnalysis<RegAllocEvictionAdvisorAnalysis>())) 896e67430ccSMircea Trofin if (auto *Log = DevModeAnalysis->getLogger(MF)) 897e67430ccSMircea Trofin Log->logFloatFinalReward(static_cast<float>( 898e67430ccSMircea Trofin calculateRegAllocScore( 899e67430ccSMircea Trofin MF, getAnalysis<MachineBlockFrequencyInfo>(), 900e67430ccSMircea Trofin getAnalysis<AAResultsWrapperPass>().getAAResults()) 901e67430ccSMircea Trofin .getScore())); 902e67430ccSMircea Trofin 903e67430ccSMircea Trofin return false; 904e67430ccSMircea Trofin } 905e67430ccSMircea Trofin #endif // #ifdef LLVM_HAVE_TF_API 906e67430ccSMircea Trofin 907e67430ccSMircea Trofin RegAllocEvictionAdvisorAnalysis *llvm::createReleaseModeAdvisor() { 908e67430ccSMircea Trofin return new ReleaseModeEvictionAdvisorAnalysis(); 909e67430ccSMircea Trofin } 910e67430ccSMircea Trofin 911e67430ccSMircea Trofin // In all cases except development mode, we don't need scoring. 912e67430ccSMircea Trofin #if !defined(LLVM_HAVE_TF_API) 913e67430ccSMircea Trofin bool RegAllocScoring::runOnMachineFunction(MachineFunction &) { return false; } 914e67430ccSMircea Trofin #endif 915