1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements some simple delegations needed for call lowering.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/Analysis.h"
15 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
16 #include "llvm/CodeGen/GlobalISel/Utils.h"
17 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetLowering.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/IR/Instructions.h"
23 #include "llvm/IR/LLVMContext.h"
24 #include "llvm/IR/Module.h"
25 #include "llvm/Target/TargetMachine.h"
26 
27 #define DEBUG_TYPE "call-lowering"
28 
29 using namespace llvm;
30 
31 void CallLowering::anchor() {}
32 
33 /// Helper function which updates \p Flags when \p AttrFn returns true.
34 static void
35 addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags,
36                     const std::function<bool(Attribute::AttrKind)> &AttrFn) {
37   if (AttrFn(Attribute::SExt))
38     Flags.setSExt();
39   if (AttrFn(Attribute::ZExt))
40     Flags.setZExt();
41   if (AttrFn(Attribute::InReg))
42     Flags.setInReg();
43   if (AttrFn(Attribute::StructRet))
44     Flags.setSRet();
45   if (AttrFn(Attribute::Nest))
46     Flags.setNest();
47   if (AttrFn(Attribute::ByVal))
48     Flags.setByVal();
49   if (AttrFn(Attribute::Preallocated))
50     Flags.setPreallocated();
51   if (AttrFn(Attribute::InAlloca))
52     Flags.setInAlloca();
53   if (AttrFn(Attribute::Returned))
54     Flags.setReturned();
55   if (AttrFn(Attribute::SwiftSelf))
56     Flags.setSwiftSelf();
57   if (AttrFn(Attribute::SwiftError))
58     Flags.setSwiftError();
59 }
60 
61 ISD::ArgFlagsTy CallLowering::getAttributesForArgIdx(const CallBase &Call,
62                                                      unsigned ArgIdx) const {
63   ISD::ArgFlagsTy Flags;
64   addFlagsUsingAttrFn(Flags, [&Call, &ArgIdx](Attribute::AttrKind Attr) {
65     return Call.paramHasAttr(ArgIdx, Attr);
66   });
67   return Flags;
68 }
69 
70 void CallLowering::addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags,
71                                              const AttributeList &Attrs,
72                                              unsigned OpIdx) const {
73   addFlagsUsingAttrFn(Flags, [&Attrs, &OpIdx](Attribute::AttrKind Attr) {
74     return Attrs.hasAttribute(OpIdx, Attr);
75   });
76 }
77 
78 bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
79                              ArrayRef<Register> ResRegs,
80                              ArrayRef<ArrayRef<Register>> ArgRegs,
81                              Register SwiftErrorVReg,
82                              std::function<unsigned()> GetCalleeReg) const {
83   CallLoweringInfo Info;
84   const DataLayout &DL = MIRBuilder.getDataLayout();
85   MachineFunction &MF = MIRBuilder.getMF();
86   bool CanBeTailCalled = CB.isTailCall() &&
87                          isInTailCallPosition(CB, MF.getTarget()) &&
88                          (MF.getFunction()
89                               .getFnAttribute("disable-tail-calls")
90                               .getValueAsString() != "true");
91 
92   // First step is to marshall all the function's parameters into the correct
93   // physregs and memory locations. Gather the sequence of argument types that
94   // we'll pass to the assigner function.
95   unsigned i = 0;
96   unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
97   for (auto &Arg : CB.args()) {
98     ArgInfo OrigArg{ArgRegs[i], Arg->getType(), getAttributesForArgIdx(CB, i),
99                     i < NumFixedArgs};
100     setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB);
101 
102     // If we have an explicit sret argument that is an Instruction, (i.e., it
103     // might point to function-local memory), we can't meaningfully tail-call.
104     if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg))
105       CanBeTailCalled = false;
106 
107     Info.OrigArgs.push_back(OrigArg);
108     ++i;
109   }
110 
111   // Try looking through a bitcast from one function type to another.
112   // Commonly happens with calls to objc_msgSend().
113   const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
114   if (const Function *F = dyn_cast<Function>(CalleeV))
115     Info.Callee = MachineOperand::CreateGA(F, 0);
116   else
117     Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
118 
119   Info.OrigRet = ArgInfo{ResRegs, CB.getType(), ISD::ArgFlagsTy{}};
120   if (!Info.OrigRet.Ty->isVoidTy())
121     setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CB);
122 
123   Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
124   Info.CallConv = CB.getCallingConv();
125   Info.SwiftErrorVReg = SwiftErrorVReg;
126   Info.IsMustTailCall = CB.isMustTailCall();
127   Info.IsTailCall = CanBeTailCalled;
128   Info.IsVarArg = CB.getFunctionType()->isVarArg();
129   return lowerCall(MIRBuilder, Info);
130 }
131 
132 template <typename FuncInfoTy>
133 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
134                                const DataLayout &DL,
135                                const FuncInfoTy &FuncInfo) const {
136   auto &Flags = Arg.Flags[0];
137   const AttributeList &Attrs = FuncInfo.getAttributes();
138   addArgFlagsFromAttributes(Flags, Attrs, OpIdx);
139 
140   if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) {
141     Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType();
142 
143     auto Ty = Attrs.getAttribute(OpIdx, Attribute::ByVal).getValueAsType();
144     Flags.setByValSize(DL.getTypeAllocSize(Ty ? Ty : ElementTy));
145 
146     // For ByVal, alignment should be passed from FE.  BE will guess if
147     // this info is not there but there are cases it cannot get right.
148     Align FrameAlign;
149     if (auto ParamAlign = FuncInfo.getParamAlign(OpIdx - 2))
150       FrameAlign = *ParamAlign;
151     else
152       FrameAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL));
153     Flags.setByValAlign(FrameAlign);
154   }
155   Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
156 }
157 
158 template void
159 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
160                                     const DataLayout &DL,
161                                     const Function &FuncInfo) const;
162 
163 template void
164 CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
165                                     const DataLayout &DL,
166                                     const CallBase &FuncInfo) const;
167 
168 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
169                                 MachineIRBuilder &MIRBuilder) const {
170   assert(SrcRegs.size() > 1 && "Nothing to pack");
171 
172   const DataLayout &DL = MIRBuilder.getMF().getDataLayout();
173   MachineRegisterInfo *MRI = MIRBuilder.getMRI();
174 
175   LLT PackedLLT = getLLTForType(*PackedTy, DL);
176 
177   SmallVector<LLT, 8> LLTs;
178   SmallVector<uint64_t, 8> Offsets;
179   computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
180   assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch");
181 
182   Register Dst = MRI->createGenericVirtualRegister(PackedLLT);
183   MIRBuilder.buildUndef(Dst);
184   for (unsigned i = 0; i < SrcRegs.size(); ++i) {
185     Register NewDst = MRI->createGenericVirtualRegister(PackedLLT);
186     MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]);
187     Dst = NewDst;
188   }
189 
190   return Dst;
191 }
192 
193 void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
194                               Type *PackedTy,
195                               MachineIRBuilder &MIRBuilder) const {
196   assert(DstRegs.size() > 1 && "Nothing to unpack");
197 
198   const DataLayout &DL = MIRBuilder.getDataLayout();
199 
200   SmallVector<LLT, 8> LLTs;
201   SmallVector<uint64_t, 8> Offsets;
202   computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
203   assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");
204 
205   for (unsigned i = 0; i < DstRegs.size(); ++i)
206     MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]);
207 }
208 
209 bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
210                                      SmallVectorImpl<ArgInfo> &Args,
211                                      ValueHandler &Handler) const {
212   MachineFunction &MF = MIRBuilder.getMF();
213   const Function &F = MF.getFunction();
214   SmallVector<CCValAssign, 16> ArgLocs;
215   CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
216   return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler);
217 }
218 
219 bool CallLowering::handleAssignments(CCState &CCInfo,
220                                      SmallVectorImpl<CCValAssign> &ArgLocs,
221                                      MachineIRBuilder &MIRBuilder,
222                                      SmallVectorImpl<ArgInfo> &Args,
223                                      ValueHandler &Handler) const {
224   MachineFunction &MF = MIRBuilder.getMF();
225   const Function &F = MF.getFunction();
226   const DataLayout &DL = F.getParent()->getDataLayout();
227 
228   unsigned NumArgs = Args.size();
229   for (unsigned i = 0; i != NumArgs; ++i) {
230     EVT CurVT = EVT::getEVT(Args[i].Ty);
231     if (CurVT.isSimple() &&
232         !Handler.assignArg(i, CurVT.getSimpleVT(), CurVT.getSimpleVT(),
233                            CCValAssign::Full, Args[i], Args[i].Flags[0],
234                            CCInfo))
235       continue;
236 
237     MVT NewVT = TLI->getRegisterTypeForCallingConv(
238         F.getContext(), F.getCallingConv(), EVT(CurVT));
239 
240     // If we need to split the type over multiple regs, check it's a scenario
241     // we currently support.
242     unsigned NumParts = TLI->getNumRegistersForCallingConv(
243         F.getContext(), F.getCallingConv(), CurVT);
244 
245     if (NumParts == 1) {
246       // Try to use the register type if we couldn't assign the VT.
247       if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],
248                             Args[i].Flags[0], CCInfo))
249         return false;
250       continue;
251     }
252 
253     assert(NumParts > 1);
254     // For now only handle exact splits.
255     if (NewVT.getSizeInBits() * NumParts != CurVT.getSizeInBits())
256       return false;
257 
258     // For incoming arguments (physregs to vregs), we could have values in
259     // physregs (or memlocs) which we want to extract and copy to vregs.
260     // During this, we might have to deal with the LLT being split across
261     // multiple regs, so we have to record this information for later.
262     //
263     // If we have outgoing args, then we have the opposite case. We have a
264     // vreg with an LLT which we want to assign to a physical location, and
265     // we might have to record that the value has to be split later.
266     if (Handler.isIncomingArgumentHandler()) {
267       // We're handling an incoming arg which is split over multiple regs.
268       // E.g. passing an s128 on AArch64.
269       ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
270       Args[i].OrigRegs.push_back(Args[i].Regs[0]);
271       Args[i].Regs.clear();
272       Args[i].Flags.clear();
273       LLT NewLLT = getLLTForMVT(NewVT);
274       // For each split register, create and assign a vreg that will store
275       // the incoming component of the larger value. These will later be
276       // merged to form the final vreg.
277       for (unsigned Part = 0; Part < NumParts; ++Part) {
278         Register Reg =
279             MIRBuilder.getMRI()->createGenericVirtualRegister(NewLLT);
280         ISD::ArgFlagsTy Flags = OrigFlags;
281         if (Part == 0) {
282           Flags.setSplit();
283         } else {
284           Flags.setOrigAlign(Align(1));
285           if (Part == NumParts - 1)
286             Flags.setSplitEnd();
287         }
288         Args[i].Regs.push_back(Reg);
289         Args[i].Flags.push_back(Flags);
290         if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],
291                               Args[i].Flags[Part], CCInfo)) {
292           // Still couldn't assign this smaller part type for some reason.
293           return false;
294         }
295       }
296     } else {
297       // This type is passed via multiple registers in the calling convention.
298       // We need to extract the individual parts.
299       Register LargeReg = Args[i].Regs[0];
300       LLT SmallTy = LLT::scalar(NewVT.getSizeInBits());
301       auto Unmerge = MIRBuilder.buildUnmerge(SmallTy, LargeReg);
302       assert(Unmerge->getNumOperands() == NumParts + 1);
303       ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
304       // We're going to replace the regs and flags with the split ones.
305       Args[i].Regs.clear();
306       Args[i].Flags.clear();
307       for (unsigned PartIdx = 0; PartIdx < NumParts; ++PartIdx) {
308         ISD::ArgFlagsTy Flags = OrigFlags;
309         if (PartIdx == 0) {
310           Flags.setSplit();
311         } else {
312           Flags.setOrigAlign(Align(1));
313           if (PartIdx == NumParts - 1)
314             Flags.setSplitEnd();
315         }
316         Args[i].Regs.push_back(Unmerge.getReg(PartIdx));
317         Args[i].Flags.push_back(Flags);
318         if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full,
319                               Args[i], Args[i].Flags[PartIdx], CCInfo))
320           return false;
321       }
322     }
323   }
324 
325   for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {
326     assert(j < ArgLocs.size() && "Skipped too many arg locs");
327 
328     CCValAssign &VA = ArgLocs[j];
329     assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
330 
331     if (VA.needsCustom()) {
332       unsigned NumArgRegs =
333           Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));
334       if (!NumArgRegs)
335         return false;
336       j += NumArgRegs;
337       continue;
338     }
339 
340     // FIXME: Pack registers if we have more than one.
341     Register ArgReg = Args[i].Regs[0];
342 
343     EVT OrigVT = EVT::getEVT(Args[i].Ty);
344     EVT VAVT = VA.getValVT();
345     const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
346 
347     // Expected to be multiple regs for a single incoming arg.
348     // There should be Regs.size() ArgLocs per argument.
349     unsigned NumArgRegs = Args[i].Regs.size();
350 
351     assert((j + (NumArgRegs - 1)) < ArgLocs.size() &&
352            "Too many regs for number of args");
353     for (unsigned Part = 0; Part < NumArgRegs; ++Part) {
354       // There should be Regs.size() ArgLocs per argument.
355       VA = ArgLocs[j + Part];
356       if (VA.isMemLoc()) {
357         // Don't currently support loading/storing a type that needs to be split
358         // to the stack. Should be easy, just not implemented yet.
359         if (NumArgRegs > 1) {
360           LLVM_DEBUG(
361             dbgs()
362             << "Load/store a split arg to/from the stack not implemented yet\n");
363           return false;
364         }
365 
366         // FIXME: Use correct address space for pointer size
367         EVT LocVT = VA.getValVT();
368         unsigned MemSize = LocVT == MVT::iPTR ? DL.getPointerSize()
369                                               : LocVT.getStoreSize();
370         unsigned Offset = VA.getLocMemOffset();
371         MachinePointerInfo MPO;
372         Register StackAddr = Handler.getStackAddress(MemSize, Offset, MPO);
373         Handler.assignValueToAddress(Args[i], StackAddr,
374                                      MemSize, MPO, VA);
375         continue;
376       }
377 
378       assert(VA.isRegLoc() && "custom loc should have been handled already");
379 
380       // GlobalISel does not currently work for scalable vectors.
381       if (OrigVT.getFixedSizeInBits() >= VAVT.getFixedSizeInBits() ||
382           !Handler.isIncomingArgumentHandler()) {
383         // This is an argument that might have been split. There should be
384         // Regs.size() ArgLocs per argument.
385 
386         // Insert the argument copies. If VAVT < OrigVT, we'll insert the merge
387         // to the original register after handling all of the parts.
388         Handler.assignValueToReg(Args[i].Regs[Part], VA.getLocReg(), VA);
389         continue;
390       }
391 
392       // This ArgLoc covers multiple pieces, so we need to split it.
393       const LLT VATy(VAVT.getSimpleVT());
394       Register NewReg =
395         MIRBuilder.getMRI()->createGenericVirtualRegister(VATy);
396       Handler.assignValueToReg(NewReg, VA.getLocReg(), VA);
397       // If it's a vector type, we either need to truncate the elements
398       // or do an unmerge to get the lower block of elements.
399       if (VATy.isVector() &&
400           VATy.getNumElements() > OrigVT.getVectorNumElements()) {
401         // Just handle the case where the VA type is 2 * original type.
402         if (VATy.getNumElements() != OrigVT.getVectorNumElements() * 2) {
403           LLVM_DEBUG(dbgs()
404                      << "Incoming promoted vector arg has too many elts");
405           return false;
406         }
407         auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg});
408         MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0));
409       } else {
410         MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0);
411       }
412     }
413 
414     // Now that all pieces have been handled, re-pack any arguments into any
415     // wider, original registers.
416     if (Handler.isIncomingArgumentHandler()) {
417       if (VAVT.getFixedSizeInBits() < OrigVT.getFixedSizeInBits()) {
418         assert(NumArgRegs >= 2);
419 
420         // Merge the split registers into the expected larger result vreg
421         // of the original call.
422         MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs);
423       }
424     }
425 
426     j += NumArgRegs - 1;
427   }
428 
429   return true;
430 }
431 
432 bool CallLowering::analyzeArgInfo(CCState &CCState,
433                                   SmallVectorImpl<ArgInfo> &Args,
434                                   CCAssignFn &AssignFnFixed,
435                                   CCAssignFn &AssignFnVarArg) const {
436   for (unsigned i = 0, e = Args.size(); i < e; ++i) {
437     MVT VT = MVT::getVT(Args[i].Ty);
438     CCAssignFn &Fn = Args[i].IsFixed ? AssignFnFixed : AssignFnVarArg;
439     if (Fn(i, VT, VT, CCValAssign::Full, Args[i].Flags[0], CCState)) {
440       // Bail out on anything we can't handle.
441       LLVM_DEBUG(dbgs() << "Cannot analyze " << EVT(VT).getEVTString()
442                         << " (arg number = " << i << "\n");
443       return false;
444     }
445   }
446   return true;
447 }
448 
449 bool CallLowering::resultsCompatible(CallLoweringInfo &Info,
450                                      MachineFunction &MF,
451                                      SmallVectorImpl<ArgInfo> &InArgs,
452                                      CCAssignFn &CalleeAssignFnFixed,
453                                      CCAssignFn &CalleeAssignFnVarArg,
454                                      CCAssignFn &CallerAssignFnFixed,
455                                      CCAssignFn &CallerAssignFnVarArg) const {
456   const Function &F = MF.getFunction();
457   CallingConv::ID CalleeCC = Info.CallConv;
458   CallingConv::ID CallerCC = F.getCallingConv();
459 
460   if (CallerCC == CalleeCC)
461     return true;
462 
463   SmallVector<CCValAssign, 16> ArgLocs1;
464   CCState CCInfo1(CalleeCC, false, MF, ArgLocs1, F.getContext());
465   if (!analyzeArgInfo(CCInfo1, InArgs, CalleeAssignFnFixed,
466                       CalleeAssignFnVarArg))
467     return false;
468 
469   SmallVector<CCValAssign, 16> ArgLocs2;
470   CCState CCInfo2(CallerCC, false, MF, ArgLocs2, F.getContext());
471   if (!analyzeArgInfo(CCInfo2, InArgs, CallerAssignFnFixed,
472                       CalleeAssignFnVarArg))
473     return false;
474 
475   // We need the argument locations to match up exactly. If there's more in
476   // one than the other, then we are done.
477   if (ArgLocs1.size() != ArgLocs2.size())
478     return false;
479 
480   // Make sure that each location is passed in exactly the same way.
481   for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) {
482     const CCValAssign &Loc1 = ArgLocs1[i];
483     const CCValAssign &Loc2 = ArgLocs2[i];
484 
485     // We need both of them to be the same. So if one is a register and one
486     // isn't, we're done.
487     if (Loc1.isRegLoc() != Loc2.isRegLoc())
488       return false;
489 
490     if (Loc1.isRegLoc()) {
491       // If they don't have the same register location, we're done.
492       if (Loc1.getLocReg() != Loc2.getLocReg())
493         return false;
494 
495       // They matched, so we can move to the next ArgLoc.
496       continue;
497     }
498 
499     // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match.
500     if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
501       return false;
502   }
503 
504   return true;
505 }
506 
507 Register CallLowering::ValueHandler::extendRegister(Register ValReg,
508                                                     CCValAssign &VA,
509                                                     unsigned MaxSizeBits) {
510   LLT LocTy{VA.getLocVT()};
511   LLT ValTy = MRI.getType(ValReg);
512   if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
513     return ValReg;
514 
515   if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
516     if (MaxSizeBits <= ValTy.getSizeInBits())
517       return ValReg;
518     LocTy = LLT::scalar(MaxSizeBits);
519   }
520 
521   switch (VA.getLocInfo()) {
522   default: break;
523   case CCValAssign::Full:
524   case CCValAssign::BCvt:
525     // FIXME: bitconverting between vector types may or may not be a
526     // nop in big-endian situations.
527     return ValReg;
528   case CCValAssign::AExt: {
529     auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
530     return MIB.getReg(0);
531   }
532   case CCValAssign::SExt: {
533     Register NewReg = MRI.createGenericVirtualRegister(LocTy);
534     MIRBuilder.buildSExt(NewReg, ValReg);
535     return NewReg;
536   }
537   case CCValAssign::ZExt: {
538     Register NewReg = MRI.createGenericVirtualRegister(LocTy);
539     MIRBuilder.buildZExt(NewReg, ValReg);
540     return NewReg;
541   }
542   }
543   llvm_unreachable("unable to extend register");
544 }
545 
546 void CallLowering::ValueHandler::anchor() {}
547