1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from gdbclientutils import * 6 7 8class TestGDBServerTargetXML(GDBRemoteTestBase): 9 @skipIfXmlSupportMissing 10 @skipIfRemote 11 @skipIfLLVMTargetMissing("X86") 12 def test_x86_64_regs(self): 13 """Test grabbing various x86_64 registers from gdbserver.""" 14 reg_data = [ 15 "0102030405060708", # rcx 16 "1112131415161718", # rdx 17 "2122232425262728", # rsi 18 "3132333435363738", # rdi 19 "4142434445464748", # rbp 20 "5152535455565758", # rsp 21 "6162636465666768", # r8 22 "7172737475767778", # r9 23 "8182838485868788", # rip 24 "91929394", # eflags 25 "0102030405060708090a", # st0 26 "1112131415161718191a", # st1 27 ] + 6 * [ 28 "2122232425262728292a" # st2..st7 29 ] + [ 30 "8182838485868788898a8b8c8d8e8f90", # xmm0 31 "9192939495969798999a9b9c9d9e9fa0", # xmm1 32 ] + 14 * [ 33 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0", # xmm2..xmm15 34 ] + [ 35 "00000000", # mxcsr 36 ] + [ 37 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0", # ymm0h 38 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0", # ymm1h 39 ] + 14 * [ 40 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0", # ymm2h..ymm15h 41 ] 42 43 class MyResponder(MockGDBServerResponder): 44 def qXferRead(self, obj, annex, offset, length): 45 if annex == "target.xml": 46 return """<?xml version="1.0"?> 47 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 48 <target> 49 <architecture>i386:x86-64</architecture> 50 <osabi>GNU/Linux</osabi> 51 <feature name="org.gnu.gdb.i386.core"> 52 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 53 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 54 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 55 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 56 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 57 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 58 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 59 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 60 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 61 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 62 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 63 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 64 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 65 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 66 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 67 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 68 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 69 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 70 </feature> 71 <feature name="org.gnu.gdb.i386.sse"> 72 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 73 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 74 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 75 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 76 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 77 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 78 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 79 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 80 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 81 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 82 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 83 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 84 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 85 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 86 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 87 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 88 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 89 </feature> 90 <feature name="org.gnu.gdb.i386.avx"> 91 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 92 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 93 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 94 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 95 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 96 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 97 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 98 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 99 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 100 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 101 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 102 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 103 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 104 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 105 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 106 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 107 </feature> 108 </target>""", False 109 else: 110 return None, False 111 112 def readRegister(self, regnum): 113 return "" 114 115 def readRegisters(self): 116 return "".join(reg_data) 117 118 def writeRegisters(self, reg_hex): 119 return "OK" 120 121 def haltReason(self): 122 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 123 124 self.server.responder = MyResponder() 125 126 target = self.createTarget("basic_eh_frame.yaml") 127 process = self.connect(target) 128 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 129 [lldb.eStateStopped]) 130 131 # test generic aliases 132 self.match("register read arg4", 133 ["rcx = 0x0807060504030201"]) 134 self.match("register read arg3", 135 ["rdx = 0x1817161514131211"]) 136 self.match("register read arg2", 137 ["rsi = 0x2827262524232221"]) 138 self.match("register read arg1", 139 ["rdi = 0x3837363534333231"]) 140 self.match("register read fp", 141 ["rbp = 0x4847464544434241"]) 142 self.match("register read sp", 143 ["rsp = 0x5857565554535251"]) 144 self.match("register read arg5", 145 ["r8 = 0x6867666564636261"]) 146 self.match("register read arg6", 147 ["r9 = 0x7877767574737271"]) 148 self.match("register read pc", 149 ["rip = 0x8887868584838281"]) 150 self.match("register read flags", 151 ["eflags = 0x94939291"]) 152 153 # both stX and xmmX should be displayed as vectors 154 self.match("register read st0", 155 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 156 self.match("register read st1", 157 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 158 self.match("register read xmm0", 159 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 160 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 161 self.match("register read xmm1", 162 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 163 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 164 165 # test pseudo-registers 166 self.filecheck("register read --all", 167 os.path.join(os.path.dirname(__file__), 168 "amd64-partial-regs.FileCheck")) 169 170 # test writing into pseudo-registers 171 self.runCmd("register write ecx 0xfffefdfc") 172 reg_data[0] = "fcfdfeff05060708" 173 self.assertPacketLogContains(["G" + "".join(reg_data)]) 174 self.match("register read rcx", 175 ["rcx = 0x08070605fffefdfc"]) 176 177 self.runCmd("register write cx 0xfbfa") 178 reg_data[0] = "fafbfeff05060708" 179 self.assertPacketLogContains(["G" + "".join(reg_data)]) 180 self.match("register read ecx", 181 ["ecx = 0xfffefbfa"]) 182 self.match("register read rcx", 183 ["rcx = 0x08070605fffefbfa"]) 184 185 self.runCmd("register write ch 0xf9") 186 reg_data[0] = "faf9feff05060708" 187 self.assertPacketLogContains(["G" + "".join(reg_data)]) 188 self.match("register read cx", 189 ["cx = 0xf9fa"]) 190 self.match("register read ecx", 191 ["ecx = 0xfffef9fa"]) 192 self.match("register read rcx", 193 ["rcx = 0x08070605fffef9fa"]) 194 195 self.runCmd("register write cl 0xf8") 196 reg_data[0] = "f8f9feff05060708" 197 self.assertPacketLogContains(["G" + "".join(reg_data)]) 198 self.match("register read cx", 199 ["cx = 0xf9f8"]) 200 self.match("register read ecx", 201 ["ecx = 0xfffef9f8"]) 202 self.match("register read rcx", 203 ["rcx = 0x08070605fffef9f8"]) 204 205 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 206 reg_data[10] = "f8f9fafbfcfdfeff090a" 207 self.assertPacketLogContains(["G" + "".join(reg_data)]) 208 self.match("register read st0", 209 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 210 211 @skipIfXmlSupportMissing 212 @skipIfRemote 213 @skipIfLLVMTargetMissing("X86") 214 def test_i386_regs(self): 215 """Test grabbing various i386 registers from gdbserver.""" 216 reg_data = [ 217 "01020304", # eax 218 "11121314", # ecx 219 "21222324", # edx 220 "31323334", # ebx 221 "41424344", # esp 222 "51525354", # ebp 223 "61626364", # esi 224 "71727374", # edi 225 "81828384", # eip 226 "91929394", # eflags 227 "0102030405060708090a", # st0 228 "1112131415161718191a", # st1 229 ] + 6 * [ 230 "2122232425262728292a" # st2..st7 231 ] + [ 232 "8182838485868788898a8b8c8d8e8f90", # xmm0 233 "9192939495969798999a9b9c9d9e9fa0", # xmm1 234 ] + 6 * [ 235 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0", # xmm2..xmm7 236 ] + [ 237 "00000000", # mxcsr 238 ] + [ 239 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0", # ymm0h 240 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0", # ymm1h 241 ] + 6 * [ 242 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0", # ymm2h..ymm7h 243 ] 244 245 class MyResponder(MockGDBServerResponder): 246 def qXferRead(self, obj, annex, offset, length): 247 if annex == "target.xml": 248 return """<?xml version="1.0"?> 249 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 250 <target> 251 <architecture>i386</architecture> 252 <osabi>GNU/Linux</osabi> 253 <feature name="org.gnu.gdb.i386.core"> 254 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 255 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 256 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 257 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 258 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 259 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 260 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 261 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 262 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 263 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 264 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 265 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 266 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 267 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 268 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 269 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 270 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 271 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 272 </feature> 273 <feature name="org.gnu.gdb.i386.sse"> 274 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 275 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 276 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 277 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 278 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 279 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 280 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 281 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 282 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 283 </feature> 284 <feature name="org.gnu.gdb.i386.avx"> 285 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 286 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 287 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 288 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 289 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 290 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 291 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 292 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 293 </feature> 294 </target>""", False 295 else: 296 return None, False 297 298 def readRegister(self, regnum): 299 return "" 300 301 def readRegisters(self): 302 return "".join(reg_data) 303 304 def writeRegisters(self, reg_hex): 305 return "OK" 306 307 def haltReason(self): 308 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 309 310 self.server.responder = MyResponder() 311 312 target = self.createTarget("basic_eh_frame-i386.yaml") 313 process = self.connect(target) 314 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 315 [lldb.eStateStopped]) 316 317 # test generic aliases 318 self.match("register read fp", 319 ["ebp = 0x54535251"]) 320 self.match("register read sp", 321 ["esp = 0x44434241"]) 322 self.match("register read pc", 323 ["eip = 0x84838281"]) 324 self.match("register read flags", 325 ["eflags = 0x94939291"]) 326 327 # test pseudo-registers 328 self.match("register read cx", 329 ["cx = 0x1211"]) 330 self.match("register read ch", 331 ["ch = 0x12"]) 332 self.match("register read cl", 333 ["cl = 0x11"]) 334 self.match("register read mm0", 335 ["mm0 = 0x0807060504030201"]) 336 self.match("register read mm1", 337 ["mm1 = 0x1817161514131211"]) 338 339 # both stX and xmmX should be displayed as vectors 340 self.match("register read st0", 341 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 342 self.match("register read st1", 343 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 344 self.match("register read xmm0", 345 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 346 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 347 self.match("register read xmm1", 348 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 349 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 350 351 # test writing into pseudo-registers 352 self.runCmd("register write cx 0xfbfa") 353 reg_data[1] = "fafb1314" 354 self.assertPacketLogContains(["G" + "".join(reg_data)]) 355 self.match("register read ecx", 356 ["ecx = 0x1413fbfa"]) 357 358 self.runCmd("register write ch 0xf9") 359 reg_data[1] = "faf91314" 360 self.assertPacketLogContains(["G" + "".join(reg_data)]) 361 self.match("register read cx", 362 ["cx = 0xf9fa"]) 363 self.match("register read ecx", 364 ["ecx = 0x1413f9fa"]) 365 366 self.runCmd("register write cl 0xf8") 367 reg_data[1] = "f8f91314" 368 self.assertPacketLogContains(["G" + "".join(reg_data)]) 369 self.match("register read cx", 370 ["cx = 0xf9f8"]) 371 self.match("register read ecx", 372 ["ecx = 0x1413f9f8"]) 373 374 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 375 reg_data[10] = "f8f9fafbfcfdfeff090a" 376 self.assertPacketLogContains(["G" + "".join(reg_data)]) 377 self.match("register read st0", 378 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 379 380 @skipIfXmlSupportMissing 381 @skipIfRemote 382 @skipIfLLVMTargetMissing("AArch64") 383 def test_aarch64_regs(self): 384 """Test grabbing various aarch64 registers from gdbserver.""" 385 class MyResponder(MockGDBServerResponder): 386 reg_data = ( 387 "0102030405060708" # x0 388 "1112131415161718" # x1 389 ) + 27 * ( 390 "2122232425262728" # x2..x28 391 ) + ( 392 "3132333435363738" # x29 (fp) 393 "4142434445464748" # x30 (lr) 394 "5152535455565758" # x31 (sp) 395 "6162636465666768" # pc 396 "71727374" # cpsr 397 "8182838485868788898a8b8c8d8e8f90" # v0 398 "9192939495969798999a9b9c9d9e9fa0" # v1 399 ) + 30 * ( 400 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 401 ) + ( 402 "00000000" # fpsr 403 "00000000" # fpcr 404 ) 405 406 def qXferRead(self, obj, annex, offset, length): 407 if annex == "target.xml": 408 return """<?xml version="1.0"?> 409 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 410 <target> 411 <architecture>aarch64</architecture> 412 <feature name="org.gnu.gdb.aarch64.core"> 413 <reg name="x0" bitsize="64" type="int" regnum="0"/> 414 <reg name="x1" bitsize="64" type="int" regnum="1"/> 415 <reg name="x2" bitsize="64" type="int" regnum="2"/> 416 <reg name="x3" bitsize="64" type="int" regnum="3"/> 417 <reg name="x4" bitsize="64" type="int" regnum="4"/> 418 <reg name="x5" bitsize="64" type="int" regnum="5"/> 419 <reg name="x6" bitsize="64" type="int" regnum="6"/> 420 <reg name="x7" bitsize="64" type="int" regnum="7"/> 421 <reg name="x8" bitsize="64" type="int" regnum="8"/> 422 <reg name="x9" bitsize="64" type="int" regnum="9"/> 423 <reg name="x10" bitsize="64" type="int" regnum="10"/> 424 <reg name="x11" bitsize="64" type="int" regnum="11"/> 425 <reg name="x12" bitsize="64" type="int" regnum="12"/> 426 <reg name="x13" bitsize="64" type="int" regnum="13"/> 427 <reg name="x14" bitsize="64" type="int" regnum="14"/> 428 <reg name="x15" bitsize="64" type="int" regnum="15"/> 429 <reg name="x16" bitsize="64" type="int" regnum="16"/> 430 <reg name="x17" bitsize="64" type="int" regnum="17"/> 431 <reg name="x18" bitsize="64" type="int" regnum="18"/> 432 <reg name="x19" bitsize="64" type="int" regnum="19"/> 433 <reg name="x20" bitsize="64" type="int" regnum="20"/> 434 <reg name="x21" bitsize="64" type="int" regnum="21"/> 435 <reg name="x22" bitsize="64" type="int" regnum="22"/> 436 <reg name="x23" bitsize="64" type="int" regnum="23"/> 437 <reg name="x24" bitsize="64" type="int" regnum="24"/> 438 <reg name="x25" bitsize="64" type="int" regnum="25"/> 439 <reg name="x26" bitsize="64" type="int" regnum="26"/> 440 <reg name="x27" bitsize="64" type="int" regnum="27"/> 441 <reg name="x28" bitsize="64" type="int" regnum="28"/> 442 <reg name="x29" bitsize="64" type="int" regnum="29"/> 443 <reg name="x30" bitsize="64" type="int" regnum="30"/> 444 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 445 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 446 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 447 </feature> 448 <feature name="org.gnu.gdb.aarch64.fpu"> 449 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 450 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 451 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 452 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 453 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 454 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 455 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 456 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 457 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 458 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 459 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 460 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 461 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 462 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 463 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 464 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 465 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 466 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 467 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 468 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 469 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 470 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 471 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 472 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 473 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 474 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 475 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 476 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 477 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 478 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 479 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 480 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 481 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 482 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 483 </feature> 484 </target>""", False 485 else: 486 return None, False 487 488 def readRegister(self, regnum): 489 return "" 490 491 def readRegisters(self): 492 return self.reg_data 493 494 def writeRegisters(self, reg_hex): 495 self.reg_data = reg_hex 496 return "OK" 497 498 def haltReason(self): 499 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 500 501 self.server.responder = MyResponder() 502 503 target = self.createTarget("basic_eh_frame-aarch64.yaml") 504 process = self.connect(target) 505 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 506 [lldb.eStateStopped]) 507 508 # test GPRs 509 self.match("register read x0", 510 ["x0 = 0x0807060504030201"]) 511 self.match("register read x1", 512 ["x1 = 0x1817161514131211"]) 513 self.match("register read x29", 514 ["x29 = 0x3837363534333231"]) 515 self.match("register read x30", 516 ["x30 = 0x4847464544434241"]) 517 self.match("register read x31", 518 ["sp = 0x5857565554535251"]) 519 self.match("register read sp", 520 ["sp = 0x5857565554535251"]) 521 self.match("register read pc", 522 ["pc = 0x6867666564636261"]) 523 self.match("register read cpsr", 524 ["cpsr = 0x74737271"]) 525 526 # test generic aliases 527 self.match("register read arg1", 528 ["x0 = 0x0807060504030201"]) 529 self.match("register read arg2", 530 ["x1 = 0x1817161514131211"]) 531 self.match("register read fp", 532 ["x29 = 0x3837363534333231"]) 533 self.match("register read lr", 534 ["x30 = 0x4847464544434241"]) 535 self.match("register read ra", 536 ["x30 = 0x4847464544434241"]) 537 self.match("register read flags", 538 ["cpsr = 0x74737271"]) 539 540 # test vector registers 541 self.match("register read v0", 542 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 543 self.match("register read v31", 544 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 545 546 # test partial registers 547 self.match("register read w0", 548 ["w0 = 0x04030201"]) 549 self.runCmd("register write w0 0xfffefdfc") 550 self.match("register read x0", 551 ["x0 = 0x08070605fffefdfc"]) 552 553 self.match("register read w1", 554 ["w1 = 0x14131211"]) 555 self.runCmd("register write w1 0xefeeedec") 556 self.match("register read x1", 557 ["x1 = 0x18171615efeeedec"]) 558 559 self.match("register read w30", 560 ["w30 = 0x44434241"]) 561 self.runCmd("register write w30 0xdfdedddc") 562 self.match("register read x30", 563 ["x30 = 0x48474645dfdedddc"]) 564 565 self.match("register read w31", 566 ["w31 = 0x54535251"]) 567 self.runCmd("register write w31 0xcfcecdcc") 568 self.match("register read x31", 569 ["sp = 0x58575655cfcecdcc"]) 570 571 # test FPU registers (overlapping with vector registers) 572 self.runCmd("register write d0 16") 573 self.match("register read v0", 574 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 575 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 576 self.match("register read d31", 577 ["d31 = 64"]) 578 579 self.runCmd("register write s0 32") 580 self.match("register read v0", 581 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 582 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 583 self.match("register read s31", 584 ["s31 = 128"]) 585 586 @skipIfXmlSupportMissing 587 @skipIfRemote 588 @skipIfLLVMTargetMissing("AArch64") 589 def test_aarch64_no_duplicate_subregs(self): 590 """Test that duplicate subregisters are not added.""" 591 class MyResponder(MockGDBServerResponder): 592 reg_data = ( 593 "0102030405060708" # x0 594 "1112131415161718" # x1 595 ) + 27 * ( 596 "2122232425262728" # x2..x28 597 ) + ( 598 "3132333435363738" # x29 (fp) 599 "4142434445464748" # x30 (lr) 600 "5152535455565758" # x31 (sp) 601 "6162636465666768" # pc 602 "71727374" # cpsr 603 ) 604 605 def qXferRead(self, obj, annex, offset, length): 606 if annex == "target.xml": 607 return """<?xml version="1.0"?> 608 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 609 <target> 610 <architecture>aarch64</architecture> 611 <feature name="org.gnu.gdb.aarch64.core"> 612 <reg name="x0" bitsize="64" type="int" regnum="0"/> 613 <reg name="x1" bitsize="64" type="int" regnum="1"/> 614 <reg name="x2" bitsize="64" type="int" regnum="2"/> 615 <reg name="x3" bitsize="64" type="int" regnum="3"/> 616 <reg name="x4" bitsize="64" type="int" regnum="4"/> 617 <reg name="x5" bitsize="64" type="int" regnum="5"/> 618 <reg name="x6" bitsize="64" type="int" regnum="6"/> 619 <reg name="x7" bitsize="64" type="int" regnum="7"/> 620 <reg name="x8" bitsize="64" type="int" regnum="8"/> 621 <reg name="x9" bitsize="64" type="int" regnum="9"/> 622 <reg name="x10" bitsize="64" type="int" regnum="10"/> 623 <reg name="x11" bitsize="64" type="int" regnum="11"/> 624 <reg name="x12" bitsize="64" type="int" regnum="12"/> 625 <reg name="x13" bitsize="64" type="int" regnum="13"/> 626 <reg name="x14" bitsize="64" type="int" regnum="14"/> 627 <reg name="x15" bitsize="64" type="int" regnum="15"/> 628 <reg name="x16" bitsize="64" type="int" regnum="16"/> 629 <reg name="x17" bitsize="64" type="int" regnum="17"/> 630 <reg name="x18" bitsize="64" type="int" regnum="18"/> 631 <reg name="x19" bitsize="64" type="int" regnum="19"/> 632 <reg name="x20" bitsize="64" type="int" regnum="20"/> 633 <reg name="x21" bitsize="64" type="int" regnum="21"/> 634 <reg name="x22" bitsize="64" type="int" regnum="22"/> 635 <reg name="x23" bitsize="64" type="int" regnum="23"/> 636 <reg name="x24" bitsize="64" type="int" regnum="24"/> 637 <reg name="x25" bitsize="64" type="int" regnum="25"/> 638 <reg name="x26" bitsize="64" type="int" regnum="26"/> 639 <reg name="x27" bitsize="64" type="int" regnum="27"/> 640 <reg name="x28" bitsize="64" type="int" regnum="28"/> 641 <reg name="x29" bitsize="64" type="int" regnum="29"/> 642 <reg name="x30" bitsize="64" type="int" regnum="30"/> 643 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 644 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 645 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 646 <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/> 647 </feature> 648 </target>""", False 649 else: 650 return None, False 651 652 def readRegister(self, regnum): 653 return "" 654 655 def readRegisters(self): 656 return self.reg_data 657 658 def haltReason(self): 659 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 660 661 self.server.responder = MyResponder() 662 663 target = self.createTarget("basic_eh_frame-aarch64.yaml") 664 process = self.connect(target) 665 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 666 [lldb.eStateStopped]) 667 668 self.match("register read x0", 669 ["x0 = 0x0807060504030201"]) 670 # w0 comes from target.xml 671 self.match("register read w0", 672 ["w0 = 0x04030201"]) 673 self.match("register read x1", 674 ["x1 = 0x1817161514131211"]) 675 # w1 should not be added 676 self.match("register read w1", 677 ["error: Invalid register name 'w1'."], 678 error=True) 679