1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from lldbsuite.test.gdbclientutils import * 6from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase 7 8 9class TestGDBServerTargetXML(GDBRemoteTestBase): 10 11 @skipIfXmlSupportMissing 12 @skipIfRemote 13 @skipIfLLVMTargetMissing("X86") 14 def test_x86_64_regs(self): 15 """Test grabbing various x86_64 registers from gdbserver.""" 16 class MyResponder(MockGDBServerResponder): 17 reg_data = ( 18 "0102030405060708" # rcx 19 "1112131415161718" # rdx 20 "2122232425262728" # rsi 21 "3132333435363738" # rdi 22 "4142434445464748" # rbp 23 "5152535455565758" # rsp 24 "6162636465666768" # r8 25 "7172737475767778" # r9 26 "8182838485868788" # rip 27 "91929394" # eflags 28 "0102030405060708090a" # st0 29 "1112131415161718191a" # st1 30 ) + 6 * ( 31 "2122232425262728292a" # st2..st7 32 ) + ( 33 "8182838485868788898a8b8c8d8e8f90" # xmm0 34 "9192939495969798999a9b9c9d9e9fa0" # xmm1 35 ) + 14 * ( 36 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm15 37 ) + ( 38 "00000000" # mxcsr 39 ) + ( 40 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 41 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 42 ) + 14 * ( 43 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm15h 44 ) 45 46 def qXferRead(self, obj, annex, offset, length): 47 if annex == "target.xml": 48 return """<?xml version="1.0"?> 49 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 50 <target> 51 <architecture>i386:x86-64</architecture> 52 <osabi>GNU/Linux</osabi> 53 <feature name="org.gnu.gdb.i386.core"> 54 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 55 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 56 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 57 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 58 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 59 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 60 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 61 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 62 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 63 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 64 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 65 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 66 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 67 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 68 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 69 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 70 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 71 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 72 </feature> 73 <feature name="org.gnu.gdb.i386.sse"> 74 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 75 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 76 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 77 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 78 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 79 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 80 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 81 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 82 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 83 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 84 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 85 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 86 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 87 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 88 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 89 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 90 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 91 </feature> 92 <feature name="org.gnu.gdb.i386.avx"> 93 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 94 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 95 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 96 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 97 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 98 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 99 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 100 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 101 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 102 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 103 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 104 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 105 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 106 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 107 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 108 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 109 </feature> 110 </target>""", False 111 else: 112 return None, False 113 114 def readRegister(self, regnum): 115 return "" 116 117 def readRegisters(self): 118 return self.reg_data 119 120 def writeRegisters(self, reg_hex): 121 self.reg_data = reg_hex 122 return "OK" 123 124 def haltReason(self): 125 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 126 127 self.server.responder = MyResponder() 128 129 target = self.createTarget("basic_eh_frame.yaml") 130 process = self.connect(target) 131 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 132 [lldb.eStateStopped]) 133 134 # test generic aliases 135 self.match("register read arg4", 136 ["rcx = 0x0807060504030201"]) 137 self.match("register read arg3", 138 ["rdx = 0x1817161514131211"]) 139 self.match("register read arg2", 140 ["rsi = 0x2827262524232221"]) 141 self.match("register read arg1", 142 ["rdi = 0x3837363534333231"]) 143 self.match("register read fp", 144 ["rbp = 0x4847464544434241"]) 145 self.match("register read sp", 146 ["rsp = 0x5857565554535251"]) 147 self.match("register read arg5", 148 ["r8 = 0x6867666564636261"]) 149 self.match("register read arg6", 150 ["r9 = 0x7877767574737271"]) 151 self.match("register read pc", 152 ["rip = 0x8887868584838281"]) 153 self.match("register read flags", 154 ["eflags = 0x94939291"]) 155 156 # both stX and xmmX should be displayed as vectors 157 self.match("register read st0", 158 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 159 self.match("register read st1", 160 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 161 self.match("register read xmm0", 162 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 163 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 164 self.match("register read xmm1", 165 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 166 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 167 168 # test pseudo-registers 169 self.filecheck("register read --all", 170 os.path.join(os.path.dirname(__file__), 171 "amd64-partial-regs.FileCheck")) 172 173 # test writing into pseudo-registers 174 self.runCmd("register write ecx 0xfffefdfc") 175 self.match("register read rcx", 176 ["rcx = 0x08070605fffefdfc"]) 177 178 self.runCmd("register write cx 0xfbfa") 179 self.match("register read ecx", 180 ["ecx = 0xfffefbfa"]) 181 self.match("register read rcx", 182 ["rcx = 0x08070605fffefbfa"]) 183 184 self.runCmd("register write ch 0xf9") 185 self.match("register read cx", 186 ["cx = 0xf9fa"]) 187 self.match("register read ecx", 188 ["ecx = 0xfffef9fa"]) 189 self.match("register read rcx", 190 ["rcx = 0x08070605fffef9fa"]) 191 192 self.runCmd("register write cl 0xf8") 193 self.match("register read cx", 194 ["cx = 0xf9f8"]) 195 self.match("register read ecx", 196 ["ecx = 0xfffef9f8"]) 197 self.match("register read rcx", 198 ["rcx = 0x08070605fffef9f8"]) 199 200 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 201 self.match("register read st0", 202 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 203 204 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 205 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 206 self.match("register read ymm0", 207 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 208 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 209 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 210 211 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 212 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 213 self.match("register read ymm0", 214 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 215 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 216 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 217 218 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 219 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 220 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 221 "0xed 0xee 0xef}\"") 222 self.match("register read ymm0", 223 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 224 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 225 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 226 227 @skipIfXmlSupportMissing 228 @skipIfRemote 229 @skipIfLLVMTargetMissing("X86") 230 def test_i386_regs(self): 231 """Test grabbing various i386 registers from gdbserver.""" 232 class MyResponder(MockGDBServerResponder): 233 reg_data = ( 234 "01020304" # eax 235 "11121314" # ecx 236 "21222324" # edx 237 "31323334" # ebx 238 "41424344" # esp 239 "51525354" # ebp 240 "61626364" # esi 241 "71727374" # edi 242 "81828384" # eip 243 "91929394" # eflags 244 "0102030405060708090a" # st0 245 "1112131415161718191a" # st1 246 ) + 6 * ( 247 "2122232425262728292a" # st2..st7 248 ) + ( 249 "8182838485868788898a8b8c8d8e8f90" # xmm0 250 "9192939495969798999a9b9c9d9e9fa0" # xmm1 251 ) + 6 * ( 252 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm7 253 ) + ( 254 "00000000" # mxcsr 255 ) + ( 256 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 257 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 258 ) + 6 * ( 259 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm7h 260 ) 261 262 def qXferRead(self, obj, annex, offset, length): 263 if annex == "target.xml": 264 return """<?xml version="1.0"?> 265 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 266 <target> 267 <architecture>i386</architecture> 268 <osabi>GNU/Linux</osabi> 269 <feature name="org.gnu.gdb.i386.core"> 270 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 271 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 272 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 273 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 274 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 275 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 276 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 277 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 278 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 279 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 280 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 281 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 282 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 283 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 284 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 285 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 286 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 287 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 288 </feature> 289 <feature name="org.gnu.gdb.i386.sse"> 290 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 291 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 292 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 293 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 294 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 295 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 296 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 297 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 298 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 299 </feature> 300 <feature name="org.gnu.gdb.i386.avx"> 301 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 302 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 303 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 304 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 305 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 306 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 307 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 308 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 309 </feature> 310 </target>""", False 311 else: 312 return None, False 313 314 def readRegister(self, regnum): 315 return "" 316 317 def readRegisters(self): 318 return self.reg_data 319 320 def writeRegisters(self, reg_hex): 321 self.reg_data = reg_hex 322 return "OK" 323 324 def haltReason(self): 325 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 326 327 self.server.responder = MyResponder() 328 329 target = self.createTarget("basic_eh_frame-i386.yaml") 330 process = self.connect(target) 331 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 332 [lldb.eStateStopped]) 333 334 # test generic aliases 335 self.match("register read fp", 336 ["ebp = 0x54535251"]) 337 self.match("register read sp", 338 ["esp = 0x44434241"]) 339 self.match("register read pc", 340 ["eip = 0x84838281"]) 341 self.match("register read flags", 342 ["eflags = 0x94939291"]) 343 344 # test pseudo-registers 345 self.match("register read cx", 346 ["cx = 0x1211"]) 347 self.match("register read ch", 348 ["ch = 0x12"]) 349 self.match("register read cl", 350 ["cl = 0x11"]) 351 self.match("register read mm0", 352 ["mm0 = 0x0807060504030201"]) 353 self.match("register read mm1", 354 ["mm1 = 0x1817161514131211"]) 355 356 # both stX and xmmX should be displayed as vectors 357 self.match("register read st0", 358 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 359 self.match("register read st1", 360 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 361 self.match("register read xmm0", 362 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 363 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 364 self.match("register read xmm1", 365 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 366 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 367 368 # test writing into pseudo-registers 369 self.runCmd("register write cx 0xfbfa") 370 self.match("register read ecx", 371 ["ecx = 0x1413fbfa"]) 372 373 self.runCmd("register write ch 0xf9") 374 self.match("register read cx", 375 ["cx = 0xf9fa"]) 376 self.match("register read ecx", 377 ["ecx = 0x1413f9fa"]) 378 379 self.runCmd("register write cl 0xf8") 380 self.match("register read cx", 381 ["cx = 0xf9f8"]) 382 self.match("register read ecx", 383 ["ecx = 0x1413f9f8"]) 384 385 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 386 self.match("register read st0", 387 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 388 389 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 390 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 391 self.match("register read ymm0", 392 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 393 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 394 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 395 396 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 397 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 398 self.match("register read ymm0", 399 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 400 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 401 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 402 403 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 404 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 405 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 406 "0xed 0xee 0xef}\"") 407 self.match("register read ymm0", 408 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 409 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 410 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 411 412 @skipIfXmlSupportMissing 413 @skipIfRemote 414 @skipIfLLVMTargetMissing("AArch64") 415 def test_aarch64_regs(self): 416 """Test grabbing various aarch64 registers from gdbserver.""" 417 class MyResponder(MockGDBServerResponder): 418 reg_data = ( 419 "0102030405060708" # x0 420 "1112131415161718" # x1 421 ) + 27 * ( 422 "2122232425262728" # x2..x28 423 ) + ( 424 "3132333435363738" # x29 (fp) 425 "4142434445464748" # x30 (lr) 426 "5152535455565758" # x31 (sp) 427 "6162636465666768" # pc 428 "71727374" # cpsr 429 "8182838485868788898a8b8c8d8e8f90" # v0 430 "9192939495969798999a9b9c9d9e9fa0" # v1 431 ) + 30 * ( 432 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 433 ) + ( 434 "00000000" # fpsr 435 "00000000" # fpcr 436 ) 437 438 def qXferRead(self, obj, annex, offset, length): 439 if annex == "target.xml": 440 return """<?xml version="1.0"?> 441 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 442 <target> 443 <architecture>aarch64</architecture> 444 <feature name="org.gnu.gdb.aarch64.core"> 445 <reg name="x0" bitsize="64" type="int" regnum="0"/> 446 <reg name="x1" bitsize="64" type="int" regnum="1"/> 447 <reg name="x2" bitsize="64" type="int" regnum="2"/> 448 <reg name="x3" bitsize="64" type="int" regnum="3"/> 449 <reg name="x4" bitsize="64" type="int" regnum="4"/> 450 <reg name="x5" bitsize="64" type="int" regnum="5"/> 451 <reg name="x6" bitsize="64" type="int" regnum="6"/> 452 <reg name="x7" bitsize="64" type="int" regnum="7"/> 453 <reg name="x8" bitsize="64" type="int" regnum="8"/> 454 <reg name="x9" bitsize="64" type="int" regnum="9"/> 455 <reg name="x10" bitsize="64" type="int" regnum="10"/> 456 <reg name="x11" bitsize="64" type="int" regnum="11"/> 457 <reg name="x12" bitsize="64" type="int" regnum="12"/> 458 <reg name="x13" bitsize="64" type="int" regnum="13"/> 459 <reg name="x14" bitsize="64" type="int" regnum="14"/> 460 <reg name="x15" bitsize="64" type="int" regnum="15"/> 461 <reg name="x16" bitsize="64" type="int" regnum="16"/> 462 <reg name="x17" bitsize="64" type="int" regnum="17"/> 463 <reg name="x18" bitsize="64" type="int" regnum="18"/> 464 <reg name="x19" bitsize="64" type="int" regnum="19"/> 465 <reg name="x20" bitsize="64" type="int" regnum="20"/> 466 <reg name="x21" bitsize="64" type="int" regnum="21"/> 467 <reg name="x22" bitsize="64" type="int" regnum="22"/> 468 <reg name="x23" bitsize="64" type="int" regnum="23"/> 469 <reg name="x24" bitsize="64" type="int" regnum="24"/> 470 <reg name="x25" bitsize="64" type="int" regnum="25"/> 471 <reg name="x26" bitsize="64" type="int" regnum="26"/> 472 <reg name="x27" bitsize="64" type="int" regnum="27"/> 473 <reg name="x28" bitsize="64" type="int" regnum="28"/> 474 <reg name="x29" bitsize="64" type="int" regnum="29"/> 475 <reg name="x30" bitsize="64" type="int" regnum="30"/> 476 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 477 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 478 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 479 </feature> 480 <feature name="org.gnu.gdb.aarch64.fpu"> 481 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 482 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 483 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 484 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 485 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 486 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 487 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 488 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 489 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 490 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 491 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 492 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 493 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 494 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 495 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 496 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 497 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 498 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 499 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 500 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 501 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 502 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 503 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 504 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 505 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 506 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 507 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 508 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 509 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 510 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 511 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 512 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 513 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 514 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 515 </feature> 516 </target>""", False 517 else: 518 return None, False 519 520 def readRegister(self, regnum): 521 return "" 522 523 def readRegisters(self): 524 return self.reg_data 525 526 def writeRegisters(self, reg_hex): 527 self.reg_data = reg_hex 528 return "OK" 529 530 def haltReason(self): 531 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 532 533 self.server.responder = MyResponder() 534 535 target = self.createTarget("basic_eh_frame-aarch64.yaml") 536 process = self.connect(target) 537 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 538 [lldb.eStateStopped]) 539 540 # test GPRs 541 self.match("register read x0", 542 ["x0 = 0x0807060504030201"]) 543 self.match("register read x1", 544 ["x1 = 0x1817161514131211"]) 545 self.match("register read x29", 546 ["x29 = 0x3837363534333231"]) 547 self.match("register read x30", 548 ["x30 = 0x4847464544434241"]) 549 self.match("register read x31", 550 ["sp = 0x5857565554535251"]) 551 self.match("register read sp", 552 ["sp = 0x5857565554535251"]) 553 self.match("register read pc", 554 ["pc = 0x6867666564636261"]) 555 self.match("register read cpsr", 556 ["cpsr = 0x74737271"]) 557 558 # test generic aliases 559 self.match("register read arg1", 560 ["x0 = 0x0807060504030201"]) 561 self.match("register read arg2", 562 ["x1 = 0x1817161514131211"]) 563 self.match("register read fp", 564 ["x29 = 0x3837363534333231"]) 565 self.match("register read lr", 566 ["x30 = 0x4847464544434241"]) 567 self.match("register read ra", 568 ["x30 = 0x4847464544434241"]) 569 self.match("register read flags", 570 ["cpsr = 0x74737271"]) 571 572 # test vector registers 573 self.match("register read v0", 574 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 575 self.match("register read v31", 576 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 577 578 # test partial registers 579 self.match("register read w0", 580 ["w0 = 0x04030201"]) 581 self.runCmd("register write w0 0xfffefdfc") 582 self.match("register read x0", 583 ["x0 = 0x08070605fffefdfc"]) 584 585 self.match("register read w1", 586 ["w1 = 0x14131211"]) 587 self.runCmd("register write w1 0xefeeedec") 588 self.match("register read x1", 589 ["x1 = 0x18171615efeeedec"]) 590 591 self.match("register read w30", 592 ["w30 = 0x44434241"]) 593 self.runCmd("register write w30 0xdfdedddc") 594 self.match("register read x30", 595 ["x30 = 0x48474645dfdedddc"]) 596 597 self.match("register read w31", 598 ["w31 = 0x54535251"]) 599 self.runCmd("register write w31 0xcfcecdcc") 600 self.match("register read x31", 601 ["sp = 0x58575655cfcecdcc"]) 602 603 # test FPU registers (overlapping with vector registers) 604 self.runCmd("register write d0 16") 605 self.match("register read v0", 606 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 607 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 608 self.match("register read d31", 609 ["d31 = 64"]) 610 611 self.runCmd("register write s0 32") 612 self.match("register read v0", 613 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 614 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 615 self.match("register read s31", 616 ["s31 = 128"]) 617 618 @skipIfXmlSupportMissing 619 @skipIfRemote 620 @skipIfLLVMTargetMissing("X86") 621 def test_x86_64_no_duplicate_subregs(self): 622 """Test that duplicate subregisters are not added (on x86_64).""" 623 class MyResponder(MockGDBServerResponder): 624 reg_data = ( 625 "0102030405060708" # rcx 626 "1112131415161718" # rdx 627 "2122232425262728" # rsi 628 "3132333435363738" # rdi 629 "4142434445464748" # rbp 630 "5152535455565758" # rsp 631 "6162636465666768" # r8 632 "7172737475767778" # r9 633 "8182838485868788" # rip 634 "91929394" # eflags 635 ) 636 637 def qXferRead(self, obj, annex, offset, length): 638 if annex == "target.xml": 639 return """<?xml version="1.0"?> 640 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 641 <target> 642 <architecture>i386:x86-64</architecture> 643 <osabi>GNU/Linux</osabi> 644 <feature name="org.gnu.gdb.i386.core"> 645 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 646 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 647 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 648 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 649 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 650 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 651 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 652 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 653 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 654 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 655 <reg name="ecx" bitsize="32" type="int" regnum="18" value_regnums="2"/> 656 </feature> 657 </target>""", False 658 else: 659 return None, False 660 661 def readRegister(self, regnum): 662 return "" 663 664 def readRegisters(self): 665 return self.reg_data 666 667 def haltReason(self): 668 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 669 670 self.server.responder = MyResponder() 671 672 target = self.createTarget("basic_eh_frame.yaml") 673 process = self.connect(target) 674 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 675 [lldb.eStateStopped]) 676 677 self.match("register read rcx", 678 ["rcx = 0x0807060504030201"]) 679 # ecx is supplied via target.xml 680 self.match("register read ecx", 681 ["ecx = 0x04030201"]) 682 self.match("register read rdx", 683 ["rdx = 0x1817161514131211"]) 684 # edx should not be added 685 self.match("register read edx", 686 ["error: Invalid register name 'edx'."], 687 error=True) 688 689 @skipIfXmlSupportMissing 690 @skipIfRemote 691 @skipIfLLVMTargetMissing("X86") 692 def test_i386_no_duplicate_subregs(self): 693 """Test that duplicate subregisters are not added (on i386).""" 694 class MyResponder(MockGDBServerResponder): 695 reg_data = ( 696 "01020304" # eax 697 "11121314" # ecx 698 "21222324" # edx 699 "31323334" # ebx 700 "41424344" # esp 701 "51525354" # ebp 702 "61626364" # esi 703 "71727374" # edi 704 "81828384" # eip 705 "91929394" # eflags 706 ) 707 708 def qXferRead(self, obj, annex, offset, length): 709 if annex == "target.xml": 710 return """<?xml version="1.0"?> 711 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 712 <target> 713 <architecture>i386</architecture> 714 <osabi>GNU/Linux</osabi> 715 <feature name="org.gnu.gdb.i386.core"> 716 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 717 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 718 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 719 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 720 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 721 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 722 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 723 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 724 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 725 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 726 <reg name="ax" bitsize="16" type="int" regnum="10" value_regnums="0"/> 727 </feature> 728 </target>""", False 729 else: 730 return None, False 731 732 def readRegister(self, regnum): 733 return "" 734 735 def readRegisters(self): 736 return self.reg_data 737 738 def haltReason(self): 739 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 740 741 self.server.responder = MyResponder() 742 743 target = self.createTarget("basic_eh_frame-i386.yaml") 744 process = self.connect(target) 745 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 746 [lldb.eStateStopped]) 747 748 self.match("register read eax", 749 ["eax = 0x04030201"]) 750 # cx is supplied via target.xml 751 self.match("register read ax", 752 ["ax = 0x0201"]) 753 self.match("register read ecx", 754 ["ecx = 0x14131211"]) 755 # dx should not be added 756 self.match("register read cx", 757 ["error: Invalid register name 'cx'."], 758 error=True) 759 760 @skipIfXmlSupportMissing 761 @skipIfRemote 762 @skipIfLLVMTargetMissing("AArch64") 763 def test_aarch64_no_duplicate_subregs(self): 764 """Test that duplicate subregisters are not added.""" 765 class MyResponder(MockGDBServerResponder): 766 reg_data = ( 767 "0102030405060708" # x0 768 "1112131415161718" # x1 769 ) + 27 * ( 770 "2122232425262728" # x2..x28 771 ) + ( 772 "3132333435363738" # x29 (fp) 773 "4142434445464748" # x30 (lr) 774 "5152535455565758" # x31 (sp) 775 "6162636465666768" # pc 776 "71727374" # cpsr 777 ) 778 779 def qXferRead(self, obj, annex, offset, length): 780 if annex == "target.xml": 781 return """<?xml version="1.0"?> 782 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 783 <target> 784 <architecture>aarch64</architecture> 785 <feature name="org.gnu.gdb.aarch64.core"> 786 <reg name="x0" bitsize="64" type="int" regnum="0"/> 787 <reg name="x1" bitsize="64" type="int" regnum="1"/> 788 <reg name="x2" bitsize="64" type="int" regnum="2"/> 789 <reg name="x3" bitsize="64" type="int" regnum="3"/> 790 <reg name="x4" bitsize="64" type="int" regnum="4"/> 791 <reg name="x5" bitsize="64" type="int" regnum="5"/> 792 <reg name="x6" bitsize="64" type="int" regnum="6"/> 793 <reg name="x7" bitsize="64" type="int" regnum="7"/> 794 <reg name="x8" bitsize="64" type="int" regnum="8"/> 795 <reg name="x9" bitsize="64" type="int" regnum="9"/> 796 <reg name="x10" bitsize="64" type="int" regnum="10"/> 797 <reg name="x11" bitsize="64" type="int" regnum="11"/> 798 <reg name="x12" bitsize="64" type="int" regnum="12"/> 799 <reg name="x13" bitsize="64" type="int" regnum="13"/> 800 <reg name="x14" bitsize="64" type="int" regnum="14"/> 801 <reg name="x15" bitsize="64" type="int" regnum="15"/> 802 <reg name="x16" bitsize="64" type="int" regnum="16"/> 803 <reg name="x17" bitsize="64" type="int" regnum="17"/> 804 <reg name="x18" bitsize="64" type="int" regnum="18"/> 805 <reg name="x19" bitsize="64" type="int" regnum="19"/> 806 <reg name="x20" bitsize="64" type="int" regnum="20"/> 807 <reg name="x21" bitsize="64" type="int" regnum="21"/> 808 <reg name="x22" bitsize="64" type="int" regnum="22"/> 809 <reg name="x23" bitsize="64" type="int" regnum="23"/> 810 <reg name="x24" bitsize="64" type="int" regnum="24"/> 811 <reg name="x25" bitsize="64" type="int" regnum="25"/> 812 <reg name="x26" bitsize="64" type="int" regnum="26"/> 813 <reg name="x27" bitsize="64" type="int" regnum="27"/> 814 <reg name="x28" bitsize="64" type="int" regnum="28"/> 815 <reg name="x29" bitsize="64" type="int" regnum="29"/> 816 <reg name="x30" bitsize="64" type="int" regnum="30"/> 817 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 818 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 819 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 820 <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/> 821 </feature> 822 </target>""", False 823 else: 824 return None, False 825 826 def readRegister(self, regnum): 827 return "" 828 829 def readRegisters(self): 830 return self.reg_data 831 832 def haltReason(self): 833 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 834 835 self.server.responder = MyResponder() 836 837 target = self.createTarget("basic_eh_frame-aarch64.yaml") 838 process = self.connect(target) 839 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 840 [lldb.eStateStopped]) 841 842 self.match("register read x0", 843 ["x0 = 0x0807060504030201"]) 844 # w0 comes from target.xml 845 self.match("register read w0", 846 ["w0 = 0x04030201"]) 847 self.match("register read x1", 848 ["x1 = 0x1817161514131211"]) 849 # w1 should not be added 850 self.match("register read w1", 851 ["error: Invalid register name 'w1'."], 852 error=True) 853