1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from gdbclientutils import * 6 7 8class TestGDBServerTargetXML(GDBRemoteTestBase): 9 @skipIfXmlSupportMissing 10 @skipIfRemote 11 @skipIfLLVMTargetMissing("X86") 12 def test_x86_64_regs(self): 13 """Test grabbing various x86_64 registers from gdbserver.""" 14 class MyResponder(MockGDBServerResponder): 15 reg_data = ( 16 "0102030405060708" # rcx 17 "1112131415161718" # rdx 18 "2122232425262728" # rsi 19 "3132333435363738" # rdi 20 "4142434445464748" # rbp 21 "5152535455565758" # rsp 22 "6162636465666768" # r8 23 "7172737475767778" # r9 24 "8182838485868788" # rip 25 "91929394" # eflags 26 "0102030405060708090a" # st0 27 "1112131415161718191a" # st1 28 ) + 6 * ( 29 "2122232425262728292a" # st2..st7 30 ) + ( 31 "8182838485868788898a8b8c8d8e8f90" # xmm0 32 "9192939495969798999a9b9c9d9e9fa0" # xmm1 33 ) + 14 * ( 34 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm15 35 ) + ( 36 "00000000" # mxcsr 37 ) + ( 38 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 39 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 40 ) + 14 * ( 41 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm15h 42 ) 43 44 def qXferRead(self, obj, annex, offset, length): 45 if annex == "target.xml": 46 return """<?xml version="1.0"?> 47 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 48 <target> 49 <architecture>i386:x86-64</architecture> 50 <osabi>GNU/Linux</osabi> 51 <feature name="org.gnu.gdb.i386.core"> 52 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 53 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 54 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 55 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 56 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 57 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 58 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 59 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 60 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 61 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 62 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 63 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 64 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 65 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 66 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 67 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 68 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 69 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 70 </feature> 71 <feature name="org.gnu.gdb.i386.sse"> 72 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 73 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 74 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 75 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 76 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 77 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 78 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 79 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 80 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 81 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 82 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 83 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 84 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 85 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 86 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 87 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 88 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 89 </feature> 90 <feature name="org.gnu.gdb.i386.avx"> 91 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 92 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 93 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 94 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 95 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 96 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 97 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 98 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 99 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 100 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 101 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 102 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 103 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 104 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 105 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 106 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 107 </feature> 108 </target>""", False 109 else: 110 return None, False 111 112 def readRegister(self, regnum): 113 return "" 114 115 def readRegisters(self): 116 return self.reg_data 117 118 def writeRegisters(self, reg_hex): 119 self.reg_data = reg_hex 120 return "OK" 121 122 def haltReason(self): 123 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 124 125 self.server.responder = MyResponder() 126 127 target = self.createTarget("basic_eh_frame.yaml") 128 process = self.connect(target) 129 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 130 [lldb.eStateStopped]) 131 132 # test generic aliases 133 self.match("register read arg4", 134 ["rcx = 0x0807060504030201"]) 135 self.match("register read arg3", 136 ["rdx = 0x1817161514131211"]) 137 self.match("register read arg2", 138 ["rsi = 0x2827262524232221"]) 139 self.match("register read arg1", 140 ["rdi = 0x3837363534333231"]) 141 self.match("register read fp", 142 ["rbp = 0x4847464544434241"]) 143 self.match("register read sp", 144 ["rsp = 0x5857565554535251"]) 145 self.match("register read arg5", 146 ["r8 = 0x6867666564636261"]) 147 self.match("register read arg6", 148 ["r9 = 0x7877767574737271"]) 149 self.match("register read pc", 150 ["rip = 0x8887868584838281"]) 151 self.match("register read flags", 152 ["eflags = 0x94939291"]) 153 154 # both stX and xmmX should be displayed as vectors 155 self.match("register read st0", 156 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 157 self.match("register read st1", 158 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 159 self.match("register read xmm0", 160 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 161 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 162 self.match("register read xmm1", 163 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 164 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 165 166 # test pseudo-registers 167 self.filecheck("register read --all", 168 os.path.join(os.path.dirname(__file__), 169 "amd64-partial-regs.FileCheck")) 170 171 # test writing into pseudo-registers 172 self.runCmd("register write ecx 0xfffefdfc") 173 self.match("register read rcx", 174 ["rcx = 0x08070605fffefdfc"]) 175 176 self.runCmd("register write cx 0xfbfa") 177 self.match("register read ecx", 178 ["ecx = 0xfffefbfa"]) 179 self.match("register read rcx", 180 ["rcx = 0x08070605fffefbfa"]) 181 182 self.runCmd("register write ch 0xf9") 183 self.match("register read cx", 184 ["cx = 0xf9fa"]) 185 self.match("register read ecx", 186 ["ecx = 0xfffef9fa"]) 187 self.match("register read rcx", 188 ["rcx = 0x08070605fffef9fa"]) 189 190 self.runCmd("register write cl 0xf8") 191 self.match("register read cx", 192 ["cx = 0xf9f8"]) 193 self.match("register read ecx", 194 ["ecx = 0xfffef9f8"]) 195 self.match("register read rcx", 196 ["rcx = 0x08070605fffef9f8"]) 197 198 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 199 self.match("register read st0", 200 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 201 202 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 203 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 204 self.match("register read ymm0", 205 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 206 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 207 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 208 209 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 210 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 211 self.match("register read ymm0", 212 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 213 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 214 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 215 216 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 217 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 218 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 219 "0xed 0xee 0xef}\"") 220 self.match("register read ymm0", 221 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 222 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 223 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 224 225 @skipIfXmlSupportMissing 226 @skipIfRemote 227 @skipIfLLVMTargetMissing("X86") 228 def test_i386_regs(self): 229 """Test grabbing various i386 registers from gdbserver.""" 230 class MyResponder(MockGDBServerResponder): 231 reg_data = ( 232 "01020304" # eax 233 "11121314" # ecx 234 "21222324" # edx 235 "31323334" # ebx 236 "41424344" # esp 237 "51525354" # ebp 238 "61626364" # esi 239 "71727374" # edi 240 "81828384" # eip 241 "91929394" # eflags 242 "0102030405060708090a" # st0 243 "1112131415161718191a" # st1 244 ) + 6 * ( 245 "2122232425262728292a" # st2..st7 246 ) + ( 247 "8182838485868788898a8b8c8d8e8f90" # xmm0 248 "9192939495969798999a9b9c9d9e9fa0" # xmm1 249 ) + 6 * ( 250 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm7 251 ) + ( 252 "00000000" # mxcsr 253 ) + ( 254 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 255 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 256 ) + 6 * ( 257 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm7h 258 ) 259 260 def qXferRead(self, obj, annex, offset, length): 261 if annex == "target.xml": 262 return """<?xml version="1.0"?> 263 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 264 <target> 265 <architecture>i386</architecture> 266 <osabi>GNU/Linux</osabi> 267 <feature name="org.gnu.gdb.i386.core"> 268 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 269 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 270 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 271 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 272 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 273 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 274 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 275 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 276 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 277 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 278 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 279 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 280 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 281 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 282 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 283 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 284 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 285 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 286 </feature> 287 <feature name="org.gnu.gdb.i386.sse"> 288 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 289 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 290 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 291 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 292 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 293 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 294 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 295 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 296 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 297 </feature> 298 <feature name="org.gnu.gdb.i386.avx"> 299 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 300 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 301 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 302 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 303 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 304 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 305 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 306 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 307 </feature> 308 </target>""", False 309 else: 310 return None, False 311 312 def readRegister(self, regnum): 313 return "" 314 315 def readRegisters(self): 316 return self.reg_data 317 318 def writeRegisters(self, reg_hex): 319 self.reg_data = reg_hex 320 return "OK" 321 322 def haltReason(self): 323 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 324 325 self.server.responder = MyResponder() 326 327 target = self.createTarget("basic_eh_frame-i386.yaml") 328 process = self.connect(target) 329 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 330 [lldb.eStateStopped]) 331 332 # test generic aliases 333 self.match("register read fp", 334 ["ebp = 0x54535251"]) 335 self.match("register read sp", 336 ["esp = 0x44434241"]) 337 self.match("register read pc", 338 ["eip = 0x84838281"]) 339 self.match("register read flags", 340 ["eflags = 0x94939291"]) 341 342 # test pseudo-registers 343 self.match("register read cx", 344 ["cx = 0x1211"]) 345 self.match("register read ch", 346 ["ch = 0x12"]) 347 self.match("register read cl", 348 ["cl = 0x11"]) 349 self.match("register read mm0", 350 ["mm0 = 0x0807060504030201"]) 351 self.match("register read mm1", 352 ["mm1 = 0x1817161514131211"]) 353 354 # both stX and xmmX should be displayed as vectors 355 self.match("register read st0", 356 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 357 self.match("register read st1", 358 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 359 self.match("register read xmm0", 360 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 361 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 362 self.match("register read xmm1", 363 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 364 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 365 366 # test writing into pseudo-registers 367 self.runCmd("register write cx 0xfbfa") 368 self.match("register read ecx", 369 ["ecx = 0x1413fbfa"]) 370 371 self.runCmd("register write ch 0xf9") 372 self.match("register read cx", 373 ["cx = 0xf9fa"]) 374 self.match("register read ecx", 375 ["ecx = 0x1413f9fa"]) 376 377 self.runCmd("register write cl 0xf8") 378 self.match("register read cx", 379 ["cx = 0xf9f8"]) 380 self.match("register read ecx", 381 ["ecx = 0x1413f9f8"]) 382 383 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 384 self.match("register read st0", 385 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 386 387 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 388 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 389 self.match("register read ymm0", 390 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 391 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 392 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 393 394 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 395 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 396 self.match("register read ymm0", 397 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 398 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 399 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 400 401 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 402 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 403 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 404 "0xed 0xee 0xef}\"") 405 self.match("register read ymm0", 406 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 407 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 408 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 409 410 @skipIfXmlSupportMissing 411 @skipIfRemote 412 @skipIfLLVMTargetMissing("AArch64") 413 def test_aarch64_regs(self): 414 """Test grabbing various aarch64 registers from gdbserver.""" 415 class MyResponder(MockGDBServerResponder): 416 reg_data = ( 417 "0102030405060708" # x0 418 "1112131415161718" # x1 419 ) + 27 * ( 420 "2122232425262728" # x2..x28 421 ) + ( 422 "3132333435363738" # x29 (fp) 423 "4142434445464748" # x30 (lr) 424 "5152535455565758" # x31 (sp) 425 "6162636465666768" # pc 426 "71727374" # cpsr 427 "8182838485868788898a8b8c8d8e8f90" # v0 428 "9192939495969798999a9b9c9d9e9fa0" # v1 429 ) + 30 * ( 430 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 431 ) + ( 432 "00000000" # fpsr 433 "00000000" # fpcr 434 ) 435 436 def qXferRead(self, obj, annex, offset, length): 437 if annex == "target.xml": 438 return """<?xml version="1.0"?> 439 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 440 <target> 441 <architecture>aarch64</architecture> 442 <feature name="org.gnu.gdb.aarch64.core"> 443 <reg name="x0" bitsize="64" type="int" regnum="0"/> 444 <reg name="x1" bitsize="64" type="int" regnum="1"/> 445 <reg name="x2" bitsize="64" type="int" regnum="2"/> 446 <reg name="x3" bitsize="64" type="int" regnum="3"/> 447 <reg name="x4" bitsize="64" type="int" regnum="4"/> 448 <reg name="x5" bitsize="64" type="int" regnum="5"/> 449 <reg name="x6" bitsize="64" type="int" regnum="6"/> 450 <reg name="x7" bitsize="64" type="int" regnum="7"/> 451 <reg name="x8" bitsize="64" type="int" regnum="8"/> 452 <reg name="x9" bitsize="64" type="int" regnum="9"/> 453 <reg name="x10" bitsize="64" type="int" regnum="10"/> 454 <reg name="x11" bitsize="64" type="int" regnum="11"/> 455 <reg name="x12" bitsize="64" type="int" regnum="12"/> 456 <reg name="x13" bitsize="64" type="int" regnum="13"/> 457 <reg name="x14" bitsize="64" type="int" regnum="14"/> 458 <reg name="x15" bitsize="64" type="int" regnum="15"/> 459 <reg name="x16" bitsize="64" type="int" regnum="16"/> 460 <reg name="x17" bitsize="64" type="int" regnum="17"/> 461 <reg name="x18" bitsize="64" type="int" regnum="18"/> 462 <reg name="x19" bitsize="64" type="int" regnum="19"/> 463 <reg name="x20" bitsize="64" type="int" regnum="20"/> 464 <reg name="x21" bitsize="64" type="int" regnum="21"/> 465 <reg name="x22" bitsize="64" type="int" regnum="22"/> 466 <reg name="x23" bitsize="64" type="int" regnum="23"/> 467 <reg name="x24" bitsize="64" type="int" regnum="24"/> 468 <reg name="x25" bitsize="64" type="int" regnum="25"/> 469 <reg name="x26" bitsize="64" type="int" regnum="26"/> 470 <reg name="x27" bitsize="64" type="int" regnum="27"/> 471 <reg name="x28" bitsize="64" type="int" regnum="28"/> 472 <reg name="x29" bitsize="64" type="int" regnum="29"/> 473 <reg name="x30" bitsize="64" type="int" regnum="30"/> 474 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 475 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 476 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 477 </feature> 478 <feature name="org.gnu.gdb.aarch64.fpu"> 479 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 480 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 481 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 482 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 483 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 484 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 485 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 486 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 487 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 488 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 489 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 490 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 491 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 492 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 493 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 494 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 495 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 496 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 497 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 498 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 499 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 500 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 501 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 502 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 503 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 504 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 505 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 506 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 507 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 508 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 509 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 510 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 511 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 512 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 513 </feature> 514 </target>""", False 515 else: 516 return None, False 517 518 def readRegister(self, regnum): 519 return "" 520 521 def readRegisters(self): 522 return self.reg_data 523 524 def writeRegisters(self, reg_hex): 525 self.reg_data = reg_hex 526 return "OK" 527 528 def haltReason(self): 529 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 530 531 self.server.responder = MyResponder() 532 533 target = self.createTarget("basic_eh_frame-aarch64.yaml") 534 process = self.connect(target) 535 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 536 [lldb.eStateStopped]) 537 538 # test GPRs 539 self.match("register read x0", 540 ["x0 = 0x0807060504030201"]) 541 self.match("register read x1", 542 ["x1 = 0x1817161514131211"]) 543 self.match("register read x29", 544 ["x29 = 0x3837363534333231"]) 545 self.match("register read x30", 546 ["x30 = 0x4847464544434241"]) 547 self.match("register read x31", 548 ["sp = 0x5857565554535251"]) 549 self.match("register read sp", 550 ["sp = 0x5857565554535251"]) 551 self.match("register read pc", 552 ["pc = 0x6867666564636261"]) 553 self.match("register read cpsr", 554 ["cpsr = 0x74737271"]) 555 556 # test generic aliases 557 self.match("register read arg1", 558 ["x0 = 0x0807060504030201"]) 559 self.match("register read arg2", 560 ["x1 = 0x1817161514131211"]) 561 self.match("register read fp", 562 ["x29 = 0x3837363534333231"]) 563 self.match("register read lr", 564 ["x30 = 0x4847464544434241"]) 565 self.match("register read ra", 566 ["x30 = 0x4847464544434241"]) 567 self.match("register read flags", 568 ["cpsr = 0x74737271"]) 569 570 # test vector registers 571 self.match("register read v0", 572 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 573 self.match("register read v31", 574 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 575 576 # test partial registers 577 self.match("register read w0", 578 ["w0 = 0x04030201"]) 579 self.runCmd("register write w0 0xfffefdfc") 580 self.match("register read x0", 581 ["x0 = 0x08070605fffefdfc"]) 582 583 self.match("register read w1", 584 ["w1 = 0x14131211"]) 585 self.runCmd("register write w1 0xefeeedec") 586 self.match("register read x1", 587 ["x1 = 0x18171615efeeedec"]) 588 589 self.match("register read w30", 590 ["w30 = 0x44434241"]) 591 self.runCmd("register write w30 0xdfdedddc") 592 self.match("register read x30", 593 ["x30 = 0x48474645dfdedddc"]) 594 595 self.match("register read w31", 596 ["w31 = 0x54535251"]) 597 self.runCmd("register write w31 0xcfcecdcc") 598 self.match("register read x31", 599 ["sp = 0x58575655cfcecdcc"]) 600 601 # test FPU registers (overlapping with vector registers) 602 self.runCmd("register write d0 16") 603 self.match("register read v0", 604 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 605 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 606 self.match("register read d31", 607 ["d31 = 64"]) 608 609 self.runCmd("register write s0 32") 610 self.match("register read v0", 611 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 612 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 613 self.match("register read s31", 614 ["s31 = 128"]) 615 616 @skipIfXmlSupportMissing 617 @skipIfRemote 618 @skipIfLLVMTargetMissing("X86") 619 def test_x86_64_no_duplicate_subregs(self): 620 """Test that duplicate subregisters are not added (on x86_64).""" 621 class MyResponder(MockGDBServerResponder): 622 reg_data = ( 623 "0102030405060708" # rcx 624 "1112131415161718" # rdx 625 "2122232425262728" # rsi 626 "3132333435363738" # rdi 627 "4142434445464748" # rbp 628 "5152535455565758" # rsp 629 "6162636465666768" # r8 630 "7172737475767778" # r9 631 "8182838485868788" # rip 632 "91929394" # eflags 633 ) 634 635 def qXferRead(self, obj, annex, offset, length): 636 if annex == "target.xml": 637 return """<?xml version="1.0"?> 638 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 639 <target> 640 <architecture>i386:x86-64</architecture> 641 <osabi>GNU/Linux</osabi> 642 <feature name="org.gnu.gdb.i386.core"> 643 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 644 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 645 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 646 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 647 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 648 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 649 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 650 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 651 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 652 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 653 <reg name="ecx" bitsize="32" type="int" regnum="18" value_regnums="2"/> 654 </feature> 655 </target>""", False 656 else: 657 return None, False 658 659 def readRegister(self, regnum): 660 return "" 661 662 def readRegisters(self): 663 return self.reg_data 664 665 def haltReason(self): 666 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 667 668 self.server.responder = MyResponder() 669 670 target = self.createTarget("basic_eh_frame.yaml") 671 process = self.connect(target) 672 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 673 [lldb.eStateStopped]) 674 675 self.match("register read rcx", 676 ["rcx = 0x0807060504030201"]) 677 # ecx is supplied via target.xml 678 self.match("register read ecx", 679 ["ecx = 0x04030201"]) 680 self.match("register read rdx", 681 ["rdx = 0x1817161514131211"]) 682 # edx should not be added 683 self.match("register read edx", 684 ["error: Invalid register name 'edx'."], 685 error=True) 686 687 @skipIfXmlSupportMissing 688 @skipIfRemote 689 @skipIfLLVMTargetMissing("X86") 690 def test_i386_no_duplicate_subregs(self): 691 """Test that duplicate subregisters are not added (on i386).""" 692 class MyResponder(MockGDBServerResponder): 693 reg_data = ( 694 "01020304" # eax 695 "11121314" # ecx 696 "21222324" # edx 697 "31323334" # ebx 698 "41424344" # esp 699 "51525354" # ebp 700 "61626364" # esi 701 "71727374" # edi 702 "81828384" # eip 703 "91929394" # eflags 704 ) 705 706 def qXferRead(self, obj, annex, offset, length): 707 if annex == "target.xml": 708 return """<?xml version="1.0"?> 709 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 710 <target> 711 <architecture>i386</architecture> 712 <osabi>GNU/Linux</osabi> 713 <feature name="org.gnu.gdb.i386.core"> 714 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 715 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 716 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 717 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 718 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 719 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 720 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 721 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 722 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 723 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 724 <reg name="ax" bitsize="16" type="int" regnum="10" value_regnums="0"/> 725 </feature> 726 </target>""", False 727 else: 728 return None, False 729 730 def readRegister(self, regnum): 731 return "" 732 733 def readRegisters(self): 734 return self.reg_data 735 736 def haltReason(self): 737 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 738 739 self.server.responder = MyResponder() 740 741 target = self.createTarget("basic_eh_frame-i386.yaml") 742 process = self.connect(target) 743 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 744 [lldb.eStateStopped]) 745 746 self.match("register read eax", 747 ["eax = 0x04030201"]) 748 # cx is supplied via target.xml 749 self.match("register read ax", 750 ["ax = 0x0201"]) 751 self.match("register read ecx", 752 ["ecx = 0x14131211"]) 753 # dx should not be added 754 self.match("register read cx", 755 ["error: Invalid register name 'cx'."], 756 error=True) 757 758 @skipIfXmlSupportMissing 759 @skipIfRemote 760 @skipIfLLVMTargetMissing("AArch64") 761 def test_aarch64_no_duplicate_subregs(self): 762 """Test that duplicate subregisters are not added.""" 763 class MyResponder(MockGDBServerResponder): 764 reg_data = ( 765 "0102030405060708" # x0 766 "1112131415161718" # x1 767 ) + 27 * ( 768 "2122232425262728" # x2..x28 769 ) + ( 770 "3132333435363738" # x29 (fp) 771 "4142434445464748" # x30 (lr) 772 "5152535455565758" # x31 (sp) 773 "6162636465666768" # pc 774 "71727374" # cpsr 775 ) 776 777 def qXferRead(self, obj, annex, offset, length): 778 if annex == "target.xml": 779 return """<?xml version="1.0"?> 780 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 781 <target> 782 <architecture>aarch64</architecture> 783 <feature name="org.gnu.gdb.aarch64.core"> 784 <reg name="x0" bitsize="64" type="int" regnum="0"/> 785 <reg name="x1" bitsize="64" type="int" regnum="1"/> 786 <reg name="x2" bitsize="64" type="int" regnum="2"/> 787 <reg name="x3" bitsize="64" type="int" regnum="3"/> 788 <reg name="x4" bitsize="64" type="int" regnum="4"/> 789 <reg name="x5" bitsize="64" type="int" regnum="5"/> 790 <reg name="x6" bitsize="64" type="int" regnum="6"/> 791 <reg name="x7" bitsize="64" type="int" regnum="7"/> 792 <reg name="x8" bitsize="64" type="int" regnum="8"/> 793 <reg name="x9" bitsize="64" type="int" regnum="9"/> 794 <reg name="x10" bitsize="64" type="int" regnum="10"/> 795 <reg name="x11" bitsize="64" type="int" regnum="11"/> 796 <reg name="x12" bitsize="64" type="int" regnum="12"/> 797 <reg name="x13" bitsize="64" type="int" regnum="13"/> 798 <reg name="x14" bitsize="64" type="int" regnum="14"/> 799 <reg name="x15" bitsize="64" type="int" regnum="15"/> 800 <reg name="x16" bitsize="64" type="int" regnum="16"/> 801 <reg name="x17" bitsize="64" type="int" regnum="17"/> 802 <reg name="x18" bitsize="64" type="int" regnum="18"/> 803 <reg name="x19" bitsize="64" type="int" regnum="19"/> 804 <reg name="x20" bitsize="64" type="int" regnum="20"/> 805 <reg name="x21" bitsize="64" type="int" regnum="21"/> 806 <reg name="x22" bitsize="64" type="int" regnum="22"/> 807 <reg name="x23" bitsize="64" type="int" regnum="23"/> 808 <reg name="x24" bitsize="64" type="int" regnum="24"/> 809 <reg name="x25" bitsize="64" type="int" regnum="25"/> 810 <reg name="x26" bitsize="64" type="int" regnum="26"/> 811 <reg name="x27" bitsize="64" type="int" regnum="27"/> 812 <reg name="x28" bitsize="64" type="int" regnum="28"/> 813 <reg name="x29" bitsize="64" type="int" regnum="29"/> 814 <reg name="x30" bitsize="64" type="int" regnum="30"/> 815 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 816 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 817 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 818 <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/> 819 </feature> 820 </target>""", False 821 else: 822 return None, False 823 824 def readRegister(self, regnum): 825 return "" 826 827 def readRegisters(self): 828 return self.reg_data 829 830 def haltReason(self): 831 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 832 833 self.server.responder = MyResponder() 834 835 target = self.createTarget("basic_eh_frame-aarch64.yaml") 836 process = self.connect(target) 837 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 838 [lldb.eStateStopped]) 839 840 self.match("register read x0", 841 ["x0 = 0x0807060504030201"]) 842 # w0 comes from target.xml 843 self.match("register read w0", 844 ["w0 = 0x04030201"]) 845 self.match("register read x1", 846 ["x1 = 0x1817161514131211"]) 847 # w1 should not be added 848 self.match("register read w1", 849 ["error: Invalid register name 'w1'."], 850 error=True) 851