1from __future__ import print_function
2import lldb
3from lldbsuite.test.lldbtest import *
4from lldbsuite.test.decorators import *
5from lldbsuite.test.gdbclientutils import *
6from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase
7
8class TestArmRegisterDefinition(GDBRemoteTestBase):
9
10    @skipIfXmlSupportMissing
11    @skipIfRemote
12    def test(self):
13        """
14        Test lldb's parsing of the <architecture> tag in the target.xml register
15        description packet.
16        """
17        class MyResponder(MockGDBServerResponder):
18
19            def qXferRead(self, obj, annex, offset, length):
20                if annex == "target.xml":
21                    return """<?xml version="1.0"?>
22                        <!DOCTYPE feature SYSTEM "gdb-target.dtd">
23                        <target>
24                        <architecture>arm</architecture>
25                        <feature name="org.gnu.gdb.arm.m-profile">
26                        <reg name="r0" bitsize="32" type="uint32" group="general"/>
27                        <reg name="r1" bitsize="32" type="uint32" group="general"/>
28                        <reg name="r2" bitsize="32" type="uint32" group="general"/>
29                        <reg name="r3" bitsize="32" type="uint32" group="general"/>
30                        <reg name="r4" bitsize="32" type="uint32" group="general"/>
31                        <reg name="r5" bitsize="32" type="uint32" group="general"/>
32                        <reg name="r6" bitsize="32" type="uint32" group="general"/>
33                        <reg name="r7" bitsize="32" type="uint32" group="general"/>
34                        <reg name="r8" bitsize="32" type="uint32" group="general"/>
35                        <reg name="r9" bitsize="32" type="uint32" group="general"/>
36                        <reg name="r10" bitsize="32" type="uint32" group="general"/>
37                        <reg name="r11" bitsize="32" type="uint32" group="general"/>
38                        <reg name="r12" bitsize="32" type="uint32" group="general"/>
39                        <reg name="sp" bitsize="32" type="data_ptr" group="general"/>
40                        <reg name="lr" bitsize="32" type="uint32" group="general"/>
41                        <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
42                        <reg name="SYS0" bitsize="9" regnum="21" type="uint32" group="system"/>
43                        <reg name="SYS1" bitsize="8" regnum="22" type="uint32" group="system"/>
44                        <reg name="SYS2" bitsize="1" regnum="23" type="uint32" group="system"/>
45                        <reg name="SYS3" bitsize="7" regnum="24" type="uint32" group="system"/>
46                        <reg name="xpsr" bitsize="32" regnum="25" type="uint32" group="general"/>
47                        <reg name="MSP" bitsize="32" regnum="26" type="uint32" group="general"/>
48                        <reg name="PSP" bitsize="32" regnum="27" type="uint32" group="general"/>
49                        <reg name="PRIMASK" bitsize="32" regnum="28" type="uint32" group="general"/>
50                        <reg name="BASEPRI" bitsize="32" regnum="29" type="uint32" group="general"/>
51                        <reg name="FAULTMASK" bitsize="32" regnum="30" type="uint32" group="general"/>
52                        <reg name="CONTROL" bitsize="32" regnum="31" type="uint32" group="general"/>
53                        <reg name="FPSCR" bitsize="32" type="uint32" group="float"/>
54                        <reg name="s0" bitsize="32" type="float" group="float"/>
55                        <reg name="s1" bitsize="32" type="float" group="float"/>
56                        <reg name="s2" bitsize="32" type="float" group="float"/>
57                        <reg name="s3" bitsize="32" type="float" group="float"/>
58                        <reg name="s4" bitsize="32" type="float" group="float"/>
59                        <reg name="s5" bitsize="32" type="float" group="float"/>
60                        <reg name="s6" bitsize="32" type="float" group="float"/>
61                        <reg name="s7" bitsize="32" type="float" group="float"/>
62                        <reg name="s8" bitsize="32" type="float" group="float"/>
63                        <reg name="s9" bitsize="32" type="float" group="float"/>
64                        <reg name="s10" bitsize="32" type="float" group="float"/>
65                        <reg name="s11" bitsize="32" type="float" group="float"/>
66                        <reg name="s12" bitsize="32" type="float" group="float"/>
67                        <reg name="s13" bitsize="32" type="float" group="float"/>
68                        <reg name="s14" bitsize="32" type="float" group="float"/>
69                        <reg name="s15" bitsize="32" type="float" group="float"/>
70                        <reg name="s16" bitsize="32" type="float" group="float"/>
71                        <reg name="s17" bitsize="32" type="float" group="float"/>
72                        <reg name="s18" bitsize="32" type="float" group="float"/>
73                        <reg name="s19" bitsize="32" type="float" group="float"/>
74                        <reg name="s20" bitsize="32" type="float" group="float"/>
75                        <reg name="s21" bitsize="32" type="float" group="float"/>
76                        <reg name="s22" bitsize="32" type="float" group="float"/>
77                        <reg name="s23" bitsize="32" type="float" group="float"/>
78                        <reg name="s24" bitsize="32" type="float" group="float"/>
79                        <reg name="s25" bitsize="32" type="float" group="float"/>
80                        <reg name="s26" bitsize="32" type="float" group="float"/>
81                        <reg name="s27" bitsize="32" type="float" group="float"/>
82                        <reg name="s28" bitsize="32" type="float" group="float"/>
83                        <reg name="s29" bitsize="32" type="float" group="float"/>
84                        <reg name="s30" bitsize="32" type="float" group="float"/>
85                        <reg name="s31" bitsize="32" type="float" group="float"/>
86                        </feature>
87                        </target>""", False
88                else:
89                    return None, False
90
91            def readRegister(self, regnum):
92                return "E01"
93
94            def readRegisters(self):
95                return "20000000f8360020001000002fcb0008f8360020a0360020200c0020000000000000000000000000000000000000000000000000b87f0120b7d100082ed20008addebeafbc00000001b87f01200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
96
97            def haltReason(self):
98                return "S05"
99
100            def qfThreadInfo(self):
101                return "mdead"
102
103            def qC(self):
104                return ""
105
106            def qSupported(self, client_supported):
107                return "PacketSize=4000;qXfer:memory-map:read-;QStartNoAckMode+;qXfer:threads:read+;hwbreak+;qXfer:features:read+"
108
109            def QThreadSuffixSupported(self):
110                return "OK"
111
112            def QListThreadsInStopReply(self):
113                return "OK"
114
115        self.server.responder = MyResponder()
116        if self.TraceOn():
117            self.runCmd("log enable gdb-remote packets")
118            self.addTearDownHook(
119                    lambda: self.runCmd("log disable gdb-remote packets"))
120
121        self.dbg.SetDefaultArchitecture("armv7em")
122        target = self.dbg.CreateTargetWithFileAndArch(None, None)
123
124        process = self.connect(target)
125
126        if self.TraceOn():
127            interp = self.dbg.GetCommandInterpreter()
128            result = lldb.SBCommandReturnObject()
129            interp.HandleCommand("target list", result)
130            print(result.GetOutput())
131
132        r0_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("r0")
133        self.assertEqual(r0_valobj.GetValueAsUnsigned(), 0x20)
134
135        pc_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("pc")
136        self.assertEqual(pc_valobj.GetValueAsUnsigned(), 0x0800d22e)
137
138        sys_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("SYS0")
139        self.assertEqual(sys_valobj.GetValueAsUnsigned(), 0xdead)
140
141        sys_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("SYS1")
142        self.assertEqual(sys_valobj.GetValueAsUnsigned(), 0xbe)
143
144        sys_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("SYS2")
145        self.assertEqual(sys_valobj.GetValueAsUnsigned(), 0xaf)
146
147        sys_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("SYS3")
148        self.assertEqual(sys_valobj.GetValueAsUnsigned(), 0xbc)
149