1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_generic, "hexagon"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 214 215 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 217 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 219 }; 220 221 // Ensure that we have an entry in the g_core_definitions for each core. If you 222 // comment out an entry above, you will need to comment out the corresponding 223 // ArchSpec::Core enumeration. 224 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 225 ArchSpec::kNumCores, 226 "make sure we have one core definition for each core"); 227 228 struct ArchDefinitionEntry { 229 ArchSpec::Core core; 230 uint32_t cpu; 231 uint32_t sub; 232 uint32_t cpu_mask; 233 uint32_t sub_mask; 234 }; 235 236 struct ArchDefinition { 237 ArchitectureType type; 238 size_t num_entries; 239 const ArchDefinitionEntry *entries; 240 const char *name; 241 }; 242 243 void ArchSpec::ListSupportedArchNames(StringList &list) { 244 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 245 list.AppendString(g_core_definitions[i].name); 246 } 247 248 void ArchSpec::AutoComplete(CompletionRequest &request) { 249 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 250 request.TryCompleteCurrentArg(g_core_definitions[i].name); 251 } 252 253 #define CPU_ANY (UINT32_MAX) 254 255 //===----------------------------------------------------------------------===// 256 // A table that gets searched linearly for matches. This table is used to 257 // convert cpu type and subtypes to architecture names, and to convert 258 // architecture names to cpu types and subtypes. The ordering is important and 259 // allows the precedence to be set when the table is built. 260 #define SUBTYPE_MASK 0x00FFFFFFu 261 262 static const ArchDefinitionEntry g_macho_arch_entries[] = { 263 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 264 UINT32_MAX, UINT32_MAX}, 265 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 266 SUBTYPE_MASK}, 267 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 268 SUBTYPE_MASK}, 269 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 270 SUBTYPE_MASK}, 271 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 272 SUBTYPE_MASK}, 273 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 302 UINT32_MAX, SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 304 UINT32_MAX, SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 306 UINT32_MAX, SUBTYPE_MASK}, 307 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 308 SUBTYPE_MASK}, 309 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 310 SUBTYPE_MASK}, 311 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 312 SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 314 SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 332 UINT32_MAX, UINT32_MAX}, 333 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 336 SUBTYPE_MASK}, 337 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 340 SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 360 UINT32_MAX, SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 362 UINT32_MAX, SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 364 UINT32_MAX, SUBTYPE_MASK}, 365 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 366 SUBTYPE_MASK}, 367 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 368 SUBTYPE_MASK}, 369 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 370 UINT32_MAX, SUBTYPE_MASK}, 371 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 372 UINT32_MAX, UINT32_MAX}, 373 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 374 SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 376 SUBTYPE_MASK}, 377 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 378 UINT32_MAX, SUBTYPE_MASK}, 379 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 380 UINT32_MAX, UINT32_MAX}, 381 // Catch any unknown mach architectures so we can always use the object and 382 // symbol mach-o files 383 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 384 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 385 0x00000000u}}; 386 387 static const ArchDefinition g_macho_arch_def = { 388 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 389 g_macho_arch_entries, "mach-o"}; 390 391 //===----------------------------------------------------------------------===// 392 // A table that gets searched linearly for matches. This table is used to 393 // convert cpu type and subtypes to architecture names, and to convert 394 // architecture names to cpu types and subtypes. The ordering is important and 395 // allows the precedence to be set when the table is built. 396 static const ArchDefinitionEntry g_elf_arch_entries[] = { 397 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 398 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 399 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 400 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 401 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 402 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 403 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 404 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 405 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 407 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 409 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 411 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 413 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 415 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 416 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 417 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 419 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 420 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 421 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 422 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 423 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 424 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 425 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 426 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 427 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 428 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 429 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 431 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 432 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 433 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 435 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 436 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 437 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 438 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 439 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 440 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 441 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 442 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 443 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 444 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 445 }; 446 447 static const ArchDefinition g_elf_arch_def = { 448 eArchTypeELF, 449 llvm::array_lengthof(g_elf_arch_entries), 450 g_elf_arch_entries, 451 "elf", 452 }; 453 454 static const ArchDefinitionEntry g_coff_arch_entries[] = { 455 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 456 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 457 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 458 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 459 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 460 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 461 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 462 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 463 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 464 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 465 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 466 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 467 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 468 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 469 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 470 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 471 }; 472 473 static const ArchDefinition g_coff_arch_def = { 474 eArchTypeCOFF, 475 llvm::array_lengthof(g_coff_arch_entries), 476 g_coff_arch_entries, 477 "pe-coff", 478 }; 479 480 //===----------------------------------------------------------------------===// 481 // Table of all ArchDefinitions 482 static const ArchDefinition *g_arch_definitions[] = { 483 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 484 485 static const size_t k_num_arch_definitions = 486 llvm::array_lengthof(g_arch_definitions); 487 488 //===----------------------------------------------------------------------===// 489 // Static helper functions. 490 491 // Get the architecture definition for a given object type. 492 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 493 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 494 const ArchDefinition *def = g_arch_definitions[i]; 495 if (def->type == arch_type) 496 return def; 497 } 498 return nullptr; 499 } 500 501 // Get an architecture definition by name. 502 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 503 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 504 if (name.equals_lower(g_core_definitions[i].name)) 505 return &g_core_definitions[i]; 506 } 507 return nullptr; 508 } 509 510 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 511 if (core < llvm::array_lengthof(g_core_definitions)) 512 return &g_core_definitions[core]; 513 return nullptr; 514 } 515 516 // Get a definition entry by cpu type and subtype. 517 static const ArchDefinitionEntry * 518 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 519 if (def == nullptr) 520 return nullptr; 521 522 const ArchDefinitionEntry *entries = def->entries; 523 for (size_t i = 0; i < def->num_entries; ++i) { 524 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 525 if (entries[i].sub == (sub & entries[i].sub_mask)) 526 return &entries[i]; 527 } 528 return nullptr; 529 } 530 531 static const ArchDefinitionEntry * 532 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 533 if (def == nullptr) 534 return nullptr; 535 536 const ArchDefinitionEntry *entries = def->entries; 537 for (size_t i = 0; i < def->num_entries; ++i) { 538 if (entries[i].core == core) 539 return &entries[i]; 540 } 541 return nullptr; 542 } 543 544 //===----------------------------------------------------------------------===// 545 // Constructors and destructors. 546 547 ArchSpec::ArchSpec() {} 548 549 ArchSpec::ArchSpec(const char *triple_cstr) { 550 if (triple_cstr) 551 SetTriple(triple_cstr); 552 } 553 554 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 555 556 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 557 558 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 559 SetArchitecture(arch_type, cpu, subtype); 560 } 561 562 ArchSpec::~ArchSpec() = default; 563 564 //===----------------------------------------------------------------------===// 565 // Assignment and initialization. 566 567 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 568 if (this != &rhs) { 569 m_triple = rhs.m_triple; 570 m_core = rhs.m_core; 571 m_byte_order = rhs.m_byte_order; 572 m_distribution_id = rhs.m_distribution_id; 573 m_flags = rhs.m_flags; 574 } 575 return *this; 576 } 577 578 void ArchSpec::Clear() { 579 m_triple = llvm::Triple(); 580 m_core = kCore_invalid; 581 m_byte_order = eByteOrderInvalid; 582 m_distribution_id.Clear(); 583 m_flags = 0; 584 } 585 586 //===----------------------------------------------------------------------===// 587 // Predicates. 588 589 const char *ArchSpec::GetArchitectureName() const { 590 const CoreDefinition *core_def = FindCoreDefinition(m_core); 591 if (core_def) 592 return core_def->name; 593 return "unknown"; 594 } 595 596 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 597 598 std::string ArchSpec::GetTargetABI() const { 599 600 std::string abi; 601 602 if (IsMIPS()) { 603 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 604 case ArchSpec::eMIPSABI_N64: 605 abi = "n64"; 606 return abi; 607 case ArchSpec::eMIPSABI_N32: 608 abi = "n32"; 609 return abi; 610 case ArchSpec::eMIPSABI_O32: 611 abi = "o32"; 612 return abi; 613 default: 614 return abi; 615 } 616 } 617 return abi; 618 } 619 620 void ArchSpec::SetFlags(std::string elf_abi) { 621 622 uint32_t flag = GetFlags(); 623 if (IsMIPS()) { 624 if (elf_abi == "n64") 625 flag |= ArchSpec::eMIPSABI_N64; 626 else if (elf_abi == "n32") 627 flag |= ArchSpec::eMIPSABI_N32; 628 else if (elf_abi == "o32") 629 flag |= ArchSpec::eMIPSABI_O32; 630 } 631 SetFlags(flag); 632 } 633 634 std::string ArchSpec::GetClangTargetCPU() const { 635 std::string cpu; 636 637 if (IsMIPS()) { 638 switch (m_core) { 639 case ArchSpec::eCore_mips32: 640 case ArchSpec::eCore_mips32el: 641 cpu = "mips32"; 642 break; 643 case ArchSpec::eCore_mips32r2: 644 case ArchSpec::eCore_mips32r2el: 645 cpu = "mips32r2"; 646 break; 647 case ArchSpec::eCore_mips32r3: 648 case ArchSpec::eCore_mips32r3el: 649 cpu = "mips32r3"; 650 break; 651 case ArchSpec::eCore_mips32r5: 652 case ArchSpec::eCore_mips32r5el: 653 cpu = "mips32r5"; 654 break; 655 case ArchSpec::eCore_mips32r6: 656 case ArchSpec::eCore_mips32r6el: 657 cpu = "mips32r6"; 658 break; 659 case ArchSpec::eCore_mips64: 660 case ArchSpec::eCore_mips64el: 661 cpu = "mips64"; 662 break; 663 case ArchSpec::eCore_mips64r2: 664 case ArchSpec::eCore_mips64r2el: 665 cpu = "mips64r2"; 666 break; 667 case ArchSpec::eCore_mips64r3: 668 case ArchSpec::eCore_mips64r3el: 669 cpu = "mips64r3"; 670 break; 671 case ArchSpec::eCore_mips64r5: 672 case ArchSpec::eCore_mips64r5el: 673 cpu = "mips64r5"; 674 break; 675 case ArchSpec::eCore_mips64r6: 676 case ArchSpec::eCore_mips64r6el: 677 cpu = "mips64r6"; 678 break; 679 default: 680 break; 681 } 682 } 683 return cpu; 684 } 685 686 uint32_t ArchSpec::GetMachOCPUType() const { 687 const CoreDefinition *core_def = FindCoreDefinition(m_core); 688 if (core_def) { 689 const ArchDefinitionEntry *arch_def = 690 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 691 if (arch_def) { 692 return arch_def->cpu; 693 } 694 } 695 return LLDB_INVALID_CPUTYPE; 696 } 697 698 uint32_t ArchSpec::GetMachOCPUSubType() const { 699 const CoreDefinition *core_def = FindCoreDefinition(m_core); 700 if (core_def) { 701 const ArchDefinitionEntry *arch_def = 702 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 703 if (arch_def) { 704 return arch_def->sub; 705 } 706 } 707 return LLDB_INVALID_CPUTYPE; 708 } 709 710 uint32_t ArchSpec::GetDataByteSize() const { 711 return 1; 712 } 713 714 uint32_t ArchSpec::GetCodeByteSize() const { 715 return 1; 716 } 717 718 llvm::Triple::ArchType ArchSpec::GetMachine() const { 719 const CoreDefinition *core_def = FindCoreDefinition(m_core); 720 if (core_def) 721 return core_def->machine; 722 723 return llvm::Triple::UnknownArch; 724 } 725 726 ConstString ArchSpec::GetDistributionId() const { 727 return m_distribution_id; 728 } 729 730 void ArchSpec::SetDistributionId(const char *distribution_id) { 731 m_distribution_id.SetCString(distribution_id); 732 } 733 734 uint32_t ArchSpec::GetAddressByteSize() const { 735 const CoreDefinition *core_def = FindCoreDefinition(m_core); 736 if (core_def) { 737 if (core_def->machine == llvm::Triple::mips64 || 738 core_def->machine == llvm::Triple::mips64el) { 739 // For N32/O32 applications Address size is 4 bytes. 740 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 741 return 4; 742 } 743 return core_def->addr_byte_size; 744 } 745 return 0; 746 } 747 748 ByteOrder ArchSpec::GetDefaultEndian() const { 749 const CoreDefinition *core_def = FindCoreDefinition(m_core); 750 if (core_def) 751 return core_def->default_byte_order; 752 return eByteOrderInvalid; 753 } 754 755 bool ArchSpec::CharIsSignedByDefault() const { 756 switch (m_triple.getArch()) { 757 default: 758 return true; 759 760 case llvm::Triple::aarch64: 761 case llvm::Triple::aarch64_32: 762 case llvm::Triple::aarch64_be: 763 case llvm::Triple::arm: 764 case llvm::Triple::armeb: 765 case llvm::Triple::thumb: 766 case llvm::Triple::thumbeb: 767 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 768 769 case llvm::Triple::ppc: 770 case llvm::Triple::ppc64: 771 return m_triple.isOSDarwin(); 772 773 case llvm::Triple::ppc64le: 774 case llvm::Triple::systemz: 775 case llvm::Triple::xcore: 776 case llvm::Triple::arc: 777 return false; 778 } 779 } 780 781 lldb::ByteOrder ArchSpec::GetByteOrder() const { 782 if (m_byte_order == eByteOrderInvalid) 783 return GetDefaultEndian(); 784 return m_byte_order; 785 } 786 787 //===----------------------------------------------------------------------===// 788 // Mutators. 789 790 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 791 m_triple = triple; 792 UpdateCore(); 793 return IsValid(); 794 } 795 796 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 797 ArchSpec &arch) { 798 // Accept "12-10" or "12.10" as cpu type/subtype 799 if (triple_str.empty()) 800 return false; 801 802 size_t pos = triple_str.find_first_of("-."); 803 if (pos == llvm::StringRef::npos) 804 return false; 805 806 llvm::StringRef cpu_str = triple_str.substr(0, pos); 807 llvm::StringRef remainder = triple_str.substr(pos + 1); 808 if (cpu_str.empty() || remainder.empty()) 809 return false; 810 811 llvm::StringRef sub_str; 812 llvm::StringRef vendor; 813 llvm::StringRef os; 814 std::tie(sub_str, remainder) = remainder.split('-'); 815 std::tie(vendor, os) = remainder.split('-'); 816 817 uint32_t cpu = 0; 818 uint32_t sub = 0; 819 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 820 return false; 821 822 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 823 return false; 824 if (!vendor.empty() && !os.empty()) { 825 arch.GetTriple().setVendorName(vendor); 826 arch.GetTriple().setOSName(os); 827 } 828 829 return true; 830 } 831 832 bool ArchSpec::SetTriple(llvm::StringRef triple) { 833 if (triple.empty()) { 834 Clear(); 835 return false; 836 } 837 838 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 839 return true; 840 841 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 842 return IsValid(); 843 } 844 845 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 846 return !normalized_triple.getArchName().empty() && 847 normalized_triple.getOSName().empty() && 848 normalized_triple.getVendorName().empty() && 849 normalized_triple.getEnvironmentName().empty(); 850 } 851 852 void ArchSpec::MergeFrom(const ArchSpec &other) { 853 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 854 GetTriple().setVendor(other.GetTriple().getVendor()); 855 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 856 GetTriple().setOS(other.GetTriple().getOS()); 857 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 858 GetTriple().setArch(other.GetTriple().getArch()); 859 860 // MachO unknown64 isn't really invalid as the debugger can still obtain 861 // information from the binary, e.g. line tables. As such, we don't update 862 // the core here. 863 if (other.GetCore() != eCore_uknownMach64) 864 UpdateCore(); 865 } 866 if (!TripleEnvironmentWasSpecified() && 867 other.TripleEnvironmentWasSpecified()) { 868 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 869 } 870 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 871 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 872 // adopt the specific arm core. 873 if (GetTriple().getArch() == llvm::Triple::arm && 874 other.GetTriple().getArch() == llvm::Triple::arm && 875 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 876 other.GetCore() != ArchSpec::eCore_arm_generic) { 877 m_core = other.GetCore(); 878 CoreUpdated(true); 879 } 880 if (GetFlags() == 0) { 881 SetFlags(other.GetFlags()); 882 } 883 } 884 885 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 886 uint32_t sub, uint32_t os) { 887 m_core = kCore_invalid; 888 bool update_triple = true; 889 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 890 if (arch_def) { 891 const ArchDefinitionEntry *arch_def_entry = 892 FindArchDefinitionEntry(arch_def, cpu, sub); 893 if (arch_def_entry) { 894 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 895 if (core_def) { 896 m_core = core_def->core; 897 update_triple = false; 898 // Always use the architecture name because it might be more 899 // descriptive than the architecture enum ("armv7" -> 900 // llvm::Triple::arm). 901 m_triple.setArchName(llvm::StringRef(core_def->name)); 902 if (arch_type == eArchTypeMachO) { 903 m_triple.setVendor(llvm::Triple::Apple); 904 905 // Don't set the OS. It could be simulator, macosx, ios, watchos, 906 // tvos, bridgeos. We could get close with the cpu type - but we 907 // can't get it right all of the time. Better to leave this unset 908 // so other sections of code will set it when they have more 909 // information. NB: don't call m_triple.setOS 910 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 911 // the ArchSpec::TripleVendorWasSpecified() method says that any 912 // OSName setting means it was specified. 913 } else if (arch_type == eArchTypeELF) { 914 switch (os) { 915 case llvm::ELF::ELFOSABI_AIX: 916 m_triple.setOS(llvm::Triple::OSType::AIX); 917 break; 918 case llvm::ELF::ELFOSABI_FREEBSD: 919 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 920 break; 921 case llvm::ELF::ELFOSABI_GNU: 922 m_triple.setOS(llvm::Triple::OSType::Linux); 923 break; 924 case llvm::ELF::ELFOSABI_NETBSD: 925 m_triple.setOS(llvm::Triple::OSType::NetBSD); 926 break; 927 case llvm::ELF::ELFOSABI_OPENBSD: 928 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 929 break; 930 case llvm::ELF::ELFOSABI_SOLARIS: 931 m_triple.setOS(llvm::Triple::OSType::Solaris); 932 break; 933 } 934 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 935 m_triple.setVendor(llvm::Triple::PC); 936 m_triple.setOS(llvm::Triple::Win32); 937 } else { 938 m_triple.setVendor(llvm::Triple::UnknownVendor); 939 m_triple.setOS(llvm::Triple::UnknownOS); 940 } 941 // Fall back onto setting the machine type if the arch by name 942 // failed... 943 if (m_triple.getArch() == llvm::Triple::UnknownArch) 944 m_triple.setArch(core_def->machine); 945 } 946 } else { 947 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 948 LLDB_LOGF(log, 949 "Unable to find a core definition for cpu 0x%" PRIx32 950 " sub %" PRId32, 951 cpu, sub); 952 } 953 } 954 CoreUpdated(update_triple); 955 return IsValid(); 956 } 957 958 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 959 const CoreDefinition *core_def = FindCoreDefinition(m_core); 960 if (core_def) 961 return core_def->min_opcode_byte_size; 962 return 0; 963 } 964 965 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 966 const CoreDefinition *core_def = FindCoreDefinition(m_core); 967 if (core_def) 968 return core_def->max_opcode_byte_size; 969 return 0; 970 } 971 972 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 973 return IsEqualTo(rhs, true); 974 } 975 976 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 977 return IsEqualTo(rhs, false); 978 } 979 980 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 981 llvm::Triple::EnvironmentType rhs) { 982 if (lhs == rhs) 983 return true; 984 985 // If any of the environment is unknown then they are compatible 986 if (lhs == llvm::Triple::UnknownEnvironment || 987 rhs == llvm::Triple::UnknownEnvironment) 988 return true; 989 990 // If one of the environment is Android and the other one is EABI then they 991 // are considered to be compatible. This is required as a workaround for 992 // shared libraries compiled for Android without the NOTE section indicating 993 // that they are using the Android ABI. 994 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 995 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 996 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 997 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 998 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 999 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1000 return true; 1001 1002 return false; 1003 } 1004 1005 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1006 // explicitly ignoring m_distribution_id in this method. 1007 1008 if (GetByteOrder() != rhs.GetByteOrder()) 1009 return false; 1010 1011 const ArchSpec::Core lhs_core = GetCore(); 1012 const ArchSpec::Core rhs_core = rhs.GetCore(); 1013 1014 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1015 1016 if (core_match) { 1017 const llvm::Triple &lhs_triple = GetTriple(); 1018 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1019 1020 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1021 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1022 if (lhs_triple_vendor != rhs_triple_vendor) { 1023 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1024 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1025 // Both architectures had the vendor specified, so if they aren't equal 1026 // then we return false 1027 if (rhs_vendor_specified && lhs_vendor_specified) 1028 return false; 1029 1030 // Only fail if both vendor types are not unknown 1031 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1032 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1033 return false; 1034 } 1035 1036 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1037 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1038 if (lhs_triple_os != rhs_triple_os) { 1039 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1040 const bool lhs_os_specified = TripleOSWasSpecified(); 1041 // Both architectures had the OS specified, so if they aren't equal then 1042 // we return false 1043 if (rhs_os_specified && lhs_os_specified) 1044 return false; 1045 1046 // Only fail if both os types are not unknown 1047 if (lhs_triple_os != llvm::Triple::UnknownOS && 1048 rhs_triple_os != llvm::Triple::UnknownOS) 1049 return false; 1050 } 1051 1052 const llvm::Triple::EnvironmentType lhs_triple_env = 1053 lhs_triple.getEnvironment(); 1054 const llvm::Triple::EnvironmentType rhs_triple_env = 1055 rhs_triple.getEnvironment(); 1056 1057 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1058 } 1059 return false; 1060 } 1061 1062 void ArchSpec::UpdateCore() { 1063 llvm::StringRef arch_name(m_triple.getArchName()); 1064 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1065 if (core_def) { 1066 m_core = core_def->core; 1067 // Set the byte order to the default byte order for an architecture. This 1068 // can be modified if needed for cases when cores handle both big and 1069 // little endian 1070 m_byte_order = core_def->default_byte_order; 1071 } else { 1072 Clear(); 1073 } 1074 } 1075 1076 //===----------------------------------------------------------------------===// 1077 // Helper methods. 1078 1079 void ArchSpec::CoreUpdated(bool update_triple) { 1080 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1081 if (core_def) { 1082 if (update_triple) 1083 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1084 m_byte_order = core_def->default_byte_order; 1085 } else { 1086 if (update_triple) 1087 m_triple = llvm::Triple(); 1088 m_byte_order = eByteOrderInvalid; 1089 } 1090 } 1091 1092 //===----------------------------------------------------------------------===// 1093 // Operators. 1094 1095 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1096 bool try_inverse, bool enforce_exact_match) { 1097 if (core1 == core2) 1098 return true; 1099 1100 switch (core1) { 1101 case ArchSpec::kCore_any: 1102 return true; 1103 1104 case ArchSpec::eCore_arm_generic: 1105 if (enforce_exact_match) 1106 break; 1107 LLVM_FALLTHROUGH; 1108 case ArchSpec::kCore_arm_any: 1109 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1110 return true; 1111 if (core2 >= ArchSpec::kCore_thumb_first && 1112 core2 <= ArchSpec::kCore_thumb_last) 1113 return true; 1114 if (core2 == ArchSpec::kCore_arm_any) 1115 return true; 1116 break; 1117 1118 case ArchSpec::kCore_x86_32_any: 1119 if ((core2 >= ArchSpec::kCore_x86_32_first && 1120 core2 <= ArchSpec::kCore_x86_32_last) || 1121 (core2 == ArchSpec::kCore_x86_32_any)) 1122 return true; 1123 break; 1124 1125 case ArchSpec::kCore_x86_64_any: 1126 if ((core2 >= ArchSpec::kCore_x86_64_first && 1127 core2 <= ArchSpec::kCore_x86_64_last) || 1128 (core2 == ArchSpec::kCore_x86_64_any)) 1129 return true; 1130 break; 1131 1132 case ArchSpec::kCore_ppc_any: 1133 if ((core2 >= ArchSpec::kCore_ppc_first && 1134 core2 <= ArchSpec::kCore_ppc_last) || 1135 (core2 == ArchSpec::kCore_ppc_any)) 1136 return true; 1137 break; 1138 1139 case ArchSpec::kCore_ppc64_any: 1140 if ((core2 >= ArchSpec::kCore_ppc64_first && 1141 core2 <= ArchSpec::kCore_ppc64_last) || 1142 (core2 == ArchSpec::kCore_ppc64_any)) 1143 return true; 1144 break; 1145 1146 case ArchSpec::eCore_arm_armv6m: 1147 if (!enforce_exact_match) { 1148 if (core2 == ArchSpec::eCore_arm_generic) 1149 return true; 1150 try_inverse = false; 1151 if (core2 == ArchSpec::eCore_arm_armv7) 1152 return true; 1153 if (core2 == ArchSpec::eCore_arm_armv6m) 1154 return true; 1155 } 1156 break; 1157 1158 case ArchSpec::kCore_hexagon_any: 1159 if ((core2 >= ArchSpec::kCore_hexagon_first && 1160 core2 <= ArchSpec::kCore_hexagon_last) || 1161 (core2 == ArchSpec::kCore_hexagon_any)) 1162 return true; 1163 break; 1164 1165 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1166 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1167 // ARMv7E-M - armv7em 1168 case ArchSpec::eCore_arm_armv7em: 1169 if (!enforce_exact_match) { 1170 if (core2 == ArchSpec::eCore_arm_generic) 1171 return true; 1172 if (core2 == ArchSpec::eCore_arm_armv7m) 1173 return true; 1174 if (core2 == ArchSpec::eCore_arm_armv6m) 1175 return true; 1176 if (core2 == ArchSpec::eCore_arm_armv7) 1177 return true; 1178 try_inverse = true; 1179 } 1180 break; 1181 1182 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1183 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1184 // ARMv7E-M - armv7em 1185 case ArchSpec::eCore_arm_armv7m: 1186 if (!enforce_exact_match) { 1187 if (core2 == ArchSpec::eCore_arm_generic) 1188 return true; 1189 if (core2 == ArchSpec::eCore_arm_armv6m) 1190 return true; 1191 if (core2 == ArchSpec::eCore_arm_armv7) 1192 return true; 1193 if (core2 == ArchSpec::eCore_arm_armv7em) 1194 return true; 1195 try_inverse = true; 1196 } 1197 break; 1198 1199 case ArchSpec::eCore_arm_armv7f: 1200 case ArchSpec::eCore_arm_armv7k: 1201 case ArchSpec::eCore_arm_armv7s: 1202 if (!enforce_exact_match) { 1203 if (core2 == ArchSpec::eCore_arm_generic) 1204 return true; 1205 if (core2 == ArchSpec::eCore_arm_armv7) 1206 return true; 1207 try_inverse = false; 1208 } 1209 break; 1210 1211 case ArchSpec::eCore_x86_64_x86_64h: 1212 if (!enforce_exact_match) { 1213 try_inverse = false; 1214 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1215 return true; 1216 } 1217 break; 1218 1219 case ArchSpec::eCore_arm_armv8: 1220 if (!enforce_exact_match) { 1221 if (core2 == ArchSpec::eCore_arm_arm64) 1222 return true; 1223 if (core2 == ArchSpec::eCore_arm_aarch64) 1224 return true; 1225 try_inverse = false; 1226 } 1227 break; 1228 1229 case ArchSpec::eCore_arm_aarch64: 1230 if (!enforce_exact_match) { 1231 if (core2 == ArchSpec::eCore_arm_arm64) 1232 return true; 1233 if (core2 == ArchSpec::eCore_arm_armv8) 1234 return true; 1235 try_inverse = false; 1236 } 1237 break; 1238 1239 case ArchSpec::eCore_arm_arm64: 1240 if (!enforce_exact_match) { 1241 if (core2 == ArchSpec::eCore_arm_aarch64) 1242 return true; 1243 if (core2 == ArchSpec::eCore_arm_armv8) 1244 return true; 1245 try_inverse = false; 1246 } 1247 break; 1248 1249 case ArchSpec::eCore_arm_arm64_32: 1250 if (!enforce_exact_match) { 1251 if (core2 == ArchSpec::eCore_arm_generic) 1252 return true; 1253 try_inverse = false; 1254 } 1255 break; 1256 1257 case ArchSpec::eCore_mips32: 1258 if (!enforce_exact_match) { 1259 if (core2 >= ArchSpec::kCore_mips32_first && 1260 core2 <= ArchSpec::kCore_mips32_last) 1261 return true; 1262 try_inverse = false; 1263 } 1264 break; 1265 1266 case ArchSpec::eCore_mips32el: 1267 if (!enforce_exact_match) { 1268 if (core2 >= ArchSpec::kCore_mips32el_first && 1269 core2 <= ArchSpec::kCore_mips32el_last) 1270 return true; 1271 try_inverse = true; 1272 } 1273 break; 1274 1275 case ArchSpec::eCore_mips64: 1276 if (!enforce_exact_match) { 1277 if (core2 >= ArchSpec::kCore_mips32_first && 1278 core2 <= ArchSpec::kCore_mips32_last) 1279 return true; 1280 if (core2 >= ArchSpec::kCore_mips64_first && 1281 core2 <= ArchSpec::kCore_mips64_last) 1282 return true; 1283 try_inverse = false; 1284 } 1285 break; 1286 1287 case ArchSpec::eCore_mips64el: 1288 if (!enforce_exact_match) { 1289 if (core2 >= ArchSpec::kCore_mips32el_first && 1290 core2 <= ArchSpec::kCore_mips32el_last) 1291 return true; 1292 if (core2 >= ArchSpec::kCore_mips64el_first && 1293 core2 <= ArchSpec::kCore_mips64el_last) 1294 return true; 1295 try_inverse = false; 1296 } 1297 break; 1298 1299 case ArchSpec::eCore_mips64r2: 1300 case ArchSpec::eCore_mips64r3: 1301 case ArchSpec::eCore_mips64r5: 1302 if (!enforce_exact_match) { 1303 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1304 return true; 1305 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1306 return true; 1307 try_inverse = false; 1308 } 1309 break; 1310 1311 case ArchSpec::eCore_mips64r2el: 1312 case ArchSpec::eCore_mips64r3el: 1313 case ArchSpec::eCore_mips64r5el: 1314 if (!enforce_exact_match) { 1315 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1316 return true; 1317 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1318 return true; 1319 try_inverse = false; 1320 } 1321 break; 1322 1323 case ArchSpec::eCore_mips32r2: 1324 case ArchSpec::eCore_mips32r3: 1325 case ArchSpec::eCore_mips32r5: 1326 if (!enforce_exact_match) { 1327 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1328 return true; 1329 } 1330 break; 1331 1332 case ArchSpec::eCore_mips32r2el: 1333 case ArchSpec::eCore_mips32r3el: 1334 case ArchSpec::eCore_mips32r5el: 1335 if (!enforce_exact_match) { 1336 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1337 return true; 1338 } 1339 break; 1340 1341 case ArchSpec::eCore_mips32r6: 1342 if (!enforce_exact_match) { 1343 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1344 return true; 1345 } 1346 break; 1347 1348 case ArchSpec::eCore_mips32r6el: 1349 if (!enforce_exact_match) { 1350 if (core2 == ArchSpec::eCore_mips32el || 1351 core2 == ArchSpec::eCore_mips32r6el) 1352 return true; 1353 } 1354 break; 1355 1356 case ArchSpec::eCore_mips64r6: 1357 if (!enforce_exact_match) { 1358 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1359 return true; 1360 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1361 return true; 1362 } 1363 break; 1364 1365 case ArchSpec::eCore_mips64r6el: 1366 if (!enforce_exact_match) { 1367 if (core2 == ArchSpec::eCore_mips32el || 1368 core2 == ArchSpec::eCore_mips32r6el) 1369 return true; 1370 if (core2 == ArchSpec::eCore_mips64el || 1371 core2 == ArchSpec::eCore_mips64r6el) 1372 return true; 1373 } 1374 break; 1375 1376 default: 1377 break; 1378 } 1379 if (try_inverse) 1380 return cores_match(core2, core1, false, enforce_exact_match); 1381 return false; 1382 } 1383 1384 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1385 const ArchSpec::Core lhs_core = lhs.GetCore(); 1386 const ArchSpec::Core rhs_core = rhs.GetCore(); 1387 return lhs_core < rhs_core; 1388 } 1389 1390 1391 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1392 return lhs.GetCore() == rhs.GetCore(); 1393 } 1394 1395 bool ArchSpec::IsFullySpecifiedTriple() const { 1396 const auto &user_specified_triple = GetTriple(); 1397 1398 bool user_triple_fully_specified = false; 1399 1400 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1401 TripleOSWasSpecified()) { 1402 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1403 TripleVendorWasSpecified()) { 1404 const unsigned unspecified = 0; 1405 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1406 user_triple_fully_specified = true; 1407 } 1408 } 1409 } 1410 1411 return user_triple_fully_specified; 1412 } 1413 1414 void ArchSpec::PiecewiseTripleCompare( 1415 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1416 bool &os_different, bool &os_version_different, bool &env_different) const { 1417 const llvm::Triple &me(GetTriple()); 1418 const llvm::Triple &them(other.GetTriple()); 1419 1420 arch_different = (me.getArch() != them.getArch()); 1421 1422 vendor_different = (me.getVendor() != them.getVendor()); 1423 1424 os_different = (me.getOS() != them.getOS()); 1425 1426 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1427 1428 env_different = (me.getEnvironment() != them.getEnvironment()); 1429 } 1430 1431 bool ArchSpec::IsAlwaysThumbInstructions() const { 1432 std::string Status; 1433 if (GetTriple().getArch() == llvm::Triple::arm || 1434 GetTriple().getArch() == llvm::Triple::thumb) { 1435 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1436 // 1437 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1438 // execute thumb instructions. We map the cores to arch names like this: 1439 // 1440 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1441 // Cortex-M7: armv7em 1442 1443 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1444 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1445 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1446 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1447 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1448 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1449 return true; 1450 } 1451 } 1452 return false; 1453 } 1454 1455 void ArchSpec::DumpTriple(Stream &s) const { 1456 const llvm::Triple &triple = GetTriple(); 1457 llvm::StringRef arch_str = triple.getArchName(); 1458 llvm::StringRef vendor_str = triple.getVendorName(); 1459 llvm::StringRef os_str = triple.getOSName(); 1460 llvm::StringRef environ_str = triple.getEnvironmentName(); 1461 1462 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1463 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1464 os_str.empty() ? "*" : os_str.str().c_str()); 1465 1466 if (!environ_str.empty()) 1467 s.Printf("-%s", environ_str.str().c_str()); 1468 } 1469