1 //===-- ArchSpec.cpp ------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "lldb/Utility/ArchSpec.h"
10 #include "lldb/Utility/LLDBLog.h"
11 
12 #include "lldb/Utility/Log.h"
13 #include "lldb/Utility/StringList.h"
14 #include "lldb/lldb-defines.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/BinaryFormat/COFF.h"
17 #include "llvm/BinaryFormat/ELF.h"
18 #include "llvm/BinaryFormat/MachO.h"
19 #include "llvm/Support/Compiler.h"
20 
21 using namespace lldb;
22 using namespace lldb_private;
23 
24 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
25                         bool try_inverse, bool enforce_exact_match);
26 
27 namespace lldb_private {
28 
29 struct CoreDefinition {
30   ByteOrder default_byte_order;
31   uint32_t addr_byte_size;
32   uint32_t min_opcode_byte_size;
33   uint32_t max_opcode_byte_size;
34   llvm::Triple::ArchType machine;
35   ArchSpec::Core core;
36   const char *const name;
37 };
38 
39 } // namespace lldb_private
40 
41 // This core information can be looked using the ArchSpec::Core as the index
42 static const CoreDefinition g_core_definitions[] = {
43     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
44      "arm"},
45     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
46      "armv4"},
47     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
48      "armv4t"},
49     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
50      "armv5"},
51     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
52      "armv5e"},
53     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
54      "armv5t"},
55     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
56      "armv6"},
57     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
58      "armv6m"},
59     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
60      "armv7"},
61     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
62      "armv7l"},
63     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
64      "armv7f"},
65     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
66      "armv7s"},
67     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
68      "armv7k"},
69     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
70      "armv7m"},
71     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
72      "armv7em"},
73     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
74      "xscale"},
75     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
76      "thumb"},
77     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
78      "thumbv4t"},
79     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
80      "thumbv5"},
81     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
82      "thumbv5e"},
83     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
84      "thumbv6"},
85     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
86      "thumbv6m"},
87     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
88      "thumbv7"},
89     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
90      "thumbv7f"},
91     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
92      "thumbv7s"},
93     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
94      "thumbv7k"},
95     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
96      "thumbv7m"},
97     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
98      "thumbv7em"},
99     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
100      ArchSpec::eCore_arm_arm64, "arm64"},
101     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
102      ArchSpec::eCore_arm_armv8, "armv8"},
103     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
104      "armv8l"},
105     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
106      ArchSpec::eCore_arm_arm64e, "arm64e"},
107     {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
108      ArchSpec::eCore_arm_arm64_32, "arm64_32"},
109     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
110      ArchSpec::eCore_arm_aarch64, "aarch64"},
111 
112     // mips32, mips32r2, mips32r3, mips32r5, mips32r6
113     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
114      "mips"},
115     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
116      "mipsr2"},
117     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
118      "mipsr3"},
119     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
120      "mipsr5"},
121     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
122      "mipsr6"},
123     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
124      "mipsel"},
125     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
126      ArchSpec::eCore_mips32r2el, "mipsr2el"},
127     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
128      ArchSpec::eCore_mips32r3el, "mipsr3el"},
129     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
130      ArchSpec::eCore_mips32r5el, "mipsr5el"},
131     {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
132      ArchSpec::eCore_mips32r6el, "mipsr6el"},
133 
134     // mips64, mips64r2, mips64r3, mips64r5, mips64r6
135     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
136      "mips64"},
137     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
138      "mips64r2"},
139     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
140      "mips64r3"},
141     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
142      "mips64r5"},
143     {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
144      "mips64r6"},
145     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
146      ArchSpec::eCore_mips64el, "mips64el"},
147     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
148      ArchSpec::eCore_mips64r2el, "mips64r2el"},
149     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
150      ArchSpec::eCore_mips64r3el, "mips64r3el"},
151     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
152      ArchSpec::eCore_mips64r5el, "mips64r5el"},
153     {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
154      ArchSpec::eCore_mips64r6el, "mips64r6el"},
155 
156     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
157      "powerpc"},
158     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
159      "ppc601"},
160     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
161      "ppc602"},
162     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
163      "ppc603"},
164     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
165      "ppc603e"},
166     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
167      "ppc603ev"},
168     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
169      "ppc604"},
170     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
171      "ppc604e"},
172     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
173      "ppc620"},
174     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
175      "ppc750"},
176     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
177      "ppc7400"},
178     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
179      "ppc7450"},
180     {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
181      "ppc970"},
182 
183     {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
184      ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
185     {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
186      "powerpc64"},
187     {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
188      ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
189 
190     {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
191      ArchSpec::eCore_s390x_generic, "s390x"},
192 
193     {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
194      ArchSpec::eCore_sparc_generic, "sparc"},
195     {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
196      ArchSpec::eCore_sparc9_generic, "sparcv9"},
197 
198     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
199      "i386"},
200     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
201      "i486"},
202     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
203      ArchSpec::eCore_x86_32_i486sx, "i486sx"},
204     {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
205      "i686"},
206 
207     {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
208      ArchSpec::eCore_x86_64_x86_64, "x86_64"},
209     {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
210      ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
211     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
212      ArchSpec::eCore_hexagon_generic, "hexagon"},
213     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
214      ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
215     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
216      ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
217 
218     {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
219      "riscv32"},
220     {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
221      "riscv64"},
222 
223     {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
224      ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
225     {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
226      ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
227     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
228 
229     {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
230 
231     {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
232      "wasm32"},
233 };
234 
235 // Ensure that we have an entry in the g_core_definitions for each core. If you
236 // comment out an entry above, you will need to comment out the corresponding
237 // ArchSpec::Core enumeration.
238 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
239                   ArchSpec::kNumCores,
240               "make sure we have one core definition for each core");
241 
242 struct ArchDefinitionEntry {
243   ArchSpec::Core core;
244   uint32_t cpu;
245   uint32_t sub;
246   uint32_t cpu_mask;
247   uint32_t sub_mask;
248 };
249 
250 struct ArchDefinition {
251   ArchitectureType type;
252   size_t num_entries;
253   const ArchDefinitionEntry *entries;
254   const char *name;
255 };
256 
ListSupportedArchNames(StringList & list)257 void ArchSpec::ListSupportedArchNames(StringList &list) {
258   for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
259     list.AppendString(g_core_definitions[i].name);
260 }
261 
AutoComplete(CompletionRequest & request)262 void ArchSpec::AutoComplete(CompletionRequest &request) {
263   for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
264     request.TryCompleteCurrentArg(g_core_definitions[i].name);
265 }
266 
267 #define CPU_ANY (UINT32_MAX)
268 
269 //===----------------------------------------------------------------------===//
270 // A table that gets searched linearly for matches. This table is used to
271 // convert cpu type and subtypes to architecture names, and to convert
272 // architecture names to cpu types and subtypes. The ordering is important and
273 // allows the precedence to be set when the table is built.
274 #define SUBTYPE_MASK 0x00FFFFFFu
275 
276 // clang-format off
277 static const ArchDefinitionEntry g_macho_arch_entries[] = {
278     {ArchSpec::eCore_arm_generic,     llvm::MachO::CPU_TYPE_ARM,        CPU_ANY,                                UINT32_MAX, UINT32_MAX},
279     {ArchSpec::eCore_arm_generic,     llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_ALL,       UINT32_MAX, SUBTYPE_MASK},
280     {ArchSpec::eCore_arm_armv4,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V4T,       UINT32_MAX, SUBTYPE_MASK},
281     {ArchSpec::eCore_arm_armv4t,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V4T,       UINT32_MAX, SUBTYPE_MASK},
282     {ArchSpec::eCore_arm_armv6,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6,        UINT32_MAX, SUBTYPE_MASK},
283     {ArchSpec::eCore_arm_armv6m,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6M,       UINT32_MAX, SUBTYPE_MASK},
284     {ArchSpec::eCore_arm_armv5,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ,     UINT32_MAX, SUBTYPE_MASK},
285     {ArchSpec::eCore_arm_armv5e,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ,     UINT32_MAX, SUBTYPE_MASK},
286     {ArchSpec::eCore_arm_armv5t,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ,     UINT32_MAX, SUBTYPE_MASK},
287     {ArchSpec::eCore_arm_xscale,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_XSCALE,    UINT32_MAX, SUBTYPE_MASK},
288     {ArchSpec::eCore_arm_armv7,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7,        UINT32_MAX, SUBTYPE_MASK},
289     {ArchSpec::eCore_arm_armv7f,      llvm::MachO::CPU_TYPE_ARM,        10,                                     UINT32_MAX, SUBTYPE_MASK},
290     {ArchSpec::eCore_arm_armv7s,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7S,       UINT32_MAX, SUBTYPE_MASK},
291     {ArchSpec::eCore_arm_armv7k,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7K,       UINT32_MAX, SUBTYPE_MASK},
292     {ArchSpec::eCore_arm_armv7m,      llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7M,       UINT32_MAX, SUBTYPE_MASK},
293     {ArchSpec::eCore_arm_armv7em,     llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7EM,      UINT32_MAX, SUBTYPE_MASK},
294     {ArchSpec::eCore_arm_arm64e,      llvm::MachO::CPU_TYPE_ARM64,      llvm::MachO::CPU_SUBTYPE_ARM64E,        UINT32_MAX, SUBTYPE_MASK},
295     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      llvm::MachO::CPU_SUBTYPE_ARM64_ALL,     UINT32_MAX, SUBTYPE_MASK},
296     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      llvm::MachO::CPU_SUBTYPE_ARM64_V8,      UINT32_MAX, SUBTYPE_MASK},
297     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      13,                                     UINT32_MAX, SUBTYPE_MASK},
298     {ArchSpec::eCore_arm_arm64_32,    llvm::MachO::CPU_TYPE_ARM64_32,   0,                                      UINT32_MAX, SUBTYPE_MASK},
299     {ArchSpec::eCore_arm_arm64_32,    llvm::MachO::CPU_TYPE_ARM64_32,   1,                                      UINT32_MAX, SUBTYPE_MASK},
300     {ArchSpec::eCore_arm_arm64,       llvm::MachO::CPU_TYPE_ARM64,      CPU_ANY,                                UINT32_MAX, SUBTYPE_MASK},
301     {ArchSpec::eCore_thumb,           llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_ALL,       UINT32_MAX, SUBTYPE_MASK},
302     {ArchSpec::eCore_thumbv4t,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V4T,       UINT32_MAX, SUBTYPE_MASK},
303     {ArchSpec::eCore_thumbv5,         llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5,        UINT32_MAX, SUBTYPE_MASK},
304     {ArchSpec::eCore_thumbv5e,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V5,        UINT32_MAX, SUBTYPE_MASK},
305     {ArchSpec::eCore_thumbv6,         llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6,        UINT32_MAX, SUBTYPE_MASK},
306     {ArchSpec::eCore_thumbv6m,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V6M,       UINT32_MAX, SUBTYPE_MASK},
307     {ArchSpec::eCore_thumbv7,         llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7,        UINT32_MAX, SUBTYPE_MASK},
308     {ArchSpec::eCore_thumbv7f,        llvm::MachO::CPU_TYPE_ARM,        10,                                     UINT32_MAX, SUBTYPE_MASK},
309     {ArchSpec::eCore_thumbv7s,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7S,       UINT32_MAX, SUBTYPE_MASK},
310     {ArchSpec::eCore_thumbv7k,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7K,       UINT32_MAX, SUBTYPE_MASK},
311     {ArchSpec::eCore_thumbv7m,        llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7M,       UINT32_MAX, SUBTYPE_MASK},
312     {ArchSpec::eCore_thumbv7em,       llvm::MachO::CPU_TYPE_ARM,        llvm::MachO::CPU_SUBTYPE_ARM_V7EM,      UINT32_MAX, SUBTYPE_MASK},
313     {ArchSpec::eCore_ppc_generic,     llvm::MachO::CPU_TYPE_POWERPC,    CPU_ANY,                                UINT32_MAX, UINT32_MAX},
314     {ArchSpec::eCore_ppc_generic,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_ALL,   UINT32_MAX, SUBTYPE_MASK},
315     {ArchSpec::eCore_ppc_ppc601,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_601,   UINT32_MAX, SUBTYPE_MASK},
316     {ArchSpec::eCore_ppc_ppc602,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_602,   UINT32_MAX, SUBTYPE_MASK},
317     {ArchSpec::eCore_ppc_ppc603,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_603,   UINT32_MAX, SUBTYPE_MASK},
318     {ArchSpec::eCore_ppc_ppc603e,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_603e,  UINT32_MAX, SUBTYPE_MASK},
319     {ArchSpec::eCore_ppc_ppc603ev,    llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
320     {ArchSpec::eCore_ppc_ppc604,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_604,   UINT32_MAX, SUBTYPE_MASK},
321     {ArchSpec::eCore_ppc_ppc604e,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_604e,  UINT32_MAX, SUBTYPE_MASK},
322     {ArchSpec::eCore_ppc_ppc620,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_620,   UINT32_MAX, SUBTYPE_MASK},
323     {ArchSpec::eCore_ppc_ppc750,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_750,   UINT32_MAX, SUBTYPE_MASK},
324     {ArchSpec::eCore_ppc_ppc7400,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_7400,  UINT32_MAX, SUBTYPE_MASK},
325     {ArchSpec::eCore_ppc_ppc7450,     llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_7450,  UINT32_MAX, SUBTYPE_MASK},
326     {ArchSpec::eCore_ppc_ppc970,      llvm::MachO::CPU_TYPE_POWERPC,    llvm::MachO::CPU_SUBTYPE_POWERPC_970,   UINT32_MAX, SUBTYPE_MASK},
327     {ArchSpec::eCore_ppc64_generic,   llvm::MachO::CPU_TYPE_POWERPC64,  llvm::MachO::CPU_SUBTYPE_POWERPC_ALL,   UINT32_MAX, SUBTYPE_MASK},
328     {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64,  CPU_ANY,                                UINT32_MAX, SUBTYPE_MASK},
329     {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64,  100,                                    UINT32_MAX, SUBTYPE_MASK},
330     {ArchSpec::eCore_x86_32_i386,     llvm::MachO::CPU_TYPE_I386,       llvm::MachO::CPU_SUBTYPE_I386_ALL,      UINT32_MAX, SUBTYPE_MASK},
331     {ArchSpec::eCore_x86_32_i486,     llvm::MachO::CPU_TYPE_I386,       llvm::MachO::CPU_SUBTYPE_486,           UINT32_MAX, SUBTYPE_MASK},
332     {ArchSpec::eCore_x86_32_i486sx,   llvm::MachO::CPU_TYPE_I386,       llvm::MachO::CPU_SUBTYPE_486SX,         UINT32_MAX, SUBTYPE_MASK},
333     {ArchSpec::eCore_x86_32_i386,     llvm::MachO::CPU_TYPE_I386,       CPU_ANY,                                UINT32_MAX, UINT32_MAX},
334     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_ALL,    UINT32_MAX, SUBTYPE_MASK},
335     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_ARCH1,     UINT32_MAX, SUBTYPE_MASK},
336     {ArchSpec::eCore_x86_64_x86_64h,  llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_H,      UINT32_MAX, SUBTYPE_MASK},
337     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     CPU_ANY, UINT32_MAX, UINT32_MAX},
338     // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
339     {ArchSpec::eCore_uknownMach32,    0,                                0,                                      0xFF000000u, 0x00000000u},
340     {ArchSpec::eCore_uknownMach64,    llvm::MachO::CPU_ARCH_ABI64,      0,                                      0xFF000000u, 0x00000000u}};
341 // clang-format on
342 
343 static const ArchDefinition g_macho_arch_def = {
344     eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries),
345     g_macho_arch_entries, "mach-o"};
346 
347 //===----------------------------------------------------------------------===//
348 // A table that gets searched linearly for matches. This table is used to
349 // convert cpu type and subtypes to architecture names, and to convert
350 // architecture names to cpu types and subtypes. The ordering is important and
351 // allows the precedence to be set when the table is built.
352 static const ArchDefinitionEntry g_elf_arch_entries[] = {
353     {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
354      0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
355     {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
356      0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
357     {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
358      0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
359     {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
360      0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
361     {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
362      ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
363     {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
364      ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
365     {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
366      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
367     {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
368      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
369     {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
370      0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
371     {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
372      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
373     {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
374      0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
375     {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
376      0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
377     {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
378      ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
379     {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
380      ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
381     {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
382      ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
383     {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
384      ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
385     {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
386      ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
387     {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
388      0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
389     {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
390      ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
391     {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
392      ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
393     {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
394      ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
395     {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
396      ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
397     {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
398      ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
399     {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
400      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
401     {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
402      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
403     {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
404      0xFFFFFFFFu}, // AVR
405     {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
406      ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
407     {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
408      ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
409 };
410 
411 static const ArchDefinition g_elf_arch_def = {
412     eArchTypeELF,
413     llvm::array_lengthof(g_elf_arch_entries),
414     g_elf_arch_entries,
415     "elf",
416 };
417 
418 static const ArchDefinitionEntry g_coff_arch_entries[] = {
419     {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
420      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
421     {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
422      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
423     {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
424      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
425     {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
426      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
427     {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
428      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
429     {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
430      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
431     {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
432      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
433     {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
434      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
435 };
436 
437 static const ArchDefinition g_coff_arch_def = {
438     eArchTypeCOFF,
439     llvm::array_lengthof(g_coff_arch_entries),
440     g_coff_arch_entries,
441     "pe-coff",
442 };
443 
444 //===----------------------------------------------------------------------===//
445 // Table of all ArchDefinitions
446 static const ArchDefinition *g_arch_definitions[] = {
447     &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def};
448 
449 static const size_t k_num_arch_definitions =
450     llvm::array_lengthof(g_arch_definitions);
451 
452 //===----------------------------------------------------------------------===//
453 // Static helper functions.
454 
455 // Get the architecture definition for a given object type.
FindArchDefinition(ArchitectureType arch_type)456 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) {
457   for (unsigned int i = 0; i < k_num_arch_definitions; ++i) {
458     const ArchDefinition *def = g_arch_definitions[i];
459     if (def->type == arch_type)
460       return def;
461   }
462   return nullptr;
463 }
464 
465 // Get an architecture definition by name.
FindCoreDefinition(llvm::StringRef name)466 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
467   for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) {
468     if (name.equals_insensitive(g_core_definitions[i].name))
469       return &g_core_definitions[i];
470   }
471   return nullptr;
472 }
473 
FindCoreDefinition(ArchSpec::Core core)474 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
475   if (core < llvm::array_lengthof(g_core_definitions))
476     return &g_core_definitions[core];
477   return nullptr;
478 }
479 
480 // Get a definition entry by cpu type and subtype.
481 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,uint32_t cpu,uint32_t sub)482 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) {
483   if (def == nullptr)
484     return nullptr;
485 
486   const ArchDefinitionEntry *entries = def->entries;
487   for (size_t i = 0; i < def->num_entries; ++i) {
488     if (entries[i].cpu == (cpu & entries[i].cpu_mask))
489       if (entries[i].sub == (sub & entries[i].sub_mask))
490         return &entries[i];
491   }
492   return nullptr;
493 }
494 
495 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,ArchSpec::Core core)496 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
497   if (def == nullptr)
498     return nullptr;
499 
500   const ArchDefinitionEntry *entries = def->entries;
501   for (size_t i = 0; i < def->num_entries; ++i) {
502     if (entries[i].core == core)
503       return &entries[i];
504   }
505   return nullptr;
506 }
507 
508 //===----------------------------------------------------------------------===//
509 // Constructors and destructors.
510 
511 ArchSpec::ArchSpec() = default;
512 
ArchSpec(const char * triple_cstr)513 ArchSpec::ArchSpec(const char *triple_cstr) {
514   if (triple_cstr)
515     SetTriple(triple_cstr);
516 }
517 
ArchSpec(llvm::StringRef triple_str)518 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
519 
ArchSpec(const llvm::Triple & triple)520 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
521 
ArchSpec(ArchitectureType arch_type,uint32_t cpu,uint32_t subtype)522 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
523   SetArchitecture(arch_type, cpu, subtype);
524 }
525 
526 ArchSpec::~ArchSpec() = default;
527 
Clear()528 void ArchSpec::Clear() {
529   m_triple = llvm::Triple();
530   m_core = kCore_invalid;
531   m_byte_order = eByteOrderInvalid;
532   m_distribution_id.Clear();
533   m_flags = 0;
534 }
535 
536 //===----------------------------------------------------------------------===//
537 // Predicates.
538 
GetArchitectureName() const539 const char *ArchSpec::GetArchitectureName() const {
540   const CoreDefinition *core_def = FindCoreDefinition(m_core);
541   if (core_def)
542     return core_def->name;
543   return "unknown";
544 }
545 
IsMIPS() const546 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
547 
GetTargetABI() const548 std::string ArchSpec::GetTargetABI() const {
549 
550   std::string abi;
551 
552   if (IsMIPS()) {
553     switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
554     case ArchSpec::eMIPSABI_N64:
555       abi = "n64";
556       return abi;
557     case ArchSpec::eMIPSABI_N32:
558       abi = "n32";
559       return abi;
560     case ArchSpec::eMIPSABI_O32:
561       abi = "o32";
562       return abi;
563     default:
564       return abi;
565     }
566   }
567   return abi;
568 }
569 
SetFlags(const std::string & elf_abi)570 void ArchSpec::SetFlags(const std::string &elf_abi) {
571 
572   uint32_t flag = GetFlags();
573   if (IsMIPS()) {
574     if (elf_abi == "n64")
575       flag |= ArchSpec::eMIPSABI_N64;
576     else if (elf_abi == "n32")
577       flag |= ArchSpec::eMIPSABI_N32;
578     else if (elf_abi == "o32")
579       flag |= ArchSpec::eMIPSABI_O32;
580   }
581   SetFlags(flag);
582 }
583 
GetClangTargetCPU() const584 std::string ArchSpec::GetClangTargetCPU() const {
585   std::string cpu;
586 
587   if (IsMIPS()) {
588     switch (m_core) {
589     case ArchSpec::eCore_mips32:
590     case ArchSpec::eCore_mips32el:
591       cpu = "mips32";
592       break;
593     case ArchSpec::eCore_mips32r2:
594     case ArchSpec::eCore_mips32r2el:
595       cpu = "mips32r2";
596       break;
597     case ArchSpec::eCore_mips32r3:
598     case ArchSpec::eCore_mips32r3el:
599       cpu = "mips32r3";
600       break;
601     case ArchSpec::eCore_mips32r5:
602     case ArchSpec::eCore_mips32r5el:
603       cpu = "mips32r5";
604       break;
605     case ArchSpec::eCore_mips32r6:
606     case ArchSpec::eCore_mips32r6el:
607       cpu = "mips32r6";
608       break;
609     case ArchSpec::eCore_mips64:
610     case ArchSpec::eCore_mips64el:
611       cpu = "mips64";
612       break;
613     case ArchSpec::eCore_mips64r2:
614     case ArchSpec::eCore_mips64r2el:
615       cpu = "mips64r2";
616       break;
617     case ArchSpec::eCore_mips64r3:
618     case ArchSpec::eCore_mips64r3el:
619       cpu = "mips64r3";
620       break;
621     case ArchSpec::eCore_mips64r5:
622     case ArchSpec::eCore_mips64r5el:
623       cpu = "mips64r5";
624       break;
625     case ArchSpec::eCore_mips64r6:
626     case ArchSpec::eCore_mips64r6el:
627       cpu = "mips64r6";
628       break;
629     default:
630       break;
631     }
632   }
633   return cpu;
634 }
635 
GetMachOCPUType() const636 uint32_t ArchSpec::GetMachOCPUType() const {
637   const CoreDefinition *core_def = FindCoreDefinition(m_core);
638   if (core_def) {
639     const ArchDefinitionEntry *arch_def =
640         FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
641     if (arch_def) {
642       return arch_def->cpu;
643     }
644   }
645   return LLDB_INVALID_CPUTYPE;
646 }
647 
GetMachOCPUSubType() const648 uint32_t ArchSpec::GetMachOCPUSubType() const {
649   const CoreDefinition *core_def = FindCoreDefinition(m_core);
650   if (core_def) {
651     const ArchDefinitionEntry *arch_def =
652         FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
653     if (arch_def) {
654       return arch_def->sub;
655     }
656   }
657   return LLDB_INVALID_CPUTYPE;
658 }
659 
GetDataByteSize() const660 uint32_t ArchSpec::GetDataByteSize() const {
661   return 1;
662 }
663 
GetCodeByteSize() const664 uint32_t ArchSpec::GetCodeByteSize() const {
665   return 1;
666 }
667 
GetMachine() const668 llvm::Triple::ArchType ArchSpec::GetMachine() const {
669   const CoreDefinition *core_def = FindCoreDefinition(m_core);
670   if (core_def)
671     return core_def->machine;
672 
673   return llvm::Triple::UnknownArch;
674 }
675 
GetDistributionId() const676 ConstString ArchSpec::GetDistributionId() const {
677   return m_distribution_id;
678 }
679 
SetDistributionId(const char * distribution_id)680 void ArchSpec::SetDistributionId(const char *distribution_id) {
681   m_distribution_id.SetCString(distribution_id);
682 }
683 
GetAddressByteSize() const684 uint32_t ArchSpec::GetAddressByteSize() const {
685   const CoreDefinition *core_def = FindCoreDefinition(m_core);
686   if (core_def) {
687     if (core_def->machine == llvm::Triple::mips64 ||
688         core_def->machine == llvm::Triple::mips64el) {
689       // For N32/O32 applications Address size is 4 bytes.
690       if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
691         return 4;
692     }
693     return core_def->addr_byte_size;
694   }
695   return 0;
696 }
697 
GetDefaultEndian() const698 ByteOrder ArchSpec::GetDefaultEndian() const {
699   const CoreDefinition *core_def = FindCoreDefinition(m_core);
700   if (core_def)
701     return core_def->default_byte_order;
702   return eByteOrderInvalid;
703 }
704 
CharIsSignedByDefault() const705 bool ArchSpec::CharIsSignedByDefault() const {
706   switch (m_triple.getArch()) {
707   default:
708     return true;
709 
710   case llvm::Triple::aarch64:
711   case llvm::Triple::aarch64_32:
712   case llvm::Triple::aarch64_be:
713   case llvm::Triple::arm:
714   case llvm::Triple::armeb:
715   case llvm::Triple::thumb:
716   case llvm::Triple::thumbeb:
717     return m_triple.isOSDarwin() || m_triple.isOSWindows();
718 
719   case llvm::Triple::ppc:
720   case llvm::Triple::ppc64:
721     return m_triple.isOSDarwin();
722 
723   case llvm::Triple::ppc64le:
724   case llvm::Triple::systemz:
725   case llvm::Triple::xcore:
726   case llvm::Triple::arc:
727     return false;
728   }
729 }
730 
GetByteOrder() const731 lldb::ByteOrder ArchSpec::GetByteOrder() const {
732   if (m_byte_order == eByteOrderInvalid)
733     return GetDefaultEndian();
734   return m_byte_order;
735 }
736 
737 //===----------------------------------------------------------------------===//
738 // Mutators.
739 
SetTriple(const llvm::Triple & triple)740 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
741   m_triple = triple;
742   UpdateCore();
743   return IsValid();
744 }
745 
ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,ArchSpec & arch)746 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
747                                                  ArchSpec &arch) {
748   // Accept "12-10" or "12.10" as cpu type/subtype
749   if (triple_str.empty())
750     return false;
751 
752   size_t pos = triple_str.find_first_of("-.");
753   if (pos == llvm::StringRef::npos)
754     return false;
755 
756   llvm::StringRef cpu_str = triple_str.substr(0, pos);
757   llvm::StringRef remainder = triple_str.substr(pos + 1);
758   if (cpu_str.empty() || remainder.empty())
759     return false;
760 
761   llvm::StringRef sub_str;
762   llvm::StringRef vendor;
763   llvm::StringRef os;
764   std::tie(sub_str, remainder) = remainder.split('-');
765   std::tie(vendor, os) = remainder.split('-');
766 
767   uint32_t cpu = 0;
768   uint32_t sub = 0;
769   if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
770     return false;
771 
772   if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
773     return false;
774   if (!vendor.empty() && !os.empty()) {
775     arch.GetTriple().setVendorName(vendor);
776     arch.GetTriple().setOSName(os);
777   }
778 
779   return true;
780 }
781 
SetTriple(llvm::StringRef triple)782 bool ArchSpec::SetTriple(llvm::StringRef triple) {
783   if (triple.empty()) {
784     Clear();
785     return false;
786   }
787 
788   if (ParseMachCPUDashSubtypeTriple(triple, *this))
789     return true;
790 
791   SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
792   return IsValid();
793 }
794 
ContainsOnlyArch(const llvm::Triple & normalized_triple)795 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
796   return !normalized_triple.getArchName().empty() &&
797          normalized_triple.getOSName().empty() &&
798          normalized_triple.getVendorName().empty() &&
799          normalized_triple.getEnvironmentName().empty();
800 }
801 
MergeFrom(const ArchSpec & other)802 void ArchSpec::MergeFrom(const ArchSpec &other) {
803   // ios-macabi always wins over macosx.
804   if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
805        GetTriple().getOS() == llvm::Triple::UnknownOS) &&
806       other.GetTriple().getOS() == llvm::Triple::IOS &&
807       other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
808     (*this) = other;
809     return;
810   }
811 
812   if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
813     GetTriple().setVendor(other.GetTriple().getVendor());
814   if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
815     GetTriple().setOS(other.GetTriple().getOS());
816   if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
817     GetTriple().setArch(other.GetTriple().getArch());
818 
819     // MachO unknown64 isn't really invalid as the debugger can still obtain
820     // information from the binary, e.g. line tables. As such, we don't update
821     // the core here.
822     if (other.GetCore() != eCore_uknownMach64)
823       UpdateCore();
824   }
825   if (!TripleEnvironmentWasSpecified() &&
826       other.TripleEnvironmentWasSpecified()) {
827     GetTriple().setEnvironment(other.GetTriple().getEnvironment());
828   }
829   // If this and other are both arm ArchSpecs and this ArchSpec is a generic
830   // "some kind of arm" spec but the other ArchSpec is a specific arm core,
831   // adopt the specific arm core.
832   if (GetTriple().getArch() == llvm::Triple::arm &&
833       other.GetTriple().getArch() == llvm::Triple::arm &&
834       IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
835       other.GetCore() != ArchSpec::eCore_arm_generic) {
836     m_core = other.GetCore();
837     CoreUpdated(false);
838   }
839   if (GetFlags() == 0) {
840     SetFlags(other.GetFlags());
841   }
842 }
843 
SetArchitecture(ArchitectureType arch_type,uint32_t cpu,uint32_t sub,uint32_t os)844 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
845                                uint32_t sub, uint32_t os) {
846   m_core = kCore_invalid;
847   bool update_triple = true;
848   const ArchDefinition *arch_def = FindArchDefinition(arch_type);
849   if (arch_def) {
850     const ArchDefinitionEntry *arch_def_entry =
851         FindArchDefinitionEntry(arch_def, cpu, sub);
852     if (arch_def_entry) {
853       const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
854       if (core_def) {
855         m_core = core_def->core;
856         update_triple = false;
857         // Always use the architecture name because it might be more
858         // descriptive than the architecture enum ("armv7" ->
859         // llvm::Triple::arm).
860         m_triple.setArchName(llvm::StringRef(core_def->name));
861         if (arch_type == eArchTypeMachO) {
862           m_triple.setVendor(llvm::Triple::Apple);
863 
864           // Don't set the OS.  It could be simulator, macosx, ios, watchos,
865           // tvos, bridgeos.  We could get close with the cpu type - but we
866           // can't get it right all of the time.  Better to leave this unset
867           // so other sections of code will set it when they have more
868           // information. NB: don't call m_triple.setOS
869           // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
870           // the ArchSpec::TripleVendorWasSpecified() method says that any
871           // OSName setting means it was specified.
872         } else if (arch_type == eArchTypeELF) {
873           switch (os) {
874           case llvm::ELF::ELFOSABI_AIX:
875             m_triple.setOS(llvm::Triple::OSType::AIX);
876             break;
877           case llvm::ELF::ELFOSABI_FREEBSD:
878             m_triple.setOS(llvm::Triple::OSType::FreeBSD);
879             break;
880           case llvm::ELF::ELFOSABI_GNU:
881             m_triple.setOS(llvm::Triple::OSType::Linux);
882             break;
883           case llvm::ELF::ELFOSABI_NETBSD:
884             m_triple.setOS(llvm::Triple::OSType::NetBSD);
885             break;
886           case llvm::ELF::ELFOSABI_OPENBSD:
887             m_triple.setOS(llvm::Triple::OSType::OpenBSD);
888             break;
889           case llvm::ELF::ELFOSABI_SOLARIS:
890             m_triple.setOS(llvm::Triple::OSType::Solaris);
891             break;
892           }
893         } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
894           m_triple.setVendor(llvm::Triple::PC);
895           m_triple.setOS(llvm::Triple::Win32);
896         } else {
897           m_triple.setVendor(llvm::Triple::UnknownVendor);
898           m_triple.setOS(llvm::Triple::UnknownOS);
899         }
900         // Fall back onto setting the machine type if the arch by name
901         // failed...
902         if (m_triple.getArch() == llvm::Triple::UnknownArch)
903           m_triple.setArch(core_def->machine);
904       }
905     } else {
906       Log *log(GetLog(LLDBLog::Target | LLDBLog::Process | LLDBLog::Platform));
907       LLDB_LOGF(log,
908                 "Unable to find a core definition for cpu 0x%" PRIx32
909                 " sub %" PRId32,
910                 cpu, sub);
911     }
912   }
913   CoreUpdated(update_triple);
914   return IsValid();
915 }
916 
GetMinimumOpcodeByteSize() const917 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
918   const CoreDefinition *core_def = FindCoreDefinition(m_core);
919   if (core_def)
920     return core_def->min_opcode_byte_size;
921   return 0;
922 }
923 
GetMaximumOpcodeByteSize() const924 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
925   const CoreDefinition *core_def = FindCoreDefinition(m_core);
926   if (core_def)
927     return core_def->max_opcode_byte_size;
928   return 0;
929 }
930 
IsExactMatch(const ArchSpec & rhs) const931 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const {
932   return IsEqualTo(rhs, true);
933 }
934 
IsCompatibleMatch(const ArchSpec & rhs) const935 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const {
936   return IsEqualTo(rhs, false);
937 }
938 
IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,llvm::Triple::EnvironmentType rhs)939 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
940                                     llvm::Triple::EnvironmentType rhs) {
941   if (lhs == rhs)
942     return true;
943 
944   // Apple simulators are a different platform than what they simulate.
945   // As the environments are different at this point, if one of them is a
946   // simulator, then they are different.
947   if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
948     return false;
949 
950   // If any of the environment is unknown then they are compatible
951   if (lhs == llvm::Triple::UnknownEnvironment ||
952       rhs == llvm::Triple::UnknownEnvironment)
953     return true;
954 
955   // If one of the environment is Android and the other one is EABI then they
956   // are considered to be compatible. This is required as a workaround for
957   // shared libraries compiled for Android without the NOTE section indicating
958   // that they are using the Android ABI.
959   if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
960       (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
961       (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
962       (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
963       (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
964       (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
965     return true;
966 
967   return false;
968 }
969 
IsEqualTo(const ArchSpec & rhs,bool exact_match) const970 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const {
971   // explicitly ignoring m_distribution_id in this method.
972 
973   if (GetByteOrder() != rhs.GetByteOrder() ||
974       !cores_match(GetCore(), rhs.GetCore(), true, exact_match))
975     return false;
976 
977   const llvm::Triple &lhs_triple = GetTriple();
978   const llvm::Triple &rhs_triple = rhs.GetTriple();
979 
980   const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
981   const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
982 
983   const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
984   const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
985 
986   bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows();
987 
988   // On Windows, the vendor field doesn't have any practical effect, but
989   // it is often set to either "pc" or "w64".
990   if ((lhs_triple_vendor != rhs_triple_vendor) &&
991       (exact_match || !both_windows)) {
992     const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
993     const bool lhs_vendor_specified = TripleVendorWasSpecified();
994     // Both architectures had the vendor specified, so if they aren't equal
995     // then we return false
996     if (rhs_vendor_specified && lhs_vendor_specified)
997       return false;
998 
999     // Only fail if both vendor types are not unknown
1000     if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
1001         rhs_triple_vendor != llvm::Triple::UnknownVendor)
1002       return false;
1003   }
1004 
1005   const llvm::Triple::EnvironmentType lhs_triple_env =
1006       lhs_triple.getEnvironment();
1007   const llvm::Triple::EnvironmentType rhs_triple_env =
1008       rhs_triple.getEnvironment();
1009 
1010   if (!exact_match) {
1011     // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1012     if ((lhs_triple_os == llvm::Triple::IOS &&
1013          lhs_triple_env == llvm::Triple::MacABI &&
1014          rhs_triple_os == llvm::Triple::MacOSX) ||
1015         (lhs_triple_os == llvm::Triple::MacOSX &&
1016          rhs_triple_os == llvm::Triple::IOS &&
1017          rhs_triple_env == llvm::Triple::MacABI))
1018       return true;
1019   }
1020 
1021   // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1022   if (lhs_triple_os == llvm::Triple::IOS &&
1023       rhs_triple_os == llvm::Triple::IOS &&
1024       (lhs_triple_env == llvm::Triple::MacABI ||
1025        rhs_triple_env == llvm::Triple::MacABI) &&
1026       lhs_triple_env != rhs_triple_env)
1027     return false;
1028 
1029   if (lhs_triple_os != rhs_triple_os) {
1030     const bool lhs_os_specified = TripleOSWasSpecified();
1031     const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1032     // If both OS types are specified and different, fail.
1033     if (lhs_os_specified && rhs_os_specified)
1034       return false;
1035 
1036     // If the pair of os+env is both unspecified, match any other os+env combo.
1037     if (!exact_match && ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1038                          (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1039       return true;
1040   }
1041 
1042   if (!exact_match && both_windows)
1043     return true; // The Windows environments (MSVC vs GNU) are compatible
1044 
1045   return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1046 }
1047 
UpdateCore()1048 void ArchSpec::UpdateCore() {
1049   llvm::StringRef arch_name(m_triple.getArchName());
1050   const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1051   if (core_def) {
1052     m_core = core_def->core;
1053     // Set the byte order to the default byte order for an architecture. This
1054     // can be modified if needed for cases when cores handle both big and
1055     // little endian
1056     m_byte_order = core_def->default_byte_order;
1057   } else {
1058     Clear();
1059   }
1060 }
1061 
1062 //===----------------------------------------------------------------------===//
1063 // Helper methods.
1064 
CoreUpdated(bool update_triple)1065 void ArchSpec::CoreUpdated(bool update_triple) {
1066   const CoreDefinition *core_def = FindCoreDefinition(m_core);
1067   if (core_def) {
1068     if (update_triple)
1069       m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1070     m_byte_order = core_def->default_byte_order;
1071   } else {
1072     if (update_triple)
1073       m_triple = llvm::Triple();
1074     m_byte_order = eByteOrderInvalid;
1075   }
1076 }
1077 
1078 //===----------------------------------------------------------------------===//
1079 // Operators.
1080 
cores_match(const ArchSpec::Core core1,const ArchSpec::Core core2,bool try_inverse,bool enforce_exact_match)1081 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1082                         bool try_inverse, bool enforce_exact_match) {
1083   if (core1 == core2)
1084     return true;
1085 
1086   switch (core1) {
1087   case ArchSpec::kCore_any:
1088     return true;
1089 
1090   case ArchSpec::eCore_arm_generic:
1091     if (enforce_exact_match)
1092       break;
1093     LLVM_FALLTHROUGH;
1094   case ArchSpec::kCore_arm_any:
1095     if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1096       return true;
1097     if (core2 >= ArchSpec::kCore_thumb_first &&
1098         core2 <= ArchSpec::kCore_thumb_last)
1099       return true;
1100     if (core2 == ArchSpec::kCore_arm_any)
1101       return true;
1102     break;
1103 
1104   case ArchSpec::kCore_x86_32_any:
1105     if ((core2 >= ArchSpec::kCore_x86_32_first &&
1106          core2 <= ArchSpec::kCore_x86_32_last) ||
1107         (core2 == ArchSpec::kCore_x86_32_any))
1108       return true;
1109     break;
1110 
1111   case ArchSpec::kCore_x86_64_any:
1112     if ((core2 >= ArchSpec::kCore_x86_64_first &&
1113          core2 <= ArchSpec::kCore_x86_64_last) ||
1114         (core2 == ArchSpec::kCore_x86_64_any))
1115       return true;
1116     break;
1117 
1118   case ArchSpec::kCore_ppc_any:
1119     if ((core2 >= ArchSpec::kCore_ppc_first &&
1120          core2 <= ArchSpec::kCore_ppc_last) ||
1121         (core2 == ArchSpec::kCore_ppc_any))
1122       return true;
1123     break;
1124 
1125   case ArchSpec::kCore_ppc64_any:
1126     if ((core2 >= ArchSpec::kCore_ppc64_first &&
1127          core2 <= ArchSpec::kCore_ppc64_last) ||
1128         (core2 == ArchSpec::kCore_ppc64_any))
1129       return true;
1130     break;
1131 
1132   case ArchSpec::kCore_hexagon_any:
1133     if ((core2 >= ArchSpec::kCore_hexagon_first &&
1134          core2 <= ArchSpec::kCore_hexagon_last) ||
1135         (core2 == ArchSpec::kCore_hexagon_any))
1136       return true;
1137     break;
1138 
1139   // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1140   // Cortex-M0 - ARMv6-M - armv6m
1141   // Cortex-M3 - ARMv7-M - armv7m
1142   // Cortex-M4 - ARMv7E-M - armv7em
1143   case ArchSpec::eCore_arm_armv7em:
1144     if (!enforce_exact_match) {
1145       if (core2 == ArchSpec::eCore_arm_generic)
1146         return true;
1147       if (core2 == ArchSpec::eCore_arm_armv7m)
1148         return true;
1149       if (core2 == ArchSpec::eCore_arm_armv6m)
1150         return true;
1151       if (core2 == ArchSpec::eCore_arm_armv7)
1152         return true;
1153       try_inverse = true;
1154     }
1155     break;
1156 
1157   // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1158   // Cortex-M0 - ARMv6-M - armv6m
1159   // Cortex-M3 - ARMv7-M - armv7m
1160   // Cortex-M4 - ARMv7E-M - armv7em
1161   case ArchSpec::eCore_arm_armv7m:
1162     if (!enforce_exact_match) {
1163       if (core2 == ArchSpec::eCore_arm_generic)
1164         return true;
1165       if (core2 == ArchSpec::eCore_arm_armv6m)
1166         return true;
1167       if (core2 == ArchSpec::eCore_arm_armv7)
1168         return true;
1169       if (core2 == ArchSpec::eCore_arm_armv7em)
1170         return true;
1171       try_inverse = true;
1172     }
1173     break;
1174 
1175   // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1176   // Cortex-M0 - ARMv6-M - armv6m
1177   // Cortex-M3 - ARMv7-M - armv7m
1178   // Cortex-M4 - ARMv7E-M - armv7em
1179   case ArchSpec::eCore_arm_armv6m:
1180     if (!enforce_exact_match) {
1181       if (core2 == ArchSpec::eCore_arm_generic)
1182         return true;
1183       if (core2 == ArchSpec::eCore_arm_armv7em)
1184         return true;
1185       if (core2 == ArchSpec::eCore_arm_armv7)
1186         return true;
1187       if (core2 == ArchSpec::eCore_arm_armv6m)
1188         return true;
1189       try_inverse = false;
1190     }
1191     break;
1192 
1193   case ArchSpec::eCore_arm_armv7f:
1194   case ArchSpec::eCore_arm_armv7k:
1195   case ArchSpec::eCore_arm_armv7s:
1196   case ArchSpec::eCore_arm_armv7l:
1197   case ArchSpec::eCore_arm_armv8l:
1198     if (!enforce_exact_match) {
1199       if (core2 == ArchSpec::eCore_arm_generic)
1200         return true;
1201       if (core2 == ArchSpec::eCore_arm_armv7)
1202         return true;
1203       try_inverse = false;
1204     }
1205     break;
1206 
1207   case ArchSpec::eCore_x86_64_x86_64h:
1208     if (!enforce_exact_match) {
1209       try_inverse = false;
1210       if (core2 == ArchSpec::eCore_x86_64_x86_64)
1211         return true;
1212     }
1213     break;
1214 
1215   case ArchSpec::eCore_arm_armv8:
1216     if (!enforce_exact_match) {
1217       if (core2 == ArchSpec::eCore_arm_arm64)
1218         return true;
1219       if (core2 == ArchSpec::eCore_arm_aarch64)
1220         return true;
1221       if (core2 == ArchSpec::eCore_arm_arm64e)
1222         return true;
1223       try_inverse = false;
1224     }
1225     break;
1226 
1227   case ArchSpec::eCore_arm_arm64e:
1228     if (!enforce_exact_match) {
1229       if (core2 == ArchSpec::eCore_arm_arm64)
1230         return true;
1231       if (core2 == ArchSpec::eCore_arm_aarch64)
1232         return true;
1233       if (core2 == ArchSpec::eCore_arm_armv8)
1234         return true;
1235       try_inverse = false;
1236     }
1237     break;
1238   case ArchSpec::eCore_arm_aarch64:
1239     if (!enforce_exact_match) {
1240       if (core2 == ArchSpec::eCore_arm_arm64)
1241         return true;
1242       if (core2 == ArchSpec::eCore_arm_armv8)
1243         return true;
1244       if (core2 == ArchSpec::eCore_arm_arm64e)
1245         return true;
1246       try_inverse = false;
1247     }
1248     break;
1249 
1250   case ArchSpec::eCore_arm_arm64:
1251     if (!enforce_exact_match) {
1252       if (core2 == ArchSpec::eCore_arm_aarch64)
1253         return true;
1254       if (core2 == ArchSpec::eCore_arm_armv8)
1255         return true;
1256       if (core2 == ArchSpec::eCore_arm_arm64e)
1257         return true;
1258       try_inverse = false;
1259     }
1260     break;
1261 
1262   case ArchSpec::eCore_arm_arm64_32:
1263     if (!enforce_exact_match) {
1264       if (core2 == ArchSpec::eCore_arm_generic)
1265         return true;
1266       try_inverse = false;
1267     }
1268     break;
1269 
1270   case ArchSpec::eCore_mips32:
1271     if (!enforce_exact_match) {
1272       if (core2 >= ArchSpec::kCore_mips32_first &&
1273           core2 <= ArchSpec::kCore_mips32_last)
1274         return true;
1275       try_inverse = false;
1276     }
1277     break;
1278 
1279   case ArchSpec::eCore_mips32el:
1280     if (!enforce_exact_match) {
1281       if (core2 >= ArchSpec::kCore_mips32el_first &&
1282           core2 <= ArchSpec::kCore_mips32el_last)
1283         return true;
1284       try_inverse = true;
1285     }
1286     break;
1287 
1288   case ArchSpec::eCore_mips64:
1289     if (!enforce_exact_match) {
1290       if (core2 >= ArchSpec::kCore_mips32_first &&
1291           core2 <= ArchSpec::kCore_mips32_last)
1292         return true;
1293       if (core2 >= ArchSpec::kCore_mips64_first &&
1294           core2 <= ArchSpec::kCore_mips64_last)
1295         return true;
1296       try_inverse = false;
1297     }
1298     break;
1299 
1300   case ArchSpec::eCore_mips64el:
1301     if (!enforce_exact_match) {
1302       if (core2 >= ArchSpec::kCore_mips32el_first &&
1303           core2 <= ArchSpec::kCore_mips32el_last)
1304         return true;
1305       if (core2 >= ArchSpec::kCore_mips64el_first &&
1306           core2 <= ArchSpec::kCore_mips64el_last)
1307         return true;
1308       try_inverse = false;
1309     }
1310     break;
1311 
1312   case ArchSpec::eCore_mips64r2:
1313   case ArchSpec::eCore_mips64r3:
1314   case ArchSpec::eCore_mips64r5:
1315     if (!enforce_exact_match) {
1316       if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1317         return true;
1318       if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1319         return true;
1320       try_inverse = false;
1321     }
1322     break;
1323 
1324   case ArchSpec::eCore_mips64r2el:
1325   case ArchSpec::eCore_mips64r3el:
1326   case ArchSpec::eCore_mips64r5el:
1327     if (!enforce_exact_match) {
1328       if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1329         return true;
1330       if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1331         return true;
1332       try_inverse = false;
1333     }
1334     break;
1335 
1336   case ArchSpec::eCore_mips32r2:
1337   case ArchSpec::eCore_mips32r3:
1338   case ArchSpec::eCore_mips32r5:
1339     if (!enforce_exact_match) {
1340       if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1341         return true;
1342     }
1343     break;
1344 
1345   case ArchSpec::eCore_mips32r2el:
1346   case ArchSpec::eCore_mips32r3el:
1347   case ArchSpec::eCore_mips32r5el:
1348     if (!enforce_exact_match) {
1349       if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1350         return true;
1351     }
1352     break;
1353 
1354   case ArchSpec::eCore_mips32r6:
1355     if (!enforce_exact_match) {
1356       if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1357         return true;
1358     }
1359     break;
1360 
1361   case ArchSpec::eCore_mips32r6el:
1362     if (!enforce_exact_match) {
1363       if (core2 == ArchSpec::eCore_mips32el ||
1364           core2 == ArchSpec::eCore_mips32r6el)
1365         return true;
1366     }
1367     break;
1368 
1369   case ArchSpec::eCore_mips64r6:
1370     if (!enforce_exact_match) {
1371       if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1372         return true;
1373       if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1374         return true;
1375     }
1376     break;
1377 
1378   case ArchSpec::eCore_mips64r6el:
1379     if (!enforce_exact_match) {
1380       if (core2 == ArchSpec::eCore_mips32el ||
1381           core2 == ArchSpec::eCore_mips32r6el)
1382         return true;
1383       if (core2 == ArchSpec::eCore_mips64el ||
1384           core2 == ArchSpec::eCore_mips64r6el)
1385         return true;
1386     }
1387     break;
1388 
1389   default:
1390     break;
1391   }
1392   if (try_inverse)
1393     return cores_match(core2, core1, false, enforce_exact_match);
1394   return false;
1395 }
1396 
operator <(const ArchSpec & lhs,const ArchSpec & rhs)1397 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1398   const ArchSpec::Core lhs_core = lhs.GetCore();
1399   const ArchSpec::Core rhs_core = rhs.GetCore();
1400   return lhs_core < rhs_core;
1401 }
1402 
1403 
operator ==(const ArchSpec & lhs,const ArchSpec & rhs)1404 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1405   return lhs.GetCore() == rhs.GetCore();
1406 }
1407 
IsFullySpecifiedTriple() const1408 bool ArchSpec::IsFullySpecifiedTriple() const {
1409   if (!TripleOSWasSpecified())
1410     return false;
1411 
1412   if (!TripleVendorWasSpecified())
1413     return false;
1414 
1415   const unsigned unspecified = 0;
1416   const llvm::Triple &triple = GetTriple();
1417   if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified)
1418     return false;
1419 
1420   return true;
1421 }
1422 
PiecewiseTripleCompare(const ArchSpec & other,bool & arch_different,bool & vendor_different,bool & os_different,bool & os_version_different,bool & env_different) const1423 void ArchSpec::PiecewiseTripleCompare(
1424     const ArchSpec &other, bool &arch_different, bool &vendor_different,
1425     bool &os_different, bool &os_version_different, bool &env_different) const {
1426   const llvm::Triple &me(GetTriple());
1427   const llvm::Triple &them(other.GetTriple());
1428 
1429   arch_different = (me.getArch() != them.getArch());
1430 
1431   vendor_different = (me.getVendor() != them.getVendor());
1432 
1433   os_different = (me.getOS() != them.getOS());
1434 
1435   os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1436 
1437   env_different = (me.getEnvironment() != them.getEnvironment());
1438 }
1439 
IsAlwaysThumbInstructions() const1440 bool ArchSpec::IsAlwaysThumbInstructions() const {
1441   std::string Status;
1442   if (GetTriple().getArch() == llvm::Triple::arm ||
1443       GetTriple().getArch() == llvm::Triple::thumb) {
1444     // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1445     //
1446     // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1447     // execute thumb instructions.  We map the cores to arch names like this:
1448     //
1449     // Cortex-M0, Cortex-M0+, Cortex-M1:  armv6m Cortex-M3: armv7m Cortex-M4,
1450     // Cortex-M7: armv7em
1451 
1452     if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1453         GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1454         GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1455         GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1456         GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1457         GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1458       return true;
1459     }
1460     // Windows on ARM is always thumb.
1461     if (GetTriple().isOSWindows())
1462       return true;
1463   }
1464   return false;
1465 }
1466 
DumpTriple(llvm::raw_ostream & s) const1467 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1468   const llvm::Triple &triple = GetTriple();
1469   llvm::StringRef arch_str = triple.getArchName();
1470   llvm::StringRef vendor_str = triple.getVendorName();
1471   llvm::StringRef os_str = triple.getOSName();
1472   llvm::StringRef environ_str = triple.getEnvironmentName();
1473 
1474   s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1475                      vendor_str.empty() ? "*" : vendor_str,
1476                      os_str.empty() ? "*" : os_str);
1477 
1478   if (!environ_str.empty())
1479     s << "-" << environ_str;
1480 }
1481 
output(const ArchSpec & Val,void *,raw_ostream & Out)1482 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *,
1483                                                 raw_ostream &Out) {
1484   Val.DumpTriple(Out);
1485 }
1486 
1487 llvm::StringRef
input(llvm::StringRef Scalar,void *,ArchSpec & Val)1488 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *,
1489                                           ArchSpec &Val) {
1490   Val = ArchSpec(Scalar);
1491   return {};
1492 }
1493