1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/StringList.h" 13 #include "lldb/lldb-defines.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/BinaryFormat/COFF.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Compiler.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26 namespace lldb_private { 27 28 struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36 }; 37 38 } // namespace lldb_private 39 40 // This core information can be looked using the ArchSpec::Core as the index 41 static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 103 ArchSpec::eCore_arm_armv8l, "armv8l"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_generic, "hexagon"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 214 215 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 217 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 219 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 220 221 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 222 "wasm32"}, 223 }; 224 225 // Ensure that we have an entry in the g_core_definitions for each core. If you 226 // comment out an entry above, you will need to comment out the corresponding 227 // ArchSpec::Core enumeration. 228 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 229 ArchSpec::kNumCores, 230 "make sure we have one core definition for each core"); 231 232 struct ArchDefinitionEntry { 233 ArchSpec::Core core; 234 uint32_t cpu; 235 uint32_t sub; 236 uint32_t cpu_mask; 237 uint32_t sub_mask; 238 }; 239 240 struct ArchDefinition { 241 ArchitectureType type; 242 size_t num_entries; 243 const ArchDefinitionEntry *entries; 244 const char *name; 245 }; 246 247 void ArchSpec::ListSupportedArchNames(StringList &list) { 248 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 249 list.AppendString(g_core_definitions[i].name); 250 } 251 252 void ArchSpec::AutoComplete(CompletionRequest &request) { 253 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 254 request.TryCompleteCurrentArg(g_core_definitions[i].name); 255 } 256 257 #define CPU_ANY (UINT32_MAX) 258 259 //===----------------------------------------------------------------------===// 260 // A table that gets searched linearly for matches. This table is used to 261 // convert cpu type and subtypes to architecture names, and to convert 262 // architecture names to cpu types and subtypes. The ordering is important and 263 // allows the precedence to be set when the table is built. 264 #define SUBTYPE_MASK 0x00FFFFFFu 265 266 static const ArchDefinitionEntry g_macho_arch_entries[] = { 267 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 268 UINT32_MAX, UINT32_MAX}, 269 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 270 SUBTYPE_MASK}, 271 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 272 SUBTYPE_MASK}, 273 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 302 SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 306 UINT32_MAX, SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 308 UINT32_MAX, SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 310 UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 312 SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 314 SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 336 UINT32_MAX, UINT32_MAX}, 337 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 340 SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 364 UINT32_MAX, SUBTYPE_MASK}, 365 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 366 UINT32_MAX, SUBTYPE_MASK}, 367 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 368 UINT32_MAX, SUBTYPE_MASK}, 369 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 370 SUBTYPE_MASK}, 371 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 372 SUBTYPE_MASK}, 373 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 374 UINT32_MAX, SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 376 UINT32_MAX, UINT32_MAX}, 377 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 378 SUBTYPE_MASK}, 379 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 380 SUBTYPE_MASK}, 381 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 382 UINT32_MAX, SUBTYPE_MASK}, 383 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 384 UINT32_MAX, UINT32_MAX}, 385 // Catch any unknown mach architectures so we can always use the object and 386 // symbol mach-o files 387 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 388 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 389 0x00000000u}}; 390 391 static const ArchDefinition g_macho_arch_def = { 392 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 393 g_macho_arch_entries, "mach-o"}; 394 395 //===----------------------------------------------------------------------===// 396 // A table that gets searched linearly for matches. This table is used to 397 // convert cpu type and subtypes to architecture names, and to convert 398 // architecture names to cpu types and subtypes. The ordering is important and 399 // allows the precedence to be set when the table is built. 400 static const ArchDefinitionEntry g_elf_arch_entries[] = { 401 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 402 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 403 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 404 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 405 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 407 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 409 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 411 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 413 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 415 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 416 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 417 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 419 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 420 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 421 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 422 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 423 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 424 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 425 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 426 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 427 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 428 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 429 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 431 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 433 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 435 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 436 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 437 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 438 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 439 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 440 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 441 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 442 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 443 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 444 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 445 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 446 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 447 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 448 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 449 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 450 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 451 }; 452 453 static const ArchDefinition g_elf_arch_def = { 454 eArchTypeELF, 455 llvm::array_lengthof(g_elf_arch_entries), 456 g_elf_arch_entries, 457 "elf", 458 }; 459 460 static const ArchDefinitionEntry g_coff_arch_entries[] = { 461 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 462 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 463 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 464 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 465 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 466 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 467 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 468 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 469 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 470 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 471 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 472 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 473 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 474 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 475 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 476 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 477 }; 478 479 static const ArchDefinition g_coff_arch_def = { 480 eArchTypeCOFF, 481 llvm::array_lengthof(g_coff_arch_entries), 482 g_coff_arch_entries, 483 "pe-coff", 484 }; 485 486 //===----------------------------------------------------------------------===// 487 // Table of all ArchDefinitions 488 static const ArchDefinition *g_arch_definitions[] = { 489 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 490 491 static const size_t k_num_arch_definitions = 492 llvm::array_lengthof(g_arch_definitions); 493 494 //===----------------------------------------------------------------------===// 495 // Static helper functions. 496 497 // Get the architecture definition for a given object type. 498 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 499 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 500 const ArchDefinition *def = g_arch_definitions[i]; 501 if (def->type == arch_type) 502 return def; 503 } 504 return nullptr; 505 } 506 507 // Get an architecture definition by name. 508 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 509 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 510 if (name.equals_lower(g_core_definitions[i].name)) 511 return &g_core_definitions[i]; 512 } 513 return nullptr; 514 } 515 516 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 517 if (core < llvm::array_lengthof(g_core_definitions)) 518 return &g_core_definitions[core]; 519 return nullptr; 520 } 521 522 // Get a definition entry by cpu type and subtype. 523 static const ArchDefinitionEntry * 524 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 525 if (def == nullptr) 526 return nullptr; 527 528 const ArchDefinitionEntry *entries = def->entries; 529 for (size_t i = 0; i < def->num_entries; ++i) { 530 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 531 if (entries[i].sub == (sub & entries[i].sub_mask)) 532 return &entries[i]; 533 } 534 return nullptr; 535 } 536 537 static const ArchDefinitionEntry * 538 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 539 if (def == nullptr) 540 return nullptr; 541 542 const ArchDefinitionEntry *entries = def->entries; 543 for (size_t i = 0; i < def->num_entries; ++i) { 544 if (entries[i].core == core) 545 return &entries[i]; 546 } 547 return nullptr; 548 } 549 550 //===----------------------------------------------------------------------===// 551 // Constructors and destructors. 552 553 ArchSpec::ArchSpec() {} 554 555 ArchSpec::ArchSpec(const char *triple_cstr) { 556 if (triple_cstr) 557 SetTriple(triple_cstr); 558 } 559 560 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 561 562 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 563 564 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 565 SetArchitecture(arch_type, cpu, subtype); 566 } 567 568 ArchSpec::~ArchSpec() = default; 569 570 void ArchSpec::Clear() { 571 m_triple = llvm::Triple(); 572 m_core = kCore_invalid; 573 m_byte_order = eByteOrderInvalid; 574 m_distribution_id.Clear(); 575 m_flags = 0; 576 } 577 578 //===----------------------------------------------------------------------===// 579 // Predicates. 580 581 const char *ArchSpec::GetArchitectureName() const { 582 const CoreDefinition *core_def = FindCoreDefinition(m_core); 583 if (core_def) 584 return core_def->name; 585 return "unknown"; 586 } 587 588 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 589 590 std::string ArchSpec::GetTargetABI() const { 591 592 std::string abi; 593 594 if (IsMIPS()) { 595 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 596 case ArchSpec::eMIPSABI_N64: 597 abi = "n64"; 598 return abi; 599 case ArchSpec::eMIPSABI_N32: 600 abi = "n32"; 601 return abi; 602 case ArchSpec::eMIPSABI_O32: 603 abi = "o32"; 604 return abi; 605 default: 606 return abi; 607 } 608 } 609 return abi; 610 } 611 612 void ArchSpec::SetFlags(std::string elf_abi) { 613 614 uint32_t flag = GetFlags(); 615 if (IsMIPS()) { 616 if (elf_abi == "n64") 617 flag |= ArchSpec::eMIPSABI_N64; 618 else if (elf_abi == "n32") 619 flag |= ArchSpec::eMIPSABI_N32; 620 else if (elf_abi == "o32") 621 flag |= ArchSpec::eMIPSABI_O32; 622 } 623 SetFlags(flag); 624 } 625 626 std::string ArchSpec::GetClangTargetCPU() const { 627 std::string cpu; 628 629 if (IsMIPS()) { 630 switch (m_core) { 631 case ArchSpec::eCore_mips32: 632 case ArchSpec::eCore_mips32el: 633 cpu = "mips32"; 634 break; 635 case ArchSpec::eCore_mips32r2: 636 case ArchSpec::eCore_mips32r2el: 637 cpu = "mips32r2"; 638 break; 639 case ArchSpec::eCore_mips32r3: 640 case ArchSpec::eCore_mips32r3el: 641 cpu = "mips32r3"; 642 break; 643 case ArchSpec::eCore_mips32r5: 644 case ArchSpec::eCore_mips32r5el: 645 cpu = "mips32r5"; 646 break; 647 case ArchSpec::eCore_mips32r6: 648 case ArchSpec::eCore_mips32r6el: 649 cpu = "mips32r6"; 650 break; 651 case ArchSpec::eCore_mips64: 652 case ArchSpec::eCore_mips64el: 653 cpu = "mips64"; 654 break; 655 case ArchSpec::eCore_mips64r2: 656 case ArchSpec::eCore_mips64r2el: 657 cpu = "mips64r2"; 658 break; 659 case ArchSpec::eCore_mips64r3: 660 case ArchSpec::eCore_mips64r3el: 661 cpu = "mips64r3"; 662 break; 663 case ArchSpec::eCore_mips64r5: 664 case ArchSpec::eCore_mips64r5el: 665 cpu = "mips64r5"; 666 break; 667 case ArchSpec::eCore_mips64r6: 668 case ArchSpec::eCore_mips64r6el: 669 cpu = "mips64r6"; 670 break; 671 default: 672 break; 673 } 674 } 675 return cpu; 676 } 677 678 uint32_t ArchSpec::GetMachOCPUType() const { 679 const CoreDefinition *core_def = FindCoreDefinition(m_core); 680 if (core_def) { 681 const ArchDefinitionEntry *arch_def = 682 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 683 if (arch_def) { 684 return arch_def->cpu; 685 } 686 } 687 return LLDB_INVALID_CPUTYPE; 688 } 689 690 uint32_t ArchSpec::GetMachOCPUSubType() const { 691 const CoreDefinition *core_def = FindCoreDefinition(m_core); 692 if (core_def) { 693 const ArchDefinitionEntry *arch_def = 694 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 695 if (arch_def) { 696 return arch_def->sub; 697 } 698 } 699 return LLDB_INVALID_CPUTYPE; 700 } 701 702 uint32_t ArchSpec::GetDataByteSize() const { 703 return 1; 704 } 705 706 uint32_t ArchSpec::GetCodeByteSize() const { 707 return 1; 708 } 709 710 llvm::Triple::ArchType ArchSpec::GetMachine() const { 711 const CoreDefinition *core_def = FindCoreDefinition(m_core); 712 if (core_def) 713 return core_def->machine; 714 715 return llvm::Triple::UnknownArch; 716 } 717 718 ConstString ArchSpec::GetDistributionId() const { 719 return m_distribution_id; 720 } 721 722 void ArchSpec::SetDistributionId(const char *distribution_id) { 723 m_distribution_id.SetCString(distribution_id); 724 } 725 726 uint32_t ArchSpec::GetAddressByteSize() const { 727 const CoreDefinition *core_def = FindCoreDefinition(m_core); 728 if (core_def) { 729 if (core_def->machine == llvm::Triple::mips64 || 730 core_def->machine == llvm::Triple::mips64el) { 731 // For N32/O32 applications Address size is 4 bytes. 732 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 733 return 4; 734 } 735 return core_def->addr_byte_size; 736 } 737 return 0; 738 } 739 740 ByteOrder ArchSpec::GetDefaultEndian() const { 741 const CoreDefinition *core_def = FindCoreDefinition(m_core); 742 if (core_def) 743 return core_def->default_byte_order; 744 return eByteOrderInvalid; 745 } 746 747 bool ArchSpec::CharIsSignedByDefault() const { 748 switch (m_triple.getArch()) { 749 default: 750 return true; 751 752 case llvm::Triple::aarch64: 753 case llvm::Triple::aarch64_32: 754 case llvm::Triple::aarch64_be: 755 case llvm::Triple::arm: 756 case llvm::Triple::armeb: 757 case llvm::Triple::thumb: 758 case llvm::Triple::thumbeb: 759 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 760 761 case llvm::Triple::ppc: 762 case llvm::Triple::ppc64: 763 return m_triple.isOSDarwin(); 764 765 case llvm::Triple::ppc64le: 766 case llvm::Triple::systemz: 767 case llvm::Triple::xcore: 768 case llvm::Triple::arc: 769 return false; 770 } 771 } 772 773 lldb::ByteOrder ArchSpec::GetByteOrder() const { 774 if (m_byte_order == eByteOrderInvalid) 775 return GetDefaultEndian(); 776 return m_byte_order; 777 } 778 779 //===----------------------------------------------------------------------===// 780 // Mutators. 781 782 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 783 m_triple = triple; 784 UpdateCore(); 785 return IsValid(); 786 } 787 788 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 789 ArchSpec &arch) { 790 // Accept "12-10" or "12.10" as cpu type/subtype 791 if (triple_str.empty()) 792 return false; 793 794 size_t pos = triple_str.find_first_of("-."); 795 if (pos == llvm::StringRef::npos) 796 return false; 797 798 llvm::StringRef cpu_str = triple_str.substr(0, pos); 799 llvm::StringRef remainder = triple_str.substr(pos + 1); 800 if (cpu_str.empty() || remainder.empty()) 801 return false; 802 803 llvm::StringRef sub_str; 804 llvm::StringRef vendor; 805 llvm::StringRef os; 806 std::tie(sub_str, remainder) = remainder.split('-'); 807 std::tie(vendor, os) = remainder.split('-'); 808 809 uint32_t cpu = 0; 810 uint32_t sub = 0; 811 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 812 return false; 813 814 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 815 return false; 816 if (!vendor.empty() && !os.empty()) { 817 arch.GetTriple().setVendorName(vendor); 818 arch.GetTriple().setOSName(os); 819 } 820 821 return true; 822 } 823 824 bool ArchSpec::SetTriple(llvm::StringRef triple) { 825 if (triple.empty()) { 826 Clear(); 827 return false; 828 } 829 830 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 831 return true; 832 833 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 834 return IsValid(); 835 } 836 837 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 838 return !normalized_triple.getArchName().empty() && 839 normalized_triple.getOSName().empty() && 840 normalized_triple.getVendorName().empty() && 841 normalized_triple.getEnvironmentName().empty(); 842 } 843 844 void ArchSpec::MergeFrom(const ArchSpec &other) { 845 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 846 GetTriple().setVendor(other.GetTriple().getVendor()); 847 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 848 GetTriple().setOS(other.GetTriple().getOS()); 849 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 850 GetTriple().setArch(other.GetTriple().getArch()); 851 852 // MachO unknown64 isn't really invalid as the debugger can still obtain 853 // information from the binary, e.g. line tables. As such, we don't update 854 // the core here. 855 if (other.GetCore() != eCore_uknownMach64) 856 UpdateCore(); 857 } 858 if (!TripleEnvironmentWasSpecified() && 859 other.TripleEnvironmentWasSpecified()) { 860 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 861 } 862 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 863 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 864 // adopt the specific arm core. 865 if (GetTriple().getArch() == llvm::Triple::arm && 866 other.GetTriple().getArch() == llvm::Triple::arm && 867 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 868 other.GetCore() != ArchSpec::eCore_arm_generic) { 869 m_core = other.GetCore(); 870 CoreUpdated(false); 871 } 872 if (GetFlags() == 0) { 873 SetFlags(other.GetFlags()); 874 } 875 } 876 877 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 878 uint32_t sub, uint32_t os) { 879 m_core = kCore_invalid; 880 bool update_triple = true; 881 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 882 if (arch_def) { 883 const ArchDefinitionEntry *arch_def_entry = 884 FindArchDefinitionEntry(arch_def, cpu, sub); 885 if (arch_def_entry) { 886 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 887 if (core_def) { 888 m_core = core_def->core; 889 update_triple = false; 890 // Always use the architecture name because it might be more 891 // descriptive than the architecture enum ("armv7" -> 892 // llvm::Triple::arm). 893 m_triple.setArchName(llvm::StringRef(core_def->name)); 894 if (arch_type == eArchTypeMachO) { 895 m_triple.setVendor(llvm::Triple::Apple); 896 897 // Don't set the OS. It could be simulator, macosx, ios, watchos, 898 // tvos, bridgeos. We could get close with the cpu type - but we 899 // can't get it right all of the time. Better to leave this unset 900 // so other sections of code will set it when they have more 901 // information. NB: don't call m_triple.setOS 902 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 903 // the ArchSpec::TripleVendorWasSpecified() method says that any 904 // OSName setting means it was specified. 905 } else if (arch_type == eArchTypeELF) { 906 switch (os) { 907 case llvm::ELF::ELFOSABI_AIX: 908 m_triple.setOS(llvm::Triple::OSType::AIX); 909 break; 910 case llvm::ELF::ELFOSABI_FREEBSD: 911 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 912 break; 913 case llvm::ELF::ELFOSABI_GNU: 914 m_triple.setOS(llvm::Triple::OSType::Linux); 915 break; 916 case llvm::ELF::ELFOSABI_NETBSD: 917 m_triple.setOS(llvm::Triple::OSType::NetBSD); 918 break; 919 case llvm::ELF::ELFOSABI_OPENBSD: 920 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 921 break; 922 case llvm::ELF::ELFOSABI_SOLARIS: 923 m_triple.setOS(llvm::Triple::OSType::Solaris); 924 break; 925 } 926 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 927 m_triple.setVendor(llvm::Triple::PC); 928 m_triple.setOS(llvm::Triple::Win32); 929 } else { 930 m_triple.setVendor(llvm::Triple::UnknownVendor); 931 m_triple.setOS(llvm::Triple::UnknownOS); 932 } 933 // Fall back onto setting the machine type if the arch by name 934 // failed... 935 if (m_triple.getArch() == llvm::Triple::UnknownArch) 936 m_triple.setArch(core_def->machine); 937 } 938 } else { 939 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 940 LLDB_LOGF(log, 941 "Unable to find a core definition for cpu 0x%" PRIx32 942 " sub %" PRId32, 943 cpu, sub); 944 } 945 } 946 CoreUpdated(update_triple); 947 return IsValid(); 948 } 949 950 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 951 const CoreDefinition *core_def = FindCoreDefinition(m_core); 952 if (core_def) 953 return core_def->min_opcode_byte_size; 954 return 0; 955 } 956 957 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 958 const CoreDefinition *core_def = FindCoreDefinition(m_core); 959 if (core_def) 960 return core_def->max_opcode_byte_size; 961 return 0; 962 } 963 964 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 965 return IsEqualTo(rhs, true); 966 } 967 968 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 969 return IsEqualTo(rhs, false); 970 } 971 972 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 973 llvm::Triple::EnvironmentType rhs) { 974 if (lhs == rhs) 975 return true; 976 977 // If any of the environment is unknown then they are compatible 978 if (lhs == llvm::Triple::UnknownEnvironment || 979 rhs == llvm::Triple::UnknownEnvironment) 980 return true; 981 982 // If one of the environment is Android and the other one is EABI then they 983 // are considered to be compatible. This is required as a workaround for 984 // shared libraries compiled for Android without the NOTE section indicating 985 // that they are using the Android ABI. 986 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 987 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 988 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 989 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 990 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 991 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 992 return true; 993 994 return false; 995 } 996 997 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 998 // explicitly ignoring m_distribution_id in this method. 999 1000 if (GetByteOrder() != rhs.GetByteOrder()) 1001 return false; 1002 1003 const ArchSpec::Core lhs_core = GetCore(); 1004 const ArchSpec::Core rhs_core = rhs.GetCore(); 1005 1006 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1007 1008 if (core_match) { 1009 const llvm::Triple &lhs_triple = GetTriple(); 1010 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1011 1012 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1013 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1014 if (lhs_triple_vendor != rhs_triple_vendor) { 1015 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1016 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1017 // Both architectures had the vendor specified, so if they aren't equal 1018 // then we return false 1019 if (rhs_vendor_specified && lhs_vendor_specified) 1020 return false; 1021 1022 // Only fail if both vendor types are not unknown 1023 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1024 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1025 return false; 1026 } 1027 1028 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1029 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1030 if (lhs_triple_os != rhs_triple_os) { 1031 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1032 const bool lhs_os_specified = TripleOSWasSpecified(); 1033 // Both architectures had the OS specified, so if they aren't equal then 1034 // we return false 1035 if (rhs_os_specified && lhs_os_specified) 1036 return false; 1037 1038 // Only fail if both os types are not unknown 1039 if (lhs_triple_os != llvm::Triple::UnknownOS && 1040 rhs_triple_os != llvm::Triple::UnknownOS) 1041 return false; 1042 } 1043 1044 const llvm::Triple::EnvironmentType lhs_triple_env = 1045 lhs_triple.getEnvironment(); 1046 const llvm::Triple::EnvironmentType rhs_triple_env = 1047 rhs_triple.getEnvironment(); 1048 1049 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1050 } 1051 return false; 1052 } 1053 1054 void ArchSpec::UpdateCore() { 1055 llvm::StringRef arch_name(m_triple.getArchName()); 1056 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1057 if (core_def) { 1058 m_core = core_def->core; 1059 // Set the byte order to the default byte order for an architecture. This 1060 // can be modified if needed for cases when cores handle both big and 1061 // little endian 1062 m_byte_order = core_def->default_byte_order; 1063 } else { 1064 Clear(); 1065 } 1066 } 1067 1068 //===----------------------------------------------------------------------===// 1069 // Helper methods. 1070 1071 void ArchSpec::CoreUpdated(bool update_triple) { 1072 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1073 if (core_def) { 1074 if (update_triple) 1075 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1076 m_byte_order = core_def->default_byte_order; 1077 } else { 1078 if (update_triple) 1079 m_triple = llvm::Triple(); 1080 m_byte_order = eByteOrderInvalid; 1081 } 1082 } 1083 1084 //===----------------------------------------------------------------------===// 1085 // Operators. 1086 1087 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1088 bool try_inverse, bool enforce_exact_match) { 1089 if (core1 == core2) 1090 return true; 1091 1092 switch (core1) { 1093 case ArchSpec::kCore_any: 1094 return true; 1095 1096 case ArchSpec::eCore_arm_generic: 1097 if (enforce_exact_match) 1098 break; 1099 LLVM_FALLTHROUGH; 1100 case ArchSpec::kCore_arm_any: 1101 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1102 return true; 1103 if (core2 >= ArchSpec::kCore_thumb_first && 1104 core2 <= ArchSpec::kCore_thumb_last) 1105 return true; 1106 if (core2 == ArchSpec::kCore_arm_any) 1107 return true; 1108 break; 1109 1110 case ArchSpec::kCore_x86_32_any: 1111 if ((core2 >= ArchSpec::kCore_x86_32_first && 1112 core2 <= ArchSpec::kCore_x86_32_last) || 1113 (core2 == ArchSpec::kCore_x86_32_any)) 1114 return true; 1115 break; 1116 1117 case ArchSpec::kCore_x86_64_any: 1118 if ((core2 >= ArchSpec::kCore_x86_64_first && 1119 core2 <= ArchSpec::kCore_x86_64_last) || 1120 (core2 == ArchSpec::kCore_x86_64_any)) 1121 return true; 1122 break; 1123 1124 case ArchSpec::kCore_ppc_any: 1125 if ((core2 >= ArchSpec::kCore_ppc_first && 1126 core2 <= ArchSpec::kCore_ppc_last) || 1127 (core2 == ArchSpec::kCore_ppc_any)) 1128 return true; 1129 break; 1130 1131 case ArchSpec::kCore_ppc64_any: 1132 if ((core2 >= ArchSpec::kCore_ppc64_first && 1133 core2 <= ArchSpec::kCore_ppc64_last) || 1134 (core2 == ArchSpec::kCore_ppc64_any)) 1135 return true; 1136 break; 1137 1138 case ArchSpec::eCore_arm_armv6m: 1139 if (!enforce_exact_match) { 1140 if (core2 == ArchSpec::eCore_arm_generic) 1141 return true; 1142 try_inverse = false; 1143 if (core2 == ArchSpec::eCore_arm_armv7) 1144 return true; 1145 if (core2 == ArchSpec::eCore_arm_armv6m) 1146 return true; 1147 } 1148 break; 1149 1150 case ArchSpec::kCore_hexagon_any: 1151 if ((core2 >= ArchSpec::kCore_hexagon_first && 1152 core2 <= ArchSpec::kCore_hexagon_last) || 1153 (core2 == ArchSpec::kCore_hexagon_any)) 1154 return true; 1155 break; 1156 1157 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1158 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1159 // ARMv7E-M - armv7em 1160 case ArchSpec::eCore_arm_armv7em: 1161 if (!enforce_exact_match) { 1162 if (core2 == ArchSpec::eCore_arm_generic) 1163 return true; 1164 if (core2 == ArchSpec::eCore_arm_armv7m) 1165 return true; 1166 if (core2 == ArchSpec::eCore_arm_armv6m) 1167 return true; 1168 if (core2 == ArchSpec::eCore_arm_armv7) 1169 return true; 1170 try_inverse = true; 1171 } 1172 break; 1173 1174 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1175 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1176 // ARMv7E-M - armv7em 1177 case ArchSpec::eCore_arm_armv7m: 1178 if (!enforce_exact_match) { 1179 if (core2 == ArchSpec::eCore_arm_generic) 1180 return true; 1181 if (core2 == ArchSpec::eCore_arm_armv6m) 1182 return true; 1183 if (core2 == ArchSpec::eCore_arm_armv7) 1184 return true; 1185 if (core2 == ArchSpec::eCore_arm_armv7em) 1186 return true; 1187 try_inverse = true; 1188 } 1189 break; 1190 1191 case ArchSpec::eCore_arm_armv7f: 1192 case ArchSpec::eCore_arm_armv7k: 1193 case ArchSpec::eCore_arm_armv7s: 1194 case ArchSpec::eCore_arm_armv7l: 1195 case ArchSpec::eCore_arm_armv8l: 1196 if (!enforce_exact_match) { 1197 if (core2 == ArchSpec::eCore_arm_generic) 1198 return true; 1199 if (core2 == ArchSpec::eCore_arm_armv7) 1200 return true; 1201 try_inverse = false; 1202 } 1203 break; 1204 1205 case ArchSpec::eCore_x86_64_x86_64h: 1206 if (!enforce_exact_match) { 1207 try_inverse = false; 1208 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1209 return true; 1210 } 1211 break; 1212 1213 case ArchSpec::eCore_arm_armv8: 1214 if (!enforce_exact_match) { 1215 if (core2 == ArchSpec::eCore_arm_arm64) 1216 return true; 1217 if (core2 == ArchSpec::eCore_arm_aarch64) 1218 return true; 1219 try_inverse = false; 1220 } 1221 break; 1222 1223 case ArchSpec::eCore_arm_aarch64: 1224 if (!enforce_exact_match) { 1225 if (core2 == ArchSpec::eCore_arm_arm64) 1226 return true; 1227 if (core2 == ArchSpec::eCore_arm_armv8) 1228 return true; 1229 try_inverse = false; 1230 } 1231 break; 1232 1233 case ArchSpec::eCore_arm_arm64: 1234 if (!enforce_exact_match) { 1235 if (core2 == ArchSpec::eCore_arm_aarch64) 1236 return true; 1237 if (core2 == ArchSpec::eCore_arm_armv8) 1238 return true; 1239 try_inverse = false; 1240 } 1241 break; 1242 1243 case ArchSpec::eCore_arm_arm64_32: 1244 if (!enforce_exact_match) { 1245 if (core2 == ArchSpec::eCore_arm_generic) 1246 return true; 1247 try_inverse = false; 1248 } 1249 break; 1250 1251 case ArchSpec::eCore_mips32: 1252 if (!enforce_exact_match) { 1253 if (core2 >= ArchSpec::kCore_mips32_first && 1254 core2 <= ArchSpec::kCore_mips32_last) 1255 return true; 1256 try_inverse = false; 1257 } 1258 break; 1259 1260 case ArchSpec::eCore_mips32el: 1261 if (!enforce_exact_match) { 1262 if (core2 >= ArchSpec::kCore_mips32el_first && 1263 core2 <= ArchSpec::kCore_mips32el_last) 1264 return true; 1265 try_inverse = true; 1266 } 1267 break; 1268 1269 case ArchSpec::eCore_mips64: 1270 if (!enforce_exact_match) { 1271 if (core2 >= ArchSpec::kCore_mips32_first && 1272 core2 <= ArchSpec::kCore_mips32_last) 1273 return true; 1274 if (core2 >= ArchSpec::kCore_mips64_first && 1275 core2 <= ArchSpec::kCore_mips64_last) 1276 return true; 1277 try_inverse = false; 1278 } 1279 break; 1280 1281 case ArchSpec::eCore_mips64el: 1282 if (!enforce_exact_match) { 1283 if (core2 >= ArchSpec::kCore_mips32el_first && 1284 core2 <= ArchSpec::kCore_mips32el_last) 1285 return true; 1286 if (core2 >= ArchSpec::kCore_mips64el_first && 1287 core2 <= ArchSpec::kCore_mips64el_last) 1288 return true; 1289 try_inverse = false; 1290 } 1291 break; 1292 1293 case ArchSpec::eCore_mips64r2: 1294 case ArchSpec::eCore_mips64r3: 1295 case ArchSpec::eCore_mips64r5: 1296 if (!enforce_exact_match) { 1297 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1298 return true; 1299 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1300 return true; 1301 try_inverse = false; 1302 } 1303 break; 1304 1305 case ArchSpec::eCore_mips64r2el: 1306 case ArchSpec::eCore_mips64r3el: 1307 case ArchSpec::eCore_mips64r5el: 1308 if (!enforce_exact_match) { 1309 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1310 return true; 1311 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1312 return true; 1313 try_inverse = false; 1314 } 1315 break; 1316 1317 case ArchSpec::eCore_mips32r2: 1318 case ArchSpec::eCore_mips32r3: 1319 case ArchSpec::eCore_mips32r5: 1320 if (!enforce_exact_match) { 1321 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1322 return true; 1323 } 1324 break; 1325 1326 case ArchSpec::eCore_mips32r2el: 1327 case ArchSpec::eCore_mips32r3el: 1328 case ArchSpec::eCore_mips32r5el: 1329 if (!enforce_exact_match) { 1330 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1331 return true; 1332 } 1333 break; 1334 1335 case ArchSpec::eCore_mips32r6: 1336 if (!enforce_exact_match) { 1337 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1338 return true; 1339 } 1340 break; 1341 1342 case ArchSpec::eCore_mips32r6el: 1343 if (!enforce_exact_match) { 1344 if (core2 == ArchSpec::eCore_mips32el || 1345 core2 == ArchSpec::eCore_mips32r6el) 1346 return true; 1347 } 1348 break; 1349 1350 case ArchSpec::eCore_mips64r6: 1351 if (!enforce_exact_match) { 1352 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1353 return true; 1354 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1355 return true; 1356 } 1357 break; 1358 1359 case ArchSpec::eCore_mips64r6el: 1360 if (!enforce_exact_match) { 1361 if (core2 == ArchSpec::eCore_mips32el || 1362 core2 == ArchSpec::eCore_mips32r6el) 1363 return true; 1364 if (core2 == ArchSpec::eCore_mips64el || 1365 core2 == ArchSpec::eCore_mips64r6el) 1366 return true; 1367 } 1368 break; 1369 1370 default: 1371 break; 1372 } 1373 if (try_inverse) 1374 return cores_match(core2, core1, false, enforce_exact_match); 1375 return false; 1376 } 1377 1378 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1379 const ArchSpec::Core lhs_core = lhs.GetCore(); 1380 const ArchSpec::Core rhs_core = rhs.GetCore(); 1381 return lhs_core < rhs_core; 1382 } 1383 1384 1385 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1386 return lhs.GetCore() == rhs.GetCore(); 1387 } 1388 1389 bool ArchSpec::IsFullySpecifiedTriple() const { 1390 const auto &user_specified_triple = GetTriple(); 1391 1392 bool user_triple_fully_specified = false; 1393 1394 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1395 TripleOSWasSpecified()) { 1396 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1397 TripleVendorWasSpecified()) { 1398 const unsigned unspecified = 0; 1399 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1400 user_triple_fully_specified = true; 1401 } 1402 } 1403 } 1404 1405 return user_triple_fully_specified; 1406 } 1407 1408 void ArchSpec::PiecewiseTripleCompare( 1409 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1410 bool &os_different, bool &os_version_different, bool &env_different) const { 1411 const llvm::Triple &me(GetTriple()); 1412 const llvm::Triple &them(other.GetTriple()); 1413 1414 arch_different = (me.getArch() != them.getArch()); 1415 1416 vendor_different = (me.getVendor() != them.getVendor()); 1417 1418 os_different = (me.getOS() != them.getOS()); 1419 1420 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1421 1422 env_different = (me.getEnvironment() != them.getEnvironment()); 1423 } 1424 1425 bool ArchSpec::IsAlwaysThumbInstructions() const { 1426 std::string Status; 1427 if (GetTriple().getArch() == llvm::Triple::arm || 1428 GetTriple().getArch() == llvm::Triple::thumb) { 1429 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1430 // 1431 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1432 // execute thumb instructions. We map the cores to arch names like this: 1433 // 1434 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1435 // Cortex-M7: armv7em 1436 1437 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1438 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1439 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1440 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1441 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1442 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1443 return true; 1444 } 1445 // Windows on ARM is always thumb. 1446 if (GetTriple().isOSWindows()) 1447 return true; 1448 } 1449 return false; 1450 } 1451 1452 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1453 const llvm::Triple &triple = GetTriple(); 1454 llvm::StringRef arch_str = triple.getArchName(); 1455 llvm::StringRef vendor_str = triple.getVendorName(); 1456 llvm::StringRef os_str = triple.getOSName(); 1457 llvm::StringRef environ_str = triple.getEnvironmentName(); 1458 1459 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1460 vendor_str.empty() ? "*" : vendor_str, 1461 os_str.empty() ? "*" : os_str); 1462 1463 if (!environ_str.empty()) 1464 s << "-" << environ_str; 1465 } 1466