1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "lldb/Utility/ArchSpec.h" 11 12 #include "lldb/Utility/Log.h" 13 #include "lldb/Utility/NameMatches.h" 14 #include "lldb/Utility/Stream.h" // for Stream 15 #include "lldb/Utility/StringList.h" 16 #include "lldb/lldb-defines.h" // for LLDB_INVALID_C... 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/Twine.h" // for Twine 19 #include "llvm/BinaryFormat/COFF.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/BinaryFormat/MachO.h" // for CPUType::CPU_T... 22 #include "llvm/Support/Compiler.h" // for LLVM_FALLTHROUGH 23 #include "llvm/Support/Host.h" 24 25 using namespace lldb; 26 using namespace lldb_private; 27 28 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 29 bool try_inverse, bool enforce_exact_match); 30 31 namespace lldb_private { 32 33 struct CoreDefinition { 34 ByteOrder default_byte_order; 35 uint32_t addr_byte_size; 36 uint32_t min_opcode_byte_size; 37 uint32_t max_opcode_byte_size; 38 llvm::Triple::ArchType machine; 39 ArchSpec::Core core; 40 const char *const name; 41 }; 42 43 } // namespace lldb_private 44 45 // This core information can be looked using the ArchSpec::Core as the index 46 static const CoreDefinition g_core_definitions[] = { 47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 48 "arm"}, 49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 50 "armv4"}, 51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 52 "armv4t"}, 53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 54 "armv5"}, 55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 56 "armv5e"}, 57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 58 "armv5t"}, 59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 60 "armv6"}, 61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 62 "armv6m"}, 63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 64 "armv7"}, 65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 66 "armv7f"}, 67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 68 "armv7s"}, 69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 70 "armv7k"}, 71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 72 "armv7m"}, 73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 74 "armv7em"}, 75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 76 "xscale"}, 77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 78 "thumb"}, 79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 80 "thumbv4t"}, 81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 82 "thumbv5"}, 83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 84 "thumbv5e"}, 85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 86 "thumbv6"}, 87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 88 "thumbv6m"}, 89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 90 "thumbv7"}, 91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 92 "thumbv7f"}, 93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 94 "thumbv7s"}, 95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 96 "thumbv7k"}, 97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 98 "thumbv7m"}, 99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 100 "thumbv7em"}, 101 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 102 ArchSpec::eCore_arm_arm64, "arm64"}, 103 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 104 ArchSpec::eCore_arm_armv8, "armv8"}, 105 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 106 ArchSpec::eCore_arm_aarch64, "aarch64"}, 107 108 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 109 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 110 "mips"}, 111 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 112 "mipsr2"}, 113 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 114 "mipsr3"}, 115 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 116 "mipsr5"}, 117 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 118 "mipsr6"}, 119 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 120 "mipsel"}, 121 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 122 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 123 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 124 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 125 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 126 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 127 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 128 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 129 130 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 131 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 132 "mips64"}, 133 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 134 "mips64r2"}, 135 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 136 "mips64r3"}, 137 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 138 "mips64r5"}, 139 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 140 "mips64r6"}, 141 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 142 ArchSpec::eCore_mips64el, "mips64el"}, 143 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 144 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 145 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 146 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 147 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 148 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 149 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 150 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 151 152 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 153 "powerpc"}, 154 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 155 "ppc601"}, 156 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 157 "ppc602"}, 158 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 159 "ppc603"}, 160 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 161 "ppc603e"}, 162 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 163 "ppc603ev"}, 164 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 165 "ppc604"}, 166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 167 "ppc604e"}, 168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 169 "ppc620"}, 170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 171 "ppc750"}, 172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 173 "ppc7400"}, 174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 175 "ppc7450"}, 176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 177 "ppc970"}, 178 179 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 180 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 181 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 182 "powerpc64"}, 183 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 184 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 185 186 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 187 ArchSpec::eCore_s390x_generic, "s390x"}, 188 189 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 190 ArchSpec::eCore_sparc_generic, "sparc"}, 191 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 192 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 193 194 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 195 "i386"}, 196 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 197 "i486"}, 198 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 199 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 200 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 201 "i686"}, 202 203 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 204 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 205 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 206 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 207 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 208 ArchSpec::eCore_hexagon_generic, "hexagon"}, 209 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 210 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 211 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 212 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 213 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 215 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 216 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 217 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 218 219 {eByteOrderBig, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba3, 220 "kalimba3"}, 221 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba4, 222 "kalimba4"}, 223 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba5, 224 "kalimba5"}}; 225 226 // Ensure that we have an entry in the g_core_definitions for each core. If you 227 // comment out an entry above, you will need to comment out the corresponding 228 // ArchSpec::Core enumeration. 229 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 230 ArchSpec::kNumCores, 231 "make sure we have one core definition for each core"); 232 233 struct ArchDefinitionEntry { 234 ArchSpec::Core core; 235 uint32_t cpu; 236 uint32_t sub; 237 uint32_t cpu_mask; 238 uint32_t sub_mask; 239 }; 240 241 struct ArchDefinition { 242 ArchitectureType type; 243 size_t num_entries; 244 const ArchDefinitionEntry *entries; 245 const char *name; 246 }; 247 248 void ArchSpec::ListSupportedArchNames(StringList &list) { 249 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 250 list.AppendString(g_core_definitions[i].name); 251 } 252 253 size_t ArchSpec::AutoComplete(CompletionRequest &request) { 254 if (!request.GetCursorArgumentPrefix().empty()) { 255 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 256 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, 257 request.GetCursorArgumentPrefix())) 258 request.AddCompletion(g_core_definitions[i].name); 259 } 260 } else { 261 StringList matches; 262 ListSupportedArchNames(matches); 263 request.AddCompletions(matches); 264 } 265 return request.GetNumberOfMatches(); 266 } 267 268 #define CPU_ANY (UINT32_MAX) 269 270 //===----------------------------------------------------------------------===// 271 // A table that gets searched linearly for matches. This table is used to 272 // convert cpu type and subtypes to architecture names, and to convert 273 // architecture names to cpu types and subtypes. The ordering is important and 274 // allows the precedence to be set when the table is built. 275 #define SUBTYPE_MASK 0x00FFFFFFu 276 277 static const ArchDefinitionEntry g_macho_arch_entries[] = { 278 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 279 UINT32_MAX, UINT32_MAX}, 280 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 303 SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 305 SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 307 SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 309 SUBTYPE_MASK}, 310 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 317 UINT32_MAX, SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 333 SUBTYPE_MASK}, 334 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 335 SUBTYPE_MASK}, 336 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 343 UINT32_MAX, UINT32_MAX}, 344 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 361 SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 363 SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 365 SUBTYPE_MASK}, 366 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 367 SUBTYPE_MASK}, 368 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 369 SUBTYPE_MASK}, 370 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 371 UINT32_MAX, SUBTYPE_MASK}, 372 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 373 UINT32_MAX, SUBTYPE_MASK}, 374 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 375 UINT32_MAX, SUBTYPE_MASK}, 376 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 379 SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 381 UINT32_MAX, SUBTYPE_MASK}, 382 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 383 UINT32_MAX, UINT32_MAX}, 384 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 385 SUBTYPE_MASK}, 386 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 387 SUBTYPE_MASK}, 388 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 389 UINT32_MAX, SUBTYPE_MASK}, 390 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 391 UINT32_MAX, UINT32_MAX}, 392 // Catch any unknown mach architectures so we can always use the object and 393 // symbol mach-o files 394 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 395 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 396 0x00000000u}}; 397 398 static const ArchDefinition g_macho_arch_def = { 399 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 400 g_macho_arch_entries, "mach-o"}; 401 402 //===----------------------------------------------------------------------===// 403 // A table that gets searched linearly for matches. This table is used to 404 // convert cpu type and subtypes to architecture names, and to convert 405 // architecture names to cpu types and subtypes. The ordering is important and 406 // allows the precedence to be set when the table is built. 407 static const ArchDefinitionEntry g_elf_arch_entries[] = { 408 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 410 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 412 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 414 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 416 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 417 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 418 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 419 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 420 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 422 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 423 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 424 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 425 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 426 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 427 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 428 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 429 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 430 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 431 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 432 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 433 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 434 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 435 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 436 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 438 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 440 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 442 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 443 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 444 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 445 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 446 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 447 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 448 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 449 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 450 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 451 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 452 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 453 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 454 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 455 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 456 {ArchSpec::eCore_kalimba3, llvm::ELF::EM_CSR_KALIMBA, 457 llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 458 {ArchSpec::eCore_kalimba4, llvm::ELF::EM_CSR_KALIMBA, 459 llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 460 {ArchSpec::eCore_kalimba5, llvm::ELF::EM_CSR_KALIMBA, 461 llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu} // KALIMBA 462 }; 463 464 static const ArchDefinition g_elf_arch_def = { 465 eArchTypeELF, 466 llvm::array_lengthof(g_elf_arch_entries), 467 g_elf_arch_entries, 468 "elf", 469 }; 470 471 static const ArchDefinitionEntry g_coff_arch_entries[] = { 472 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 474 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 475 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 476 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 477 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 478 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 479 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 480 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 481 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 482 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 483 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 484 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 485 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 486 }; 487 488 static const ArchDefinition g_coff_arch_def = { 489 eArchTypeCOFF, 490 llvm::array_lengthof(g_coff_arch_entries), 491 g_coff_arch_entries, 492 "pe-coff", 493 }; 494 495 //===----------------------------------------------------------------------===// 496 // Table of all ArchDefinitions 497 static const ArchDefinition *g_arch_definitions[] = { 498 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 499 500 static const size_t k_num_arch_definitions = 501 llvm::array_lengthof(g_arch_definitions); 502 503 //===----------------------------------------------------------------------===// 504 // Static helper functions. 505 506 // Get the architecture definition for a given object type. 507 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 508 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 509 const ArchDefinition *def = g_arch_definitions[i]; 510 if (def->type == arch_type) 511 return def; 512 } 513 return nullptr; 514 } 515 516 // Get an architecture definition by name. 517 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 518 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 519 if (name.equals_lower(g_core_definitions[i].name)) 520 return &g_core_definitions[i]; 521 } 522 return nullptr; 523 } 524 525 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 526 if (core < llvm::array_lengthof(g_core_definitions)) 527 return &g_core_definitions[core]; 528 return nullptr; 529 } 530 531 // Get a definition entry by cpu type and subtype. 532 static const ArchDefinitionEntry * 533 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 534 if (def == nullptr) 535 return nullptr; 536 537 const ArchDefinitionEntry *entries = def->entries; 538 for (size_t i = 0; i < def->num_entries; ++i) { 539 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 540 if (entries[i].sub == (sub & entries[i].sub_mask)) 541 return &entries[i]; 542 } 543 return nullptr; 544 } 545 546 static const ArchDefinitionEntry * 547 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 548 if (def == nullptr) 549 return nullptr; 550 551 const ArchDefinitionEntry *entries = def->entries; 552 for (size_t i = 0; i < def->num_entries; ++i) { 553 if (entries[i].core == core) 554 return &entries[i]; 555 } 556 return nullptr; 557 } 558 559 //===----------------------------------------------------------------------===// 560 // Constructors and destructors. 561 562 ArchSpec::ArchSpec() {} 563 564 ArchSpec::ArchSpec(const char *triple_cstr) { 565 if (triple_cstr) 566 SetTriple(triple_cstr); 567 } 568 569 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 570 571 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 572 573 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 574 SetArchitecture(arch_type, cpu, subtype); 575 } 576 577 ArchSpec::~ArchSpec() = default; 578 579 //===----------------------------------------------------------------------===// 580 // Assignment and initialization. 581 582 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 583 if (this != &rhs) { 584 m_triple = rhs.m_triple; 585 m_core = rhs.m_core; 586 m_byte_order = rhs.m_byte_order; 587 m_distribution_id = rhs.m_distribution_id; 588 m_flags = rhs.m_flags; 589 } 590 return *this; 591 } 592 593 void ArchSpec::Clear() { 594 m_triple = llvm::Triple(); 595 m_core = kCore_invalid; 596 m_byte_order = eByteOrderInvalid; 597 m_distribution_id.Clear(); 598 m_flags = 0; 599 } 600 601 //===----------------------------------------------------------------------===// 602 // Predicates. 603 604 const char *ArchSpec::GetArchitectureName() const { 605 const CoreDefinition *core_def = FindCoreDefinition(m_core); 606 if (core_def) 607 return core_def->name; 608 return "unknown"; 609 } 610 611 bool ArchSpec::IsMIPS() const { 612 const llvm::Triple::ArchType machine = GetMachine(); 613 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 614 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) 615 return true; 616 return false; 617 } 618 619 std::string ArchSpec::GetTargetABI() const { 620 621 std::string abi; 622 623 if (IsMIPS()) { 624 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 625 case ArchSpec::eMIPSABI_N64: 626 abi = "n64"; 627 return abi; 628 case ArchSpec::eMIPSABI_N32: 629 abi = "n32"; 630 return abi; 631 case ArchSpec::eMIPSABI_O32: 632 abi = "o32"; 633 return abi; 634 default: 635 return abi; 636 } 637 } 638 return abi; 639 } 640 641 void ArchSpec::SetFlags(std::string elf_abi) { 642 643 uint32_t flag = GetFlags(); 644 if (IsMIPS()) { 645 if (elf_abi == "n64") 646 flag |= ArchSpec::eMIPSABI_N64; 647 else if (elf_abi == "n32") 648 flag |= ArchSpec::eMIPSABI_N32; 649 else if (elf_abi == "o32") 650 flag |= ArchSpec::eMIPSABI_O32; 651 } 652 SetFlags(flag); 653 } 654 655 std::string ArchSpec::GetClangTargetCPU() const { 656 std::string cpu; 657 const llvm::Triple::ArchType machine = GetMachine(); 658 659 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 660 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) { 661 switch (m_core) { 662 case ArchSpec::eCore_mips32: 663 case ArchSpec::eCore_mips32el: 664 cpu = "mips32"; 665 break; 666 case ArchSpec::eCore_mips32r2: 667 case ArchSpec::eCore_mips32r2el: 668 cpu = "mips32r2"; 669 break; 670 case ArchSpec::eCore_mips32r3: 671 case ArchSpec::eCore_mips32r3el: 672 cpu = "mips32r3"; 673 break; 674 case ArchSpec::eCore_mips32r5: 675 case ArchSpec::eCore_mips32r5el: 676 cpu = "mips32r5"; 677 break; 678 case ArchSpec::eCore_mips32r6: 679 case ArchSpec::eCore_mips32r6el: 680 cpu = "mips32r6"; 681 break; 682 case ArchSpec::eCore_mips64: 683 case ArchSpec::eCore_mips64el: 684 cpu = "mips64"; 685 break; 686 case ArchSpec::eCore_mips64r2: 687 case ArchSpec::eCore_mips64r2el: 688 cpu = "mips64r2"; 689 break; 690 case ArchSpec::eCore_mips64r3: 691 case ArchSpec::eCore_mips64r3el: 692 cpu = "mips64r3"; 693 break; 694 case ArchSpec::eCore_mips64r5: 695 case ArchSpec::eCore_mips64r5el: 696 cpu = "mips64r5"; 697 break; 698 case ArchSpec::eCore_mips64r6: 699 case ArchSpec::eCore_mips64r6el: 700 cpu = "mips64r6"; 701 break; 702 default: 703 break; 704 } 705 } 706 return cpu; 707 } 708 709 uint32_t ArchSpec::GetMachOCPUType() const { 710 const CoreDefinition *core_def = FindCoreDefinition(m_core); 711 if (core_def) { 712 const ArchDefinitionEntry *arch_def = 713 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 714 if (arch_def) { 715 return arch_def->cpu; 716 } 717 } 718 return LLDB_INVALID_CPUTYPE; 719 } 720 721 uint32_t ArchSpec::GetMachOCPUSubType() const { 722 const CoreDefinition *core_def = FindCoreDefinition(m_core); 723 if (core_def) { 724 const ArchDefinitionEntry *arch_def = 725 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 726 if (arch_def) { 727 return arch_def->sub; 728 } 729 } 730 return LLDB_INVALID_CPUTYPE; 731 } 732 733 uint32_t ArchSpec::GetDataByteSize() const { 734 switch (m_core) { 735 case eCore_kalimba3: 736 return 4; 737 case eCore_kalimba4: 738 return 1; 739 case eCore_kalimba5: 740 return 4; 741 default: 742 return 1; 743 } 744 return 1; 745 } 746 747 uint32_t ArchSpec::GetCodeByteSize() const { 748 switch (m_core) { 749 case eCore_kalimba3: 750 return 4; 751 case eCore_kalimba4: 752 return 1; 753 case eCore_kalimba5: 754 return 1; 755 default: 756 return 1; 757 } 758 return 1; 759 } 760 761 llvm::Triple::ArchType ArchSpec::GetMachine() const { 762 const CoreDefinition *core_def = FindCoreDefinition(m_core); 763 if (core_def) 764 return core_def->machine; 765 766 return llvm::Triple::UnknownArch; 767 } 768 769 const ConstString &ArchSpec::GetDistributionId() const { 770 return m_distribution_id; 771 } 772 773 void ArchSpec::SetDistributionId(const char *distribution_id) { 774 m_distribution_id.SetCString(distribution_id); 775 } 776 777 uint32_t ArchSpec::GetAddressByteSize() const { 778 const CoreDefinition *core_def = FindCoreDefinition(m_core); 779 if (core_def) { 780 if (core_def->machine == llvm::Triple::mips64 || 781 core_def->machine == llvm::Triple::mips64el) { 782 // For N32/O32 applications Address size is 4 bytes. 783 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 784 return 4; 785 } 786 return core_def->addr_byte_size; 787 } 788 return 0; 789 } 790 791 ByteOrder ArchSpec::GetDefaultEndian() const { 792 const CoreDefinition *core_def = FindCoreDefinition(m_core); 793 if (core_def) 794 return core_def->default_byte_order; 795 return eByteOrderInvalid; 796 } 797 798 bool ArchSpec::CharIsSignedByDefault() const { 799 switch (m_triple.getArch()) { 800 default: 801 return true; 802 803 case llvm::Triple::aarch64: 804 case llvm::Triple::aarch64_be: 805 case llvm::Triple::arm: 806 case llvm::Triple::armeb: 807 case llvm::Triple::thumb: 808 case llvm::Triple::thumbeb: 809 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 810 811 case llvm::Triple::ppc: 812 case llvm::Triple::ppc64: 813 return m_triple.isOSDarwin(); 814 815 case llvm::Triple::ppc64le: 816 case llvm::Triple::systemz: 817 case llvm::Triple::xcore: 818 case llvm::Triple::arc: 819 return false; 820 } 821 } 822 823 lldb::ByteOrder ArchSpec::GetByteOrder() const { 824 if (m_byte_order == eByteOrderInvalid) 825 return GetDefaultEndian(); 826 return m_byte_order; 827 } 828 829 //===----------------------------------------------------------------------===// 830 // Mutators. 831 832 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 833 m_triple = triple; 834 UpdateCore(); 835 return IsValid(); 836 } 837 838 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 839 ArchSpec &arch) { 840 // Accept "12-10" or "12.10" as cpu type/subtype 841 if (triple_str.empty()) 842 return false; 843 844 size_t pos = triple_str.find_first_of("-."); 845 if (pos == llvm::StringRef::npos) 846 return false; 847 848 llvm::StringRef cpu_str = triple_str.substr(0, pos); 849 llvm::StringRef remainder = triple_str.substr(pos + 1); 850 if (cpu_str.empty() || remainder.empty()) 851 return false; 852 853 llvm::StringRef sub_str; 854 llvm::StringRef vendor; 855 llvm::StringRef os; 856 std::tie(sub_str, remainder) = remainder.split('-'); 857 std::tie(vendor, os) = remainder.split('-'); 858 859 uint32_t cpu = 0; 860 uint32_t sub = 0; 861 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 862 return false; 863 864 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 865 return false; 866 if (!vendor.empty() && !os.empty()) { 867 arch.GetTriple().setVendorName(vendor); 868 arch.GetTriple().setOSName(os); 869 } 870 871 return true; 872 } 873 874 bool ArchSpec::SetTriple(llvm::StringRef triple) { 875 if (triple.empty()) { 876 Clear(); 877 return false; 878 } 879 880 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 881 return true; 882 883 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 884 return IsValid(); 885 } 886 887 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 888 return !normalized_triple.getArchName().empty() && 889 normalized_triple.getOSName().empty() && 890 normalized_triple.getVendorName().empty() && 891 normalized_triple.getEnvironmentName().empty(); 892 } 893 894 void ArchSpec::MergeFrom(const ArchSpec &other) { 895 if (TripleVendorIsUnspecifiedUnknown() && 896 !other.TripleVendorIsUnspecifiedUnknown()) 897 GetTriple().setVendor(other.GetTriple().getVendor()); 898 if (TripleOSIsUnspecifiedUnknown() && !other.TripleOSIsUnspecifiedUnknown()) 899 GetTriple().setOS(other.GetTriple().getOS()); 900 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 901 GetTriple().setArch(other.GetTriple().getArch()); 902 903 // MachO unknown64 isn't really invalid as the debugger can still obtain 904 // information from the binary, e.g. line tables. As such, we don't update 905 // the core here. 906 if (other.GetCore() != eCore_uknownMach64) 907 UpdateCore(); 908 } 909 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 910 !TripleVendorWasSpecified()) { 911 if (other.TripleVendorWasSpecified()) 912 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 913 } 914 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 915 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 916 // adopt the specific arm core. 917 if (GetTriple().getArch() == llvm::Triple::arm && 918 other.GetTriple().getArch() == llvm::Triple::arm && 919 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 920 other.GetCore() != ArchSpec::eCore_arm_generic) { 921 m_core = other.GetCore(); 922 CoreUpdated(true); 923 } 924 if (GetFlags() == 0) { 925 SetFlags(other.GetFlags()); 926 } 927 } 928 929 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 930 uint32_t sub, uint32_t os) { 931 m_core = kCore_invalid; 932 bool update_triple = true; 933 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 934 if (arch_def) { 935 const ArchDefinitionEntry *arch_def_entry = 936 FindArchDefinitionEntry(arch_def, cpu, sub); 937 if (arch_def_entry) { 938 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 939 if (core_def) { 940 m_core = core_def->core; 941 update_triple = false; 942 // Always use the architecture name because it might be more 943 // descriptive than the architecture enum ("armv7" -> 944 // llvm::Triple::arm). 945 m_triple.setArchName(llvm::StringRef(core_def->name)); 946 if (arch_type == eArchTypeMachO) { 947 m_triple.setVendor(llvm::Triple::Apple); 948 949 // Don't set the OS. It could be simulator, macosx, ios, watchos, 950 // tvos. We could get close with the cpu type - but we can't get it 951 // right all of the time. Better to leave this unset so other 952 // sections of code will set it when they have more information. 953 // NB: don't call m_triple.setOS (llvm::Triple::UnknownOS). That sets 954 // the OSName to 955 // "unknown" and the ArchSpec::TripleVendorWasSpecified() method says 956 // that any OSName setting means it was specified. 957 } else if (arch_type == eArchTypeELF) { 958 switch (os) { 959 case llvm::ELF::ELFOSABI_AIX: 960 m_triple.setOS(llvm::Triple::OSType::AIX); 961 break; 962 case llvm::ELF::ELFOSABI_FREEBSD: 963 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 964 break; 965 case llvm::ELF::ELFOSABI_GNU: 966 m_triple.setOS(llvm::Triple::OSType::Linux); 967 break; 968 case llvm::ELF::ELFOSABI_NETBSD: 969 m_triple.setOS(llvm::Triple::OSType::NetBSD); 970 break; 971 case llvm::ELF::ELFOSABI_OPENBSD: 972 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 973 break; 974 case llvm::ELF::ELFOSABI_SOLARIS: 975 m_triple.setOS(llvm::Triple::OSType::Solaris); 976 break; 977 } 978 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 979 m_triple.setVendor(llvm::Triple::PC); 980 m_triple.setOS(llvm::Triple::Win32); 981 } else { 982 m_triple.setVendor(llvm::Triple::UnknownVendor); 983 m_triple.setOS(llvm::Triple::UnknownOS); 984 } 985 // Fall back onto setting the machine type if the arch by name 986 // failed... 987 if (m_triple.getArch() == llvm::Triple::UnknownArch) 988 m_triple.setArch(core_def->machine); 989 } 990 } else { 991 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 992 if (log) 993 log->Printf("Unable to find a core definition for cpu 0x%" PRIx32 " sub %" PRId32, cpu, sub); 994 } 995 } 996 CoreUpdated(update_triple); 997 return IsValid(); 998 } 999 1000 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 1001 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1002 if (core_def) 1003 return core_def->min_opcode_byte_size; 1004 return 0; 1005 } 1006 1007 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 1008 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1009 if (core_def) 1010 return core_def->max_opcode_byte_size; 1011 return 0; 1012 } 1013 1014 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 1015 return IsEqualTo(rhs, true); 1016 } 1017 1018 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 1019 return IsEqualTo(rhs, false); 1020 } 1021 1022 static bool isCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 1023 llvm::Triple::EnvironmentType rhs) { 1024 if (lhs == rhs) 1025 return true; 1026 1027 // If any of the environment is unknown then they are compatible 1028 if (lhs == llvm::Triple::UnknownEnvironment || 1029 rhs == llvm::Triple::UnknownEnvironment) 1030 return true; 1031 1032 // If one of the environment is Android and the other one is EABI then they 1033 // are considered to be compatible. This is required as a workaround for 1034 // shared libraries compiled for Android without the NOTE section indicating 1035 // that they are using the Android ABI. 1036 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 1037 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 1038 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1039 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1040 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1041 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1042 return true; 1043 1044 return false; 1045 } 1046 1047 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1048 // explicitly ignoring m_distribution_id in this method. 1049 1050 if (GetByteOrder() != rhs.GetByteOrder()) 1051 return false; 1052 1053 const ArchSpec::Core lhs_core = GetCore(); 1054 const ArchSpec::Core rhs_core = rhs.GetCore(); 1055 1056 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1057 1058 if (core_match) { 1059 const llvm::Triple &lhs_triple = GetTriple(); 1060 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1061 1062 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1063 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1064 if (lhs_triple_vendor != rhs_triple_vendor) { 1065 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1066 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1067 // Both architectures had the vendor specified, so if they aren't equal 1068 // then we return false 1069 if (rhs_vendor_specified && lhs_vendor_specified) 1070 return false; 1071 1072 // Only fail if both vendor types are not unknown 1073 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1074 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1075 return false; 1076 } 1077 1078 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1079 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1080 if (lhs_triple_os != rhs_triple_os) { 1081 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1082 const bool lhs_os_specified = TripleOSWasSpecified(); 1083 // Both architectures had the OS specified, so if they aren't equal then 1084 // we return false 1085 if (rhs_os_specified && lhs_os_specified) 1086 return false; 1087 1088 // Only fail if both os types are not unknown 1089 if (lhs_triple_os != llvm::Triple::UnknownOS && 1090 rhs_triple_os != llvm::Triple::UnknownOS) 1091 return false; 1092 } 1093 1094 const llvm::Triple::EnvironmentType lhs_triple_env = 1095 lhs_triple.getEnvironment(); 1096 const llvm::Triple::EnvironmentType rhs_triple_env = 1097 rhs_triple.getEnvironment(); 1098 1099 if (!isCompatibleEnvironment(lhs_triple_env, rhs_triple_env)) 1100 return false; 1101 return true; 1102 } 1103 return false; 1104 } 1105 1106 void ArchSpec::UpdateCore() { 1107 llvm::StringRef arch_name(m_triple.getArchName()); 1108 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1109 if (core_def) { 1110 m_core = core_def->core; 1111 // Set the byte order to the default byte order for an architecture. This 1112 // can be modified if needed for cases when cores handle both big and 1113 // little endian 1114 m_byte_order = core_def->default_byte_order; 1115 } else { 1116 Clear(); 1117 } 1118 } 1119 1120 //===----------------------------------------------------------------------===// 1121 // Helper methods. 1122 1123 void ArchSpec::CoreUpdated(bool update_triple) { 1124 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1125 if (core_def) { 1126 if (update_triple) 1127 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1128 m_byte_order = core_def->default_byte_order; 1129 } else { 1130 if (update_triple) 1131 m_triple = llvm::Triple(); 1132 m_byte_order = eByteOrderInvalid; 1133 } 1134 } 1135 1136 //===----------------------------------------------------------------------===// 1137 // Operators. 1138 1139 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1140 bool try_inverse, bool enforce_exact_match) { 1141 if (core1 == core2) 1142 return true; 1143 1144 switch (core1) { 1145 case ArchSpec::kCore_any: 1146 return true; 1147 1148 case ArchSpec::eCore_arm_generic: 1149 if (enforce_exact_match) 1150 break; 1151 LLVM_FALLTHROUGH; 1152 case ArchSpec::kCore_arm_any: 1153 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1154 return true; 1155 if (core2 >= ArchSpec::kCore_thumb_first && 1156 core2 <= ArchSpec::kCore_thumb_last) 1157 return true; 1158 if (core2 == ArchSpec::kCore_arm_any) 1159 return true; 1160 break; 1161 1162 case ArchSpec::kCore_x86_32_any: 1163 if ((core2 >= ArchSpec::kCore_x86_32_first && 1164 core2 <= ArchSpec::kCore_x86_32_last) || 1165 (core2 == ArchSpec::kCore_x86_32_any)) 1166 return true; 1167 break; 1168 1169 case ArchSpec::kCore_x86_64_any: 1170 if ((core2 >= ArchSpec::kCore_x86_64_first && 1171 core2 <= ArchSpec::kCore_x86_64_last) || 1172 (core2 == ArchSpec::kCore_x86_64_any)) 1173 return true; 1174 break; 1175 1176 case ArchSpec::kCore_ppc_any: 1177 if ((core2 >= ArchSpec::kCore_ppc_first && 1178 core2 <= ArchSpec::kCore_ppc_last) || 1179 (core2 == ArchSpec::kCore_ppc_any)) 1180 return true; 1181 break; 1182 1183 case ArchSpec::kCore_ppc64_any: 1184 if ((core2 >= ArchSpec::kCore_ppc64_first && 1185 core2 <= ArchSpec::kCore_ppc64_last) || 1186 (core2 == ArchSpec::kCore_ppc64_any)) 1187 return true; 1188 break; 1189 1190 case ArchSpec::eCore_arm_armv6m: 1191 if (!enforce_exact_match) { 1192 if (core2 == ArchSpec::eCore_arm_generic) 1193 return true; 1194 try_inverse = false; 1195 if (core2 == ArchSpec::eCore_arm_armv7) 1196 return true; 1197 if (core2 == ArchSpec::eCore_arm_armv6m) 1198 return true; 1199 } 1200 break; 1201 1202 case ArchSpec::kCore_hexagon_any: 1203 if ((core2 >= ArchSpec::kCore_hexagon_first && 1204 core2 <= ArchSpec::kCore_hexagon_last) || 1205 (core2 == ArchSpec::kCore_hexagon_any)) 1206 return true; 1207 break; 1208 1209 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1210 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1211 // ARMv7E-M - armv7em 1212 case ArchSpec::eCore_arm_armv7em: 1213 if (!enforce_exact_match) { 1214 if (core2 == ArchSpec::eCore_arm_generic) 1215 return true; 1216 if (core2 == ArchSpec::eCore_arm_armv7m) 1217 return true; 1218 if (core2 == ArchSpec::eCore_arm_armv6m) 1219 return true; 1220 if (core2 == ArchSpec::eCore_arm_armv7) 1221 return true; 1222 try_inverse = true; 1223 } 1224 break; 1225 1226 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1227 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1228 // ARMv7E-M - armv7em 1229 case ArchSpec::eCore_arm_armv7m: 1230 if (!enforce_exact_match) { 1231 if (core2 == ArchSpec::eCore_arm_generic) 1232 return true; 1233 if (core2 == ArchSpec::eCore_arm_armv6m) 1234 return true; 1235 if (core2 == ArchSpec::eCore_arm_armv7) 1236 return true; 1237 if (core2 == ArchSpec::eCore_arm_armv7em) 1238 return true; 1239 try_inverse = true; 1240 } 1241 break; 1242 1243 case ArchSpec::eCore_arm_armv7f: 1244 case ArchSpec::eCore_arm_armv7k: 1245 case ArchSpec::eCore_arm_armv7s: 1246 if (!enforce_exact_match) { 1247 if (core2 == ArchSpec::eCore_arm_generic) 1248 return true; 1249 if (core2 == ArchSpec::eCore_arm_armv7) 1250 return true; 1251 try_inverse = false; 1252 } 1253 break; 1254 1255 case ArchSpec::eCore_x86_64_x86_64h: 1256 if (!enforce_exact_match) { 1257 try_inverse = false; 1258 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1259 return true; 1260 } 1261 break; 1262 1263 case ArchSpec::eCore_arm_armv8: 1264 if (!enforce_exact_match) { 1265 if (core2 == ArchSpec::eCore_arm_arm64) 1266 return true; 1267 if (core2 == ArchSpec::eCore_arm_aarch64) 1268 return true; 1269 try_inverse = false; 1270 } 1271 break; 1272 1273 case ArchSpec::eCore_arm_aarch64: 1274 if (!enforce_exact_match) { 1275 if (core2 == ArchSpec::eCore_arm_arm64) 1276 return true; 1277 if (core2 == ArchSpec::eCore_arm_armv8) 1278 return true; 1279 try_inverse = false; 1280 } 1281 break; 1282 1283 case ArchSpec::eCore_arm_arm64: 1284 if (!enforce_exact_match) { 1285 if (core2 == ArchSpec::eCore_arm_aarch64) 1286 return true; 1287 if (core2 == ArchSpec::eCore_arm_armv8) 1288 return true; 1289 try_inverse = false; 1290 } 1291 break; 1292 1293 case ArchSpec::eCore_mips32: 1294 if (!enforce_exact_match) { 1295 if (core2 >= ArchSpec::kCore_mips32_first && 1296 core2 <= ArchSpec::kCore_mips32_last) 1297 return true; 1298 try_inverse = false; 1299 } 1300 break; 1301 1302 case ArchSpec::eCore_mips32el: 1303 if (!enforce_exact_match) { 1304 if (core2 >= ArchSpec::kCore_mips32el_first && 1305 core2 <= ArchSpec::kCore_mips32el_last) 1306 return true; 1307 try_inverse = true; 1308 } 1309 break; 1310 1311 case ArchSpec::eCore_mips64: 1312 if (!enforce_exact_match) { 1313 if (core2 >= ArchSpec::kCore_mips32_first && 1314 core2 <= ArchSpec::kCore_mips32_last) 1315 return true; 1316 if (core2 >= ArchSpec::kCore_mips64_first && 1317 core2 <= ArchSpec::kCore_mips64_last) 1318 return true; 1319 try_inverse = false; 1320 } 1321 break; 1322 1323 case ArchSpec::eCore_mips64el: 1324 if (!enforce_exact_match) { 1325 if (core2 >= ArchSpec::kCore_mips32el_first && 1326 core2 <= ArchSpec::kCore_mips32el_last) 1327 return true; 1328 if (core2 >= ArchSpec::kCore_mips64el_first && 1329 core2 <= ArchSpec::kCore_mips64el_last) 1330 return true; 1331 try_inverse = false; 1332 } 1333 break; 1334 1335 case ArchSpec::eCore_mips64r2: 1336 case ArchSpec::eCore_mips64r3: 1337 case ArchSpec::eCore_mips64r5: 1338 if (!enforce_exact_match) { 1339 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1340 return true; 1341 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1342 return true; 1343 try_inverse = false; 1344 } 1345 break; 1346 1347 case ArchSpec::eCore_mips64r2el: 1348 case ArchSpec::eCore_mips64r3el: 1349 case ArchSpec::eCore_mips64r5el: 1350 if (!enforce_exact_match) { 1351 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1352 return true; 1353 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1354 return true; 1355 try_inverse = false; 1356 } 1357 break; 1358 1359 case ArchSpec::eCore_mips32r2: 1360 case ArchSpec::eCore_mips32r3: 1361 case ArchSpec::eCore_mips32r5: 1362 if (!enforce_exact_match) { 1363 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1364 return true; 1365 } 1366 break; 1367 1368 case ArchSpec::eCore_mips32r2el: 1369 case ArchSpec::eCore_mips32r3el: 1370 case ArchSpec::eCore_mips32r5el: 1371 if (!enforce_exact_match) { 1372 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1373 return true; 1374 } 1375 break; 1376 1377 case ArchSpec::eCore_mips32r6: 1378 if (!enforce_exact_match) { 1379 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1380 return true; 1381 } 1382 break; 1383 1384 case ArchSpec::eCore_mips32r6el: 1385 if (!enforce_exact_match) { 1386 if (core2 == ArchSpec::eCore_mips32el || 1387 core2 == ArchSpec::eCore_mips32r6el) 1388 return true; 1389 } 1390 break; 1391 1392 case ArchSpec::eCore_mips64r6: 1393 if (!enforce_exact_match) { 1394 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1395 return true; 1396 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1397 return true; 1398 } 1399 break; 1400 1401 case ArchSpec::eCore_mips64r6el: 1402 if (!enforce_exact_match) { 1403 if (core2 == ArchSpec::eCore_mips32el || 1404 core2 == ArchSpec::eCore_mips32r6el) 1405 return true; 1406 if (core2 == ArchSpec::eCore_mips64el || 1407 core2 == ArchSpec::eCore_mips64r6el) 1408 return true; 1409 } 1410 break; 1411 1412 default: 1413 break; 1414 } 1415 if (try_inverse) 1416 return cores_match(core2, core1, false, enforce_exact_match); 1417 return false; 1418 } 1419 1420 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1421 const ArchSpec::Core lhs_core = lhs.GetCore(); 1422 const ArchSpec::Core rhs_core = rhs.GetCore(); 1423 return lhs_core < rhs_core; 1424 } 1425 1426 1427 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1428 return lhs.GetCore() == rhs.GetCore(); 1429 } 1430 1431 bool ArchSpec::IsFullySpecifiedTriple() const { 1432 const auto &user_specified_triple = GetTriple(); 1433 1434 bool user_triple_fully_specified = false; 1435 1436 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1437 TripleOSWasSpecified()) { 1438 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1439 TripleVendorWasSpecified()) { 1440 const unsigned unspecified = 0; 1441 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1442 user_triple_fully_specified = true; 1443 } 1444 } 1445 } 1446 1447 return user_triple_fully_specified; 1448 } 1449 1450 void ArchSpec::PiecewiseTripleCompare( 1451 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1452 bool &os_different, bool &os_version_different, bool &env_different) const { 1453 const llvm::Triple &me(GetTriple()); 1454 const llvm::Triple &them(other.GetTriple()); 1455 1456 arch_different = (me.getArch() != them.getArch()); 1457 1458 vendor_different = (me.getVendor() != them.getVendor()); 1459 1460 os_different = (me.getOS() != them.getOS()); 1461 1462 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1463 1464 env_different = (me.getEnvironment() != them.getEnvironment()); 1465 } 1466 1467 bool ArchSpec::IsAlwaysThumbInstructions() const { 1468 std::string Status; 1469 if (GetTriple().getArch() == llvm::Triple::arm || 1470 GetTriple().getArch() == llvm::Triple::thumb) { 1471 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1472 // 1473 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1474 // execute thumb instructions. We map the cores to arch names like this: 1475 // 1476 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1477 // Cortex-M7: armv7em 1478 1479 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1480 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1481 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1482 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1483 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1484 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1485 return true; 1486 } 1487 } 1488 return false; 1489 } 1490 1491 void ArchSpec::DumpTriple(Stream &s) const { 1492 const llvm::Triple &triple = GetTriple(); 1493 llvm::StringRef arch_str = triple.getArchName(); 1494 llvm::StringRef vendor_str = triple.getVendorName(); 1495 llvm::StringRef os_str = triple.getOSName(); 1496 llvm::StringRef environ_str = triple.getEnvironmentName(); 1497 1498 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1499 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1500 os_str.empty() ? "*" : os_str.str().c_str()); 1501 1502 if (!environ_str.empty()) 1503 s.Printf("-%s", environ_str.str().c_str()); 1504 } 1505