1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 65 "armv7l"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 67 "armv7f"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 69 "armv7s"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 71 "armv7k"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 73 "armv7m"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 75 "armv7em"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 77 "xscale"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 79 "thumb"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 81 "thumbv4t"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 83 "thumbv5"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 85 "thumbv5e"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 87 "thumbv6"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 89 "thumbv6m"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 91 "thumbv7"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 93 "thumbv7f"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 95 "thumbv7s"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 97 "thumbv7k"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 99 "thumbv7m"}, 100 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 101 "thumbv7em"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_arm64, "arm64"}, 104 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 105 ArchSpec::eCore_arm_armv8, "armv8"}, 106 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 107 ArchSpec::eCore_arm_armv8l, "armv8l"}, 108 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 109 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 110 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 111 ArchSpec::eCore_arm_aarch64, "aarch64"}, 112 113 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 115 "mips"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 117 "mipsr2"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 119 "mipsr3"}, 120 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 121 "mipsr5"}, 122 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 123 "mipsr6"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 125 "mipsel"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 130 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 131 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 132 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 133 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 134 135 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 137 "mips64"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 139 "mips64r2"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 141 "mips64r3"}, 142 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 143 "mips64r5"}, 144 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 145 "mips64r6"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64el, "mips64el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 152 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 153 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 154 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 155 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 156 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 158 "powerpc"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 160 "ppc601"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 162 "ppc602"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 164 "ppc603"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 166 "ppc603e"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 168 "ppc603ev"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 170 "ppc604"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 172 "ppc604e"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 174 "ppc620"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 176 "ppc750"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 178 "ppc7400"}, 179 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 180 "ppc7450"}, 181 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 182 "ppc970"}, 183 184 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 185 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 186 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 187 "powerpc64"}, 188 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 189 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 190 191 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 192 ArchSpec::eCore_s390x_generic, "s390x"}, 193 194 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 195 ArchSpec::eCore_sparc_generic, "sparc"}, 196 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 197 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 198 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 200 "i386"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 202 "i486"}, 203 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 204 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 205 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 206 "i686"}, 207 208 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 209 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 210 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 211 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_generic, "hexagon"}, 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 215 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 216 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 217 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 218 219 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 220 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 221 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 222 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 223 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"} 224 }; 225 226 // Ensure that we have an entry in the g_core_definitions for each core. If you 227 // comment out an entry above, you will need to comment out the corresponding 228 // ArchSpec::Core enumeration. 229 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 230 ArchSpec::kNumCores, 231 "make sure we have one core definition for each core"); 232 233 struct ArchDefinitionEntry { 234 ArchSpec::Core core; 235 uint32_t cpu; 236 uint32_t sub; 237 uint32_t cpu_mask; 238 uint32_t sub_mask; 239 }; 240 241 struct ArchDefinition { 242 ArchitectureType type; 243 size_t num_entries; 244 const ArchDefinitionEntry *entries; 245 const char *name; 246 }; 247 248 void ArchSpec::ListSupportedArchNames(StringList &list) { 249 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 250 list.AppendString(g_core_definitions[i].name); 251 } 252 253 void ArchSpec::AutoComplete(CompletionRequest &request) { 254 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 255 request.TryCompleteCurrentArg(g_core_definitions[i].name); 256 } 257 258 #define CPU_ANY (UINT32_MAX) 259 260 //===----------------------------------------------------------------------===// 261 // A table that gets searched linearly for matches. This table is used to 262 // convert cpu type and subtypes to architecture names, and to convert 263 // architecture names to cpu types and subtypes. The ordering is important and 264 // allows the precedence to be set when the table is built. 265 #define SUBTYPE_MASK 0x00FFFFFFu 266 267 static const ArchDefinitionEntry g_macho_arch_entries[] = { 268 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 269 UINT32_MAX, UINT32_MAX}, 270 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 271 SUBTYPE_MASK}, 272 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 273 SUBTYPE_MASK}, 274 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 275 SUBTYPE_MASK}, 276 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 277 SUBTYPE_MASK}, 278 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 279 SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 303 SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 305 SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 307 UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 309 UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 311 UINT32_MAX, SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 317 SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 333 SUBTYPE_MASK}, 334 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 335 SUBTYPE_MASK}, 336 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 337 UINT32_MAX, UINT32_MAX}, 338 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 343 SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 361 SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 363 SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 365 UINT32_MAX, SUBTYPE_MASK}, 366 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 367 UINT32_MAX, SUBTYPE_MASK}, 368 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 369 UINT32_MAX, SUBTYPE_MASK}, 370 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 371 SUBTYPE_MASK}, 372 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 373 SUBTYPE_MASK}, 374 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 375 UINT32_MAX, SUBTYPE_MASK}, 376 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 377 UINT32_MAX, UINT32_MAX}, 378 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 379 SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 381 SUBTYPE_MASK}, 382 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 383 UINT32_MAX, SUBTYPE_MASK}, 384 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 385 UINT32_MAX, UINT32_MAX}, 386 // Catch any unknown mach architectures so we can always use the object and 387 // symbol mach-o files 388 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 389 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 390 0x00000000u}}; 391 392 static const ArchDefinition g_macho_arch_def = { 393 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 394 g_macho_arch_entries, "mach-o"}; 395 396 //===----------------------------------------------------------------------===// 397 // A table that gets searched linearly for matches. This table is used to 398 // convert cpu type and subtypes to architecture names, and to convert 399 // architecture names to cpu types and subtypes. The ordering is important and 400 // allows the precedence to be set when the table is built. 401 static const ArchDefinitionEntry g_elf_arch_entries[] = { 402 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 403 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 404 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 405 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 406 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 407 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 408 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 410 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 412 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 414 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 416 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 417 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 418 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 419 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 420 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 421 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 422 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 423 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 424 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 425 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 426 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 427 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 428 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 429 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 430 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 431 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 432 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 433 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 434 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 435 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 436 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 437 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 438 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 440 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 442 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 443 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 444 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 445 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 446 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 447 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 448 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 449 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 450 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 451 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARC 452 }; 453 454 static const ArchDefinition g_elf_arch_def = { 455 eArchTypeELF, 456 llvm::array_lengthof(g_elf_arch_entries), 457 g_elf_arch_entries, 458 "elf", 459 }; 460 461 static const ArchDefinitionEntry g_coff_arch_entries[] = { 462 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 463 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 464 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 465 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 466 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 467 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 468 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 469 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 470 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 472 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 474 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 475 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 476 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 477 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 478 }; 479 480 static const ArchDefinition g_coff_arch_def = { 481 eArchTypeCOFF, 482 llvm::array_lengthof(g_coff_arch_entries), 483 g_coff_arch_entries, 484 "pe-coff", 485 }; 486 487 //===----------------------------------------------------------------------===// 488 // Table of all ArchDefinitions 489 static const ArchDefinition *g_arch_definitions[] = { 490 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 491 492 static const size_t k_num_arch_definitions = 493 llvm::array_lengthof(g_arch_definitions); 494 495 //===----------------------------------------------------------------------===// 496 // Static helper functions. 497 498 // Get the architecture definition for a given object type. 499 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 500 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 501 const ArchDefinition *def = g_arch_definitions[i]; 502 if (def->type == arch_type) 503 return def; 504 } 505 return nullptr; 506 } 507 508 // Get an architecture definition by name. 509 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 510 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 511 if (name.equals_lower(g_core_definitions[i].name)) 512 return &g_core_definitions[i]; 513 } 514 return nullptr; 515 } 516 517 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 518 if (core < llvm::array_lengthof(g_core_definitions)) 519 return &g_core_definitions[core]; 520 return nullptr; 521 } 522 523 // Get a definition entry by cpu type and subtype. 524 static const ArchDefinitionEntry * 525 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 526 if (def == nullptr) 527 return nullptr; 528 529 const ArchDefinitionEntry *entries = def->entries; 530 for (size_t i = 0; i < def->num_entries; ++i) { 531 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 532 if (entries[i].sub == (sub & entries[i].sub_mask)) 533 return &entries[i]; 534 } 535 return nullptr; 536 } 537 538 static const ArchDefinitionEntry * 539 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 540 if (def == nullptr) 541 return nullptr; 542 543 const ArchDefinitionEntry *entries = def->entries; 544 for (size_t i = 0; i < def->num_entries; ++i) { 545 if (entries[i].core == core) 546 return &entries[i]; 547 } 548 return nullptr; 549 } 550 551 //===----------------------------------------------------------------------===// 552 // Constructors and destructors. 553 554 ArchSpec::ArchSpec() {} 555 556 ArchSpec::ArchSpec(const char *triple_cstr) { 557 if (triple_cstr) 558 SetTriple(triple_cstr); 559 } 560 561 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 562 563 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 564 565 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 566 SetArchitecture(arch_type, cpu, subtype); 567 } 568 569 ArchSpec::~ArchSpec() = default; 570 571 void ArchSpec::Clear() { 572 m_triple = llvm::Triple(); 573 m_core = kCore_invalid; 574 m_byte_order = eByteOrderInvalid; 575 m_distribution_id.Clear(); 576 m_flags = 0; 577 } 578 579 //===----------------------------------------------------------------------===// 580 // Predicates. 581 582 const char *ArchSpec::GetArchitectureName() const { 583 const CoreDefinition *core_def = FindCoreDefinition(m_core); 584 if (core_def) 585 return core_def->name; 586 return "unknown"; 587 } 588 589 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 590 591 std::string ArchSpec::GetTargetABI() const { 592 593 std::string abi; 594 595 if (IsMIPS()) { 596 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 597 case ArchSpec::eMIPSABI_N64: 598 abi = "n64"; 599 return abi; 600 case ArchSpec::eMIPSABI_N32: 601 abi = "n32"; 602 return abi; 603 case ArchSpec::eMIPSABI_O32: 604 abi = "o32"; 605 return abi; 606 default: 607 return abi; 608 } 609 } 610 return abi; 611 } 612 613 void ArchSpec::SetFlags(std::string elf_abi) { 614 615 uint32_t flag = GetFlags(); 616 if (IsMIPS()) { 617 if (elf_abi == "n64") 618 flag |= ArchSpec::eMIPSABI_N64; 619 else if (elf_abi == "n32") 620 flag |= ArchSpec::eMIPSABI_N32; 621 else if (elf_abi == "o32") 622 flag |= ArchSpec::eMIPSABI_O32; 623 } 624 SetFlags(flag); 625 } 626 627 std::string ArchSpec::GetClangTargetCPU() const { 628 std::string cpu; 629 630 if (IsMIPS()) { 631 switch (m_core) { 632 case ArchSpec::eCore_mips32: 633 case ArchSpec::eCore_mips32el: 634 cpu = "mips32"; 635 break; 636 case ArchSpec::eCore_mips32r2: 637 case ArchSpec::eCore_mips32r2el: 638 cpu = "mips32r2"; 639 break; 640 case ArchSpec::eCore_mips32r3: 641 case ArchSpec::eCore_mips32r3el: 642 cpu = "mips32r3"; 643 break; 644 case ArchSpec::eCore_mips32r5: 645 case ArchSpec::eCore_mips32r5el: 646 cpu = "mips32r5"; 647 break; 648 case ArchSpec::eCore_mips32r6: 649 case ArchSpec::eCore_mips32r6el: 650 cpu = "mips32r6"; 651 break; 652 case ArchSpec::eCore_mips64: 653 case ArchSpec::eCore_mips64el: 654 cpu = "mips64"; 655 break; 656 case ArchSpec::eCore_mips64r2: 657 case ArchSpec::eCore_mips64r2el: 658 cpu = "mips64r2"; 659 break; 660 case ArchSpec::eCore_mips64r3: 661 case ArchSpec::eCore_mips64r3el: 662 cpu = "mips64r3"; 663 break; 664 case ArchSpec::eCore_mips64r5: 665 case ArchSpec::eCore_mips64r5el: 666 cpu = "mips64r5"; 667 break; 668 case ArchSpec::eCore_mips64r6: 669 case ArchSpec::eCore_mips64r6el: 670 cpu = "mips64r6"; 671 break; 672 default: 673 break; 674 } 675 } 676 return cpu; 677 } 678 679 uint32_t ArchSpec::GetMachOCPUType() const { 680 const CoreDefinition *core_def = FindCoreDefinition(m_core); 681 if (core_def) { 682 const ArchDefinitionEntry *arch_def = 683 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 684 if (arch_def) { 685 return arch_def->cpu; 686 } 687 } 688 return LLDB_INVALID_CPUTYPE; 689 } 690 691 uint32_t ArchSpec::GetMachOCPUSubType() const { 692 const CoreDefinition *core_def = FindCoreDefinition(m_core); 693 if (core_def) { 694 const ArchDefinitionEntry *arch_def = 695 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 696 if (arch_def) { 697 return arch_def->sub; 698 } 699 } 700 return LLDB_INVALID_CPUTYPE; 701 } 702 703 uint32_t ArchSpec::GetDataByteSize() const { 704 return 1; 705 } 706 707 uint32_t ArchSpec::GetCodeByteSize() const { 708 return 1; 709 } 710 711 llvm::Triple::ArchType ArchSpec::GetMachine() const { 712 const CoreDefinition *core_def = FindCoreDefinition(m_core); 713 if (core_def) 714 return core_def->machine; 715 716 return llvm::Triple::UnknownArch; 717 } 718 719 ConstString ArchSpec::GetDistributionId() const { 720 return m_distribution_id; 721 } 722 723 void ArchSpec::SetDistributionId(const char *distribution_id) { 724 m_distribution_id.SetCString(distribution_id); 725 } 726 727 uint32_t ArchSpec::GetAddressByteSize() const { 728 const CoreDefinition *core_def = FindCoreDefinition(m_core); 729 if (core_def) { 730 if (core_def->machine == llvm::Triple::mips64 || 731 core_def->machine == llvm::Triple::mips64el) { 732 // For N32/O32 applications Address size is 4 bytes. 733 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 734 return 4; 735 } 736 return core_def->addr_byte_size; 737 } 738 return 0; 739 } 740 741 ByteOrder ArchSpec::GetDefaultEndian() const { 742 const CoreDefinition *core_def = FindCoreDefinition(m_core); 743 if (core_def) 744 return core_def->default_byte_order; 745 return eByteOrderInvalid; 746 } 747 748 bool ArchSpec::CharIsSignedByDefault() const { 749 switch (m_triple.getArch()) { 750 default: 751 return true; 752 753 case llvm::Triple::aarch64: 754 case llvm::Triple::aarch64_32: 755 case llvm::Triple::aarch64_be: 756 case llvm::Triple::arm: 757 case llvm::Triple::armeb: 758 case llvm::Triple::thumb: 759 case llvm::Triple::thumbeb: 760 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 761 762 case llvm::Triple::ppc: 763 case llvm::Triple::ppc64: 764 return m_triple.isOSDarwin(); 765 766 case llvm::Triple::ppc64le: 767 case llvm::Triple::systemz: 768 case llvm::Triple::xcore: 769 case llvm::Triple::arc: 770 return false; 771 } 772 } 773 774 lldb::ByteOrder ArchSpec::GetByteOrder() const { 775 if (m_byte_order == eByteOrderInvalid) 776 return GetDefaultEndian(); 777 return m_byte_order; 778 } 779 780 //===----------------------------------------------------------------------===// 781 // Mutators. 782 783 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 784 m_triple = triple; 785 UpdateCore(); 786 return IsValid(); 787 } 788 789 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 790 ArchSpec &arch) { 791 // Accept "12-10" or "12.10" as cpu type/subtype 792 if (triple_str.empty()) 793 return false; 794 795 size_t pos = triple_str.find_first_of("-."); 796 if (pos == llvm::StringRef::npos) 797 return false; 798 799 llvm::StringRef cpu_str = triple_str.substr(0, pos); 800 llvm::StringRef remainder = triple_str.substr(pos + 1); 801 if (cpu_str.empty() || remainder.empty()) 802 return false; 803 804 llvm::StringRef sub_str; 805 llvm::StringRef vendor; 806 llvm::StringRef os; 807 std::tie(sub_str, remainder) = remainder.split('-'); 808 std::tie(vendor, os) = remainder.split('-'); 809 810 uint32_t cpu = 0; 811 uint32_t sub = 0; 812 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 813 return false; 814 815 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 816 return false; 817 if (!vendor.empty() && !os.empty()) { 818 arch.GetTriple().setVendorName(vendor); 819 arch.GetTriple().setOSName(os); 820 } 821 822 return true; 823 } 824 825 bool ArchSpec::SetTriple(llvm::StringRef triple) { 826 if (triple.empty()) { 827 Clear(); 828 return false; 829 } 830 831 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 832 return true; 833 834 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 835 return IsValid(); 836 } 837 838 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 839 return !normalized_triple.getArchName().empty() && 840 normalized_triple.getOSName().empty() && 841 normalized_triple.getVendorName().empty() && 842 normalized_triple.getEnvironmentName().empty(); 843 } 844 845 void ArchSpec::MergeFrom(const ArchSpec &other) { 846 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 847 GetTriple().setVendor(other.GetTriple().getVendor()); 848 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 849 GetTriple().setOS(other.GetTriple().getOS()); 850 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 851 GetTriple().setArch(other.GetTriple().getArch()); 852 853 // MachO unknown64 isn't really invalid as the debugger can still obtain 854 // information from the binary, e.g. line tables. As such, we don't update 855 // the core here. 856 if (other.GetCore() != eCore_uknownMach64) 857 UpdateCore(); 858 } 859 if (!TripleEnvironmentWasSpecified() && 860 other.TripleEnvironmentWasSpecified()) { 861 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 862 } 863 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 864 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 865 // adopt the specific arm core. 866 if (GetTriple().getArch() == llvm::Triple::arm && 867 other.GetTriple().getArch() == llvm::Triple::arm && 868 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 869 other.GetCore() != ArchSpec::eCore_arm_generic) { 870 m_core = other.GetCore(); 871 CoreUpdated(true); 872 } 873 if (GetFlags() == 0) { 874 SetFlags(other.GetFlags()); 875 } 876 } 877 878 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 879 uint32_t sub, uint32_t os) { 880 m_core = kCore_invalid; 881 bool update_triple = true; 882 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 883 if (arch_def) { 884 const ArchDefinitionEntry *arch_def_entry = 885 FindArchDefinitionEntry(arch_def, cpu, sub); 886 if (arch_def_entry) { 887 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 888 if (core_def) { 889 m_core = core_def->core; 890 update_triple = false; 891 // Always use the architecture name because it might be more 892 // descriptive than the architecture enum ("armv7" -> 893 // llvm::Triple::arm). 894 m_triple.setArchName(llvm::StringRef(core_def->name)); 895 if (arch_type == eArchTypeMachO) { 896 m_triple.setVendor(llvm::Triple::Apple); 897 898 // Don't set the OS. It could be simulator, macosx, ios, watchos, 899 // tvos, bridgeos. We could get close with the cpu type - but we 900 // can't get it right all of the time. Better to leave this unset 901 // so other sections of code will set it when they have more 902 // information. NB: don't call m_triple.setOS 903 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 904 // the ArchSpec::TripleVendorWasSpecified() method says that any 905 // OSName setting means it was specified. 906 } else if (arch_type == eArchTypeELF) { 907 switch (os) { 908 case llvm::ELF::ELFOSABI_AIX: 909 m_triple.setOS(llvm::Triple::OSType::AIX); 910 break; 911 case llvm::ELF::ELFOSABI_FREEBSD: 912 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 913 break; 914 case llvm::ELF::ELFOSABI_GNU: 915 m_triple.setOS(llvm::Triple::OSType::Linux); 916 break; 917 case llvm::ELF::ELFOSABI_NETBSD: 918 m_triple.setOS(llvm::Triple::OSType::NetBSD); 919 break; 920 case llvm::ELF::ELFOSABI_OPENBSD: 921 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 922 break; 923 case llvm::ELF::ELFOSABI_SOLARIS: 924 m_triple.setOS(llvm::Triple::OSType::Solaris); 925 break; 926 } 927 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 928 m_triple.setVendor(llvm::Triple::PC); 929 m_triple.setOS(llvm::Triple::Win32); 930 } else { 931 m_triple.setVendor(llvm::Triple::UnknownVendor); 932 m_triple.setOS(llvm::Triple::UnknownOS); 933 } 934 // Fall back onto setting the machine type if the arch by name 935 // failed... 936 if (m_triple.getArch() == llvm::Triple::UnknownArch) 937 m_triple.setArch(core_def->machine); 938 } 939 } else { 940 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 941 LLDB_LOGF(log, 942 "Unable to find a core definition for cpu 0x%" PRIx32 943 " sub %" PRId32, 944 cpu, sub); 945 } 946 } 947 CoreUpdated(update_triple); 948 return IsValid(); 949 } 950 951 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 952 const CoreDefinition *core_def = FindCoreDefinition(m_core); 953 if (core_def) 954 return core_def->min_opcode_byte_size; 955 return 0; 956 } 957 958 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 959 const CoreDefinition *core_def = FindCoreDefinition(m_core); 960 if (core_def) 961 return core_def->max_opcode_byte_size; 962 return 0; 963 } 964 965 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 966 return IsEqualTo(rhs, true); 967 } 968 969 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 970 return IsEqualTo(rhs, false); 971 } 972 973 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 974 llvm::Triple::EnvironmentType rhs) { 975 if (lhs == rhs) 976 return true; 977 978 // If any of the environment is unknown then they are compatible 979 if (lhs == llvm::Triple::UnknownEnvironment || 980 rhs == llvm::Triple::UnknownEnvironment) 981 return true; 982 983 // If one of the environment is Android and the other one is EABI then they 984 // are considered to be compatible. This is required as a workaround for 985 // shared libraries compiled for Android without the NOTE section indicating 986 // that they are using the Android ABI. 987 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 988 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 989 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 990 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 991 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 992 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 993 return true; 994 995 return false; 996 } 997 998 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 999 // explicitly ignoring m_distribution_id in this method. 1000 1001 if (GetByteOrder() != rhs.GetByteOrder()) 1002 return false; 1003 1004 const ArchSpec::Core lhs_core = GetCore(); 1005 const ArchSpec::Core rhs_core = rhs.GetCore(); 1006 1007 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1008 1009 if (core_match) { 1010 const llvm::Triple &lhs_triple = GetTriple(); 1011 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1012 1013 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1014 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1015 if (lhs_triple_vendor != rhs_triple_vendor) { 1016 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1017 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1018 // Both architectures had the vendor specified, so if they aren't equal 1019 // then we return false 1020 if (rhs_vendor_specified && lhs_vendor_specified) 1021 return false; 1022 1023 // Only fail if both vendor types are not unknown 1024 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1025 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1026 return false; 1027 } 1028 1029 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1030 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1031 if (lhs_triple_os != rhs_triple_os) { 1032 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1033 const bool lhs_os_specified = TripleOSWasSpecified(); 1034 // Both architectures had the OS specified, so if they aren't equal then 1035 // we return false 1036 if (rhs_os_specified && lhs_os_specified) 1037 return false; 1038 1039 // Only fail if both os types are not unknown 1040 if (lhs_triple_os != llvm::Triple::UnknownOS && 1041 rhs_triple_os != llvm::Triple::UnknownOS) 1042 return false; 1043 } 1044 1045 const llvm::Triple::EnvironmentType lhs_triple_env = 1046 lhs_triple.getEnvironment(); 1047 const llvm::Triple::EnvironmentType rhs_triple_env = 1048 rhs_triple.getEnvironment(); 1049 1050 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1051 } 1052 return false; 1053 } 1054 1055 void ArchSpec::UpdateCore() { 1056 llvm::StringRef arch_name(m_triple.getArchName()); 1057 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1058 if (core_def) { 1059 m_core = core_def->core; 1060 // Set the byte order to the default byte order for an architecture. This 1061 // can be modified if needed for cases when cores handle both big and 1062 // little endian 1063 m_byte_order = core_def->default_byte_order; 1064 } else { 1065 Clear(); 1066 } 1067 } 1068 1069 //===----------------------------------------------------------------------===// 1070 // Helper methods. 1071 1072 void ArchSpec::CoreUpdated(bool update_triple) { 1073 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1074 if (core_def) { 1075 if (update_triple) 1076 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1077 m_byte_order = core_def->default_byte_order; 1078 } else { 1079 if (update_triple) 1080 m_triple = llvm::Triple(); 1081 m_byte_order = eByteOrderInvalid; 1082 } 1083 } 1084 1085 //===----------------------------------------------------------------------===// 1086 // Operators. 1087 1088 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1089 bool try_inverse, bool enforce_exact_match) { 1090 if (core1 == core2) 1091 return true; 1092 1093 switch (core1) { 1094 case ArchSpec::kCore_any: 1095 return true; 1096 1097 case ArchSpec::eCore_arm_generic: 1098 if (enforce_exact_match) 1099 break; 1100 LLVM_FALLTHROUGH; 1101 case ArchSpec::kCore_arm_any: 1102 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1103 return true; 1104 if (core2 >= ArchSpec::kCore_thumb_first && 1105 core2 <= ArchSpec::kCore_thumb_last) 1106 return true; 1107 if (core2 == ArchSpec::kCore_arm_any) 1108 return true; 1109 break; 1110 1111 case ArchSpec::kCore_x86_32_any: 1112 if ((core2 >= ArchSpec::kCore_x86_32_first && 1113 core2 <= ArchSpec::kCore_x86_32_last) || 1114 (core2 == ArchSpec::kCore_x86_32_any)) 1115 return true; 1116 break; 1117 1118 case ArchSpec::kCore_x86_64_any: 1119 if ((core2 >= ArchSpec::kCore_x86_64_first && 1120 core2 <= ArchSpec::kCore_x86_64_last) || 1121 (core2 == ArchSpec::kCore_x86_64_any)) 1122 return true; 1123 break; 1124 1125 case ArchSpec::kCore_ppc_any: 1126 if ((core2 >= ArchSpec::kCore_ppc_first && 1127 core2 <= ArchSpec::kCore_ppc_last) || 1128 (core2 == ArchSpec::kCore_ppc_any)) 1129 return true; 1130 break; 1131 1132 case ArchSpec::kCore_ppc64_any: 1133 if ((core2 >= ArchSpec::kCore_ppc64_first && 1134 core2 <= ArchSpec::kCore_ppc64_last) || 1135 (core2 == ArchSpec::kCore_ppc64_any)) 1136 return true; 1137 break; 1138 1139 case ArchSpec::eCore_arm_armv6m: 1140 if (!enforce_exact_match) { 1141 if (core2 == ArchSpec::eCore_arm_generic) 1142 return true; 1143 try_inverse = false; 1144 if (core2 == ArchSpec::eCore_arm_armv7) 1145 return true; 1146 if (core2 == ArchSpec::eCore_arm_armv6m) 1147 return true; 1148 } 1149 break; 1150 1151 case ArchSpec::kCore_hexagon_any: 1152 if ((core2 >= ArchSpec::kCore_hexagon_first && 1153 core2 <= ArchSpec::kCore_hexagon_last) || 1154 (core2 == ArchSpec::kCore_hexagon_any)) 1155 return true; 1156 break; 1157 1158 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1159 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1160 // ARMv7E-M - armv7em 1161 case ArchSpec::eCore_arm_armv7em: 1162 if (!enforce_exact_match) { 1163 if (core2 == ArchSpec::eCore_arm_generic) 1164 return true; 1165 if (core2 == ArchSpec::eCore_arm_armv7m) 1166 return true; 1167 if (core2 == ArchSpec::eCore_arm_armv6m) 1168 return true; 1169 if (core2 == ArchSpec::eCore_arm_armv7) 1170 return true; 1171 try_inverse = true; 1172 } 1173 break; 1174 1175 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1176 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1177 // ARMv7E-M - armv7em 1178 case ArchSpec::eCore_arm_armv7m: 1179 if (!enforce_exact_match) { 1180 if (core2 == ArchSpec::eCore_arm_generic) 1181 return true; 1182 if (core2 == ArchSpec::eCore_arm_armv6m) 1183 return true; 1184 if (core2 == ArchSpec::eCore_arm_armv7) 1185 return true; 1186 if (core2 == ArchSpec::eCore_arm_armv7em) 1187 return true; 1188 try_inverse = true; 1189 } 1190 break; 1191 1192 case ArchSpec::eCore_arm_armv7f: 1193 case ArchSpec::eCore_arm_armv7k: 1194 case ArchSpec::eCore_arm_armv7s: 1195 case ArchSpec::eCore_arm_armv7l: 1196 case ArchSpec::eCore_arm_armv8l: 1197 if (!enforce_exact_match) { 1198 if (core2 == ArchSpec::eCore_arm_generic) 1199 return true; 1200 if (core2 == ArchSpec::eCore_arm_armv7) 1201 return true; 1202 try_inverse = false; 1203 } 1204 break; 1205 1206 case ArchSpec::eCore_x86_64_x86_64h: 1207 if (!enforce_exact_match) { 1208 try_inverse = false; 1209 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1210 return true; 1211 } 1212 break; 1213 1214 case ArchSpec::eCore_arm_armv8: 1215 if (!enforce_exact_match) { 1216 if (core2 == ArchSpec::eCore_arm_arm64) 1217 return true; 1218 if (core2 == ArchSpec::eCore_arm_aarch64) 1219 return true; 1220 try_inverse = false; 1221 } 1222 break; 1223 1224 case ArchSpec::eCore_arm_aarch64: 1225 if (!enforce_exact_match) { 1226 if (core2 == ArchSpec::eCore_arm_arm64) 1227 return true; 1228 if (core2 == ArchSpec::eCore_arm_armv8) 1229 return true; 1230 try_inverse = false; 1231 } 1232 break; 1233 1234 case ArchSpec::eCore_arm_arm64: 1235 if (!enforce_exact_match) { 1236 if (core2 == ArchSpec::eCore_arm_aarch64) 1237 return true; 1238 if (core2 == ArchSpec::eCore_arm_armv8) 1239 return true; 1240 try_inverse = false; 1241 } 1242 break; 1243 1244 case ArchSpec::eCore_arm_arm64_32: 1245 if (!enforce_exact_match) { 1246 if (core2 == ArchSpec::eCore_arm_generic) 1247 return true; 1248 try_inverse = false; 1249 } 1250 break; 1251 1252 case ArchSpec::eCore_mips32: 1253 if (!enforce_exact_match) { 1254 if (core2 >= ArchSpec::kCore_mips32_first && 1255 core2 <= ArchSpec::kCore_mips32_last) 1256 return true; 1257 try_inverse = false; 1258 } 1259 break; 1260 1261 case ArchSpec::eCore_mips32el: 1262 if (!enforce_exact_match) { 1263 if (core2 >= ArchSpec::kCore_mips32el_first && 1264 core2 <= ArchSpec::kCore_mips32el_last) 1265 return true; 1266 try_inverse = true; 1267 } 1268 break; 1269 1270 case ArchSpec::eCore_mips64: 1271 if (!enforce_exact_match) { 1272 if (core2 >= ArchSpec::kCore_mips32_first && 1273 core2 <= ArchSpec::kCore_mips32_last) 1274 return true; 1275 if (core2 >= ArchSpec::kCore_mips64_first && 1276 core2 <= ArchSpec::kCore_mips64_last) 1277 return true; 1278 try_inverse = false; 1279 } 1280 break; 1281 1282 case ArchSpec::eCore_mips64el: 1283 if (!enforce_exact_match) { 1284 if (core2 >= ArchSpec::kCore_mips32el_first && 1285 core2 <= ArchSpec::kCore_mips32el_last) 1286 return true; 1287 if (core2 >= ArchSpec::kCore_mips64el_first && 1288 core2 <= ArchSpec::kCore_mips64el_last) 1289 return true; 1290 try_inverse = false; 1291 } 1292 break; 1293 1294 case ArchSpec::eCore_mips64r2: 1295 case ArchSpec::eCore_mips64r3: 1296 case ArchSpec::eCore_mips64r5: 1297 if (!enforce_exact_match) { 1298 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1299 return true; 1300 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1301 return true; 1302 try_inverse = false; 1303 } 1304 break; 1305 1306 case ArchSpec::eCore_mips64r2el: 1307 case ArchSpec::eCore_mips64r3el: 1308 case ArchSpec::eCore_mips64r5el: 1309 if (!enforce_exact_match) { 1310 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1311 return true; 1312 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1313 return true; 1314 try_inverse = false; 1315 } 1316 break; 1317 1318 case ArchSpec::eCore_mips32r2: 1319 case ArchSpec::eCore_mips32r3: 1320 case ArchSpec::eCore_mips32r5: 1321 if (!enforce_exact_match) { 1322 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1323 return true; 1324 } 1325 break; 1326 1327 case ArchSpec::eCore_mips32r2el: 1328 case ArchSpec::eCore_mips32r3el: 1329 case ArchSpec::eCore_mips32r5el: 1330 if (!enforce_exact_match) { 1331 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1332 return true; 1333 } 1334 break; 1335 1336 case ArchSpec::eCore_mips32r6: 1337 if (!enforce_exact_match) { 1338 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1339 return true; 1340 } 1341 break; 1342 1343 case ArchSpec::eCore_mips32r6el: 1344 if (!enforce_exact_match) { 1345 if (core2 == ArchSpec::eCore_mips32el || 1346 core2 == ArchSpec::eCore_mips32r6el) 1347 return true; 1348 } 1349 break; 1350 1351 case ArchSpec::eCore_mips64r6: 1352 if (!enforce_exact_match) { 1353 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1354 return true; 1355 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1356 return true; 1357 } 1358 break; 1359 1360 case ArchSpec::eCore_mips64r6el: 1361 if (!enforce_exact_match) { 1362 if (core2 == ArchSpec::eCore_mips32el || 1363 core2 == ArchSpec::eCore_mips32r6el) 1364 return true; 1365 if (core2 == ArchSpec::eCore_mips64el || 1366 core2 == ArchSpec::eCore_mips64r6el) 1367 return true; 1368 } 1369 break; 1370 1371 default: 1372 break; 1373 } 1374 if (try_inverse) 1375 return cores_match(core2, core1, false, enforce_exact_match); 1376 return false; 1377 } 1378 1379 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1380 const ArchSpec::Core lhs_core = lhs.GetCore(); 1381 const ArchSpec::Core rhs_core = rhs.GetCore(); 1382 return lhs_core < rhs_core; 1383 } 1384 1385 1386 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1387 return lhs.GetCore() == rhs.GetCore(); 1388 } 1389 1390 bool ArchSpec::IsFullySpecifiedTriple() const { 1391 const auto &user_specified_triple = GetTriple(); 1392 1393 bool user_triple_fully_specified = false; 1394 1395 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1396 TripleOSWasSpecified()) { 1397 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1398 TripleVendorWasSpecified()) { 1399 const unsigned unspecified = 0; 1400 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1401 user_triple_fully_specified = true; 1402 } 1403 } 1404 } 1405 1406 return user_triple_fully_specified; 1407 } 1408 1409 void ArchSpec::PiecewiseTripleCompare( 1410 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1411 bool &os_different, bool &os_version_different, bool &env_different) const { 1412 const llvm::Triple &me(GetTriple()); 1413 const llvm::Triple &them(other.GetTriple()); 1414 1415 arch_different = (me.getArch() != them.getArch()); 1416 1417 vendor_different = (me.getVendor() != them.getVendor()); 1418 1419 os_different = (me.getOS() != them.getOS()); 1420 1421 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1422 1423 env_different = (me.getEnvironment() != them.getEnvironment()); 1424 } 1425 1426 bool ArchSpec::IsAlwaysThumbInstructions() const { 1427 std::string Status; 1428 if (GetTriple().getArch() == llvm::Triple::arm || 1429 GetTriple().getArch() == llvm::Triple::thumb) { 1430 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1431 // 1432 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1433 // execute thumb instructions. We map the cores to arch names like this: 1434 // 1435 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1436 // Cortex-M7: armv7em 1437 1438 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1439 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1440 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1441 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1442 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1443 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1444 return true; 1445 } 1446 } 1447 return false; 1448 } 1449 1450 void ArchSpec::DumpTriple(Stream &s) const { 1451 const llvm::Triple &triple = GetTriple(); 1452 llvm::StringRef arch_str = triple.getArchName(); 1453 llvm::StringRef vendor_str = triple.getVendorName(); 1454 llvm::StringRef os_str = triple.getOSName(); 1455 llvm::StringRef environ_str = triple.getEnvironmentName(); 1456 1457 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1458 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1459 os_str.empty() ? "*" : os_str.str().c_str()); 1460 1461 if (!environ_str.empty()) 1462 s.Printf("-%s", environ_str.str().c_str()); 1463 } 1464