1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "lldb/Utility/ArchSpec.h" 11 12 #include "lldb/Utility/Log.h" 13 #include "lldb/Utility/NameMatches.h" 14 #include "lldb/Utility/Stream.h" // for Stream 15 #include "lldb/Utility/StringList.h" 16 #include "lldb/lldb-defines.h" // for LLDB_INVALID_C... 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/Twine.h" // for Twine 19 #include "llvm/BinaryFormat/COFF.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/BinaryFormat/MachO.h" // for CPUType::CPU_T... 22 #include "llvm/Support/Compiler.h" // for LLVM_FALLTHROUGH 23 #include "llvm/Support/Host.h" 24 25 using namespace lldb; 26 using namespace lldb_private; 27 28 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 29 bool try_inverse, bool enforce_exact_match); 30 31 namespace lldb_private { 32 33 struct CoreDefinition { 34 ByteOrder default_byte_order; 35 uint32_t addr_byte_size; 36 uint32_t min_opcode_byte_size; 37 uint32_t max_opcode_byte_size; 38 llvm::Triple::ArchType machine; 39 ArchSpec::Core core; 40 const char *const name; 41 }; 42 43 } // namespace lldb_private 44 45 // This core information can be looked using the ArchSpec::Core as the index 46 static const CoreDefinition g_core_definitions[] = { 47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 48 "arm"}, 49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 50 "armv4"}, 51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 52 "armv4t"}, 53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 54 "armv5"}, 55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 56 "armv5e"}, 57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 58 "armv5t"}, 59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 60 "armv6"}, 61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 62 "armv6m"}, 63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 64 "armv7"}, 65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 66 "armv7f"}, 67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 68 "armv7s"}, 69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 70 "armv7k"}, 71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 72 "armv7m"}, 73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 74 "armv7em"}, 75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 76 "xscale"}, 77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 78 "thumb"}, 79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 80 "thumbv4t"}, 81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 82 "thumbv5"}, 83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 84 "thumbv5e"}, 85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 86 "thumbv6"}, 87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 88 "thumbv6m"}, 89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 90 "thumbv7"}, 91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 92 "thumbv7f"}, 93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 94 "thumbv7s"}, 95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 96 "thumbv7k"}, 97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 98 "thumbv7m"}, 99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 100 "thumbv7em"}, 101 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 102 ArchSpec::eCore_arm_arm64, "arm64"}, 103 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 104 ArchSpec::eCore_arm_armv8, "armv8"}, 105 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 106 ArchSpec::eCore_arm_aarch64, "aarch64"}, 107 108 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 109 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 110 "mips"}, 111 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 112 "mipsr2"}, 113 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 114 "mipsr3"}, 115 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 116 "mipsr5"}, 117 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 118 "mipsr6"}, 119 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 120 "mipsel"}, 121 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 122 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 123 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 124 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 125 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 126 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 127 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 128 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 129 130 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 131 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 132 "mips64"}, 133 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 134 "mips64r2"}, 135 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 136 "mips64r3"}, 137 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 138 "mips64r5"}, 139 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 140 "mips64r6"}, 141 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 142 ArchSpec::eCore_mips64el, "mips64el"}, 143 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 144 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 145 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 146 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 147 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 148 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 149 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 150 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 151 152 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 153 "powerpc"}, 154 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 155 "ppc601"}, 156 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 157 "ppc602"}, 158 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 159 "ppc603"}, 160 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 161 "ppc603e"}, 162 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 163 "ppc603ev"}, 164 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 165 "ppc604"}, 166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 167 "ppc604e"}, 168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 169 "ppc620"}, 170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 171 "ppc750"}, 172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 173 "ppc7400"}, 174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 175 "ppc7450"}, 176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 177 "ppc970"}, 178 179 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 180 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 181 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 182 "powerpc64"}, 183 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 184 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 185 186 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 187 ArchSpec::eCore_s390x_generic, "s390x"}, 188 189 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 190 ArchSpec::eCore_sparc_generic, "sparc"}, 191 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 192 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 193 194 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 195 "i386"}, 196 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 197 "i486"}, 198 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 199 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 200 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 201 "i686"}, 202 203 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 204 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 205 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 206 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 207 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 208 ArchSpec::eCore_hexagon_generic, "hexagon"}, 209 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 210 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 211 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 212 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 213 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 215 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 216 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 217 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 218 219 {eByteOrderBig, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba3, 220 "kalimba3"}, 221 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba4, 222 "kalimba4"}, 223 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba5, 224 "kalimba5"}}; 225 226 // Ensure that we have an entry in the g_core_definitions for each core. If you 227 // comment out an entry above, you will need to comment out the corresponding 228 // ArchSpec::Core enumeration. 229 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 230 ArchSpec::kNumCores, 231 "make sure we have one core definition for each core"); 232 233 struct ArchDefinitionEntry { 234 ArchSpec::Core core; 235 uint32_t cpu; 236 uint32_t sub; 237 uint32_t cpu_mask; 238 uint32_t sub_mask; 239 }; 240 241 struct ArchDefinition { 242 ArchitectureType type; 243 size_t num_entries; 244 const ArchDefinitionEntry *entries; 245 const char *name; 246 }; 247 248 size_t ArchSpec::AutoComplete(llvm::StringRef name, StringList &matches) { 249 if (!name.empty()) { 250 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 251 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, name)) 252 matches.AppendString(g_core_definitions[i].name); 253 } 254 } else { 255 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 256 matches.AppendString(g_core_definitions[i].name); 257 } 258 return matches.GetSize(); 259 } 260 261 #define CPU_ANY (UINT32_MAX) 262 263 //===----------------------------------------------------------------------===// 264 // A table that gets searched linearly for matches. This table is used to 265 // convert cpu type and subtypes to architecture names, and to convert 266 // architecture names to cpu types and subtypes. The ordering is important and 267 // allows the precedence to be set when the table is built. 268 #define SUBTYPE_MASK 0x00FFFFFFu 269 270 static const ArchDefinitionEntry g_macho_arch_entries[] = { 271 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 272 UINT32_MAX, UINT32_MAX}, 273 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 302 SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 306 SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 308 SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 310 UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 312 SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 314 SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 336 UINT32_MAX, UINT32_MAX}, 337 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 340 SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 364 UINT32_MAX, SUBTYPE_MASK}, 365 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 366 UINT32_MAX, SUBTYPE_MASK}, 367 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 368 UINT32_MAX, SUBTYPE_MASK}, 369 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 370 SUBTYPE_MASK}, 371 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 372 SUBTYPE_MASK}, 373 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 374 UINT32_MAX, SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 376 UINT32_MAX, UINT32_MAX}, 377 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 378 SUBTYPE_MASK}, 379 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 380 SUBTYPE_MASK}, 381 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 382 UINT32_MAX, SUBTYPE_MASK}, 383 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 384 UINT32_MAX, UINT32_MAX}, 385 // Catch any unknown mach architectures so we can always use the object and 386 // symbol mach-o files 387 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 388 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 389 0x00000000u}}; 390 391 static const ArchDefinition g_macho_arch_def = { 392 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 393 g_macho_arch_entries, "mach-o"}; 394 395 //===----------------------------------------------------------------------===// 396 // A table that gets searched linearly for matches. This table is used to 397 // convert cpu type and subtypes to architecture names, and to convert 398 // architecture names to cpu types and subtypes. The ordering is important and 399 // allows the precedence to be set when the table is built. 400 static const ArchDefinitionEntry g_elf_arch_entries[] = { 401 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 402 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 403 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 404 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 405 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 407 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 409 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 411 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 413 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 415 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 416 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 417 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 419 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 420 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 421 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 422 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 423 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 424 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 425 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 426 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 427 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 428 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 429 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 431 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 433 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 435 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 436 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 437 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 438 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 439 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 440 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 441 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 442 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 443 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 444 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 445 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 446 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 447 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 448 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 449 {ArchSpec::eCore_kalimba3, llvm::ELF::EM_CSR_KALIMBA, 450 llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 451 {ArchSpec::eCore_kalimba4, llvm::ELF::EM_CSR_KALIMBA, 452 llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 453 {ArchSpec::eCore_kalimba5, llvm::ELF::EM_CSR_KALIMBA, 454 llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu} // KALIMBA 455 }; 456 457 static const ArchDefinition g_elf_arch_def = { 458 eArchTypeELF, 459 llvm::array_lengthof(g_elf_arch_entries), 460 g_elf_arch_entries, 461 "elf", 462 }; 463 464 static const ArchDefinitionEntry g_coff_arch_entries[] = { 465 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 466 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 467 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 468 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 469 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 470 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 471 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 472 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 473 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 474 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 475 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 476 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 477 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 478 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 479 }; 480 481 static const ArchDefinition g_coff_arch_def = { 482 eArchTypeCOFF, 483 llvm::array_lengthof(g_coff_arch_entries), 484 g_coff_arch_entries, 485 "pe-coff", 486 }; 487 488 //===----------------------------------------------------------------------===// 489 // Table of all ArchDefinitions 490 static const ArchDefinition *g_arch_definitions[] = { 491 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 492 493 static const size_t k_num_arch_definitions = 494 llvm::array_lengthof(g_arch_definitions); 495 496 //===----------------------------------------------------------------------===// 497 // Static helper functions. 498 499 // Get the architecture definition for a given object type. 500 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 501 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 502 const ArchDefinition *def = g_arch_definitions[i]; 503 if (def->type == arch_type) 504 return def; 505 } 506 return nullptr; 507 } 508 509 // Get an architecture definition by name. 510 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 511 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 512 if (name.equals_lower(g_core_definitions[i].name)) 513 return &g_core_definitions[i]; 514 } 515 return nullptr; 516 } 517 518 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 519 if (core < llvm::array_lengthof(g_core_definitions)) 520 return &g_core_definitions[core]; 521 return nullptr; 522 } 523 524 // Get a definition entry by cpu type and subtype. 525 static const ArchDefinitionEntry * 526 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 527 if (def == nullptr) 528 return nullptr; 529 530 const ArchDefinitionEntry *entries = def->entries; 531 for (size_t i = 0; i < def->num_entries; ++i) { 532 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 533 if (entries[i].sub == (sub & entries[i].sub_mask)) 534 return &entries[i]; 535 } 536 return nullptr; 537 } 538 539 static const ArchDefinitionEntry * 540 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 541 if (def == nullptr) 542 return nullptr; 543 544 const ArchDefinitionEntry *entries = def->entries; 545 for (size_t i = 0; i < def->num_entries; ++i) { 546 if (entries[i].core == core) 547 return &entries[i]; 548 } 549 return nullptr; 550 } 551 552 //===----------------------------------------------------------------------===// 553 // Constructors and destructors. 554 555 ArchSpec::ArchSpec() {} 556 557 ArchSpec::ArchSpec(const char *triple_cstr) { 558 if (triple_cstr) 559 SetTriple(triple_cstr); 560 } 561 562 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 563 564 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 565 566 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 567 SetArchitecture(arch_type, cpu, subtype); 568 } 569 570 ArchSpec::~ArchSpec() = default; 571 572 //===----------------------------------------------------------------------===// 573 // Assignment and initialization. 574 575 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 576 if (this != &rhs) { 577 m_triple = rhs.m_triple; 578 m_core = rhs.m_core; 579 m_byte_order = rhs.m_byte_order; 580 m_distribution_id = rhs.m_distribution_id; 581 m_flags = rhs.m_flags; 582 } 583 return *this; 584 } 585 586 void ArchSpec::Clear() { 587 m_triple = llvm::Triple(); 588 m_core = kCore_invalid; 589 m_byte_order = eByteOrderInvalid; 590 m_distribution_id.Clear(); 591 m_flags = 0; 592 } 593 594 //===----------------------------------------------------------------------===// 595 // Predicates. 596 597 const char *ArchSpec::GetArchitectureName() const { 598 const CoreDefinition *core_def = FindCoreDefinition(m_core); 599 if (core_def) 600 return core_def->name; 601 return "unknown"; 602 } 603 604 bool ArchSpec::IsMIPS() const { 605 const llvm::Triple::ArchType machine = GetMachine(); 606 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 607 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) 608 return true; 609 return false; 610 } 611 612 std::string ArchSpec::GetTargetABI() const { 613 614 std::string abi; 615 616 if (IsMIPS()) { 617 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 618 case ArchSpec::eMIPSABI_N64: 619 abi = "n64"; 620 return abi; 621 case ArchSpec::eMIPSABI_N32: 622 abi = "n32"; 623 return abi; 624 case ArchSpec::eMIPSABI_O32: 625 abi = "o32"; 626 return abi; 627 default: 628 return abi; 629 } 630 } 631 return abi; 632 } 633 634 void ArchSpec::SetFlags(std::string elf_abi) { 635 636 uint32_t flag = GetFlags(); 637 if (IsMIPS()) { 638 if (elf_abi == "n64") 639 flag |= ArchSpec::eMIPSABI_N64; 640 else if (elf_abi == "n32") 641 flag |= ArchSpec::eMIPSABI_N32; 642 else if (elf_abi == "o32") 643 flag |= ArchSpec::eMIPSABI_O32; 644 } 645 SetFlags(flag); 646 } 647 648 std::string ArchSpec::GetClangTargetCPU() const { 649 std::string cpu; 650 const llvm::Triple::ArchType machine = GetMachine(); 651 652 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 653 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) { 654 switch (m_core) { 655 case ArchSpec::eCore_mips32: 656 case ArchSpec::eCore_mips32el: 657 cpu = "mips32"; 658 break; 659 case ArchSpec::eCore_mips32r2: 660 case ArchSpec::eCore_mips32r2el: 661 cpu = "mips32r2"; 662 break; 663 case ArchSpec::eCore_mips32r3: 664 case ArchSpec::eCore_mips32r3el: 665 cpu = "mips32r3"; 666 break; 667 case ArchSpec::eCore_mips32r5: 668 case ArchSpec::eCore_mips32r5el: 669 cpu = "mips32r5"; 670 break; 671 case ArchSpec::eCore_mips32r6: 672 case ArchSpec::eCore_mips32r6el: 673 cpu = "mips32r6"; 674 break; 675 case ArchSpec::eCore_mips64: 676 case ArchSpec::eCore_mips64el: 677 cpu = "mips64"; 678 break; 679 case ArchSpec::eCore_mips64r2: 680 case ArchSpec::eCore_mips64r2el: 681 cpu = "mips64r2"; 682 break; 683 case ArchSpec::eCore_mips64r3: 684 case ArchSpec::eCore_mips64r3el: 685 cpu = "mips64r3"; 686 break; 687 case ArchSpec::eCore_mips64r5: 688 case ArchSpec::eCore_mips64r5el: 689 cpu = "mips64r5"; 690 break; 691 case ArchSpec::eCore_mips64r6: 692 case ArchSpec::eCore_mips64r6el: 693 cpu = "mips64r6"; 694 break; 695 default: 696 break; 697 } 698 } 699 return cpu; 700 } 701 702 uint32_t ArchSpec::GetMachOCPUType() const { 703 const CoreDefinition *core_def = FindCoreDefinition(m_core); 704 if (core_def) { 705 const ArchDefinitionEntry *arch_def = 706 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 707 if (arch_def) { 708 return arch_def->cpu; 709 } 710 } 711 return LLDB_INVALID_CPUTYPE; 712 } 713 714 uint32_t ArchSpec::GetMachOCPUSubType() const { 715 const CoreDefinition *core_def = FindCoreDefinition(m_core); 716 if (core_def) { 717 const ArchDefinitionEntry *arch_def = 718 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 719 if (arch_def) { 720 return arch_def->sub; 721 } 722 } 723 return LLDB_INVALID_CPUTYPE; 724 } 725 726 uint32_t ArchSpec::GetDataByteSize() const { 727 switch (m_core) { 728 case eCore_kalimba3: 729 return 4; 730 case eCore_kalimba4: 731 return 1; 732 case eCore_kalimba5: 733 return 4; 734 default: 735 return 1; 736 } 737 return 1; 738 } 739 740 uint32_t ArchSpec::GetCodeByteSize() const { 741 switch (m_core) { 742 case eCore_kalimba3: 743 return 4; 744 case eCore_kalimba4: 745 return 1; 746 case eCore_kalimba5: 747 return 1; 748 default: 749 return 1; 750 } 751 return 1; 752 } 753 754 llvm::Triple::ArchType ArchSpec::GetMachine() const { 755 const CoreDefinition *core_def = FindCoreDefinition(m_core); 756 if (core_def) 757 return core_def->machine; 758 759 return llvm::Triple::UnknownArch; 760 } 761 762 const ConstString &ArchSpec::GetDistributionId() const { 763 return m_distribution_id; 764 } 765 766 void ArchSpec::SetDistributionId(const char *distribution_id) { 767 m_distribution_id.SetCString(distribution_id); 768 } 769 770 uint32_t ArchSpec::GetAddressByteSize() const { 771 const CoreDefinition *core_def = FindCoreDefinition(m_core); 772 if (core_def) { 773 if (core_def->machine == llvm::Triple::mips64 || 774 core_def->machine == llvm::Triple::mips64el) { 775 // For N32/O32 applications Address size is 4 bytes. 776 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 777 return 4; 778 } 779 return core_def->addr_byte_size; 780 } 781 return 0; 782 } 783 784 ByteOrder ArchSpec::GetDefaultEndian() const { 785 const CoreDefinition *core_def = FindCoreDefinition(m_core); 786 if (core_def) 787 return core_def->default_byte_order; 788 return eByteOrderInvalid; 789 } 790 791 bool ArchSpec::CharIsSignedByDefault() const { 792 switch (m_triple.getArch()) { 793 default: 794 return true; 795 796 case llvm::Triple::aarch64: 797 case llvm::Triple::aarch64_be: 798 case llvm::Triple::arm: 799 case llvm::Triple::armeb: 800 case llvm::Triple::thumb: 801 case llvm::Triple::thumbeb: 802 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 803 804 case llvm::Triple::ppc: 805 case llvm::Triple::ppc64: 806 return m_triple.isOSDarwin(); 807 808 case llvm::Triple::ppc64le: 809 case llvm::Triple::systemz: 810 case llvm::Triple::xcore: 811 return false; 812 } 813 } 814 815 lldb::ByteOrder ArchSpec::GetByteOrder() const { 816 if (m_byte_order == eByteOrderInvalid) 817 return GetDefaultEndian(); 818 return m_byte_order; 819 } 820 821 //===----------------------------------------------------------------------===// 822 // Mutators. 823 824 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 825 m_triple = triple; 826 UpdateCore(); 827 return IsValid(); 828 } 829 830 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 831 ArchSpec &arch) { 832 // Accept "12-10" or "12.10" as cpu type/subtype 833 if (triple_str.empty()) 834 return false; 835 836 size_t pos = triple_str.find_first_of("-."); 837 if (pos == llvm::StringRef::npos) 838 return false; 839 840 llvm::StringRef cpu_str = triple_str.substr(0, pos); 841 llvm::StringRef remainder = triple_str.substr(pos + 1); 842 if (cpu_str.empty() || remainder.empty()) 843 return false; 844 845 llvm::StringRef sub_str; 846 llvm::StringRef vendor; 847 llvm::StringRef os; 848 std::tie(sub_str, remainder) = remainder.split('-'); 849 std::tie(vendor, os) = remainder.split('-'); 850 851 uint32_t cpu = 0; 852 uint32_t sub = 0; 853 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 854 return false; 855 856 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 857 return false; 858 if (!vendor.empty() && !os.empty()) { 859 arch.GetTriple().setVendorName(vendor); 860 arch.GetTriple().setOSName(os); 861 } 862 863 return true; 864 } 865 866 bool ArchSpec::SetTriple(llvm::StringRef triple) { 867 if (triple.empty()) { 868 Clear(); 869 return false; 870 } 871 872 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 873 return true; 874 875 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 876 return IsValid(); 877 } 878 879 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 880 return !normalized_triple.getArchName().empty() && 881 normalized_triple.getOSName().empty() && 882 normalized_triple.getVendorName().empty() && 883 normalized_triple.getEnvironmentName().empty(); 884 } 885 886 void ArchSpec::MergeFrom(const ArchSpec &other) { 887 if (TripleVendorIsUnspecifiedUnknown() && 888 !other.TripleVendorIsUnspecifiedUnknown()) 889 GetTriple().setVendor(other.GetTriple().getVendor()); 890 if (TripleOSIsUnspecifiedUnknown() && !other.TripleOSIsUnspecifiedUnknown()) 891 GetTriple().setOS(other.GetTriple().getOS()); 892 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 893 GetTriple().setArch(other.GetTriple().getArch()); 894 895 // MachO unknown64 isn't really invalid as the debugger can still obtain 896 // information from the binary, e.g. line tables. As such, we don't update 897 // the core here. 898 if (other.GetCore() != eCore_uknownMach64) 899 UpdateCore(); 900 } 901 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 902 !TripleVendorWasSpecified()) { 903 if (other.TripleVendorWasSpecified()) 904 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 905 } 906 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 907 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 908 // adopt the specific arm core. 909 if (GetTriple().getArch() == llvm::Triple::arm && 910 other.GetTriple().getArch() == llvm::Triple::arm && 911 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 912 other.GetCore() != ArchSpec::eCore_arm_generic) { 913 m_core = other.GetCore(); 914 CoreUpdated(true); 915 } 916 if (GetFlags() == 0) { 917 SetFlags(other.GetFlags()); 918 } 919 } 920 921 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 922 uint32_t sub, uint32_t os) { 923 m_core = kCore_invalid; 924 bool update_triple = true; 925 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 926 if (arch_def) { 927 const ArchDefinitionEntry *arch_def_entry = 928 FindArchDefinitionEntry(arch_def, cpu, sub); 929 if (arch_def_entry) { 930 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 931 if (core_def) { 932 m_core = core_def->core; 933 update_triple = false; 934 // Always use the architecture name because it might be more 935 // descriptive than the architecture enum ("armv7" -> 936 // llvm::Triple::arm). 937 m_triple.setArchName(llvm::StringRef(core_def->name)); 938 if (arch_type == eArchTypeMachO) { 939 m_triple.setVendor(llvm::Triple::Apple); 940 941 // Don't set the OS. It could be simulator, macosx, ios, watchos, 942 // tvos. We could get close with the cpu type - but we can't get it 943 // right all of the time. Better to leave this unset so other 944 // sections of code will set it when they have more information. 945 // NB: don't call m_triple.setOS (llvm::Triple::UnknownOS). That sets 946 // the OSName to 947 // "unknown" and the ArchSpec::TripleVendorWasSpecified() method says 948 // that any OSName setting means it was specified. 949 } else if (arch_type == eArchTypeELF) { 950 switch (os) { 951 case llvm::ELF::ELFOSABI_AIX: 952 m_triple.setOS(llvm::Triple::OSType::AIX); 953 break; 954 case llvm::ELF::ELFOSABI_FREEBSD: 955 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 956 break; 957 case llvm::ELF::ELFOSABI_GNU: 958 m_triple.setOS(llvm::Triple::OSType::Linux); 959 break; 960 case llvm::ELF::ELFOSABI_NETBSD: 961 m_triple.setOS(llvm::Triple::OSType::NetBSD); 962 break; 963 case llvm::ELF::ELFOSABI_OPENBSD: 964 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 965 break; 966 case llvm::ELF::ELFOSABI_SOLARIS: 967 m_triple.setOS(llvm::Triple::OSType::Solaris); 968 break; 969 } 970 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 971 m_triple.setVendor(llvm::Triple::PC); 972 m_triple.setOS(llvm::Triple::Win32); 973 } else { 974 m_triple.setVendor(llvm::Triple::UnknownVendor); 975 m_triple.setOS(llvm::Triple::UnknownOS); 976 } 977 // Fall back onto setting the machine type if the arch by name 978 // failed... 979 if (m_triple.getArch() == llvm::Triple::UnknownArch) 980 m_triple.setArch(core_def->machine); 981 } 982 } else { 983 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 984 if (log) 985 log->Printf("Unable to find a core definition for cpu 0x%" PRIx32 " sub %" PRId32, cpu, sub); 986 } 987 } 988 CoreUpdated(update_triple); 989 return IsValid(); 990 } 991 992 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 993 const CoreDefinition *core_def = FindCoreDefinition(m_core); 994 if (core_def) 995 return core_def->min_opcode_byte_size; 996 return 0; 997 } 998 999 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 1000 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1001 if (core_def) 1002 return core_def->max_opcode_byte_size; 1003 return 0; 1004 } 1005 1006 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 1007 return IsEqualTo(rhs, true); 1008 } 1009 1010 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 1011 return IsEqualTo(rhs, false); 1012 } 1013 1014 static bool isCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 1015 llvm::Triple::EnvironmentType rhs) { 1016 if (lhs == rhs) 1017 return true; 1018 1019 // If any of the environment is unknown then they are compatible 1020 if (lhs == llvm::Triple::UnknownEnvironment || 1021 rhs == llvm::Triple::UnknownEnvironment) 1022 return true; 1023 1024 // If one of the environment is Android and the other one is EABI then they 1025 // are considered to be compatible. This is required as a workaround for 1026 // shared libraries compiled for Android without the NOTE section indicating 1027 // that they are using the Android ABI. 1028 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 1029 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 1030 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1031 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1032 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1033 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1034 return true; 1035 1036 return false; 1037 } 1038 1039 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1040 // explicitly ignoring m_distribution_id in this method. 1041 1042 if (GetByteOrder() != rhs.GetByteOrder()) 1043 return false; 1044 1045 const ArchSpec::Core lhs_core = GetCore(); 1046 const ArchSpec::Core rhs_core = rhs.GetCore(); 1047 1048 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1049 1050 if (core_match) { 1051 const llvm::Triple &lhs_triple = GetTriple(); 1052 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1053 1054 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1055 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1056 if (lhs_triple_vendor != rhs_triple_vendor) { 1057 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1058 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1059 // Both architectures had the vendor specified, so if they aren't equal 1060 // then we return false 1061 if (rhs_vendor_specified && lhs_vendor_specified) 1062 return false; 1063 1064 // Only fail if both vendor types are not unknown 1065 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1066 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1067 return false; 1068 } 1069 1070 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1071 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1072 if (lhs_triple_os != rhs_triple_os) { 1073 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1074 const bool lhs_os_specified = TripleOSWasSpecified(); 1075 // Both architectures had the OS specified, so if they aren't equal then 1076 // we return false 1077 if (rhs_os_specified && lhs_os_specified) 1078 return false; 1079 1080 // Only fail if both os types are not unknown 1081 if (lhs_triple_os != llvm::Triple::UnknownOS && 1082 rhs_triple_os != llvm::Triple::UnknownOS) 1083 return false; 1084 } 1085 1086 const llvm::Triple::EnvironmentType lhs_triple_env = 1087 lhs_triple.getEnvironment(); 1088 const llvm::Triple::EnvironmentType rhs_triple_env = 1089 rhs_triple.getEnvironment(); 1090 1091 if (!isCompatibleEnvironment(lhs_triple_env, rhs_triple_env)) 1092 return false; 1093 return true; 1094 } 1095 return false; 1096 } 1097 1098 void ArchSpec::UpdateCore() { 1099 llvm::StringRef arch_name(m_triple.getArchName()); 1100 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1101 if (core_def) { 1102 m_core = core_def->core; 1103 // Set the byte order to the default byte order for an architecture. This 1104 // can be modified if needed for cases when cores handle both big and 1105 // little endian 1106 m_byte_order = core_def->default_byte_order; 1107 } else { 1108 Clear(); 1109 } 1110 } 1111 1112 //===----------------------------------------------------------------------===// 1113 // Helper methods. 1114 1115 void ArchSpec::CoreUpdated(bool update_triple) { 1116 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1117 if (core_def) { 1118 if (update_triple) 1119 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1120 m_byte_order = core_def->default_byte_order; 1121 } else { 1122 if (update_triple) 1123 m_triple = llvm::Triple(); 1124 m_byte_order = eByteOrderInvalid; 1125 } 1126 } 1127 1128 //===----------------------------------------------------------------------===// 1129 // Operators. 1130 1131 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1132 bool try_inverse, bool enforce_exact_match) { 1133 if (core1 == core2) 1134 return true; 1135 1136 switch (core1) { 1137 case ArchSpec::kCore_any: 1138 return true; 1139 1140 case ArchSpec::eCore_arm_generic: 1141 if (enforce_exact_match) 1142 break; 1143 LLVM_FALLTHROUGH; 1144 case ArchSpec::kCore_arm_any: 1145 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1146 return true; 1147 if (core2 >= ArchSpec::kCore_thumb_first && 1148 core2 <= ArchSpec::kCore_thumb_last) 1149 return true; 1150 if (core2 == ArchSpec::kCore_arm_any) 1151 return true; 1152 break; 1153 1154 case ArchSpec::kCore_x86_32_any: 1155 if ((core2 >= ArchSpec::kCore_x86_32_first && 1156 core2 <= ArchSpec::kCore_x86_32_last) || 1157 (core2 == ArchSpec::kCore_x86_32_any)) 1158 return true; 1159 break; 1160 1161 case ArchSpec::kCore_x86_64_any: 1162 if ((core2 >= ArchSpec::kCore_x86_64_first && 1163 core2 <= ArchSpec::kCore_x86_64_last) || 1164 (core2 == ArchSpec::kCore_x86_64_any)) 1165 return true; 1166 break; 1167 1168 case ArchSpec::kCore_ppc_any: 1169 if ((core2 >= ArchSpec::kCore_ppc_first && 1170 core2 <= ArchSpec::kCore_ppc_last) || 1171 (core2 == ArchSpec::kCore_ppc_any)) 1172 return true; 1173 break; 1174 1175 case ArchSpec::kCore_ppc64_any: 1176 if ((core2 >= ArchSpec::kCore_ppc64_first && 1177 core2 <= ArchSpec::kCore_ppc64_last) || 1178 (core2 == ArchSpec::kCore_ppc64_any)) 1179 return true; 1180 break; 1181 1182 case ArchSpec::eCore_arm_armv6m: 1183 if (!enforce_exact_match) { 1184 if (core2 == ArchSpec::eCore_arm_generic) 1185 return true; 1186 try_inverse = false; 1187 if (core2 == ArchSpec::eCore_arm_armv7) 1188 return true; 1189 if (core2 == ArchSpec::eCore_arm_armv6m) 1190 return true; 1191 } 1192 break; 1193 1194 case ArchSpec::kCore_hexagon_any: 1195 if ((core2 >= ArchSpec::kCore_hexagon_first && 1196 core2 <= ArchSpec::kCore_hexagon_last) || 1197 (core2 == ArchSpec::kCore_hexagon_any)) 1198 return true; 1199 break; 1200 1201 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1202 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1203 // ARMv7E-M - armv7em 1204 case ArchSpec::eCore_arm_armv7em: 1205 if (!enforce_exact_match) { 1206 if (core2 == ArchSpec::eCore_arm_generic) 1207 return true; 1208 if (core2 == ArchSpec::eCore_arm_armv7m) 1209 return true; 1210 if (core2 == ArchSpec::eCore_arm_armv6m) 1211 return true; 1212 if (core2 == ArchSpec::eCore_arm_armv7) 1213 return true; 1214 try_inverse = true; 1215 } 1216 break; 1217 1218 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1219 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1220 // ARMv7E-M - armv7em 1221 case ArchSpec::eCore_arm_armv7m: 1222 if (!enforce_exact_match) { 1223 if (core2 == ArchSpec::eCore_arm_generic) 1224 return true; 1225 if (core2 == ArchSpec::eCore_arm_armv6m) 1226 return true; 1227 if (core2 == ArchSpec::eCore_arm_armv7) 1228 return true; 1229 if (core2 == ArchSpec::eCore_arm_armv7em) 1230 return true; 1231 try_inverse = true; 1232 } 1233 break; 1234 1235 case ArchSpec::eCore_arm_armv7f: 1236 case ArchSpec::eCore_arm_armv7k: 1237 case ArchSpec::eCore_arm_armv7s: 1238 if (!enforce_exact_match) { 1239 if (core2 == ArchSpec::eCore_arm_generic) 1240 return true; 1241 if (core2 == ArchSpec::eCore_arm_armv7) 1242 return true; 1243 try_inverse = false; 1244 } 1245 break; 1246 1247 case ArchSpec::eCore_x86_64_x86_64h: 1248 if (!enforce_exact_match) { 1249 try_inverse = false; 1250 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1251 return true; 1252 } 1253 break; 1254 1255 case ArchSpec::eCore_arm_armv8: 1256 if (!enforce_exact_match) { 1257 if (core2 == ArchSpec::eCore_arm_arm64) 1258 return true; 1259 if (core2 == ArchSpec::eCore_arm_aarch64) 1260 return true; 1261 try_inverse = false; 1262 } 1263 break; 1264 1265 case ArchSpec::eCore_arm_aarch64: 1266 if (!enforce_exact_match) { 1267 if (core2 == ArchSpec::eCore_arm_arm64) 1268 return true; 1269 if (core2 == ArchSpec::eCore_arm_armv8) 1270 return true; 1271 try_inverse = false; 1272 } 1273 break; 1274 1275 case ArchSpec::eCore_arm_arm64: 1276 if (!enforce_exact_match) { 1277 if (core2 == ArchSpec::eCore_arm_aarch64) 1278 return true; 1279 if (core2 == ArchSpec::eCore_arm_armv8) 1280 return true; 1281 try_inverse = false; 1282 } 1283 break; 1284 1285 case ArchSpec::eCore_mips32: 1286 if (!enforce_exact_match) { 1287 if (core2 >= ArchSpec::kCore_mips32_first && 1288 core2 <= ArchSpec::kCore_mips32_last) 1289 return true; 1290 try_inverse = false; 1291 } 1292 break; 1293 1294 case ArchSpec::eCore_mips32el: 1295 if (!enforce_exact_match) { 1296 if (core2 >= ArchSpec::kCore_mips32el_first && 1297 core2 <= ArchSpec::kCore_mips32el_last) 1298 return true; 1299 try_inverse = true; 1300 } 1301 break; 1302 1303 case ArchSpec::eCore_mips64: 1304 if (!enforce_exact_match) { 1305 if (core2 >= ArchSpec::kCore_mips32_first && 1306 core2 <= ArchSpec::kCore_mips32_last) 1307 return true; 1308 if (core2 >= ArchSpec::kCore_mips64_first && 1309 core2 <= ArchSpec::kCore_mips64_last) 1310 return true; 1311 try_inverse = false; 1312 } 1313 break; 1314 1315 case ArchSpec::eCore_mips64el: 1316 if (!enforce_exact_match) { 1317 if (core2 >= ArchSpec::kCore_mips32el_first && 1318 core2 <= ArchSpec::kCore_mips32el_last) 1319 return true; 1320 if (core2 >= ArchSpec::kCore_mips64el_first && 1321 core2 <= ArchSpec::kCore_mips64el_last) 1322 return true; 1323 try_inverse = false; 1324 } 1325 break; 1326 1327 case ArchSpec::eCore_mips64r2: 1328 case ArchSpec::eCore_mips64r3: 1329 case ArchSpec::eCore_mips64r5: 1330 if (!enforce_exact_match) { 1331 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1332 return true; 1333 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1334 return true; 1335 try_inverse = false; 1336 } 1337 break; 1338 1339 case ArchSpec::eCore_mips64r2el: 1340 case ArchSpec::eCore_mips64r3el: 1341 case ArchSpec::eCore_mips64r5el: 1342 if (!enforce_exact_match) { 1343 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1344 return true; 1345 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1346 return true; 1347 try_inverse = false; 1348 } 1349 break; 1350 1351 case ArchSpec::eCore_mips32r2: 1352 case ArchSpec::eCore_mips32r3: 1353 case ArchSpec::eCore_mips32r5: 1354 if (!enforce_exact_match) { 1355 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1356 return true; 1357 } 1358 break; 1359 1360 case ArchSpec::eCore_mips32r2el: 1361 case ArchSpec::eCore_mips32r3el: 1362 case ArchSpec::eCore_mips32r5el: 1363 if (!enforce_exact_match) { 1364 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1365 return true; 1366 } 1367 break; 1368 1369 case ArchSpec::eCore_mips32r6: 1370 if (!enforce_exact_match) { 1371 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1372 return true; 1373 } 1374 break; 1375 1376 case ArchSpec::eCore_mips32r6el: 1377 if (!enforce_exact_match) { 1378 if (core2 == ArchSpec::eCore_mips32el || 1379 core2 == ArchSpec::eCore_mips32r6el) 1380 return true; 1381 } 1382 break; 1383 1384 case ArchSpec::eCore_mips64r6: 1385 if (!enforce_exact_match) { 1386 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1387 return true; 1388 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1389 return true; 1390 } 1391 break; 1392 1393 case ArchSpec::eCore_mips64r6el: 1394 if (!enforce_exact_match) { 1395 if (core2 == ArchSpec::eCore_mips32el || 1396 core2 == ArchSpec::eCore_mips32r6el) 1397 return true; 1398 if (core2 == ArchSpec::eCore_mips64el || 1399 core2 == ArchSpec::eCore_mips64r6el) 1400 return true; 1401 } 1402 break; 1403 1404 default: 1405 break; 1406 } 1407 if (try_inverse) 1408 return cores_match(core2, core1, false, enforce_exact_match); 1409 return false; 1410 } 1411 1412 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1413 const ArchSpec::Core lhs_core = lhs.GetCore(); 1414 const ArchSpec::Core rhs_core = rhs.GetCore(); 1415 return lhs_core < rhs_core; 1416 } 1417 1418 1419 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1420 return lhs.GetCore() == rhs.GetCore(); 1421 } 1422 1423 bool ArchSpec::IsFullySpecifiedTriple() const { 1424 const auto &user_specified_triple = GetTriple(); 1425 1426 bool user_triple_fully_specified = false; 1427 1428 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1429 TripleOSWasSpecified()) { 1430 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1431 TripleVendorWasSpecified()) { 1432 const unsigned unspecified = 0; 1433 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1434 user_triple_fully_specified = true; 1435 } 1436 } 1437 } 1438 1439 return user_triple_fully_specified; 1440 } 1441 1442 void ArchSpec::PiecewiseTripleCompare( 1443 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1444 bool &os_different, bool &os_version_different, bool &env_different) const { 1445 const llvm::Triple &me(GetTriple()); 1446 const llvm::Triple &them(other.GetTriple()); 1447 1448 arch_different = (me.getArch() != them.getArch()); 1449 1450 vendor_different = (me.getVendor() != them.getVendor()); 1451 1452 os_different = (me.getOS() != them.getOS()); 1453 1454 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1455 1456 env_different = (me.getEnvironment() != them.getEnvironment()); 1457 } 1458 1459 bool ArchSpec::IsAlwaysThumbInstructions() const { 1460 std::string Status; 1461 if (GetTriple().getArch() == llvm::Triple::arm || 1462 GetTriple().getArch() == llvm::Triple::thumb) { 1463 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1464 // 1465 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1466 // execute thumb instructions. We map the cores to arch names like this: 1467 // 1468 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1469 // Cortex-M7: armv7em 1470 1471 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1472 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1473 GetCore() == ArchSpec::Core::eCore_arm_armv6m) { 1474 return true; 1475 } 1476 } 1477 return false; 1478 } 1479 1480 void ArchSpec::DumpTriple(Stream &s) const { 1481 const llvm::Triple &triple = GetTriple(); 1482 llvm::StringRef arch_str = triple.getArchName(); 1483 llvm::StringRef vendor_str = triple.getVendorName(); 1484 llvm::StringRef os_str = triple.getOSName(); 1485 llvm::StringRef environ_str = triple.getEnvironmentName(); 1486 1487 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1488 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1489 os_str.empty() ? "*" : os_str.str().c_str()); 1490 1491 if (!environ_str.empty()) 1492 s.Printf("-%s", environ_str.str().c_str()); 1493 } 1494