1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 105 ArchSpec::eCore_arm_aarch64, "aarch64"}, 106 107 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 108 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 109 "mips"}, 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 111 "mipsr2"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 113 "mipsr3"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 115 "mipsr5"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 117 "mipsr6"}, 118 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 119 "mipsel"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 121 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 128 129 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 130 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 131 "mips64"}, 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 133 "mips64r2"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 135 "mips64r3"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 137 "mips64r5"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 139 "mips64r6"}, 140 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 141 ArchSpec::eCore_mips64el, "mips64el"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 150 151 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 152 "powerpc"}, 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 154 "ppc601"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 156 "ppc602"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 158 "ppc603"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 160 "ppc603e"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 162 "ppc603ev"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 164 "ppc604"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 166 "ppc604e"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 168 "ppc620"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 170 "ppc750"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 172 "ppc7400"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 174 "ppc7450"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 176 "ppc970"}, 177 178 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 179 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 180 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 181 "powerpc64"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 183 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 184 185 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 186 ArchSpec::eCore_s390x_generic, "s390x"}, 187 188 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 189 ArchSpec::eCore_sparc_generic, "sparc"}, 190 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 191 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 192 193 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 194 "i386"}, 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 196 "i486"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 198 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 200 "i686"}, 201 202 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 203 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 206 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 207 ArchSpec::eCore_hexagon_generic, "hexagon"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 212 213 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 214 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 215 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 217 }; 218 219 // Ensure that we have an entry in the g_core_definitions for each core. If you 220 // comment out an entry above, you will need to comment out the corresponding 221 // ArchSpec::Core enumeration. 222 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 223 ArchSpec::kNumCores, 224 "make sure we have one core definition for each core"); 225 226 struct ArchDefinitionEntry { 227 ArchSpec::Core core; 228 uint32_t cpu; 229 uint32_t sub; 230 uint32_t cpu_mask; 231 uint32_t sub_mask; 232 }; 233 234 struct ArchDefinition { 235 ArchitectureType type; 236 size_t num_entries; 237 const ArchDefinitionEntry *entries; 238 const char *name; 239 }; 240 241 void ArchSpec::ListSupportedArchNames(StringList &list) { 242 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 243 list.AppendString(g_core_definitions[i].name); 244 } 245 246 void ArchSpec::AutoComplete(CompletionRequest &request) { 247 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 248 request.TryCompleteCurrentArg(g_core_definitions[i].name); 249 } 250 251 #define CPU_ANY (UINT32_MAX) 252 253 //===----------------------------------------------------------------------===// 254 // A table that gets searched linearly for matches. This table is used to 255 // convert cpu type and subtypes to architecture names, and to convert 256 // architecture names to cpu types and subtypes. The ordering is important and 257 // allows the precedence to be set when the table is built. 258 #define SUBTYPE_MASK 0x00FFFFFFu 259 260 static const ArchDefinitionEntry g_macho_arch_entries[] = { 261 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 262 UINT32_MAX, UINT32_MAX}, 263 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 264 SUBTYPE_MASK}, 265 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 266 SUBTYPE_MASK}, 267 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 268 SUBTYPE_MASK}, 269 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 270 SUBTYPE_MASK}, 271 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 272 SUBTYPE_MASK}, 273 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 300 UINT32_MAX, SUBTYPE_MASK}, 301 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 302 SUBTYPE_MASK}, 303 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 306 SUBTYPE_MASK}, 307 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 308 SUBTYPE_MASK}, 309 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 310 SUBTYPE_MASK}, 311 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 312 SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 314 SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 326 UINT32_MAX, UINT32_MAX}, 327 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 336 SUBTYPE_MASK}, 337 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 340 SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 354 UINT32_MAX, SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 356 UINT32_MAX, SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 358 UINT32_MAX, SUBTYPE_MASK}, 359 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 364 UINT32_MAX, SUBTYPE_MASK}, 365 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 366 UINT32_MAX, UINT32_MAX}, 367 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 368 SUBTYPE_MASK}, 369 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 370 SUBTYPE_MASK}, 371 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 372 UINT32_MAX, SUBTYPE_MASK}, 373 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 374 UINT32_MAX, UINT32_MAX}, 375 // Catch any unknown mach architectures so we can always use the object and 376 // symbol mach-o files 377 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 378 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 379 0x00000000u}}; 380 381 static const ArchDefinition g_macho_arch_def = { 382 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 383 g_macho_arch_entries, "mach-o"}; 384 385 //===----------------------------------------------------------------------===// 386 // A table that gets searched linearly for matches. This table is used to 387 // convert cpu type and subtypes to architecture names, and to convert 388 // architecture names to cpu types and subtypes. The ordering is important and 389 // allows the precedence to be set when the table is built. 390 static const ArchDefinitionEntry g_elf_arch_entries[] = { 391 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 392 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 393 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 394 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 395 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 396 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 397 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 398 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 399 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 400 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 401 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 402 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 403 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 404 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 405 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 407 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 409 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 410 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 411 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 413 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 415 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 416 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 417 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 418 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 419 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 420 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 421 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 422 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 423 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 424 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 425 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 426 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 427 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 428 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 429 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 431 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 433 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 435 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 436 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 437 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 438 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 439 }; 440 441 static const ArchDefinition g_elf_arch_def = { 442 eArchTypeELF, 443 llvm::array_lengthof(g_elf_arch_entries), 444 g_elf_arch_entries, 445 "elf", 446 }; 447 448 static const ArchDefinitionEntry g_coff_arch_entries[] = { 449 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 450 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 451 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 452 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 453 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 454 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 455 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 456 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 457 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 458 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 459 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 460 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 461 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 462 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 463 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 464 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 465 }; 466 467 static const ArchDefinition g_coff_arch_def = { 468 eArchTypeCOFF, 469 llvm::array_lengthof(g_coff_arch_entries), 470 g_coff_arch_entries, 471 "pe-coff", 472 }; 473 474 //===----------------------------------------------------------------------===// 475 // Table of all ArchDefinitions 476 static const ArchDefinition *g_arch_definitions[] = { 477 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 478 479 static const size_t k_num_arch_definitions = 480 llvm::array_lengthof(g_arch_definitions); 481 482 //===----------------------------------------------------------------------===// 483 // Static helper functions. 484 485 // Get the architecture definition for a given object type. 486 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 487 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 488 const ArchDefinition *def = g_arch_definitions[i]; 489 if (def->type == arch_type) 490 return def; 491 } 492 return nullptr; 493 } 494 495 // Get an architecture definition by name. 496 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 497 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 498 if (name.equals_lower(g_core_definitions[i].name)) 499 return &g_core_definitions[i]; 500 } 501 return nullptr; 502 } 503 504 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 505 if (core < llvm::array_lengthof(g_core_definitions)) 506 return &g_core_definitions[core]; 507 return nullptr; 508 } 509 510 // Get a definition entry by cpu type and subtype. 511 static const ArchDefinitionEntry * 512 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 513 if (def == nullptr) 514 return nullptr; 515 516 const ArchDefinitionEntry *entries = def->entries; 517 for (size_t i = 0; i < def->num_entries; ++i) { 518 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 519 if (entries[i].sub == (sub & entries[i].sub_mask)) 520 return &entries[i]; 521 } 522 return nullptr; 523 } 524 525 static const ArchDefinitionEntry * 526 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 527 if (def == nullptr) 528 return nullptr; 529 530 const ArchDefinitionEntry *entries = def->entries; 531 for (size_t i = 0; i < def->num_entries; ++i) { 532 if (entries[i].core == core) 533 return &entries[i]; 534 } 535 return nullptr; 536 } 537 538 //===----------------------------------------------------------------------===// 539 // Constructors and destructors. 540 541 ArchSpec::ArchSpec() {} 542 543 ArchSpec::ArchSpec(const char *triple_cstr) { 544 if (triple_cstr) 545 SetTriple(triple_cstr); 546 } 547 548 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 549 550 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 551 552 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 553 SetArchitecture(arch_type, cpu, subtype); 554 } 555 556 ArchSpec::~ArchSpec() = default; 557 558 //===----------------------------------------------------------------------===// 559 // Assignment and initialization. 560 561 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 562 if (this != &rhs) { 563 m_triple = rhs.m_triple; 564 m_core = rhs.m_core; 565 m_byte_order = rhs.m_byte_order; 566 m_distribution_id = rhs.m_distribution_id; 567 m_flags = rhs.m_flags; 568 } 569 return *this; 570 } 571 572 void ArchSpec::Clear() { 573 m_triple = llvm::Triple(); 574 m_core = kCore_invalid; 575 m_byte_order = eByteOrderInvalid; 576 m_distribution_id.Clear(); 577 m_flags = 0; 578 } 579 580 //===----------------------------------------------------------------------===// 581 // Predicates. 582 583 const char *ArchSpec::GetArchitectureName() const { 584 const CoreDefinition *core_def = FindCoreDefinition(m_core); 585 if (core_def) 586 return core_def->name; 587 return "unknown"; 588 } 589 590 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 591 592 std::string ArchSpec::GetTargetABI() const { 593 594 std::string abi; 595 596 if (IsMIPS()) { 597 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 598 case ArchSpec::eMIPSABI_N64: 599 abi = "n64"; 600 return abi; 601 case ArchSpec::eMIPSABI_N32: 602 abi = "n32"; 603 return abi; 604 case ArchSpec::eMIPSABI_O32: 605 abi = "o32"; 606 return abi; 607 default: 608 return abi; 609 } 610 } 611 return abi; 612 } 613 614 void ArchSpec::SetFlags(std::string elf_abi) { 615 616 uint32_t flag = GetFlags(); 617 if (IsMIPS()) { 618 if (elf_abi == "n64") 619 flag |= ArchSpec::eMIPSABI_N64; 620 else if (elf_abi == "n32") 621 flag |= ArchSpec::eMIPSABI_N32; 622 else if (elf_abi == "o32") 623 flag |= ArchSpec::eMIPSABI_O32; 624 } 625 SetFlags(flag); 626 } 627 628 std::string ArchSpec::GetClangTargetCPU() const { 629 std::string cpu; 630 631 if (IsMIPS()) { 632 switch (m_core) { 633 case ArchSpec::eCore_mips32: 634 case ArchSpec::eCore_mips32el: 635 cpu = "mips32"; 636 break; 637 case ArchSpec::eCore_mips32r2: 638 case ArchSpec::eCore_mips32r2el: 639 cpu = "mips32r2"; 640 break; 641 case ArchSpec::eCore_mips32r3: 642 case ArchSpec::eCore_mips32r3el: 643 cpu = "mips32r3"; 644 break; 645 case ArchSpec::eCore_mips32r5: 646 case ArchSpec::eCore_mips32r5el: 647 cpu = "mips32r5"; 648 break; 649 case ArchSpec::eCore_mips32r6: 650 case ArchSpec::eCore_mips32r6el: 651 cpu = "mips32r6"; 652 break; 653 case ArchSpec::eCore_mips64: 654 case ArchSpec::eCore_mips64el: 655 cpu = "mips64"; 656 break; 657 case ArchSpec::eCore_mips64r2: 658 case ArchSpec::eCore_mips64r2el: 659 cpu = "mips64r2"; 660 break; 661 case ArchSpec::eCore_mips64r3: 662 case ArchSpec::eCore_mips64r3el: 663 cpu = "mips64r3"; 664 break; 665 case ArchSpec::eCore_mips64r5: 666 case ArchSpec::eCore_mips64r5el: 667 cpu = "mips64r5"; 668 break; 669 case ArchSpec::eCore_mips64r6: 670 case ArchSpec::eCore_mips64r6el: 671 cpu = "mips64r6"; 672 break; 673 default: 674 break; 675 } 676 } 677 return cpu; 678 } 679 680 uint32_t ArchSpec::GetMachOCPUType() const { 681 const CoreDefinition *core_def = FindCoreDefinition(m_core); 682 if (core_def) { 683 const ArchDefinitionEntry *arch_def = 684 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 685 if (arch_def) { 686 return arch_def->cpu; 687 } 688 } 689 return LLDB_INVALID_CPUTYPE; 690 } 691 692 uint32_t ArchSpec::GetMachOCPUSubType() const { 693 const CoreDefinition *core_def = FindCoreDefinition(m_core); 694 if (core_def) { 695 const ArchDefinitionEntry *arch_def = 696 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 697 if (arch_def) { 698 return arch_def->sub; 699 } 700 } 701 return LLDB_INVALID_CPUTYPE; 702 } 703 704 uint32_t ArchSpec::GetDataByteSize() const { 705 return 1; 706 } 707 708 uint32_t ArchSpec::GetCodeByteSize() const { 709 return 1; 710 } 711 712 llvm::Triple::ArchType ArchSpec::GetMachine() const { 713 const CoreDefinition *core_def = FindCoreDefinition(m_core); 714 if (core_def) 715 return core_def->machine; 716 717 return llvm::Triple::UnknownArch; 718 } 719 720 ConstString ArchSpec::GetDistributionId() const { 721 return m_distribution_id; 722 } 723 724 void ArchSpec::SetDistributionId(const char *distribution_id) { 725 m_distribution_id.SetCString(distribution_id); 726 } 727 728 uint32_t ArchSpec::GetAddressByteSize() const { 729 const CoreDefinition *core_def = FindCoreDefinition(m_core); 730 if (core_def) { 731 if (core_def->machine == llvm::Triple::mips64 || 732 core_def->machine == llvm::Triple::mips64el) { 733 // For N32/O32 applications Address size is 4 bytes. 734 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 735 return 4; 736 } 737 return core_def->addr_byte_size; 738 } 739 return 0; 740 } 741 742 ByteOrder ArchSpec::GetDefaultEndian() const { 743 const CoreDefinition *core_def = FindCoreDefinition(m_core); 744 if (core_def) 745 return core_def->default_byte_order; 746 return eByteOrderInvalid; 747 } 748 749 bool ArchSpec::CharIsSignedByDefault() const { 750 switch (m_triple.getArch()) { 751 default: 752 return true; 753 754 case llvm::Triple::aarch64: 755 case llvm::Triple::aarch64_be: 756 case llvm::Triple::arm: 757 case llvm::Triple::armeb: 758 case llvm::Triple::thumb: 759 case llvm::Triple::thumbeb: 760 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 761 762 case llvm::Triple::ppc: 763 case llvm::Triple::ppc64: 764 return m_triple.isOSDarwin(); 765 766 case llvm::Triple::ppc64le: 767 case llvm::Triple::systemz: 768 case llvm::Triple::xcore: 769 case llvm::Triple::arc: 770 return false; 771 } 772 } 773 774 lldb::ByteOrder ArchSpec::GetByteOrder() const { 775 if (m_byte_order == eByteOrderInvalid) 776 return GetDefaultEndian(); 777 return m_byte_order; 778 } 779 780 //===----------------------------------------------------------------------===// 781 // Mutators. 782 783 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 784 m_triple = triple; 785 UpdateCore(); 786 return IsValid(); 787 } 788 789 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 790 ArchSpec &arch) { 791 // Accept "12-10" or "12.10" as cpu type/subtype 792 if (triple_str.empty()) 793 return false; 794 795 size_t pos = triple_str.find_first_of("-."); 796 if (pos == llvm::StringRef::npos) 797 return false; 798 799 llvm::StringRef cpu_str = triple_str.substr(0, pos); 800 llvm::StringRef remainder = triple_str.substr(pos + 1); 801 if (cpu_str.empty() || remainder.empty()) 802 return false; 803 804 llvm::StringRef sub_str; 805 llvm::StringRef vendor; 806 llvm::StringRef os; 807 std::tie(sub_str, remainder) = remainder.split('-'); 808 std::tie(vendor, os) = remainder.split('-'); 809 810 uint32_t cpu = 0; 811 uint32_t sub = 0; 812 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 813 return false; 814 815 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 816 return false; 817 if (!vendor.empty() && !os.empty()) { 818 arch.GetTriple().setVendorName(vendor); 819 arch.GetTriple().setOSName(os); 820 } 821 822 return true; 823 } 824 825 bool ArchSpec::SetTriple(llvm::StringRef triple) { 826 if (triple.empty()) { 827 Clear(); 828 return false; 829 } 830 831 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 832 return true; 833 834 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 835 return IsValid(); 836 } 837 838 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 839 return !normalized_triple.getArchName().empty() && 840 normalized_triple.getOSName().empty() && 841 normalized_triple.getVendorName().empty() && 842 normalized_triple.getEnvironmentName().empty(); 843 } 844 845 void ArchSpec::MergeFrom(const ArchSpec &other) { 846 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 847 GetTriple().setVendor(other.GetTriple().getVendor()); 848 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 849 GetTriple().setOS(other.GetTriple().getOS()); 850 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 851 GetTriple().setArch(other.GetTriple().getArch()); 852 853 // MachO unknown64 isn't really invalid as the debugger can still obtain 854 // information from the binary, e.g. line tables. As such, we don't update 855 // the core here. 856 if (other.GetCore() != eCore_uknownMach64) 857 UpdateCore(); 858 } 859 if (!TripleEnvironmentWasSpecified() && 860 other.TripleEnvironmentWasSpecified()) { 861 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 862 } 863 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 864 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 865 // adopt the specific arm core. 866 if (GetTriple().getArch() == llvm::Triple::arm && 867 other.GetTriple().getArch() == llvm::Triple::arm && 868 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 869 other.GetCore() != ArchSpec::eCore_arm_generic) { 870 m_core = other.GetCore(); 871 CoreUpdated(true); 872 } 873 if (GetFlags() == 0) { 874 SetFlags(other.GetFlags()); 875 } 876 } 877 878 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 879 uint32_t sub, uint32_t os) { 880 m_core = kCore_invalid; 881 bool update_triple = true; 882 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 883 if (arch_def) { 884 const ArchDefinitionEntry *arch_def_entry = 885 FindArchDefinitionEntry(arch_def, cpu, sub); 886 if (arch_def_entry) { 887 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 888 if (core_def) { 889 m_core = core_def->core; 890 update_triple = false; 891 // Always use the architecture name because it might be more 892 // descriptive than the architecture enum ("armv7" -> 893 // llvm::Triple::arm). 894 m_triple.setArchName(llvm::StringRef(core_def->name)); 895 if (arch_type == eArchTypeMachO) { 896 m_triple.setVendor(llvm::Triple::Apple); 897 898 // Don't set the OS. It could be simulator, macosx, ios, watchos, 899 // tvos, bridgeos. We could get close with the cpu type - but we 900 // can't get it right all of the time. Better to leave this unset 901 // so other sections of code will set it when they have more 902 // information. NB: don't call m_triple.setOS 903 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 904 // the ArchSpec::TripleVendorWasSpecified() method says that any 905 // OSName setting means it was specified. 906 } else if (arch_type == eArchTypeELF) { 907 switch (os) { 908 case llvm::ELF::ELFOSABI_AIX: 909 m_triple.setOS(llvm::Triple::OSType::AIX); 910 break; 911 case llvm::ELF::ELFOSABI_FREEBSD: 912 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 913 break; 914 case llvm::ELF::ELFOSABI_GNU: 915 m_triple.setOS(llvm::Triple::OSType::Linux); 916 break; 917 case llvm::ELF::ELFOSABI_NETBSD: 918 m_triple.setOS(llvm::Triple::OSType::NetBSD); 919 break; 920 case llvm::ELF::ELFOSABI_OPENBSD: 921 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 922 break; 923 case llvm::ELF::ELFOSABI_SOLARIS: 924 m_triple.setOS(llvm::Triple::OSType::Solaris); 925 break; 926 } 927 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 928 m_triple.setVendor(llvm::Triple::PC); 929 m_triple.setOS(llvm::Triple::Win32); 930 } else { 931 m_triple.setVendor(llvm::Triple::UnknownVendor); 932 m_triple.setOS(llvm::Triple::UnknownOS); 933 } 934 // Fall back onto setting the machine type if the arch by name 935 // failed... 936 if (m_triple.getArch() == llvm::Triple::UnknownArch) 937 m_triple.setArch(core_def->machine); 938 } 939 } else { 940 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 941 LLDB_LOGF(log, 942 "Unable to find a core definition for cpu 0x%" PRIx32 943 " sub %" PRId32, 944 cpu, sub); 945 } 946 } 947 CoreUpdated(update_triple); 948 return IsValid(); 949 } 950 951 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 952 const CoreDefinition *core_def = FindCoreDefinition(m_core); 953 if (core_def) 954 return core_def->min_opcode_byte_size; 955 return 0; 956 } 957 958 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 959 const CoreDefinition *core_def = FindCoreDefinition(m_core); 960 if (core_def) 961 return core_def->max_opcode_byte_size; 962 return 0; 963 } 964 965 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 966 return IsEqualTo(rhs, true); 967 } 968 969 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 970 return IsEqualTo(rhs, false); 971 } 972 973 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 974 llvm::Triple::EnvironmentType rhs) { 975 if (lhs == rhs) 976 return true; 977 978 // If any of the environment is unknown then they are compatible 979 if (lhs == llvm::Triple::UnknownEnvironment || 980 rhs == llvm::Triple::UnknownEnvironment) 981 return true; 982 983 // If one of the environment is Android and the other one is EABI then they 984 // are considered to be compatible. This is required as a workaround for 985 // shared libraries compiled for Android without the NOTE section indicating 986 // that they are using the Android ABI. 987 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 988 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 989 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 990 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 991 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 992 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 993 return true; 994 995 return false; 996 } 997 998 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 999 // explicitly ignoring m_distribution_id in this method. 1000 1001 if (GetByteOrder() != rhs.GetByteOrder()) 1002 return false; 1003 1004 const ArchSpec::Core lhs_core = GetCore(); 1005 const ArchSpec::Core rhs_core = rhs.GetCore(); 1006 1007 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1008 1009 if (core_match) { 1010 const llvm::Triple &lhs_triple = GetTriple(); 1011 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1012 1013 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1014 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1015 if (lhs_triple_vendor != rhs_triple_vendor) { 1016 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1017 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1018 // Both architectures had the vendor specified, so if they aren't equal 1019 // then we return false 1020 if (rhs_vendor_specified && lhs_vendor_specified) 1021 return false; 1022 1023 // Only fail if both vendor types are not unknown 1024 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1025 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1026 return false; 1027 } 1028 1029 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1030 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1031 if (lhs_triple_os != rhs_triple_os) { 1032 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1033 const bool lhs_os_specified = TripleOSWasSpecified(); 1034 // Both architectures had the OS specified, so if they aren't equal then 1035 // we return false 1036 if (rhs_os_specified && lhs_os_specified) 1037 return false; 1038 1039 // Only fail if both os types are not unknown 1040 if (lhs_triple_os != llvm::Triple::UnknownOS && 1041 rhs_triple_os != llvm::Triple::UnknownOS) 1042 return false; 1043 } 1044 1045 const llvm::Triple::EnvironmentType lhs_triple_env = 1046 lhs_triple.getEnvironment(); 1047 const llvm::Triple::EnvironmentType rhs_triple_env = 1048 rhs_triple.getEnvironment(); 1049 1050 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1051 } 1052 return false; 1053 } 1054 1055 void ArchSpec::UpdateCore() { 1056 llvm::StringRef arch_name(m_triple.getArchName()); 1057 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1058 if (core_def) { 1059 m_core = core_def->core; 1060 // Set the byte order to the default byte order for an architecture. This 1061 // can be modified if needed for cases when cores handle both big and 1062 // little endian 1063 m_byte_order = core_def->default_byte_order; 1064 } else { 1065 Clear(); 1066 } 1067 } 1068 1069 //===----------------------------------------------------------------------===// 1070 // Helper methods. 1071 1072 void ArchSpec::CoreUpdated(bool update_triple) { 1073 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1074 if (core_def) { 1075 if (update_triple) 1076 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1077 m_byte_order = core_def->default_byte_order; 1078 } else { 1079 if (update_triple) 1080 m_triple = llvm::Triple(); 1081 m_byte_order = eByteOrderInvalid; 1082 } 1083 } 1084 1085 //===----------------------------------------------------------------------===// 1086 // Operators. 1087 1088 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1089 bool try_inverse, bool enforce_exact_match) { 1090 if (core1 == core2) 1091 return true; 1092 1093 switch (core1) { 1094 case ArchSpec::kCore_any: 1095 return true; 1096 1097 case ArchSpec::eCore_arm_generic: 1098 if (enforce_exact_match) 1099 break; 1100 LLVM_FALLTHROUGH; 1101 case ArchSpec::kCore_arm_any: 1102 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1103 return true; 1104 if (core2 >= ArchSpec::kCore_thumb_first && 1105 core2 <= ArchSpec::kCore_thumb_last) 1106 return true; 1107 if (core2 == ArchSpec::kCore_arm_any) 1108 return true; 1109 break; 1110 1111 case ArchSpec::kCore_x86_32_any: 1112 if ((core2 >= ArchSpec::kCore_x86_32_first && 1113 core2 <= ArchSpec::kCore_x86_32_last) || 1114 (core2 == ArchSpec::kCore_x86_32_any)) 1115 return true; 1116 break; 1117 1118 case ArchSpec::kCore_x86_64_any: 1119 if ((core2 >= ArchSpec::kCore_x86_64_first && 1120 core2 <= ArchSpec::kCore_x86_64_last) || 1121 (core2 == ArchSpec::kCore_x86_64_any)) 1122 return true; 1123 break; 1124 1125 case ArchSpec::kCore_ppc_any: 1126 if ((core2 >= ArchSpec::kCore_ppc_first && 1127 core2 <= ArchSpec::kCore_ppc_last) || 1128 (core2 == ArchSpec::kCore_ppc_any)) 1129 return true; 1130 break; 1131 1132 case ArchSpec::kCore_ppc64_any: 1133 if ((core2 >= ArchSpec::kCore_ppc64_first && 1134 core2 <= ArchSpec::kCore_ppc64_last) || 1135 (core2 == ArchSpec::kCore_ppc64_any)) 1136 return true; 1137 break; 1138 1139 case ArchSpec::eCore_arm_armv6m: 1140 if (!enforce_exact_match) { 1141 if (core2 == ArchSpec::eCore_arm_generic) 1142 return true; 1143 try_inverse = false; 1144 if (core2 == ArchSpec::eCore_arm_armv7) 1145 return true; 1146 if (core2 == ArchSpec::eCore_arm_armv6m) 1147 return true; 1148 } 1149 break; 1150 1151 case ArchSpec::kCore_hexagon_any: 1152 if ((core2 >= ArchSpec::kCore_hexagon_first && 1153 core2 <= ArchSpec::kCore_hexagon_last) || 1154 (core2 == ArchSpec::kCore_hexagon_any)) 1155 return true; 1156 break; 1157 1158 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1159 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1160 // ARMv7E-M - armv7em 1161 case ArchSpec::eCore_arm_armv7em: 1162 if (!enforce_exact_match) { 1163 if (core2 == ArchSpec::eCore_arm_generic) 1164 return true; 1165 if (core2 == ArchSpec::eCore_arm_armv7m) 1166 return true; 1167 if (core2 == ArchSpec::eCore_arm_armv6m) 1168 return true; 1169 if (core2 == ArchSpec::eCore_arm_armv7) 1170 return true; 1171 try_inverse = true; 1172 } 1173 break; 1174 1175 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1176 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1177 // ARMv7E-M - armv7em 1178 case ArchSpec::eCore_arm_armv7m: 1179 if (!enforce_exact_match) { 1180 if (core2 == ArchSpec::eCore_arm_generic) 1181 return true; 1182 if (core2 == ArchSpec::eCore_arm_armv6m) 1183 return true; 1184 if (core2 == ArchSpec::eCore_arm_armv7) 1185 return true; 1186 if (core2 == ArchSpec::eCore_arm_armv7em) 1187 return true; 1188 try_inverse = true; 1189 } 1190 break; 1191 1192 case ArchSpec::eCore_arm_armv7f: 1193 case ArchSpec::eCore_arm_armv7k: 1194 case ArchSpec::eCore_arm_armv7s: 1195 if (!enforce_exact_match) { 1196 if (core2 == ArchSpec::eCore_arm_generic) 1197 return true; 1198 if (core2 == ArchSpec::eCore_arm_armv7) 1199 return true; 1200 try_inverse = false; 1201 } 1202 break; 1203 1204 case ArchSpec::eCore_x86_64_x86_64h: 1205 if (!enforce_exact_match) { 1206 try_inverse = false; 1207 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1208 return true; 1209 } 1210 break; 1211 1212 case ArchSpec::eCore_arm_armv8: 1213 if (!enforce_exact_match) { 1214 if (core2 == ArchSpec::eCore_arm_arm64) 1215 return true; 1216 if (core2 == ArchSpec::eCore_arm_aarch64) 1217 return true; 1218 try_inverse = false; 1219 } 1220 break; 1221 1222 case ArchSpec::eCore_arm_aarch64: 1223 if (!enforce_exact_match) { 1224 if (core2 == ArchSpec::eCore_arm_arm64) 1225 return true; 1226 if (core2 == ArchSpec::eCore_arm_armv8) 1227 return true; 1228 try_inverse = false; 1229 } 1230 break; 1231 1232 case ArchSpec::eCore_arm_arm64: 1233 if (!enforce_exact_match) { 1234 if (core2 == ArchSpec::eCore_arm_aarch64) 1235 return true; 1236 if (core2 == ArchSpec::eCore_arm_armv8) 1237 return true; 1238 try_inverse = false; 1239 } 1240 break; 1241 1242 case ArchSpec::eCore_mips32: 1243 if (!enforce_exact_match) { 1244 if (core2 >= ArchSpec::kCore_mips32_first && 1245 core2 <= ArchSpec::kCore_mips32_last) 1246 return true; 1247 try_inverse = false; 1248 } 1249 break; 1250 1251 case ArchSpec::eCore_mips32el: 1252 if (!enforce_exact_match) { 1253 if (core2 >= ArchSpec::kCore_mips32el_first && 1254 core2 <= ArchSpec::kCore_mips32el_last) 1255 return true; 1256 try_inverse = true; 1257 } 1258 break; 1259 1260 case ArchSpec::eCore_mips64: 1261 if (!enforce_exact_match) { 1262 if (core2 >= ArchSpec::kCore_mips32_first && 1263 core2 <= ArchSpec::kCore_mips32_last) 1264 return true; 1265 if (core2 >= ArchSpec::kCore_mips64_first && 1266 core2 <= ArchSpec::kCore_mips64_last) 1267 return true; 1268 try_inverse = false; 1269 } 1270 break; 1271 1272 case ArchSpec::eCore_mips64el: 1273 if (!enforce_exact_match) { 1274 if (core2 >= ArchSpec::kCore_mips32el_first && 1275 core2 <= ArchSpec::kCore_mips32el_last) 1276 return true; 1277 if (core2 >= ArchSpec::kCore_mips64el_first && 1278 core2 <= ArchSpec::kCore_mips64el_last) 1279 return true; 1280 try_inverse = false; 1281 } 1282 break; 1283 1284 case ArchSpec::eCore_mips64r2: 1285 case ArchSpec::eCore_mips64r3: 1286 case ArchSpec::eCore_mips64r5: 1287 if (!enforce_exact_match) { 1288 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1289 return true; 1290 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1291 return true; 1292 try_inverse = false; 1293 } 1294 break; 1295 1296 case ArchSpec::eCore_mips64r2el: 1297 case ArchSpec::eCore_mips64r3el: 1298 case ArchSpec::eCore_mips64r5el: 1299 if (!enforce_exact_match) { 1300 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1301 return true; 1302 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1303 return true; 1304 try_inverse = false; 1305 } 1306 break; 1307 1308 case ArchSpec::eCore_mips32r2: 1309 case ArchSpec::eCore_mips32r3: 1310 case ArchSpec::eCore_mips32r5: 1311 if (!enforce_exact_match) { 1312 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1313 return true; 1314 } 1315 break; 1316 1317 case ArchSpec::eCore_mips32r2el: 1318 case ArchSpec::eCore_mips32r3el: 1319 case ArchSpec::eCore_mips32r5el: 1320 if (!enforce_exact_match) { 1321 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1322 return true; 1323 } 1324 break; 1325 1326 case ArchSpec::eCore_mips32r6: 1327 if (!enforce_exact_match) { 1328 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1329 return true; 1330 } 1331 break; 1332 1333 case ArchSpec::eCore_mips32r6el: 1334 if (!enforce_exact_match) { 1335 if (core2 == ArchSpec::eCore_mips32el || 1336 core2 == ArchSpec::eCore_mips32r6el) 1337 return true; 1338 } 1339 break; 1340 1341 case ArchSpec::eCore_mips64r6: 1342 if (!enforce_exact_match) { 1343 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1344 return true; 1345 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1346 return true; 1347 } 1348 break; 1349 1350 case ArchSpec::eCore_mips64r6el: 1351 if (!enforce_exact_match) { 1352 if (core2 == ArchSpec::eCore_mips32el || 1353 core2 == ArchSpec::eCore_mips32r6el) 1354 return true; 1355 if (core2 == ArchSpec::eCore_mips64el || 1356 core2 == ArchSpec::eCore_mips64r6el) 1357 return true; 1358 } 1359 break; 1360 1361 default: 1362 break; 1363 } 1364 if (try_inverse) 1365 return cores_match(core2, core1, false, enforce_exact_match); 1366 return false; 1367 } 1368 1369 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1370 const ArchSpec::Core lhs_core = lhs.GetCore(); 1371 const ArchSpec::Core rhs_core = rhs.GetCore(); 1372 return lhs_core < rhs_core; 1373 } 1374 1375 1376 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1377 return lhs.GetCore() == rhs.GetCore(); 1378 } 1379 1380 bool ArchSpec::IsFullySpecifiedTriple() const { 1381 const auto &user_specified_triple = GetTriple(); 1382 1383 bool user_triple_fully_specified = false; 1384 1385 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1386 TripleOSWasSpecified()) { 1387 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1388 TripleVendorWasSpecified()) { 1389 const unsigned unspecified = 0; 1390 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1391 user_triple_fully_specified = true; 1392 } 1393 } 1394 } 1395 1396 return user_triple_fully_specified; 1397 } 1398 1399 void ArchSpec::PiecewiseTripleCompare( 1400 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1401 bool &os_different, bool &os_version_different, bool &env_different) const { 1402 const llvm::Triple &me(GetTriple()); 1403 const llvm::Triple &them(other.GetTriple()); 1404 1405 arch_different = (me.getArch() != them.getArch()); 1406 1407 vendor_different = (me.getVendor() != them.getVendor()); 1408 1409 os_different = (me.getOS() != them.getOS()); 1410 1411 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1412 1413 env_different = (me.getEnvironment() != them.getEnvironment()); 1414 } 1415 1416 bool ArchSpec::IsAlwaysThumbInstructions() const { 1417 std::string Status; 1418 if (GetTriple().getArch() == llvm::Triple::arm || 1419 GetTriple().getArch() == llvm::Triple::thumb) { 1420 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1421 // 1422 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1423 // execute thumb instructions. We map the cores to arch names like this: 1424 // 1425 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1426 // Cortex-M7: armv7em 1427 1428 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1429 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1430 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1431 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1432 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1433 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1434 return true; 1435 } 1436 } 1437 return false; 1438 } 1439 1440 void ArchSpec::DumpTriple(Stream &s) const { 1441 const llvm::Triple &triple = GetTriple(); 1442 llvm::StringRef arch_str = triple.getArchName(); 1443 llvm::StringRef vendor_str = triple.getVendorName(); 1444 llvm::StringRef os_str = triple.getOSName(); 1445 llvm::StringRef environ_str = triple.getEnvironmentName(); 1446 1447 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1448 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1449 os_str.empty() ? "*" : os_str.str().c_str()); 1450 1451 if (!environ_str.empty()) 1452 s.Printf("-%s", environ_str.str().c_str()); 1453 } 1454