1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/StringList.h" 13 #include "lldb/lldb-defines.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/BinaryFormat/COFF.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Compiler.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26 namespace lldb_private { 27 28 struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36 }; 37 38 } // namespace lldb_private 39 40 // This core information can be looked using the ArchSpec::Core as the index 41 static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 103 ArchSpec::eCore_arm_armv8l, "armv8l"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_generic, "hexagon"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 214 215 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 217 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 219 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 220 221 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"}, 222 223 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 224 "wasm32"}, 225 }; 226 227 // Ensure that we have an entry in the g_core_definitions for each core. If you 228 // comment out an entry above, you will need to comment out the corresponding 229 // ArchSpec::Core enumeration. 230 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 231 ArchSpec::kNumCores, 232 "make sure we have one core definition for each core"); 233 234 struct ArchDefinitionEntry { 235 ArchSpec::Core core; 236 uint32_t cpu; 237 uint32_t sub; 238 uint32_t cpu_mask; 239 uint32_t sub_mask; 240 }; 241 242 struct ArchDefinition { 243 ArchitectureType type; 244 size_t num_entries; 245 const ArchDefinitionEntry *entries; 246 const char *name; 247 }; 248 249 void ArchSpec::ListSupportedArchNames(StringList &list) { 250 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 251 list.AppendString(g_core_definitions[i].name); 252 } 253 254 void ArchSpec::AutoComplete(CompletionRequest &request) { 255 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 256 request.TryCompleteCurrentArg(g_core_definitions[i].name); 257 } 258 259 #define CPU_ANY (UINT32_MAX) 260 261 //===----------------------------------------------------------------------===// 262 // A table that gets searched linearly for matches. This table is used to 263 // convert cpu type and subtypes to architecture names, and to convert 264 // architecture names to cpu types and subtypes. The ordering is important and 265 // allows the precedence to be set when the table is built. 266 #define SUBTYPE_MASK 0x00FFFFFFu 267 268 static const ArchDefinitionEntry g_macho_arch_entries[] = { 269 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 270 UINT32_MAX, UINT32_MAX}, 271 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 272 SUBTYPE_MASK}, 273 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 2, UINT32_MAX, 302 SUBTYPE_MASK}, // FIXME: This should be arm64e once the triple exists. 303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 306 SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 308 SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 310 UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 312 UINT32_MAX, SUBTYPE_MASK}, 313 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 314 UINT32_MAX, SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 336 SUBTYPE_MASK}, 337 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 340 UINT32_MAX, UINT32_MAX}, 341 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 364 SUBTYPE_MASK}, 365 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 366 SUBTYPE_MASK}, 367 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 368 UINT32_MAX, SUBTYPE_MASK}, 369 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 370 UINT32_MAX, SUBTYPE_MASK}, 371 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 372 UINT32_MAX, SUBTYPE_MASK}, 373 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 374 SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 376 SUBTYPE_MASK}, 377 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 378 UINT32_MAX, SUBTYPE_MASK}, 379 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 380 UINT32_MAX, UINT32_MAX}, 381 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 382 SUBTYPE_MASK}, 383 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 384 SUBTYPE_MASK}, 385 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 386 UINT32_MAX, SUBTYPE_MASK}, 387 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 388 UINT32_MAX, UINT32_MAX}, 389 // Catch any unknown mach architectures so we can always use the object and 390 // symbol mach-o files 391 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 392 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 393 0x00000000u}}; 394 395 static const ArchDefinition g_macho_arch_def = { 396 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 397 g_macho_arch_entries, "mach-o"}; 398 399 //===----------------------------------------------------------------------===// 400 // A table that gets searched linearly for matches. This table is used to 401 // convert cpu type and subtypes to architecture names, and to convert 402 // architecture names to cpu types and subtypes. The ordering is important and 403 // allows the precedence to be set when the table is built. 404 static const ArchDefinitionEntry g_elf_arch_entries[] = { 405 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 407 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 409 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 411 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 413 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 415 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 416 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 417 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 419 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 420 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 421 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 422 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 423 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 424 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 425 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 426 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 427 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 428 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 429 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 431 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 433 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 435 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 436 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 437 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 438 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 439 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 440 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 441 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 442 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 443 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 444 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 445 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 446 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 447 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 448 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 449 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 450 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 451 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 452 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 453 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 454 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 455 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 456 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR 457 }; 458 459 static const ArchDefinition g_elf_arch_def = { 460 eArchTypeELF, 461 llvm::array_lengthof(g_elf_arch_entries), 462 g_elf_arch_entries, 463 "elf", 464 }; 465 466 static const ArchDefinitionEntry g_coff_arch_entries[] = { 467 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 468 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 469 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 470 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 471 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 472 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 473 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 474 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 475 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 476 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 477 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 478 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 479 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 480 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 481 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 482 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 483 }; 484 485 static const ArchDefinition g_coff_arch_def = { 486 eArchTypeCOFF, 487 llvm::array_lengthof(g_coff_arch_entries), 488 g_coff_arch_entries, 489 "pe-coff", 490 }; 491 492 //===----------------------------------------------------------------------===// 493 // Table of all ArchDefinitions 494 static const ArchDefinition *g_arch_definitions[] = { 495 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 496 497 static const size_t k_num_arch_definitions = 498 llvm::array_lengthof(g_arch_definitions); 499 500 //===----------------------------------------------------------------------===// 501 // Static helper functions. 502 503 // Get the architecture definition for a given object type. 504 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 505 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 506 const ArchDefinition *def = g_arch_definitions[i]; 507 if (def->type == arch_type) 508 return def; 509 } 510 return nullptr; 511 } 512 513 // Get an architecture definition by name. 514 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 515 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 516 if (name.equals_lower(g_core_definitions[i].name)) 517 return &g_core_definitions[i]; 518 } 519 return nullptr; 520 } 521 522 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 523 if (core < llvm::array_lengthof(g_core_definitions)) 524 return &g_core_definitions[core]; 525 return nullptr; 526 } 527 528 // Get a definition entry by cpu type and subtype. 529 static const ArchDefinitionEntry * 530 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 531 if (def == nullptr) 532 return nullptr; 533 534 const ArchDefinitionEntry *entries = def->entries; 535 for (size_t i = 0; i < def->num_entries; ++i) { 536 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 537 if (entries[i].sub == (sub & entries[i].sub_mask)) 538 return &entries[i]; 539 } 540 return nullptr; 541 } 542 543 static const ArchDefinitionEntry * 544 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 545 if (def == nullptr) 546 return nullptr; 547 548 const ArchDefinitionEntry *entries = def->entries; 549 for (size_t i = 0; i < def->num_entries; ++i) { 550 if (entries[i].core == core) 551 return &entries[i]; 552 } 553 return nullptr; 554 } 555 556 //===----------------------------------------------------------------------===// 557 // Constructors and destructors. 558 559 ArchSpec::ArchSpec() {} 560 561 ArchSpec::ArchSpec(const char *triple_cstr) { 562 if (triple_cstr) 563 SetTriple(triple_cstr); 564 } 565 566 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 567 568 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 569 570 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 571 SetArchitecture(arch_type, cpu, subtype); 572 } 573 574 ArchSpec::~ArchSpec() = default; 575 576 void ArchSpec::Clear() { 577 m_triple = llvm::Triple(); 578 m_core = kCore_invalid; 579 m_byte_order = eByteOrderInvalid; 580 m_distribution_id.Clear(); 581 m_flags = 0; 582 } 583 584 //===----------------------------------------------------------------------===// 585 // Predicates. 586 587 const char *ArchSpec::GetArchitectureName() const { 588 const CoreDefinition *core_def = FindCoreDefinition(m_core); 589 if (core_def) 590 return core_def->name; 591 return "unknown"; 592 } 593 594 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 595 596 std::string ArchSpec::GetTargetABI() const { 597 598 std::string abi; 599 600 if (IsMIPS()) { 601 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 602 case ArchSpec::eMIPSABI_N64: 603 abi = "n64"; 604 return abi; 605 case ArchSpec::eMIPSABI_N32: 606 abi = "n32"; 607 return abi; 608 case ArchSpec::eMIPSABI_O32: 609 abi = "o32"; 610 return abi; 611 default: 612 return abi; 613 } 614 } 615 return abi; 616 } 617 618 void ArchSpec::SetFlags(const std::string &elf_abi) { 619 620 uint32_t flag = GetFlags(); 621 if (IsMIPS()) { 622 if (elf_abi == "n64") 623 flag |= ArchSpec::eMIPSABI_N64; 624 else if (elf_abi == "n32") 625 flag |= ArchSpec::eMIPSABI_N32; 626 else if (elf_abi == "o32") 627 flag |= ArchSpec::eMIPSABI_O32; 628 } 629 SetFlags(flag); 630 } 631 632 std::string ArchSpec::GetClangTargetCPU() const { 633 std::string cpu; 634 635 if (IsMIPS()) { 636 switch (m_core) { 637 case ArchSpec::eCore_mips32: 638 case ArchSpec::eCore_mips32el: 639 cpu = "mips32"; 640 break; 641 case ArchSpec::eCore_mips32r2: 642 case ArchSpec::eCore_mips32r2el: 643 cpu = "mips32r2"; 644 break; 645 case ArchSpec::eCore_mips32r3: 646 case ArchSpec::eCore_mips32r3el: 647 cpu = "mips32r3"; 648 break; 649 case ArchSpec::eCore_mips32r5: 650 case ArchSpec::eCore_mips32r5el: 651 cpu = "mips32r5"; 652 break; 653 case ArchSpec::eCore_mips32r6: 654 case ArchSpec::eCore_mips32r6el: 655 cpu = "mips32r6"; 656 break; 657 case ArchSpec::eCore_mips64: 658 case ArchSpec::eCore_mips64el: 659 cpu = "mips64"; 660 break; 661 case ArchSpec::eCore_mips64r2: 662 case ArchSpec::eCore_mips64r2el: 663 cpu = "mips64r2"; 664 break; 665 case ArchSpec::eCore_mips64r3: 666 case ArchSpec::eCore_mips64r3el: 667 cpu = "mips64r3"; 668 break; 669 case ArchSpec::eCore_mips64r5: 670 case ArchSpec::eCore_mips64r5el: 671 cpu = "mips64r5"; 672 break; 673 case ArchSpec::eCore_mips64r6: 674 case ArchSpec::eCore_mips64r6el: 675 cpu = "mips64r6"; 676 break; 677 default: 678 break; 679 } 680 } 681 return cpu; 682 } 683 684 uint32_t ArchSpec::GetMachOCPUType() const { 685 const CoreDefinition *core_def = FindCoreDefinition(m_core); 686 if (core_def) { 687 const ArchDefinitionEntry *arch_def = 688 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 689 if (arch_def) { 690 return arch_def->cpu; 691 } 692 } 693 return LLDB_INVALID_CPUTYPE; 694 } 695 696 uint32_t ArchSpec::GetMachOCPUSubType() const { 697 const CoreDefinition *core_def = FindCoreDefinition(m_core); 698 if (core_def) { 699 const ArchDefinitionEntry *arch_def = 700 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 701 if (arch_def) { 702 return arch_def->sub; 703 } 704 } 705 return LLDB_INVALID_CPUTYPE; 706 } 707 708 uint32_t ArchSpec::GetDataByteSize() const { 709 return 1; 710 } 711 712 uint32_t ArchSpec::GetCodeByteSize() const { 713 return 1; 714 } 715 716 llvm::Triple::ArchType ArchSpec::GetMachine() const { 717 const CoreDefinition *core_def = FindCoreDefinition(m_core); 718 if (core_def) 719 return core_def->machine; 720 721 return llvm::Triple::UnknownArch; 722 } 723 724 ConstString ArchSpec::GetDistributionId() const { 725 return m_distribution_id; 726 } 727 728 void ArchSpec::SetDistributionId(const char *distribution_id) { 729 m_distribution_id.SetCString(distribution_id); 730 } 731 732 uint32_t ArchSpec::GetAddressByteSize() const { 733 const CoreDefinition *core_def = FindCoreDefinition(m_core); 734 if (core_def) { 735 if (core_def->machine == llvm::Triple::mips64 || 736 core_def->machine == llvm::Triple::mips64el) { 737 // For N32/O32 applications Address size is 4 bytes. 738 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 739 return 4; 740 } 741 return core_def->addr_byte_size; 742 } 743 return 0; 744 } 745 746 ByteOrder ArchSpec::GetDefaultEndian() const { 747 const CoreDefinition *core_def = FindCoreDefinition(m_core); 748 if (core_def) 749 return core_def->default_byte_order; 750 return eByteOrderInvalid; 751 } 752 753 bool ArchSpec::CharIsSignedByDefault() const { 754 switch (m_triple.getArch()) { 755 default: 756 return true; 757 758 case llvm::Triple::aarch64: 759 case llvm::Triple::aarch64_32: 760 case llvm::Triple::aarch64_be: 761 case llvm::Triple::arm: 762 case llvm::Triple::armeb: 763 case llvm::Triple::thumb: 764 case llvm::Triple::thumbeb: 765 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 766 767 case llvm::Triple::ppc: 768 case llvm::Triple::ppc64: 769 return m_triple.isOSDarwin(); 770 771 case llvm::Triple::ppc64le: 772 case llvm::Triple::systemz: 773 case llvm::Triple::xcore: 774 case llvm::Triple::arc: 775 return false; 776 } 777 } 778 779 lldb::ByteOrder ArchSpec::GetByteOrder() const { 780 if (m_byte_order == eByteOrderInvalid) 781 return GetDefaultEndian(); 782 return m_byte_order; 783 } 784 785 //===----------------------------------------------------------------------===// 786 // Mutators. 787 788 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 789 m_triple = triple; 790 UpdateCore(); 791 return IsValid(); 792 } 793 794 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 795 ArchSpec &arch) { 796 // Accept "12-10" or "12.10" as cpu type/subtype 797 if (triple_str.empty()) 798 return false; 799 800 size_t pos = triple_str.find_first_of("-."); 801 if (pos == llvm::StringRef::npos) 802 return false; 803 804 llvm::StringRef cpu_str = triple_str.substr(0, pos); 805 llvm::StringRef remainder = triple_str.substr(pos + 1); 806 if (cpu_str.empty() || remainder.empty()) 807 return false; 808 809 llvm::StringRef sub_str; 810 llvm::StringRef vendor; 811 llvm::StringRef os; 812 std::tie(sub_str, remainder) = remainder.split('-'); 813 std::tie(vendor, os) = remainder.split('-'); 814 815 uint32_t cpu = 0; 816 uint32_t sub = 0; 817 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 818 return false; 819 820 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 821 return false; 822 if (!vendor.empty() && !os.empty()) { 823 arch.GetTriple().setVendorName(vendor); 824 arch.GetTriple().setOSName(os); 825 } 826 827 return true; 828 } 829 830 bool ArchSpec::SetTriple(llvm::StringRef triple) { 831 if (triple.empty()) { 832 Clear(); 833 return false; 834 } 835 836 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 837 return true; 838 839 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 840 return IsValid(); 841 } 842 843 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 844 return !normalized_triple.getArchName().empty() && 845 normalized_triple.getOSName().empty() && 846 normalized_triple.getVendorName().empty() && 847 normalized_triple.getEnvironmentName().empty(); 848 } 849 850 void ArchSpec::MergeFrom(const ArchSpec &other) { 851 // ios-macabi always wins over macosx. 852 if ((GetTriple().getOS() == llvm::Triple::MacOSX || 853 GetTriple().getOS() == llvm::Triple::UnknownOS) && 854 other.GetTriple().getOS() == llvm::Triple::IOS && 855 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) { 856 (*this) = other; 857 return; 858 } 859 860 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 861 GetTriple().setVendor(other.GetTriple().getVendor()); 862 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 863 GetTriple().setOS(other.GetTriple().getOS()); 864 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 865 GetTriple().setArch(other.GetTriple().getArch()); 866 867 // MachO unknown64 isn't really invalid as the debugger can still obtain 868 // information from the binary, e.g. line tables. As such, we don't update 869 // the core here. 870 if (other.GetCore() != eCore_uknownMach64) 871 UpdateCore(); 872 } 873 if (!TripleEnvironmentWasSpecified() && 874 other.TripleEnvironmentWasSpecified()) { 875 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 876 } 877 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 878 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 879 // adopt the specific arm core. 880 if (GetTriple().getArch() == llvm::Triple::arm && 881 other.GetTriple().getArch() == llvm::Triple::arm && 882 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 883 other.GetCore() != ArchSpec::eCore_arm_generic) { 884 m_core = other.GetCore(); 885 CoreUpdated(false); 886 } 887 if (GetFlags() == 0) { 888 SetFlags(other.GetFlags()); 889 } 890 } 891 892 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 893 uint32_t sub, uint32_t os) { 894 m_core = kCore_invalid; 895 bool update_triple = true; 896 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 897 if (arch_def) { 898 const ArchDefinitionEntry *arch_def_entry = 899 FindArchDefinitionEntry(arch_def, cpu, sub); 900 if (arch_def_entry) { 901 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 902 if (core_def) { 903 m_core = core_def->core; 904 update_triple = false; 905 // Always use the architecture name because it might be more 906 // descriptive than the architecture enum ("armv7" -> 907 // llvm::Triple::arm). 908 m_triple.setArchName(llvm::StringRef(core_def->name)); 909 if (arch_type == eArchTypeMachO) { 910 m_triple.setVendor(llvm::Triple::Apple); 911 912 // Don't set the OS. It could be simulator, macosx, ios, watchos, 913 // tvos, bridgeos. We could get close with the cpu type - but we 914 // can't get it right all of the time. Better to leave this unset 915 // so other sections of code will set it when they have more 916 // information. NB: don't call m_triple.setOS 917 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 918 // the ArchSpec::TripleVendorWasSpecified() method says that any 919 // OSName setting means it was specified. 920 } else if (arch_type == eArchTypeELF) { 921 switch (os) { 922 case llvm::ELF::ELFOSABI_AIX: 923 m_triple.setOS(llvm::Triple::OSType::AIX); 924 break; 925 case llvm::ELF::ELFOSABI_FREEBSD: 926 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 927 break; 928 case llvm::ELF::ELFOSABI_GNU: 929 m_triple.setOS(llvm::Triple::OSType::Linux); 930 break; 931 case llvm::ELF::ELFOSABI_NETBSD: 932 m_triple.setOS(llvm::Triple::OSType::NetBSD); 933 break; 934 case llvm::ELF::ELFOSABI_OPENBSD: 935 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 936 break; 937 case llvm::ELF::ELFOSABI_SOLARIS: 938 m_triple.setOS(llvm::Triple::OSType::Solaris); 939 break; 940 } 941 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 942 m_triple.setVendor(llvm::Triple::PC); 943 m_triple.setOS(llvm::Triple::Win32); 944 } else { 945 m_triple.setVendor(llvm::Triple::UnknownVendor); 946 m_triple.setOS(llvm::Triple::UnknownOS); 947 } 948 // Fall back onto setting the machine type if the arch by name 949 // failed... 950 if (m_triple.getArch() == llvm::Triple::UnknownArch) 951 m_triple.setArch(core_def->machine); 952 } 953 } else { 954 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 955 LLDB_LOGF(log, 956 "Unable to find a core definition for cpu 0x%" PRIx32 957 " sub %" PRId32, 958 cpu, sub); 959 } 960 } 961 CoreUpdated(update_triple); 962 return IsValid(); 963 } 964 965 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 966 const CoreDefinition *core_def = FindCoreDefinition(m_core); 967 if (core_def) 968 return core_def->min_opcode_byte_size; 969 return 0; 970 } 971 972 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 973 const CoreDefinition *core_def = FindCoreDefinition(m_core); 974 if (core_def) 975 return core_def->max_opcode_byte_size; 976 return 0; 977 } 978 979 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 980 return IsEqualTo(rhs, true); 981 } 982 983 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 984 return IsEqualTo(rhs, false); 985 } 986 987 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 988 llvm::Triple::EnvironmentType rhs) { 989 if (lhs == rhs) 990 return true; 991 992 // Apple simulators are a different platform than what they simulate. 993 // As the environments are different at this point, if one of them is a 994 // simulator, then they are different. 995 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator) 996 return false; 997 998 // If any of the environment is unknown then they are compatible 999 if (lhs == llvm::Triple::UnknownEnvironment || 1000 rhs == llvm::Triple::UnknownEnvironment) 1001 return true; 1002 1003 // If one of the environment is Android and the other one is EABI then they 1004 // are considered to be compatible. This is required as a workaround for 1005 // shared libraries compiled for Android without the NOTE section indicating 1006 // that they are using the Android ABI. 1007 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 1008 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 1009 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1010 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1011 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1012 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1013 return true; 1014 1015 return false; 1016 } 1017 1018 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1019 // explicitly ignoring m_distribution_id in this method. 1020 1021 if (GetByteOrder() != rhs.GetByteOrder() || 1022 !cores_match(GetCore(), rhs.GetCore(), true, exact_match)) 1023 return false; 1024 1025 const llvm::Triple &lhs_triple = GetTriple(); 1026 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1027 1028 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1029 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1030 if (lhs_triple_vendor != rhs_triple_vendor) { 1031 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1032 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1033 // Both architectures had the vendor specified, so if they aren't equal 1034 // then we return false 1035 if (rhs_vendor_specified && lhs_vendor_specified) 1036 return false; 1037 1038 // Only fail if both vendor types are not unknown 1039 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1040 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1041 return false; 1042 } 1043 1044 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1045 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1046 const llvm::Triple::EnvironmentType lhs_triple_env = 1047 lhs_triple.getEnvironment(); 1048 const llvm::Triple::EnvironmentType rhs_triple_env = 1049 rhs_triple.getEnvironment(); 1050 1051 if (!exact_match) { 1052 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match. 1053 if ((lhs_triple_os == llvm::Triple::IOS && 1054 lhs_triple_env == llvm::Triple::MacABI && 1055 rhs_triple_os == llvm::Triple::MacOSX) || 1056 (lhs_triple_os == llvm::Triple::MacOSX && 1057 rhs_triple_os == llvm::Triple::IOS && 1058 rhs_triple_env == llvm::Triple::MacABI)) 1059 return true; 1060 } 1061 1062 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible. 1063 if (lhs_triple_os == llvm::Triple::IOS && 1064 rhs_triple_os == llvm::Triple::IOS && 1065 (lhs_triple_env == llvm::Triple::MacABI || 1066 rhs_triple_env == llvm::Triple::MacABI) && 1067 lhs_triple_env != rhs_triple_env) 1068 return false; 1069 1070 if (lhs_triple_os != rhs_triple_os) { 1071 const bool lhs_os_specified = TripleOSWasSpecified(); 1072 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1073 // If both OS types are specified and different, fail. 1074 if (lhs_os_specified && rhs_os_specified) 1075 return false; 1076 1077 // If the pair of os+env is both unspecified, match any other os+env combo. 1078 if (!exact_match && ((!lhs_os_specified && !lhs_triple.hasEnvironment()) || 1079 (!rhs_os_specified && !rhs_triple.hasEnvironment()))) 1080 return true; 1081 } 1082 1083 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1084 } 1085 1086 void ArchSpec::UpdateCore() { 1087 llvm::StringRef arch_name(m_triple.getArchName()); 1088 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1089 if (core_def) { 1090 m_core = core_def->core; 1091 // Set the byte order to the default byte order for an architecture. This 1092 // can be modified if needed for cases when cores handle both big and 1093 // little endian 1094 m_byte_order = core_def->default_byte_order; 1095 } else { 1096 Clear(); 1097 } 1098 } 1099 1100 //===----------------------------------------------------------------------===// 1101 // Helper methods. 1102 1103 void ArchSpec::CoreUpdated(bool update_triple) { 1104 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1105 if (core_def) { 1106 if (update_triple) 1107 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1108 m_byte_order = core_def->default_byte_order; 1109 } else { 1110 if (update_triple) 1111 m_triple = llvm::Triple(); 1112 m_byte_order = eByteOrderInvalid; 1113 } 1114 } 1115 1116 //===----------------------------------------------------------------------===// 1117 // Operators. 1118 1119 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1120 bool try_inverse, bool enforce_exact_match) { 1121 if (core1 == core2) 1122 return true; 1123 1124 switch (core1) { 1125 case ArchSpec::kCore_any: 1126 return true; 1127 1128 case ArchSpec::eCore_arm_generic: 1129 if (enforce_exact_match) 1130 break; 1131 LLVM_FALLTHROUGH; 1132 case ArchSpec::kCore_arm_any: 1133 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1134 return true; 1135 if (core2 >= ArchSpec::kCore_thumb_first && 1136 core2 <= ArchSpec::kCore_thumb_last) 1137 return true; 1138 if (core2 == ArchSpec::kCore_arm_any) 1139 return true; 1140 break; 1141 1142 case ArchSpec::kCore_x86_32_any: 1143 if ((core2 >= ArchSpec::kCore_x86_32_first && 1144 core2 <= ArchSpec::kCore_x86_32_last) || 1145 (core2 == ArchSpec::kCore_x86_32_any)) 1146 return true; 1147 break; 1148 1149 case ArchSpec::kCore_x86_64_any: 1150 if ((core2 >= ArchSpec::kCore_x86_64_first && 1151 core2 <= ArchSpec::kCore_x86_64_last) || 1152 (core2 == ArchSpec::kCore_x86_64_any)) 1153 return true; 1154 break; 1155 1156 case ArchSpec::kCore_ppc_any: 1157 if ((core2 >= ArchSpec::kCore_ppc_first && 1158 core2 <= ArchSpec::kCore_ppc_last) || 1159 (core2 == ArchSpec::kCore_ppc_any)) 1160 return true; 1161 break; 1162 1163 case ArchSpec::kCore_ppc64_any: 1164 if ((core2 >= ArchSpec::kCore_ppc64_first && 1165 core2 <= ArchSpec::kCore_ppc64_last) || 1166 (core2 == ArchSpec::kCore_ppc64_any)) 1167 return true; 1168 break; 1169 1170 case ArchSpec::eCore_arm_armv6m: 1171 if (!enforce_exact_match) { 1172 if (core2 == ArchSpec::eCore_arm_generic) 1173 return true; 1174 try_inverse = false; 1175 if (core2 == ArchSpec::eCore_arm_armv7) 1176 return true; 1177 if (core2 == ArchSpec::eCore_arm_armv6m) 1178 return true; 1179 } 1180 break; 1181 1182 case ArchSpec::kCore_hexagon_any: 1183 if ((core2 >= ArchSpec::kCore_hexagon_first && 1184 core2 <= ArchSpec::kCore_hexagon_last) || 1185 (core2 == ArchSpec::kCore_hexagon_any)) 1186 return true; 1187 break; 1188 1189 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1190 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1191 // ARMv7E-M - armv7em 1192 case ArchSpec::eCore_arm_armv7em: 1193 if (!enforce_exact_match) { 1194 if (core2 == ArchSpec::eCore_arm_generic) 1195 return true; 1196 if (core2 == ArchSpec::eCore_arm_armv7m) 1197 return true; 1198 if (core2 == ArchSpec::eCore_arm_armv6m) 1199 return true; 1200 if (core2 == ArchSpec::eCore_arm_armv7) 1201 return true; 1202 try_inverse = true; 1203 } 1204 break; 1205 1206 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1207 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1208 // ARMv7E-M - armv7em 1209 case ArchSpec::eCore_arm_armv7m: 1210 if (!enforce_exact_match) { 1211 if (core2 == ArchSpec::eCore_arm_generic) 1212 return true; 1213 if (core2 == ArchSpec::eCore_arm_armv6m) 1214 return true; 1215 if (core2 == ArchSpec::eCore_arm_armv7) 1216 return true; 1217 if (core2 == ArchSpec::eCore_arm_armv7em) 1218 return true; 1219 try_inverse = true; 1220 } 1221 break; 1222 1223 case ArchSpec::eCore_arm_armv7f: 1224 case ArchSpec::eCore_arm_armv7k: 1225 case ArchSpec::eCore_arm_armv7s: 1226 case ArchSpec::eCore_arm_armv7l: 1227 case ArchSpec::eCore_arm_armv8l: 1228 if (!enforce_exact_match) { 1229 if (core2 == ArchSpec::eCore_arm_generic) 1230 return true; 1231 if (core2 == ArchSpec::eCore_arm_armv7) 1232 return true; 1233 try_inverse = false; 1234 } 1235 break; 1236 1237 case ArchSpec::eCore_x86_64_x86_64h: 1238 if (!enforce_exact_match) { 1239 try_inverse = false; 1240 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1241 return true; 1242 } 1243 break; 1244 1245 case ArchSpec::eCore_arm_armv8: 1246 if (!enforce_exact_match) { 1247 if (core2 == ArchSpec::eCore_arm_arm64) 1248 return true; 1249 if (core2 == ArchSpec::eCore_arm_aarch64) 1250 return true; 1251 try_inverse = false; 1252 } 1253 break; 1254 1255 case ArchSpec::eCore_arm_aarch64: 1256 if (!enforce_exact_match) { 1257 if (core2 == ArchSpec::eCore_arm_arm64) 1258 return true; 1259 if (core2 == ArchSpec::eCore_arm_armv8) 1260 return true; 1261 try_inverse = false; 1262 } 1263 break; 1264 1265 case ArchSpec::eCore_arm_arm64: 1266 if (!enforce_exact_match) { 1267 if (core2 == ArchSpec::eCore_arm_aarch64) 1268 return true; 1269 if (core2 == ArchSpec::eCore_arm_armv8) 1270 return true; 1271 try_inverse = false; 1272 } 1273 break; 1274 1275 case ArchSpec::eCore_arm_arm64_32: 1276 if (!enforce_exact_match) { 1277 if (core2 == ArchSpec::eCore_arm_generic) 1278 return true; 1279 try_inverse = false; 1280 } 1281 break; 1282 1283 case ArchSpec::eCore_mips32: 1284 if (!enforce_exact_match) { 1285 if (core2 >= ArchSpec::kCore_mips32_first && 1286 core2 <= ArchSpec::kCore_mips32_last) 1287 return true; 1288 try_inverse = false; 1289 } 1290 break; 1291 1292 case ArchSpec::eCore_mips32el: 1293 if (!enforce_exact_match) { 1294 if (core2 >= ArchSpec::kCore_mips32el_first && 1295 core2 <= ArchSpec::kCore_mips32el_last) 1296 return true; 1297 try_inverse = true; 1298 } 1299 break; 1300 1301 case ArchSpec::eCore_mips64: 1302 if (!enforce_exact_match) { 1303 if (core2 >= ArchSpec::kCore_mips32_first && 1304 core2 <= ArchSpec::kCore_mips32_last) 1305 return true; 1306 if (core2 >= ArchSpec::kCore_mips64_first && 1307 core2 <= ArchSpec::kCore_mips64_last) 1308 return true; 1309 try_inverse = false; 1310 } 1311 break; 1312 1313 case ArchSpec::eCore_mips64el: 1314 if (!enforce_exact_match) { 1315 if (core2 >= ArchSpec::kCore_mips32el_first && 1316 core2 <= ArchSpec::kCore_mips32el_last) 1317 return true; 1318 if (core2 >= ArchSpec::kCore_mips64el_first && 1319 core2 <= ArchSpec::kCore_mips64el_last) 1320 return true; 1321 try_inverse = false; 1322 } 1323 break; 1324 1325 case ArchSpec::eCore_mips64r2: 1326 case ArchSpec::eCore_mips64r3: 1327 case ArchSpec::eCore_mips64r5: 1328 if (!enforce_exact_match) { 1329 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1330 return true; 1331 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1332 return true; 1333 try_inverse = false; 1334 } 1335 break; 1336 1337 case ArchSpec::eCore_mips64r2el: 1338 case ArchSpec::eCore_mips64r3el: 1339 case ArchSpec::eCore_mips64r5el: 1340 if (!enforce_exact_match) { 1341 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1342 return true; 1343 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1344 return true; 1345 try_inverse = false; 1346 } 1347 break; 1348 1349 case ArchSpec::eCore_mips32r2: 1350 case ArchSpec::eCore_mips32r3: 1351 case ArchSpec::eCore_mips32r5: 1352 if (!enforce_exact_match) { 1353 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1354 return true; 1355 } 1356 break; 1357 1358 case ArchSpec::eCore_mips32r2el: 1359 case ArchSpec::eCore_mips32r3el: 1360 case ArchSpec::eCore_mips32r5el: 1361 if (!enforce_exact_match) { 1362 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1363 return true; 1364 } 1365 break; 1366 1367 case ArchSpec::eCore_mips32r6: 1368 if (!enforce_exact_match) { 1369 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1370 return true; 1371 } 1372 break; 1373 1374 case ArchSpec::eCore_mips32r6el: 1375 if (!enforce_exact_match) { 1376 if (core2 == ArchSpec::eCore_mips32el || 1377 core2 == ArchSpec::eCore_mips32r6el) 1378 return true; 1379 } 1380 break; 1381 1382 case ArchSpec::eCore_mips64r6: 1383 if (!enforce_exact_match) { 1384 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1385 return true; 1386 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1387 return true; 1388 } 1389 break; 1390 1391 case ArchSpec::eCore_mips64r6el: 1392 if (!enforce_exact_match) { 1393 if (core2 == ArchSpec::eCore_mips32el || 1394 core2 == ArchSpec::eCore_mips32r6el) 1395 return true; 1396 if (core2 == ArchSpec::eCore_mips64el || 1397 core2 == ArchSpec::eCore_mips64r6el) 1398 return true; 1399 } 1400 break; 1401 1402 default: 1403 break; 1404 } 1405 if (try_inverse) 1406 return cores_match(core2, core1, false, enforce_exact_match); 1407 return false; 1408 } 1409 1410 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1411 const ArchSpec::Core lhs_core = lhs.GetCore(); 1412 const ArchSpec::Core rhs_core = rhs.GetCore(); 1413 return lhs_core < rhs_core; 1414 } 1415 1416 1417 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1418 return lhs.GetCore() == rhs.GetCore(); 1419 } 1420 1421 bool ArchSpec::IsFullySpecifiedTriple() const { 1422 const auto &user_specified_triple = GetTriple(); 1423 1424 bool user_triple_fully_specified = false; 1425 1426 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1427 TripleOSWasSpecified()) { 1428 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1429 TripleVendorWasSpecified()) { 1430 const unsigned unspecified = 0; 1431 if (!user_specified_triple.isOSDarwin() || 1432 user_specified_triple.getOSMajorVersion() != unspecified) { 1433 user_triple_fully_specified = true; 1434 } 1435 } 1436 } 1437 1438 return user_triple_fully_specified; 1439 } 1440 1441 void ArchSpec::PiecewiseTripleCompare( 1442 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1443 bool &os_different, bool &os_version_different, bool &env_different) const { 1444 const llvm::Triple &me(GetTriple()); 1445 const llvm::Triple &them(other.GetTriple()); 1446 1447 arch_different = (me.getArch() != them.getArch()); 1448 1449 vendor_different = (me.getVendor() != them.getVendor()); 1450 1451 os_different = (me.getOS() != them.getOS()); 1452 1453 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1454 1455 env_different = (me.getEnvironment() != them.getEnvironment()); 1456 } 1457 1458 bool ArchSpec::IsAlwaysThumbInstructions() const { 1459 std::string Status; 1460 if (GetTriple().getArch() == llvm::Triple::arm || 1461 GetTriple().getArch() == llvm::Triple::thumb) { 1462 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1463 // 1464 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1465 // execute thumb instructions. We map the cores to arch names like this: 1466 // 1467 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1468 // Cortex-M7: armv7em 1469 1470 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1471 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1472 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1473 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1474 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1475 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1476 return true; 1477 } 1478 // Windows on ARM is always thumb. 1479 if (GetTriple().isOSWindows()) 1480 return true; 1481 } 1482 return false; 1483 } 1484 1485 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1486 const llvm::Triple &triple = GetTriple(); 1487 llvm::StringRef arch_str = triple.getArchName(); 1488 llvm::StringRef vendor_str = triple.getVendorName(); 1489 llvm::StringRef os_str = triple.getOSName(); 1490 llvm::StringRef environ_str = triple.getEnvironmentName(); 1491 1492 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1493 vendor_str.empty() ? "*" : vendor_str, 1494 os_str.empty() ? "*" : os_str); 1495 1496 if (!environ_str.empty()) 1497 s << "-" << environ_str; 1498 } 1499 1500 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *, 1501 raw_ostream &Out) { 1502 Val.DumpTriple(Out); 1503 } 1504 1505 llvm::StringRef 1506 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *, 1507 ArchSpec &Val) { 1508 Val = ArchSpec(Scalar); 1509 return {}; 1510 } 1511