1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "lldb/Utility/ArchSpec.h" 11 12 #include "lldb/Utility/Log.h" 13 #include "lldb/Utility/NameMatches.h" 14 #include "lldb/Utility/Stream.h" // for Stream 15 #include "lldb/Utility/StringList.h" 16 #include "lldb/lldb-defines.h" // for LLDB_INVALID_C... 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/Twine.h" // for Twine 19 #include "llvm/BinaryFormat/COFF.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/BinaryFormat/MachO.h" // for CPUType::CPU_T... 22 #include "llvm/Support/Compiler.h" // for LLVM_FALLTHROUGH 23 #include "llvm/Support/Host.h" 24 25 using namespace lldb; 26 using namespace lldb_private; 27 28 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 29 bool try_inverse, bool enforce_exact_match); 30 31 namespace lldb_private { 32 33 struct CoreDefinition { 34 ByteOrder default_byte_order; 35 uint32_t addr_byte_size; 36 uint32_t min_opcode_byte_size; 37 uint32_t max_opcode_byte_size; 38 llvm::Triple::ArchType machine; 39 ArchSpec::Core core; 40 const char *const name; 41 }; 42 43 } // namespace lldb_private 44 45 // This core information can be looked using the ArchSpec::Core as the index 46 static const CoreDefinition g_core_definitions[] = { 47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 48 "arm"}, 49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 50 "armv4"}, 51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 52 "armv4t"}, 53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 54 "armv5"}, 55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 56 "armv5e"}, 57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 58 "armv5t"}, 59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 60 "armv6"}, 61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 62 "armv6m"}, 63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 64 "armv7"}, 65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 66 "armv7f"}, 67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 68 "armv7s"}, 69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 70 "armv7k"}, 71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 72 "armv7m"}, 73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 74 "armv7em"}, 75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 76 "xscale"}, 77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 78 "thumb"}, 79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 80 "thumbv4t"}, 81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 82 "thumbv5"}, 83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 84 "thumbv5e"}, 85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 86 "thumbv6"}, 87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 88 "thumbv6m"}, 89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 90 "thumbv7"}, 91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 92 "thumbv7f"}, 93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 94 "thumbv7s"}, 95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 96 "thumbv7k"}, 97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 98 "thumbv7m"}, 99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 100 "thumbv7em"}, 101 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 102 ArchSpec::eCore_arm_arm64, "arm64"}, 103 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 104 ArchSpec::eCore_arm_armv8, "armv8"}, 105 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 106 ArchSpec::eCore_arm_aarch64, "aarch64"}, 107 108 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 109 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 110 "mips"}, 111 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 112 "mipsr2"}, 113 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 114 "mipsr3"}, 115 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 116 "mipsr5"}, 117 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 118 "mipsr6"}, 119 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 120 "mipsel"}, 121 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 122 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 123 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 124 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 125 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 126 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 127 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 128 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 129 130 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 131 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 132 "mips64"}, 133 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 134 "mips64r2"}, 135 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 136 "mips64r3"}, 137 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 138 "mips64r5"}, 139 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 140 "mips64r6"}, 141 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 142 ArchSpec::eCore_mips64el, "mips64el"}, 143 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 144 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 145 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 146 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 147 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 148 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 149 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 150 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 151 152 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 153 "powerpc"}, 154 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 155 "ppc601"}, 156 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 157 "ppc602"}, 158 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 159 "ppc603"}, 160 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 161 "ppc603e"}, 162 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 163 "ppc603ev"}, 164 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 165 "ppc604"}, 166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 167 "ppc604e"}, 168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 169 "ppc620"}, 170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 171 "ppc750"}, 172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 173 "ppc7400"}, 174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 175 "ppc7450"}, 176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 177 "ppc970"}, 178 179 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 180 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 181 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 182 "powerpc64"}, 183 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 184 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 185 186 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 187 ArchSpec::eCore_s390x_generic, "s390x"}, 188 189 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 190 ArchSpec::eCore_sparc_generic, "sparc"}, 191 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 192 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 193 194 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 195 "i386"}, 196 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 197 "i486"}, 198 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 199 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 200 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 201 "i686"}, 202 203 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 204 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 205 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 206 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 207 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 208 ArchSpec::eCore_hexagon_generic, "hexagon"}, 209 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 210 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 211 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 212 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 213 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 215 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 216 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 217 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 218 219 {eByteOrderBig, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba3, 220 "kalimba3"}, 221 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba4, 222 "kalimba4"}, 223 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba5, 224 "kalimba5"}}; 225 226 // Ensure that we have an entry in the g_core_definitions for each core. If you 227 // comment out an entry above, you will need to comment out the corresponding 228 // ArchSpec::Core enumeration. 229 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 230 ArchSpec::kNumCores, 231 "make sure we have one core definition for each core"); 232 233 struct ArchDefinitionEntry { 234 ArchSpec::Core core; 235 uint32_t cpu; 236 uint32_t sub; 237 uint32_t cpu_mask; 238 uint32_t sub_mask; 239 }; 240 241 struct ArchDefinition { 242 ArchitectureType type; 243 size_t num_entries; 244 const ArchDefinitionEntry *entries; 245 const char *name; 246 }; 247 248 void ArchSpec::ListSupportedArchNames(StringList &list) { 249 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 250 list.AppendString(g_core_definitions[i].name); 251 } 252 253 size_t ArchSpec::AutoComplete(CompletionRequest &request) { 254 if (!request.GetCursorArgumentPrefix().empty()) { 255 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 256 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, 257 request.GetCursorArgumentPrefix())) 258 request.GetMatches().AppendString(g_core_definitions[i].name); 259 } 260 } else { 261 ListSupportedArchNames(request.GetMatches()); 262 } 263 return request.GetMatches().GetSize(); 264 } 265 266 #define CPU_ANY (UINT32_MAX) 267 268 //===----------------------------------------------------------------------===// 269 // A table that gets searched linearly for matches. This table is used to 270 // convert cpu type and subtypes to architecture names, and to convert 271 // architecture names to cpu types and subtypes. The ordering is important and 272 // allows the precedence to be set when the table is built. 273 #define SUBTYPE_MASK 0x00FFFFFFu 274 275 static const ArchDefinitionEntry g_macho_arch_entries[] = { 276 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 277 UINT32_MAX, UINT32_MAX}, 278 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 279 SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 303 SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 305 SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 307 SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 309 SUBTYPE_MASK}, 310 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 315 UINT32_MAX, SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 317 SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 333 SUBTYPE_MASK}, 334 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 335 SUBTYPE_MASK}, 336 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 341 UINT32_MAX, UINT32_MAX}, 342 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 343 SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 361 SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 363 SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 365 SUBTYPE_MASK}, 366 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 367 SUBTYPE_MASK}, 368 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 369 UINT32_MAX, SUBTYPE_MASK}, 370 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 371 UINT32_MAX, SUBTYPE_MASK}, 372 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 373 UINT32_MAX, SUBTYPE_MASK}, 374 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 375 SUBTYPE_MASK}, 376 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 379 UINT32_MAX, SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 381 UINT32_MAX, UINT32_MAX}, 382 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 383 SUBTYPE_MASK}, 384 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 385 SUBTYPE_MASK}, 386 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 387 UINT32_MAX, SUBTYPE_MASK}, 388 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 389 UINT32_MAX, UINT32_MAX}, 390 // Catch any unknown mach architectures so we can always use the object and 391 // symbol mach-o files 392 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 393 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 394 0x00000000u}}; 395 396 static const ArchDefinition g_macho_arch_def = { 397 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 398 g_macho_arch_entries, "mach-o"}; 399 400 //===----------------------------------------------------------------------===// 401 // A table that gets searched linearly for matches. This table is used to 402 // convert cpu type and subtypes to architecture names, and to convert 403 // architecture names to cpu types and subtypes. The ordering is important and 404 // allows the precedence to be set when the table is built. 405 static const ArchDefinitionEntry g_elf_arch_entries[] = { 406 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 407 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 408 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 410 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 412 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 414 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 416 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 417 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 418 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 419 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 420 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 422 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 423 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 424 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 425 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 426 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 427 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 428 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 429 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 430 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 431 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 432 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 433 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 434 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 435 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 436 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 438 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 440 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 441 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 442 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 443 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 444 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 445 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 446 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 447 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 448 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 449 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 450 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 451 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 452 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 453 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 454 {ArchSpec::eCore_kalimba3, llvm::ELF::EM_CSR_KALIMBA, 455 llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 456 {ArchSpec::eCore_kalimba4, llvm::ELF::EM_CSR_KALIMBA, 457 llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 458 {ArchSpec::eCore_kalimba5, llvm::ELF::EM_CSR_KALIMBA, 459 llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu} // KALIMBA 460 }; 461 462 static const ArchDefinition g_elf_arch_def = { 463 eArchTypeELF, 464 llvm::array_lengthof(g_elf_arch_entries), 465 g_elf_arch_entries, 466 "elf", 467 }; 468 469 static const ArchDefinitionEntry g_coff_arch_entries[] = { 470 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 472 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 474 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 475 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 476 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 477 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 478 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 479 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 480 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 481 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 482 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 483 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 484 }; 485 486 static const ArchDefinition g_coff_arch_def = { 487 eArchTypeCOFF, 488 llvm::array_lengthof(g_coff_arch_entries), 489 g_coff_arch_entries, 490 "pe-coff", 491 }; 492 493 //===----------------------------------------------------------------------===// 494 // Table of all ArchDefinitions 495 static const ArchDefinition *g_arch_definitions[] = { 496 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 497 498 static const size_t k_num_arch_definitions = 499 llvm::array_lengthof(g_arch_definitions); 500 501 //===----------------------------------------------------------------------===// 502 // Static helper functions. 503 504 // Get the architecture definition for a given object type. 505 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 506 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 507 const ArchDefinition *def = g_arch_definitions[i]; 508 if (def->type == arch_type) 509 return def; 510 } 511 return nullptr; 512 } 513 514 // Get an architecture definition by name. 515 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 516 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 517 if (name.equals_lower(g_core_definitions[i].name)) 518 return &g_core_definitions[i]; 519 } 520 return nullptr; 521 } 522 523 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 524 if (core < llvm::array_lengthof(g_core_definitions)) 525 return &g_core_definitions[core]; 526 return nullptr; 527 } 528 529 // Get a definition entry by cpu type and subtype. 530 static const ArchDefinitionEntry * 531 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 532 if (def == nullptr) 533 return nullptr; 534 535 const ArchDefinitionEntry *entries = def->entries; 536 for (size_t i = 0; i < def->num_entries; ++i) { 537 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 538 if (entries[i].sub == (sub & entries[i].sub_mask)) 539 return &entries[i]; 540 } 541 return nullptr; 542 } 543 544 static const ArchDefinitionEntry * 545 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 546 if (def == nullptr) 547 return nullptr; 548 549 const ArchDefinitionEntry *entries = def->entries; 550 for (size_t i = 0; i < def->num_entries; ++i) { 551 if (entries[i].core == core) 552 return &entries[i]; 553 } 554 return nullptr; 555 } 556 557 //===----------------------------------------------------------------------===// 558 // Constructors and destructors. 559 560 ArchSpec::ArchSpec() {} 561 562 ArchSpec::ArchSpec(const char *triple_cstr) { 563 if (triple_cstr) 564 SetTriple(triple_cstr); 565 } 566 567 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 568 569 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 570 571 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 572 SetArchitecture(arch_type, cpu, subtype); 573 } 574 575 ArchSpec::~ArchSpec() = default; 576 577 //===----------------------------------------------------------------------===// 578 // Assignment and initialization. 579 580 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 581 if (this != &rhs) { 582 m_triple = rhs.m_triple; 583 m_core = rhs.m_core; 584 m_byte_order = rhs.m_byte_order; 585 m_distribution_id = rhs.m_distribution_id; 586 m_flags = rhs.m_flags; 587 } 588 return *this; 589 } 590 591 void ArchSpec::Clear() { 592 m_triple = llvm::Triple(); 593 m_core = kCore_invalid; 594 m_byte_order = eByteOrderInvalid; 595 m_distribution_id.Clear(); 596 m_flags = 0; 597 } 598 599 //===----------------------------------------------------------------------===// 600 // Predicates. 601 602 const char *ArchSpec::GetArchitectureName() const { 603 const CoreDefinition *core_def = FindCoreDefinition(m_core); 604 if (core_def) 605 return core_def->name; 606 return "unknown"; 607 } 608 609 bool ArchSpec::IsMIPS() const { 610 const llvm::Triple::ArchType machine = GetMachine(); 611 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 612 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) 613 return true; 614 return false; 615 } 616 617 std::string ArchSpec::GetTargetABI() const { 618 619 std::string abi; 620 621 if (IsMIPS()) { 622 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 623 case ArchSpec::eMIPSABI_N64: 624 abi = "n64"; 625 return abi; 626 case ArchSpec::eMIPSABI_N32: 627 abi = "n32"; 628 return abi; 629 case ArchSpec::eMIPSABI_O32: 630 abi = "o32"; 631 return abi; 632 default: 633 return abi; 634 } 635 } 636 return abi; 637 } 638 639 void ArchSpec::SetFlags(std::string elf_abi) { 640 641 uint32_t flag = GetFlags(); 642 if (IsMIPS()) { 643 if (elf_abi == "n64") 644 flag |= ArchSpec::eMIPSABI_N64; 645 else if (elf_abi == "n32") 646 flag |= ArchSpec::eMIPSABI_N32; 647 else if (elf_abi == "o32") 648 flag |= ArchSpec::eMIPSABI_O32; 649 } 650 SetFlags(flag); 651 } 652 653 std::string ArchSpec::GetClangTargetCPU() const { 654 std::string cpu; 655 const llvm::Triple::ArchType machine = GetMachine(); 656 657 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 658 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) { 659 switch (m_core) { 660 case ArchSpec::eCore_mips32: 661 case ArchSpec::eCore_mips32el: 662 cpu = "mips32"; 663 break; 664 case ArchSpec::eCore_mips32r2: 665 case ArchSpec::eCore_mips32r2el: 666 cpu = "mips32r2"; 667 break; 668 case ArchSpec::eCore_mips32r3: 669 case ArchSpec::eCore_mips32r3el: 670 cpu = "mips32r3"; 671 break; 672 case ArchSpec::eCore_mips32r5: 673 case ArchSpec::eCore_mips32r5el: 674 cpu = "mips32r5"; 675 break; 676 case ArchSpec::eCore_mips32r6: 677 case ArchSpec::eCore_mips32r6el: 678 cpu = "mips32r6"; 679 break; 680 case ArchSpec::eCore_mips64: 681 case ArchSpec::eCore_mips64el: 682 cpu = "mips64"; 683 break; 684 case ArchSpec::eCore_mips64r2: 685 case ArchSpec::eCore_mips64r2el: 686 cpu = "mips64r2"; 687 break; 688 case ArchSpec::eCore_mips64r3: 689 case ArchSpec::eCore_mips64r3el: 690 cpu = "mips64r3"; 691 break; 692 case ArchSpec::eCore_mips64r5: 693 case ArchSpec::eCore_mips64r5el: 694 cpu = "mips64r5"; 695 break; 696 case ArchSpec::eCore_mips64r6: 697 case ArchSpec::eCore_mips64r6el: 698 cpu = "mips64r6"; 699 break; 700 default: 701 break; 702 } 703 } 704 return cpu; 705 } 706 707 uint32_t ArchSpec::GetMachOCPUType() const { 708 const CoreDefinition *core_def = FindCoreDefinition(m_core); 709 if (core_def) { 710 const ArchDefinitionEntry *arch_def = 711 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 712 if (arch_def) { 713 return arch_def->cpu; 714 } 715 } 716 return LLDB_INVALID_CPUTYPE; 717 } 718 719 uint32_t ArchSpec::GetMachOCPUSubType() const { 720 const CoreDefinition *core_def = FindCoreDefinition(m_core); 721 if (core_def) { 722 const ArchDefinitionEntry *arch_def = 723 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 724 if (arch_def) { 725 return arch_def->sub; 726 } 727 } 728 return LLDB_INVALID_CPUTYPE; 729 } 730 731 uint32_t ArchSpec::GetDataByteSize() const { 732 switch (m_core) { 733 case eCore_kalimba3: 734 return 4; 735 case eCore_kalimba4: 736 return 1; 737 case eCore_kalimba5: 738 return 4; 739 default: 740 return 1; 741 } 742 return 1; 743 } 744 745 uint32_t ArchSpec::GetCodeByteSize() const { 746 switch (m_core) { 747 case eCore_kalimba3: 748 return 4; 749 case eCore_kalimba4: 750 return 1; 751 case eCore_kalimba5: 752 return 1; 753 default: 754 return 1; 755 } 756 return 1; 757 } 758 759 llvm::Triple::ArchType ArchSpec::GetMachine() const { 760 const CoreDefinition *core_def = FindCoreDefinition(m_core); 761 if (core_def) 762 return core_def->machine; 763 764 return llvm::Triple::UnknownArch; 765 } 766 767 const ConstString &ArchSpec::GetDistributionId() const { 768 return m_distribution_id; 769 } 770 771 void ArchSpec::SetDistributionId(const char *distribution_id) { 772 m_distribution_id.SetCString(distribution_id); 773 } 774 775 uint32_t ArchSpec::GetAddressByteSize() const { 776 const CoreDefinition *core_def = FindCoreDefinition(m_core); 777 if (core_def) { 778 if (core_def->machine == llvm::Triple::mips64 || 779 core_def->machine == llvm::Triple::mips64el) { 780 // For N32/O32 applications Address size is 4 bytes. 781 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 782 return 4; 783 } 784 return core_def->addr_byte_size; 785 } 786 return 0; 787 } 788 789 ByteOrder ArchSpec::GetDefaultEndian() const { 790 const CoreDefinition *core_def = FindCoreDefinition(m_core); 791 if (core_def) 792 return core_def->default_byte_order; 793 return eByteOrderInvalid; 794 } 795 796 bool ArchSpec::CharIsSignedByDefault() const { 797 switch (m_triple.getArch()) { 798 default: 799 return true; 800 801 case llvm::Triple::aarch64: 802 case llvm::Triple::aarch64_be: 803 case llvm::Triple::arm: 804 case llvm::Triple::armeb: 805 case llvm::Triple::thumb: 806 case llvm::Triple::thumbeb: 807 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 808 809 case llvm::Triple::ppc: 810 case llvm::Triple::ppc64: 811 return m_triple.isOSDarwin(); 812 813 case llvm::Triple::ppc64le: 814 case llvm::Triple::systemz: 815 case llvm::Triple::xcore: 816 return false; 817 } 818 } 819 820 lldb::ByteOrder ArchSpec::GetByteOrder() const { 821 if (m_byte_order == eByteOrderInvalid) 822 return GetDefaultEndian(); 823 return m_byte_order; 824 } 825 826 //===----------------------------------------------------------------------===// 827 // Mutators. 828 829 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 830 m_triple = triple; 831 UpdateCore(); 832 return IsValid(); 833 } 834 835 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 836 ArchSpec &arch) { 837 // Accept "12-10" or "12.10" as cpu type/subtype 838 if (triple_str.empty()) 839 return false; 840 841 size_t pos = triple_str.find_first_of("-."); 842 if (pos == llvm::StringRef::npos) 843 return false; 844 845 llvm::StringRef cpu_str = triple_str.substr(0, pos); 846 llvm::StringRef remainder = triple_str.substr(pos + 1); 847 if (cpu_str.empty() || remainder.empty()) 848 return false; 849 850 llvm::StringRef sub_str; 851 llvm::StringRef vendor; 852 llvm::StringRef os; 853 std::tie(sub_str, remainder) = remainder.split('-'); 854 std::tie(vendor, os) = remainder.split('-'); 855 856 uint32_t cpu = 0; 857 uint32_t sub = 0; 858 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 859 return false; 860 861 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 862 return false; 863 if (!vendor.empty() && !os.empty()) { 864 arch.GetTriple().setVendorName(vendor); 865 arch.GetTriple().setOSName(os); 866 } 867 868 return true; 869 } 870 871 bool ArchSpec::SetTriple(llvm::StringRef triple) { 872 if (triple.empty()) { 873 Clear(); 874 return false; 875 } 876 877 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 878 return true; 879 880 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 881 return IsValid(); 882 } 883 884 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 885 return !normalized_triple.getArchName().empty() && 886 normalized_triple.getOSName().empty() && 887 normalized_triple.getVendorName().empty() && 888 normalized_triple.getEnvironmentName().empty(); 889 } 890 891 void ArchSpec::MergeFrom(const ArchSpec &other) { 892 if (TripleVendorIsUnspecifiedUnknown() && 893 !other.TripleVendorIsUnspecifiedUnknown()) 894 GetTriple().setVendor(other.GetTriple().getVendor()); 895 if (TripleOSIsUnspecifiedUnknown() && !other.TripleOSIsUnspecifiedUnknown()) 896 GetTriple().setOS(other.GetTriple().getOS()); 897 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 898 GetTriple().setArch(other.GetTriple().getArch()); 899 900 // MachO unknown64 isn't really invalid as the debugger can still obtain 901 // information from the binary, e.g. line tables. As such, we don't update 902 // the core here. 903 if (other.GetCore() != eCore_uknownMach64) 904 UpdateCore(); 905 } 906 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 907 !TripleVendorWasSpecified()) { 908 if (other.TripleVendorWasSpecified()) 909 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 910 } 911 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 912 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 913 // adopt the specific arm core. 914 if (GetTriple().getArch() == llvm::Triple::arm && 915 other.GetTriple().getArch() == llvm::Triple::arm && 916 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 917 other.GetCore() != ArchSpec::eCore_arm_generic) { 918 m_core = other.GetCore(); 919 CoreUpdated(true); 920 } 921 if (GetFlags() == 0) { 922 SetFlags(other.GetFlags()); 923 } 924 } 925 926 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 927 uint32_t sub, uint32_t os) { 928 m_core = kCore_invalid; 929 bool update_triple = true; 930 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 931 if (arch_def) { 932 const ArchDefinitionEntry *arch_def_entry = 933 FindArchDefinitionEntry(arch_def, cpu, sub); 934 if (arch_def_entry) { 935 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 936 if (core_def) { 937 m_core = core_def->core; 938 update_triple = false; 939 // Always use the architecture name because it might be more 940 // descriptive than the architecture enum ("armv7" -> 941 // llvm::Triple::arm). 942 m_triple.setArchName(llvm::StringRef(core_def->name)); 943 if (arch_type == eArchTypeMachO) { 944 m_triple.setVendor(llvm::Triple::Apple); 945 946 // Don't set the OS. It could be simulator, macosx, ios, watchos, 947 // tvos. We could get close with the cpu type - but we can't get it 948 // right all of the time. Better to leave this unset so other 949 // sections of code will set it when they have more information. 950 // NB: don't call m_triple.setOS (llvm::Triple::UnknownOS). That sets 951 // the OSName to 952 // "unknown" and the ArchSpec::TripleVendorWasSpecified() method says 953 // that any OSName setting means it was specified. 954 } else if (arch_type == eArchTypeELF) { 955 switch (os) { 956 case llvm::ELF::ELFOSABI_AIX: 957 m_triple.setOS(llvm::Triple::OSType::AIX); 958 break; 959 case llvm::ELF::ELFOSABI_FREEBSD: 960 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 961 break; 962 case llvm::ELF::ELFOSABI_GNU: 963 m_triple.setOS(llvm::Triple::OSType::Linux); 964 break; 965 case llvm::ELF::ELFOSABI_NETBSD: 966 m_triple.setOS(llvm::Triple::OSType::NetBSD); 967 break; 968 case llvm::ELF::ELFOSABI_OPENBSD: 969 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 970 break; 971 case llvm::ELF::ELFOSABI_SOLARIS: 972 m_triple.setOS(llvm::Triple::OSType::Solaris); 973 break; 974 } 975 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 976 m_triple.setVendor(llvm::Triple::PC); 977 m_triple.setOS(llvm::Triple::Win32); 978 } else { 979 m_triple.setVendor(llvm::Triple::UnknownVendor); 980 m_triple.setOS(llvm::Triple::UnknownOS); 981 } 982 // Fall back onto setting the machine type if the arch by name 983 // failed... 984 if (m_triple.getArch() == llvm::Triple::UnknownArch) 985 m_triple.setArch(core_def->machine); 986 } 987 } else { 988 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 989 if (log) 990 log->Printf("Unable to find a core definition for cpu 0x%" PRIx32 " sub %" PRId32, cpu, sub); 991 } 992 } 993 CoreUpdated(update_triple); 994 return IsValid(); 995 } 996 997 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 998 const CoreDefinition *core_def = FindCoreDefinition(m_core); 999 if (core_def) 1000 return core_def->min_opcode_byte_size; 1001 return 0; 1002 } 1003 1004 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 1005 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1006 if (core_def) 1007 return core_def->max_opcode_byte_size; 1008 return 0; 1009 } 1010 1011 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 1012 return IsEqualTo(rhs, true); 1013 } 1014 1015 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 1016 return IsEqualTo(rhs, false); 1017 } 1018 1019 static bool isCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 1020 llvm::Triple::EnvironmentType rhs) { 1021 if (lhs == rhs) 1022 return true; 1023 1024 // If any of the environment is unknown then they are compatible 1025 if (lhs == llvm::Triple::UnknownEnvironment || 1026 rhs == llvm::Triple::UnknownEnvironment) 1027 return true; 1028 1029 // If one of the environment is Android and the other one is EABI then they 1030 // are considered to be compatible. This is required as a workaround for 1031 // shared libraries compiled for Android without the NOTE section indicating 1032 // that they are using the Android ABI. 1033 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 1034 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 1035 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1036 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1037 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1038 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1039 return true; 1040 1041 return false; 1042 } 1043 1044 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1045 // explicitly ignoring m_distribution_id in this method. 1046 1047 if (GetByteOrder() != rhs.GetByteOrder()) 1048 return false; 1049 1050 const ArchSpec::Core lhs_core = GetCore(); 1051 const ArchSpec::Core rhs_core = rhs.GetCore(); 1052 1053 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1054 1055 if (core_match) { 1056 const llvm::Triple &lhs_triple = GetTriple(); 1057 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1058 1059 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1060 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1061 if (lhs_triple_vendor != rhs_triple_vendor) { 1062 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1063 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1064 // Both architectures had the vendor specified, so if they aren't equal 1065 // then we return false 1066 if (rhs_vendor_specified && lhs_vendor_specified) 1067 return false; 1068 1069 // Only fail if both vendor types are not unknown 1070 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1071 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1072 return false; 1073 } 1074 1075 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1076 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1077 if (lhs_triple_os != rhs_triple_os) { 1078 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1079 const bool lhs_os_specified = TripleOSWasSpecified(); 1080 // Both architectures had the OS specified, so if they aren't equal then 1081 // we return false 1082 if (rhs_os_specified && lhs_os_specified) 1083 return false; 1084 1085 // Only fail if both os types are not unknown 1086 if (lhs_triple_os != llvm::Triple::UnknownOS && 1087 rhs_triple_os != llvm::Triple::UnknownOS) 1088 return false; 1089 } 1090 1091 const llvm::Triple::EnvironmentType lhs_triple_env = 1092 lhs_triple.getEnvironment(); 1093 const llvm::Triple::EnvironmentType rhs_triple_env = 1094 rhs_triple.getEnvironment(); 1095 1096 if (!isCompatibleEnvironment(lhs_triple_env, rhs_triple_env)) 1097 return false; 1098 return true; 1099 } 1100 return false; 1101 } 1102 1103 void ArchSpec::UpdateCore() { 1104 llvm::StringRef arch_name(m_triple.getArchName()); 1105 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1106 if (core_def) { 1107 m_core = core_def->core; 1108 // Set the byte order to the default byte order for an architecture. This 1109 // can be modified if needed for cases when cores handle both big and 1110 // little endian 1111 m_byte_order = core_def->default_byte_order; 1112 } else { 1113 Clear(); 1114 } 1115 } 1116 1117 //===----------------------------------------------------------------------===// 1118 // Helper methods. 1119 1120 void ArchSpec::CoreUpdated(bool update_triple) { 1121 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1122 if (core_def) { 1123 if (update_triple) 1124 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1125 m_byte_order = core_def->default_byte_order; 1126 } else { 1127 if (update_triple) 1128 m_triple = llvm::Triple(); 1129 m_byte_order = eByteOrderInvalid; 1130 } 1131 } 1132 1133 //===----------------------------------------------------------------------===// 1134 // Operators. 1135 1136 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1137 bool try_inverse, bool enforce_exact_match) { 1138 if (core1 == core2) 1139 return true; 1140 1141 switch (core1) { 1142 case ArchSpec::kCore_any: 1143 return true; 1144 1145 case ArchSpec::eCore_arm_generic: 1146 if (enforce_exact_match) 1147 break; 1148 LLVM_FALLTHROUGH; 1149 case ArchSpec::kCore_arm_any: 1150 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1151 return true; 1152 if (core2 >= ArchSpec::kCore_thumb_first && 1153 core2 <= ArchSpec::kCore_thumb_last) 1154 return true; 1155 if (core2 == ArchSpec::kCore_arm_any) 1156 return true; 1157 break; 1158 1159 case ArchSpec::kCore_x86_32_any: 1160 if ((core2 >= ArchSpec::kCore_x86_32_first && 1161 core2 <= ArchSpec::kCore_x86_32_last) || 1162 (core2 == ArchSpec::kCore_x86_32_any)) 1163 return true; 1164 break; 1165 1166 case ArchSpec::kCore_x86_64_any: 1167 if ((core2 >= ArchSpec::kCore_x86_64_first && 1168 core2 <= ArchSpec::kCore_x86_64_last) || 1169 (core2 == ArchSpec::kCore_x86_64_any)) 1170 return true; 1171 break; 1172 1173 case ArchSpec::kCore_ppc_any: 1174 if ((core2 >= ArchSpec::kCore_ppc_first && 1175 core2 <= ArchSpec::kCore_ppc_last) || 1176 (core2 == ArchSpec::kCore_ppc_any)) 1177 return true; 1178 break; 1179 1180 case ArchSpec::kCore_ppc64_any: 1181 if ((core2 >= ArchSpec::kCore_ppc64_first && 1182 core2 <= ArchSpec::kCore_ppc64_last) || 1183 (core2 == ArchSpec::kCore_ppc64_any)) 1184 return true; 1185 break; 1186 1187 case ArchSpec::eCore_arm_armv6m: 1188 if (!enforce_exact_match) { 1189 if (core2 == ArchSpec::eCore_arm_generic) 1190 return true; 1191 try_inverse = false; 1192 if (core2 == ArchSpec::eCore_arm_armv7) 1193 return true; 1194 if (core2 == ArchSpec::eCore_arm_armv6m) 1195 return true; 1196 } 1197 break; 1198 1199 case ArchSpec::kCore_hexagon_any: 1200 if ((core2 >= ArchSpec::kCore_hexagon_first && 1201 core2 <= ArchSpec::kCore_hexagon_last) || 1202 (core2 == ArchSpec::kCore_hexagon_any)) 1203 return true; 1204 break; 1205 1206 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1207 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1208 // ARMv7E-M - armv7em 1209 case ArchSpec::eCore_arm_armv7em: 1210 if (!enforce_exact_match) { 1211 if (core2 == ArchSpec::eCore_arm_generic) 1212 return true; 1213 if (core2 == ArchSpec::eCore_arm_armv7m) 1214 return true; 1215 if (core2 == ArchSpec::eCore_arm_armv6m) 1216 return true; 1217 if (core2 == ArchSpec::eCore_arm_armv7) 1218 return true; 1219 try_inverse = true; 1220 } 1221 break; 1222 1223 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1224 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1225 // ARMv7E-M - armv7em 1226 case ArchSpec::eCore_arm_armv7m: 1227 if (!enforce_exact_match) { 1228 if (core2 == ArchSpec::eCore_arm_generic) 1229 return true; 1230 if (core2 == ArchSpec::eCore_arm_armv6m) 1231 return true; 1232 if (core2 == ArchSpec::eCore_arm_armv7) 1233 return true; 1234 if (core2 == ArchSpec::eCore_arm_armv7em) 1235 return true; 1236 try_inverse = true; 1237 } 1238 break; 1239 1240 case ArchSpec::eCore_arm_armv7f: 1241 case ArchSpec::eCore_arm_armv7k: 1242 case ArchSpec::eCore_arm_armv7s: 1243 if (!enforce_exact_match) { 1244 if (core2 == ArchSpec::eCore_arm_generic) 1245 return true; 1246 if (core2 == ArchSpec::eCore_arm_armv7) 1247 return true; 1248 try_inverse = false; 1249 } 1250 break; 1251 1252 case ArchSpec::eCore_x86_64_x86_64h: 1253 if (!enforce_exact_match) { 1254 try_inverse = false; 1255 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1256 return true; 1257 } 1258 break; 1259 1260 case ArchSpec::eCore_arm_armv8: 1261 if (!enforce_exact_match) { 1262 if (core2 == ArchSpec::eCore_arm_arm64) 1263 return true; 1264 if (core2 == ArchSpec::eCore_arm_aarch64) 1265 return true; 1266 try_inverse = false; 1267 } 1268 break; 1269 1270 case ArchSpec::eCore_arm_aarch64: 1271 if (!enforce_exact_match) { 1272 if (core2 == ArchSpec::eCore_arm_arm64) 1273 return true; 1274 if (core2 == ArchSpec::eCore_arm_armv8) 1275 return true; 1276 try_inverse = false; 1277 } 1278 break; 1279 1280 case ArchSpec::eCore_arm_arm64: 1281 if (!enforce_exact_match) { 1282 if (core2 == ArchSpec::eCore_arm_aarch64) 1283 return true; 1284 if (core2 == ArchSpec::eCore_arm_armv8) 1285 return true; 1286 try_inverse = false; 1287 } 1288 break; 1289 1290 case ArchSpec::eCore_mips32: 1291 if (!enforce_exact_match) { 1292 if (core2 >= ArchSpec::kCore_mips32_first && 1293 core2 <= ArchSpec::kCore_mips32_last) 1294 return true; 1295 try_inverse = false; 1296 } 1297 break; 1298 1299 case ArchSpec::eCore_mips32el: 1300 if (!enforce_exact_match) { 1301 if (core2 >= ArchSpec::kCore_mips32el_first && 1302 core2 <= ArchSpec::kCore_mips32el_last) 1303 return true; 1304 try_inverse = true; 1305 } 1306 break; 1307 1308 case ArchSpec::eCore_mips64: 1309 if (!enforce_exact_match) { 1310 if (core2 >= ArchSpec::kCore_mips32_first && 1311 core2 <= ArchSpec::kCore_mips32_last) 1312 return true; 1313 if (core2 >= ArchSpec::kCore_mips64_first && 1314 core2 <= ArchSpec::kCore_mips64_last) 1315 return true; 1316 try_inverse = false; 1317 } 1318 break; 1319 1320 case ArchSpec::eCore_mips64el: 1321 if (!enforce_exact_match) { 1322 if (core2 >= ArchSpec::kCore_mips32el_first && 1323 core2 <= ArchSpec::kCore_mips32el_last) 1324 return true; 1325 if (core2 >= ArchSpec::kCore_mips64el_first && 1326 core2 <= ArchSpec::kCore_mips64el_last) 1327 return true; 1328 try_inverse = false; 1329 } 1330 break; 1331 1332 case ArchSpec::eCore_mips64r2: 1333 case ArchSpec::eCore_mips64r3: 1334 case ArchSpec::eCore_mips64r5: 1335 if (!enforce_exact_match) { 1336 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1337 return true; 1338 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1339 return true; 1340 try_inverse = false; 1341 } 1342 break; 1343 1344 case ArchSpec::eCore_mips64r2el: 1345 case ArchSpec::eCore_mips64r3el: 1346 case ArchSpec::eCore_mips64r5el: 1347 if (!enforce_exact_match) { 1348 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1349 return true; 1350 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1351 return true; 1352 try_inverse = false; 1353 } 1354 break; 1355 1356 case ArchSpec::eCore_mips32r2: 1357 case ArchSpec::eCore_mips32r3: 1358 case ArchSpec::eCore_mips32r5: 1359 if (!enforce_exact_match) { 1360 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1361 return true; 1362 } 1363 break; 1364 1365 case ArchSpec::eCore_mips32r2el: 1366 case ArchSpec::eCore_mips32r3el: 1367 case ArchSpec::eCore_mips32r5el: 1368 if (!enforce_exact_match) { 1369 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1370 return true; 1371 } 1372 break; 1373 1374 case ArchSpec::eCore_mips32r6: 1375 if (!enforce_exact_match) { 1376 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1377 return true; 1378 } 1379 break; 1380 1381 case ArchSpec::eCore_mips32r6el: 1382 if (!enforce_exact_match) { 1383 if (core2 == ArchSpec::eCore_mips32el || 1384 core2 == ArchSpec::eCore_mips32r6el) 1385 return true; 1386 } 1387 break; 1388 1389 case ArchSpec::eCore_mips64r6: 1390 if (!enforce_exact_match) { 1391 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1392 return true; 1393 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1394 return true; 1395 } 1396 break; 1397 1398 case ArchSpec::eCore_mips64r6el: 1399 if (!enforce_exact_match) { 1400 if (core2 == ArchSpec::eCore_mips32el || 1401 core2 == ArchSpec::eCore_mips32r6el) 1402 return true; 1403 if (core2 == ArchSpec::eCore_mips64el || 1404 core2 == ArchSpec::eCore_mips64r6el) 1405 return true; 1406 } 1407 break; 1408 1409 default: 1410 break; 1411 } 1412 if (try_inverse) 1413 return cores_match(core2, core1, false, enforce_exact_match); 1414 return false; 1415 } 1416 1417 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1418 const ArchSpec::Core lhs_core = lhs.GetCore(); 1419 const ArchSpec::Core rhs_core = rhs.GetCore(); 1420 return lhs_core < rhs_core; 1421 } 1422 1423 1424 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1425 return lhs.GetCore() == rhs.GetCore(); 1426 } 1427 1428 bool ArchSpec::IsFullySpecifiedTriple() const { 1429 const auto &user_specified_triple = GetTriple(); 1430 1431 bool user_triple_fully_specified = false; 1432 1433 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1434 TripleOSWasSpecified()) { 1435 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1436 TripleVendorWasSpecified()) { 1437 const unsigned unspecified = 0; 1438 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1439 user_triple_fully_specified = true; 1440 } 1441 } 1442 } 1443 1444 return user_triple_fully_specified; 1445 } 1446 1447 void ArchSpec::PiecewiseTripleCompare( 1448 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1449 bool &os_different, bool &os_version_different, bool &env_different) const { 1450 const llvm::Triple &me(GetTriple()); 1451 const llvm::Triple &them(other.GetTriple()); 1452 1453 arch_different = (me.getArch() != them.getArch()); 1454 1455 vendor_different = (me.getVendor() != them.getVendor()); 1456 1457 os_different = (me.getOS() != them.getOS()); 1458 1459 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1460 1461 env_different = (me.getEnvironment() != them.getEnvironment()); 1462 } 1463 1464 bool ArchSpec::IsAlwaysThumbInstructions() const { 1465 std::string Status; 1466 if (GetTriple().getArch() == llvm::Triple::arm || 1467 GetTriple().getArch() == llvm::Triple::thumb) { 1468 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1469 // 1470 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1471 // execute thumb instructions. We map the cores to arch names like this: 1472 // 1473 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1474 // Cortex-M7: armv7em 1475 1476 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1477 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1478 GetCore() == ArchSpec::Core::eCore_arm_armv6m) { 1479 return true; 1480 } 1481 } 1482 return false; 1483 } 1484 1485 void ArchSpec::DumpTriple(Stream &s) const { 1486 const llvm::Triple &triple = GetTriple(); 1487 llvm::StringRef arch_str = triple.getArchName(); 1488 llvm::StringRef vendor_str = triple.getVendorName(); 1489 llvm::StringRef os_str = triple.getOSName(); 1490 llvm::StringRef environ_str = triple.getEnvironmentName(); 1491 1492 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1493 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1494 os_str.empty() ? "*" : os_str.str().c_str()); 1495 1496 if (!environ_str.empty()) 1497 s.Printf("-%s", environ_str.str().c_str()); 1498 } 1499