1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_generic, "hexagon"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 214 215 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 217 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 219 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"} 220 }; 221 222 // Ensure that we have an entry in the g_core_definitions for each core. If you 223 // comment out an entry above, you will need to comment out the corresponding 224 // ArchSpec::Core enumeration. 225 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 226 ArchSpec::kNumCores, 227 "make sure we have one core definition for each core"); 228 229 struct ArchDefinitionEntry { 230 ArchSpec::Core core; 231 uint32_t cpu; 232 uint32_t sub; 233 uint32_t cpu_mask; 234 uint32_t sub_mask; 235 }; 236 237 struct ArchDefinition { 238 ArchitectureType type; 239 size_t num_entries; 240 const ArchDefinitionEntry *entries; 241 const char *name; 242 }; 243 244 void ArchSpec::ListSupportedArchNames(StringList &list) { 245 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 246 list.AppendString(g_core_definitions[i].name); 247 } 248 249 void ArchSpec::AutoComplete(CompletionRequest &request) { 250 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 251 request.TryCompleteCurrentArg(g_core_definitions[i].name); 252 } 253 254 #define CPU_ANY (UINT32_MAX) 255 256 //===----------------------------------------------------------------------===// 257 // A table that gets searched linearly for matches. This table is used to 258 // convert cpu type and subtypes to architecture names, and to convert 259 // architecture names to cpu types and subtypes. The ordering is important and 260 // allows the precedence to be set when the table is built. 261 #define SUBTYPE_MASK 0x00FFFFFFu 262 263 static const ArchDefinitionEntry g_macho_arch_entries[] = { 264 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 265 UINT32_MAX, UINT32_MAX}, 266 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 267 SUBTYPE_MASK}, 268 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 269 SUBTYPE_MASK}, 270 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 271 SUBTYPE_MASK}, 272 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 273 SUBTYPE_MASK}, 274 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 275 SUBTYPE_MASK}, 276 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 277 SUBTYPE_MASK}, 278 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 279 SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 303 UINT32_MAX, SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 305 UINT32_MAX, SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 307 UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 309 SUBTYPE_MASK}, 310 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 317 SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 333 UINT32_MAX, UINT32_MAX}, 334 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 335 SUBTYPE_MASK}, 336 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 343 SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 361 UINT32_MAX, SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 363 UINT32_MAX, SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 365 UINT32_MAX, SUBTYPE_MASK}, 366 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 367 SUBTYPE_MASK}, 368 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 369 SUBTYPE_MASK}, 370 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 371 UINT32_MAX, SUBTYPE_MASK}, 372 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 373 UINT32_MAX, UINT32_MAX}, 374 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 375 SUBTYPE_MASK}, 376 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 379 UINT32_MAX, SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 381 UINT32_MAX, UINT32_MAX}, 382 // Catch any unknown mach architectures so we can always use the object and 383 // symbol mach-o files 384 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 385 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 386 0x00000000u}}; 387 388 static const ArchDefinition g_macho_arch_def = { 389 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 390 g_macho_arch_entries, "mach-o"}; 391 392 //===----------------------------------------------------------------------===// 393 // A table that gets searched linearly for matches. This table is used to 394 // convert cpu type and subtypes to architecture names, and to convert 395 // architecture names to cpu types and subtypes. The ordering is important and 396 // allows the precedence to be set when the table is built. 397 static const ArchDefinitionEntry g_elf_arch_entries[] = { 398 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 399 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 400 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 401 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 402 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 403 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 404 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 405 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 406 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 407 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 408 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 410 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 412 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 414 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 416 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 417 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 418 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 419 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 420 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 422 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 423 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 424 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 425 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 426 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 427 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 428 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 429 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 430 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 431 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 432 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 433 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 434 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 435 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 436 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 438 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 440 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 442 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 443 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 444 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 445 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 446 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 447 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARC 448 }; 449 450 static const ArchDefinition g_elf_arch_def = { 451 eArchTypeELF, 452 llvm::array_lengthof(g_elf_arch_entries), 453 g_elf_arch_entries, 454 "elf", 455 }; 456 457 static const ArchDefinitionEntry g_coff_arch_entries[] = { 458 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 459 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 460 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 461 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 462 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 463 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 464 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 465 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 466 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 467 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 468 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 469 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 470 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 472 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 474 }; 475 476 static const ArchDefinition g_coff_arch_def = { 477 eArchTypeCOFF, 478 llvm::array_lengthof(g_coff_arch_entries), 479 g_coff_arch_entries, 480 "pe-coff", 481 }; 482 483 //===----------------------------------------------------------------------===// 484 // Table of all ArchDefinitions 485 static const ArchDefinition *g_arch_definitions[] = { 486 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 487 488 static const size_t k_num_arch_definitions = 489 llvm::array_lengthof(g_arch_definitions); 490 491 //===----------------------------------------------------------------------===// 492 // Static helper functions. 493 494 // Get the architecture definition for a given object type. 495 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 496 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 497 const ArchDefinition *def = g_arch_definitions[i]; 498 if (def->type == arch_type) 499 return def; 500 } 501 return nullptr; 502 } 503 504 // Get an architecture definition by name. 505 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 506 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 507 if (name.equals_lower(g_core_definitions[i].name)) 508 return &g_core_definitions[i]; 509 } 510 return nullptr; 511 } 512 513 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 514 if (core < llvm::array_lengthof(g_core_definitions)) 515 return &g_core_definitions[core]; 516 return nullptr; 517 } 518 519 // Get a definition entry by cpu type and subtype. 520 static const ArchDefinitionEntry * 521 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 522 if (def == nullptr) 523 return nullptr; 524 525 const ArchDefinitionEntry *entries = def->entries; 526 for (size_t i = 0; i < def->num_entries; ++i) { 527 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 528 if (entries[i].sub == (sub & entries[i].sub_mask)) 529 return &entries[i]; 530 } 531 return nullptr; 532 } 533 534 static const ArchDefinitionEntry * 535 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 536 if (def == nullptr) 537 return nullptr; 538 539 const ArchDefinitionEntry *entries = def->entries; 540 for (size_t i = 0; i < def->num_entries; ++i) { 541 if (entries[i].core == core) 542 return &entries[i]; 543 } 544 return nullptr; 545 } 546 547 //===----------------------------------------------------------------------===// 548 // Constructors and destructors. 549 550 ArchSpec::ArchSpec() {} 551 552 ArchSpec::ArchSpec(const char *triple_cstr) { 553 if (triple_cstr) 554 SetTriple(triple_cstr); 555 } 556 557 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 558 559 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 560 561 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 562 SetArchitecture(arch_type, cpu, subtype); 563 } 564 565 ArchSpec::~ArchSpec() = default; 566 567 //===----------------------------------------------------------------------===// 568 // Assignment and initialization. 569 570 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 571 if (this != &rhs) { 572 m_triple = rhs.m_triple; 573 m_core = rhs.m_core; 574 m_byte_order = rhs.m_byte_order; 575 m_distribution_id = rhs.m_distribution_id; 576 m_flags = rhs.m_flags; 577 } 578 return *this; 579 } 580 581 void ArchSpec::Clear() { 582 m_triple = llvm::Triple(); 583 m_core = kCore_invalid; 584 m_byte_order = eByteOrderInvalid; 585 m_distribution_id.Clear(); 586 m_flags = 0; 587 } 588 589 //===----------------------------------------------------------------------===// 590 // Predicates. 591 592 const char *ArchSpec::GetArchitectureName() const { 593 const CoreDefinition *core_def = FindCoreDefinition(m_core); 594 if (core_def) 595 return core_def->name; 596 return "unknown"; 597 } 598 599 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 600 601 std::string ArchSpec::GetTargetABI() const { 602 603 std::string abi; 604 605 if (IsMIPS()) { 606 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 607 case ArchSpec::eMIPSABI_N64: 608 abi = "n64"; 609 return abi; 610 case ArchSpec::eMIPSABI_N32: 611 abi = "n32"; 612 return abi; 613 case ArchSpec::eMIPSABI_O32: 614 abi = "o32"; 615 return abi; 616 default: 617 return abi; 618 } 619 } 620 return abi; 621 } 622 623 void ArchSpec::SetFlags(std::string elf_abi) { 624 625 uint32_t flag = GetFlags(); 626 if (IsMIPS()) { 627 if (elf_abi == "n64") 628 flag |= ArchSpec::eMIPSABI_N64; 629 else if (elf_abi == "n32") 630 flag |= ArchSpec::eMIPSABI_N32; 631 else if (elf_abi == "o32") 632 flag |= ArchSpec::eMIPSABI_O32; 633 } 634 SetFlags(flag); 635 } 636 637 std::string ArchSpec::GetClangTargetCPU() const { 638 std::string cpu; 639 640 if (IsMIPS()) { 641 switch (m_core) { 642 case ArchSpec::eCore_mips32: 643 case ArchSpec::eCore_mips32el: 644 cpu = "mips32"; 645 break; 646 case ArchSpec::eCore_mips32r2: 647 case ArchSpec::eCore_mips32r2el: 648 cpu = "mips32r2"; 649 break; 650 case ArchSpec::eCore_mips32r3: 651 case ArchSpec::eCore_mips32r3el: 652 cpu = "mips32r3"; 653 break; 654 case ArchSpec::eCore_mips32r5: 655 case ArchSpec::eCore_mips32r5el: 656 cpu = "mips32r5"; 657 break; 658 case ArchSpec::eCore_mips32r6: 659 case ArchSpec::eCore_mips32r6el: 660 cpu = "mips32r6"; 661 break; 662 case ArchSpec::eCore_mips64: 663 case ArchSpec::eCore_mips64el: 664 cpu = "mips64"; 665 break; 666 case ArchSpec::eCore_mips64r2: 667 case ArchSpec::eCore_mips64r2el: 668 cpu = "mips64r2"; 669 break; 670 case ArchSpec::eCore_mips64r3: 671 case ArchSpec::eCore_mips64r3el: 672 cpu = "mips64r3"; 673 break; 674 case ArchSpec::eCore_mips64r5: 675 case ArchSpec::eCore_mips64r5el: 676 cpu = "mips64r5"; 677 break; 678 case ArchSpec::eCore_mips64r6: 679 case ArchSpec::eCore_mips64r6el: 680 cpu = "mips64r6"; 681 break; 682 default: 683 break; 684 } 685 } 686 return cpu; 687 } 688 689 uint32_t ArchSpec::GetMachOCPUType() const { 690 const CoreDefinition *core_def = FindCoreDefinition(m_core); 691 if (core_def) { 692 const ArchDefinitionEntry *arch_def = 693 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 694 if (arch_def) { 695 return arch_def->cpu; 696 } 697 } 698 return LLDB_INVALID_CPUTYPE; 699 } 700 701 uint32_t ArchSpec::GetMachOCPUSubType() const { 702 const CoreDefinition *core_def = FindCoreDefinition(m_core); 703 if (core_def) { 704 const ArchDefinitionEntry *arch_def = 705 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 706 if (arch_def) { 707 return arch_def->sub; 708 } 709 } 710 return LLDB_INVALID_CPUTYPE; 711 } 712 713 uint32_t ArchSpec::GetDataByteSize() const { 714 return 1; 715 } 716 717 uint32_t ArchSpec::GetCodeByteSize() const { 718 return 1; 719 } 720 721 llvm::Triple::ArchType ArchSpec::GetMachine() const { 722 const CoreDefinition *core_def = FindCoreDefinition(m_core); 723 if (core_def) 724 return core_def->machine; 725 726 return llvm::Triple::UnknownArch; 727 } 728 729 ConstString ArchSpec::GetDistributionId() const { 730 return m_distribution_id; 731 } 732 733 void ArchSpec::SetDistributionId(const char *distribution_id) { 734 m_distribution_id.SetCString(distribution_id); 735 } 736 737 uint32_t ArchSpec::GetAddressByteSize() const { 738 const CoreDefinition *core_def = FindCoreDefinition(m_core); 739 if (core_def) { 740 if (core_def->machine == llvm::Triple::mips64 || 741 core_def->machine == llvm::Triple::mips64el) { 742 // For N32/O32 applications Address size is 4 bytes. 743 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 744 return 4; 745 } 746 return core_def->addr_byte_size; 747 } 748 return 0; 749 } 750 751 ByteOrder ArchSpec::GetDefaultEndian() const { 752 const CoreDefinition *core_def = FindCoreDefinition(m_core); 753 if (core_def) 754 return core_def->default_byte_order; 755 return eByteOrderInvalid; 756 } 757 758 bool ArchSpec::CharIsSignedByDefault() const { 759 switch (m_triple.getArch()) { 760 default: 761 return true; 762 763 case llvm::Triple::aarch64: 764 case llvm::Triple::aarch64_32: 765 case llvm::Triple::aarch64_be: 766 case llvm::Triple::arm: 767 case llvm::Triple::armeb: 768 case llvm::Triple::thumb: 769 case llvm::Triple::thumbeb: 770 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 771 772 case llvm::Triple::ppc: 773 case llvm::Triple::ppc64: 774 return m_triple.isOSDarwin(); 775 776 case llvm::Triple::ppc64le: 777 case llvm::Triple::systemz: 778 case llvm::Triple::xcore: 779 case llvm::Triple::arc: 780 return false; 781 } 782 } 783 784 lldb::ByteOrder ArchSpec::GetByteOrder() const { 785 if (m_byte_order == eByteOrderInvalid) 786 return GetDefaultEndian(); 787 return m_byte_order; 788 } 789 790 //===----------------------------------------------------------------------===// 791 // Mutators. 792 793 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 794 m_triple = triple; 795 UpdateCore(); 796 return IsValid(); 797 } 798 799 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 800 ArchSpec &arch) { 801 // Accept "12-10" or "12.10" as cpu type/subtype 802 if (triple_str.empty()) 803 return false; 804 805 size_t pos = triple_str.find_first_of("-."); 806 if (pos == llvm::StringRef::npos) 807 return false; 808 809 llvm::StringRef cpu_str = triple_str.substr(0, pos); 810 llvm::StringRef remainder = triple_str.substr(pos + 1); 811 if (cpu_str.empty() || remainder.empty()) 812 return false; 813 814 llvm::StringRef sub_str; 815 llvm::StringRef vendor; 816 llvm::StringRef os; 817 std::tie(sub_str, remainder) = remainder.split('-'); 818 std::tie(vendor, os) = remainder.split('-'); 819 820 uint32_t cpu = 0; 821 uint32_t sub = 0; 822 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 823 return false; 824 825 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 826 return false; 827 if (!vendor.empty() && !os.empty()) { 828 arch.GetTriple().setVendorName(vendor); 829 arch.GetTriple().setOSName(os); 830 } 831 832 return true; 833 } 834 835 bool ArchSpec::SetTriple(llvm::StringRef triple) { 836 if (triple.empty()) { 837 Clear(); 838 return false; 839 } 840 841 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 842 return true; 843 844 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 845 return IsValid(); 846 } 847 848 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 849 return !normalized_triple.getArchName().empty() && 850 normalized_triple.getOSName().empty() && 851 normalized_triple.getVendorName().empty() && 852 normalized_triple.getEnvironmentName().empty(); 853 } 854 855 void ArchSpec::MergeFrom(const ArchSpec &other) { 856 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 857 GetTriple().setVendor(other.GetTriple().getVendor()); 858 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 859 GetTriple().setOS(other.GetTriple().getOS()); 860 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 861 GetTriple().setArch(other.GetTriple().getArch()); 862 863 // MachO unknown64 isn't really invalid as the debugger can still obtain 864 // information from the binary, e.g. line tables. As such, we don't update 865 // the core here. 866 if (other.GetCore() != eCore_uknownMach64) 867 UpdateCore(); 868 } 869 if (!TripleEnvironmentWasSpecified() && 870 other.TripleEnvironmentWasSpecified()) { 871 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 872 } 873 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 874 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 875 // adopt the specific arm core. 876 if (GetTriple().getArch() == llvm::Triple::arm && 877 other.GetTriple().getArch() == llvm::Triple::arm && 878 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 879 other.GetCore() != ArchSpec::eCore_arm_generic) { 880 m_core = other.GetCore(); 881 CoreUpdated(true); 882 } 883 if (GetFlags() == 0) { 884 SetFlags(other.GetFlags()); 885 } 886 } 887 888 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 889 uint32_t sub, uint32_t os) { 890 m_core = kCore_invalid; 891 bool update_triple = true; 892 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 893 if (arch_def) { 894 const ArchDefinitionEntry *arch_def_entry = 895 FindArchDefinitionEntry(arch_def, cpu, sub); 896 if (arch_def_entry) { 897 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 898 if (core_def) { 899 m_core = core_def->core; 900 update_triple = false; 901 // Always use the architecture name because it might be more 902 // descriptive than the architecture enum ("armv7" -> 903 // llvm::Triple::arm). 904 m_triple.setArchName(llvm::StringRef(core_def->name)); 905 if (arch_type == eArchTypeMachO) { 906 m_triple.setVendor(llvm::Triple::Apple); 907 908 // Don't set the OS. It could be simulator, macosx, ios, watchos, 909 // tvos, bridgeos. We could get close with the cpu type - but we 910 // can't get it right all of the time. Better to leave this unset 911 // so other sections of code will set it when they have more 912 // information. NB: don't call m_triple.setOS 913 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 914 // the ArchSpec::TripleVendorWasSpecified() method says that any 915 // OSName setting means it was specified. 916 } else if (arch_type == eArchTypeELF) { 917 switch (os) { 918 case llvm::ELF::ELFOSABI_AIX: 919 m_triple.setOS(llvm::Triple::OSType::AIX); 920 break; 921 case llvm::ELF::ELFOSABI_FREEBSD: 922 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 923 break; 924 case llvm::ELF::ELFOSABI_GNU: 925 m_triple.setOS(llvm::Triple::OSType::Linux); 926 break; 927 case llvm::ELF::ELFOSABI_NETBSD: 928 m_triple.setOS(llvm::Triple::OSType::NetBSD); 929 break; 930 case llvm::ELF::ELFOSABI_OPENBSD: 931 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 932 break; 933 case llvm::ELF::ELFOSABI_SOLARIS: 934 m_triple.setOS(llvm::Triple::OSType::Solaris); 935 break; 936 } 937 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 938 m_triple.setVendor(llvm::Triple::PC); 939 m_triple.setOS(llvm::Triple::Win32); 940 } else { 941 m_triple.setVendor(llvm::Triple::UnknownVendor); 942 m_triple.setOS(llvm::Triple::UnknownOS); 943 } 944 // Fall back onto setting the machine type if the arch by name 945 // failed... 946 if (m_triple.getArch() == llvm::Triple::UnknownArch) 947 m_triple.setArch(core_def->machine); 948 } 949 } else { 950 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 951 LLDB_LOGF(log, 952 "Unable to find a core definition for cpu 0x%" PRIx32 953 " sub %" PRId32, 954 cpu, sub); 955 } 956 } 957 CoreUpdated(update_triple); 958 return IsValid(); 959 } 960 961 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 962 const CoreDefinition *core_def = FindCoreDefinition(m_core); 963 if (core_def) 964 return core_def->min_opcode_byte_size; 965 return 0; 966 } 967 968 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 969 const CoreDefinition *core_def = FindCoreDefinition(m_core); 970 if (core_def) 971 return core_def->max_opcode_byte_size; 972 return 0; 973 } 974 975 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 976 return IsEqualTo(rhs, true); 977 } 978 979 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 980 return IsEqualTo(rhs, false); 981 } 982 983 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 984 llvm::Triple::EnvironmentType rhs) { 985 if (lhs == rhs) 986 return true; 987 988 // If any of the environment is unknown then they are compatible 989 if (lhs == llvm::Triple::UnknownEnvironment || 990 rhs == llvm::Triple::UnknownEnvironment) 991 return true; 992 993 // If one of the environment is Android and the other one is EABI then they 994 // are considered to be compatible. This is required as a workaround for 995 // shared libraries compiled for Android without the NOTE section indicating 996 // that they are using the Android ABI. 997 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 998 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 999 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1000 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1001 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1002 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1003 return true; 1004 1005 return false; 1006 } 1007 1008 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1009 // explicitly ignoring m_distribution_id in this method. 1010 1011 if (GetByteOrder() != rhs.GetByteOrder()) 1012 return false; 1013 1014 const ArchSpec::Core lhs_core = GetCore(); 1015 const ArchSpec::Core rhs_core = rhs.GetCore(); 1016 1017 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1018 1019 if (core_match) { 1020 const llvm::Triple &lhs_triple = GetTriple(); 1021 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1022 1023 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1024 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1025 if (lhs_triple_vendor != rhs_triple_vendor) { 1026 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1027 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1028 // Both architectures had the vendor specified, so if they aren't equal 1029 // then we return false 1030 if (rhs_vendor_specified && lhs_vendor_specified) 1031 return false; 1032 1033 // Only fail if both vendor types are not unknown 1034 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1035 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1036 return false; 1037 } 1038 1039 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1040 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1041 if (lhs_triple_os != rhs_triple_os) { 1042 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1043 const bool lhs_os_specified = TripleOSWasSpecified(); 1044 // Both architectures had the OS specified, so if they aren't equal then 1045 // we return false 1046 if (rhs_os_specified && lhs_os_specified) 1047 return false; 1048 1049 // Only fail if both os types are not unknown 1050 if (lhs_triple_os != llvm::Triple::UnknownOS && 1051 rhs_triple_os != llvm::Triple::UnknownOS) 1052 return false; 1053 } 1054 1055 const llvm::Triple::EnvironmentType lhs_triple_env = 1056 lhs_triple.getEnvironment(); 1057 const llvm::Triple::EnvironmentType rhs_triple_env = 1058 rhs_triple.getEnvironment(); 1059 1060 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1061 } 1062 return false; 1063 } 1064 1065 void ArchSpec::UpdateCore() { 1066 llvm::StringRef arch_name(m_triple.getArchName()); 1067 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1068 if (core_def) { 1069 m_core = core_def->core; 1070 // Set the byte order to the default byte order for an architecture. This 1071 // can be modified if needed for cases when cores handle both big and 1072 // little endian 1073 m_byte_order = core_def->default_byte_order; 1074 } else { 1075 Clear(); 1076 } 1077 } 1078 1079 //===----------------------------------------------------------------------===// 1080 // Helper methods. 1081 1082 void ArchSpec::CoreUpdated(bool update_triple) { 1083 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1084 if (core_def) { 1085 if (update_triple) 1086 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1087 m_byte_order = core_def->default_byte_order; 1088 } else { 1089 if (update_triple) 1090 m_triple = llvm::Triple(); 1091 m_byte_order = eByteOrderInvalid; 1092 } 1093 } 1094 1095 //===----------------------------------------------------------------------===// 1096 // Operators. 1097 1098 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1099 bool try_inverse, bool enforce_exact_match) { 1100 if (core1 == core2) 1101 return true; 1102 1103 switch (core1) { 1104 case ArchSpec::kCore_any: 1105 return true; 1106 1107 case ArchSpec::eCore_arm_generic: 1108 if (enforce_exact_match) 1109 break; 1110 LLVM_FALLTHROUGH; 1111 case ArchSpec::kCore_arm_any: 1112 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1113 return true; 1114 if (core2 >= ArchSpec::kCore_thumb_first && 1115 core2 <= ArchSpec::kCore_thumb_last) 1116 return true; 1117 if (core2 == ArchSpec::kCore_arm_any) 1118 return true; 1119 break; 1120 1121 case ArchSpec::kCore_x86_32_any: 1122 if ((core2 >= ArchSpec::kCore_x86_32_first && 1123 core2 <= ArchSpec::kCore_x86_32_last) || 1124 (core2 == ArchSpec::kCore_x86_32_any)) 1125 return true; 1126 break; 1127 1128 case ArchSpec::kCore_x86_64_any: 1129 if ((core2 >= ArchSpec::kCore_x86_64_first && 1130 core2 <= ArchSpec::kCore_x86_64_last) || 1131 (core2 == ArchSpec::kCore_x86_64_any)) 1132 return true; 1133 break; 1134 1135 case ArchSpec::kCore_ppc_any: 1136 if ((core2 >= ArchSpec::kCore_ppc_first && 1137 core2 <= ArchSpec::kCore_ppc_last) || 1138 (core2 == ArchSpec::kCore_ppc_any)) 1139 return true; 1140 break; 1141 1142 case ArchSpec::kCore_ppc64_any: 1143 if ((core2 >= ArchSpec::kCore_ppc64_first && 1144 core2 <= ArchSpec::kCore_ppc64_last) || 1145 (core2 == ArchSpec::kCore_ppc64_any)) 1146 return true; 1147 break; 1148 1149 case ArchSpec::eCore_arm_armv6m: 1150 if (!enforce_exact_match) { 1151 if (core2 == ArchSpec::eCore_arm_generic) 1152 return true; 1153 try_inverse = false; 1154 if (core2 == ArchSpec::eCore_arm_armv7) 1155 return true; 1156 if (core2 == ArchSpec::eCore_arm_armv6m) 1157 return true; 1158 } 1159 break; 1160 1161 case ArchSpec::kCore_hexagon_any: 1162 if ((core2 >= ArchSpec::kCore_hexagon_first && 1163 core2 <= ArchSpec::kCore_hexagon_last) || 1164 (core2 == ArchSpec::kCore_hexagon_any)) 1165 return true; 1166 break; 1167 1168 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1169 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1170 // ARMv7E-M - armv7em 1171 case ArchSpec::eCore_arm_armv7em: 1172 if (!enforce_exact_match) { 1173 if (core2 == ArchSpec::eCore_arm_generic) 1174 return true; 1175 if (core2 == ArchSpec::eCore_arm_armv7m) 1176 return true; 1177 if (core2 == ArchSpec::eCore_arm_armv6m) 1178 return true; 1179 if (core2 == ArchSpec::eCore_arm_armv7) 1180 return true; 1181 try_inverse = true; 1182 } 1183 break; 1184 1185 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1186 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1187 // ARMv7E-M - armv7em 1188 case ArchSpec::eCore_arm_armv7m: 1189 if (!enforce_exact_match) { 1190 if (core2 == ArchSpec::eCore_arm_generic) 1191 return true; 1192 if (core2 == ArchSpec::eCore_arm_armv6m) 1193 return true; 1194 if (core2 == ArchSpec::eCore_arm_armv7) 1195 return true; 1196 if (core2 == ArchSpec::eCore_arm_armv7em) 1197 return true; 1198 try_inverse = true; 1199 } 1200 break; 1201 1202 case ArchSpec::eCore_arm_armv7f: 1203 case ArchSpec::eCore_arm_armv7k: 1204 case ArchSpec::eCore_arm_armv7s: 1205 if (!enforce_exact_match) { 1206 if (core2 == ArchSpec::eCore_arm_generic) 1207 return true; 1208 if (core2 == ArchSpec::eCore_arm_armv7) 1209 return true; 1210 try_inverse = false; 1211 } 1212 break; 1213 1214 case ArchSpec::eCore_x86_64_x86_64h: 1215 if (!enforce_exact_match) { 1216 try_inverse = false; 1217 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1218 return true; 1219 } 1220 break; 1221 1222 case ArchSpec::eCore_arm_armv8: 1223 if (!enforce_exact_match) { 1224 if (core2 == ArchSpec::eCore_arm_arm64) 1225 return true; 1226 if (core2 == ArchSpec::eCore_arm_aarch64) 1227 return true; 1228 try_inverse = false; 1229 } 1230 break; 1231 1232 case ArchSpec::eCore_arm_aarch64: 1233 if (!enforce_exact_match) { 1234 if (core2 == ArchSpec::eCore_arm_arm64) 1235 return true; 1236 if (core2 == ArchSpec::eCore_arm_armv8) 1237 return true; 1238 try_inverse = false; 1239 } 1240 break; 1241 1242 case ArchSpec::eCore_arm_arm64: 1243 if (!enforce_exact_match) { 1244 if (core2 == ArchSpec::eCore_arm_aarch64) 1245 return true; 1246 if (core2 == ArchSpec::eCore_arm_armv8) 1247 return true; 1248 try_inverse = false; 1249 } 1250 break; 1251 1252 case ArchSpec::eCore_arm_arm64_32: 1253 if (!enforce_exact_match) { 1254 if (core2 == ArchSpec::eCore_arm_generic) 1255 return true; 1256 try_inverse = false; 1257 } 1258 break; 1259 1260 case ArchSpec::eCore_mips32: 1261 if (!enforce_exact_match) { 1262 if (core2 >= ArchSpec::kCore_mips32_first && 1263 core2 <= ArchSpec::kCore_mips32_last) 1264 return true; 1265 try_inverse = false; 1266 } 1267 break; 1268 1269 case ArchSpec::eCore_mips32el: 1270 if (!enforce_exact_match) { 1271 if (core2 >= ArchSpec::kCore_mips32el_first && 1272 core2 <= ArchSpec::kCore_mips32el_last) 1273 return true; 1274 try_inverse = true; 1275 } 1276 break; 1277 1278 case ArchSpec::eCore_mips64: 1279 if (!enforce_exact_match) { 1280 if (core2 >= ArchSpec::kCore_mips32_first && 1281 core2 <= ArchSpec::kCore_mips32_last) 1282 return true; 1283 if (core2 >= ArchSpec::kCore_mips64_first && 1284 core2 <= ArchSpec::kCore_mips64_last) 1285 return true; 1286 try_inverse = false; 1287 } 1288 break; 1289 1290 case ArchSpec::eCore_mips64el: 1291 if (!enforce_exact_match) { 1292 if (core2 >= ArchSpec::kCore_mips32el_first && 1293 core2 <= ArchSpec::kCore_mips32el_last) 1294 return true; 1295 if (core2 >= ArchSpec::kCore_mips64el_first && 1296 core2 <= ArchSpec::kCore_mips64el_last) 1297 return true; 1298 try_inverse = false; 1299 } 1300 break; 1301 1302 case ArchSpec::eCore_mips64r2: 1303 case ArchSpec::eCore_mips64r3: 1304 case ArchSpec::eCore_mips64r5: 1305 if (!enforce_exact_match) { 1306 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1307 return true; 1308 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1309 return true; 1310 try_inverse = false; 1311 } 1312 break; 1313 1314 case ArchSpec::eCore_mips64r2el: 1315 case ArchSpec::eCore_mips64r3el: 1316 case ArchSpec::eCore_mips64r5el: 1317 if (!enforce_exact_match) { 1318 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1319 return true; 1320 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1321 return true; 1322 try_inverse = false; 1323 } 1324 break; 1325 1326 case ArchSpec::eCore_mips32r2: 1327 case ArchSpec::eCore_mips32r3: 1328 case ArchSpec::eCore_mips32r5: 1329 if (!enforce_exact_match) { 1330 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1331 return true; 1332 } 1333 break; 1334 1335 case ArchSpec::eCore_mips32r2el: 1336 case ArchSpec::eCore_mips32r3el: 1337 case ArchSpec::eCore_mips32r5el: 1338 if (!enforce_exact_match) { 1339 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1340 return true; 1341 } 1342 break; 1343 1344 case ArchSpec::eCore_mips32r6: 1345 if (!enforce_exact_match) { 1346 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1347 return true; 1348 } 1349 break; 1350 1351 case ArchSpec::eCore_mips32r6el: 1352 if (!enforce_exact_match) { 1353 if (core2 == ArchSpec::eCore_mips32el || 1354 core2 == ArchSpec::eCore_mips32r6el) 1355 return true; 1356 } 1357 break; 1358 1359 case ArchSpec::eCore_mips64r6: 1360 if (!enforce_exact_match) { 1361 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1362 return true; 1363 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1364 return true; 1365 } 1366 break; 1367 1368 case ArchSpec::eCore_mips64r6el: 1369 if (!enforce_exact_match) { 1370 if (core2 == ArchSpec::eCore_mips32el || 1371 core2 == ArchSpec::eCore_mips32r6el) 1372 return true; 1373 if (core2 == ArchSpec::eCore_mips64el || 1374 core2 == ArchSpec::eCore_mips64r6el) 1375 return true; 1376 } 1377 break; 1378 1379 default: 1380 break; 1381 } 1382 if (try_inverse) 1383 return cores_match(core2, core1, false, enforce_exact_match); 1384 return false; 1385 } 1386 1387 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1388 const ArchSpec::Core lhs_core = lhs.GetCore(); 1389 const ArchSpec::Core rhs_core = rhs.GetCore(); 1390 return lhs_core < rhs_core; 1391 } 1392 1393 1394 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1395 return lhs.GetCore() == rhs.GetCore(); 1396 } 1397 1398 bool ArchSpec::IsFullySpecifiedTriple() const { 1399 const auto &user_specified_triple = GetTriple(); 1400 1401 bool user_triple_fully_specified = false; 1402 1403 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1404 TripleOSWasSpecified()) { 1405 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1406 TripleVendorWasSpecified()) { 1407 const unsigned unspecified = 0; 1408 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1409 user_triple_fully_specified = true; 1410 } 1411 } 1412 } 1413 1414 return user_triple_fully_specified; 1415 } 1416 1417 void ArchSpec::PiecewiseTripleCompare( 1418 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1419 bool &os_different, bool &os_version_different, bool &env_different) const { 1420 const llvm::Triple &me(GetTriple()); 1421 const llvm::Triple &them(other.GetTriple()); 1422 1423 arch_different = (me.getArch() != them.getArch()); 1424 1425 vendor_different = (me.getVendor() != them.getVendor()); 1426 1427 os_different = (me.getOS() != them.getOS()); 1428 1429 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1430 1431 env_different = (me.getEnvironment() != them.getEnvironment()); 1432 } 1433 1434 bool ArchSpec::IsAlwaysThumbInstructions() const { 1435 std::string Status; 1436 if (GetTriple().getArch() == llvm::Triple::arm || 1437 GetTriple().getArch() == llvm::Triple::thumb) { 1438 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1439 // 1440 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1441 // execute thumb instructions. We map the cores to arch names like this: 1442 // 1443 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1444 // Cortex-M7: armv7em 1445 1446 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1447 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1448 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1449 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1450 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1451 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1452 return true; 1453 } 1454 } 1455 return false; 1456 } 1457 1458 void ArchSpec::DumpTriple(Stream &s) const { 1459 const llvm::Triple &triple = GetTriple(); 1460 llvm::StringRef arch_str = triple.getArchName(); 1461 llvm::StringRef vendor_str = triple.getVendorName(); 1462 llvm::StringRef os_str = triple.getOSName(); 1463 llvm::StringRef environ_str = triple.getEnvironmentName(); 1464 1465 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1466 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1467 os_str.empty() ? "*" : os_str.str().c_str()); 1468 1469 if (!environ_str.empty()) 1470 s.Printf("-%s", environ_str.str().c_str()); 1471 } 1472