1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 105 ArchSpec::eCore_arm_aarch64, "aarch64"}, 106 107 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 108 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 109 "mips"}, 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 111 "mipsr2"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 113 "mipsr3"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 115 "mipsr5"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 117 "mipsr6"}, 118 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 119 "mipsel"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 121 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 128 129 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 130 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 131 "mips64"}, 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 133 "mips64r2"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 135 "mips64r3"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 137 "mips64r5"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 139 "mips64r6"}, 140 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 141 ArchSpec::eCore_mips64el, "mips64el"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 150 151 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 152 "powerpc"}, 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 154 "ppc601"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 156 "ppc602"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 158 "ppc603"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 160 "ppc603e"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 162 "ppc603ev"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 164 "ppc604"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 166 "ppc604e"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 168 "ppc620"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 170 "ppc750"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 172 "ppc7400"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 174 "ppc7450"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 176 "ppc970"}, 177 178 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 179 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 180 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 181 "powerpc64"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 183 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 184 185 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 186 ArchSpec::eCore_s390x_generic, "s390x"}, 187 188 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 189 ArchSpec::eCore_sparc_generic, "sparc"}, 190 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 191 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 192 193 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 194 "i386"}, 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 196 "i486"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 198 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 200 "i686"}, 201 202 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 203 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 206 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 207 ArchSpec::eCore_hexagon_generic, "hexagon"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 212 213 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 214 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 215 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 217 }; 218 219 // Ensure that we have an entry in the g_core_definitions for each core. If you 220 // comment out an entry above, you will need to comment out the corresponding 221 // ArchSpec::Core enumeration. 222 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 223 ArchSpec::kNumCores, 224 "make sure we have one core definition for each core"); 225 226 struct ArchDefinitionEntry { 227 ArchSpec::Core core; 228 uint32_t cpu; 229 uint32_t sub; 230 uint32_t cpu_mask; 231 uint32_t sub_mask; 232 }; 233 234 struct ArchDefinition { 235 ArchitectureType type; 236 size_t num_entries; 237 const ArchDefinitionEntry *entries; 238 const char *name; 239 }; 240 241 void ArchSpec::ListSupportedArchNames(StringList &list) { 242 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 243 list.AppendString(g_core_definitions[i].name); 244 } 245 246 void ArchSpec::AutoComplete(CompletionRequest &request) { 247 if (!request.GetCursorArgumentPrefix().empty()) { 248 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 249 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, 250 request.GetCursorArgumentPrefix())) 251 request.AddCompletion(g_core_definitions[i].name); 252 } 253 } else { 254 StringList matches; 255 ListSupportedArchNames(matches); 256 request.AddCompletions(matches); 257 } 258 } 259 260 #define CPU_ANY (UINT32_MAX) 261 262 //===----------------------------------------------------------------------===// 263 // A table that gets searched linearly for matches. This table is used to 264 // convert cpu type and subtypes to architecture names, and to convert 265 // architecture names to cpu types and subtypes. The ordering is important and 266 // allows the precedence to be set when the table is built. 267 #define SUBTYPE_MASK 0x00FFFFFFu 268 269 static const ArchDefinitionEntry g_macho_arch_entries[] = { 270 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 271 UINT32_MAX, UINT32_MAX}, 272 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 273 SUBTYPE_MASK}, 274 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 275 SUBTYPE_MASK}, 276 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 277 SUBTYPE_MASK}, 278 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 279 SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 303 SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 305 SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 307 SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 309 UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 317 SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 333 SUBTYPE_MASK}, 334 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 335 UINT32_MAX, UINT32_MAX}, 336 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 343 SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 361 SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 363 UINT32_MAX, SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 365 UINT32_MAX, SUBTYPE_MASK}, 366 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 367 UINT32_MAX, SUBTYPE_MASK}, 368 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 369 SUBTYPE_MASK}, 370 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 371 SUBTYPE_MASK}, 372 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 373 UINT32_MAX, SUBTYPE_MASK}, 374 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 375 UINT32_MAX, UINT32_MAX}, 376 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 379 SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 381 UINT32_MAX, SUBTYPE_MASK}, 382 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 383 UINT32_MAX, UINT32_MAX}, 384 // Catch any unknown mach architectures so we can always use the object and 385 // symbol mach-o files 386 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 387 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 388 0x00000000u}}; 389 390 static const ArchDefinition g_macho_arch_def = { 391 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 392 g_macho_arch_entries, "mach-o"}; 393 394 //===----------------------------------------------------------------------===// 395 // A table that gets searched linearly for matches. This table is used to 396 // convert cpu type and subtypes to architecture names, and to convert 397 // architecture names to cpu types and subtypes. The ordering is important and 398 // allows the precedence to be set when the table is built. 399 static const ArchDefinitionEntry g_elf_arch_entries[] = { 400 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 401 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 402 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 403 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 404 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 405 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 406 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 407 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 408 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 410 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 412 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 414 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 416 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 417 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 418 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 419 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 420 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 422 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 423 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 424 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 425 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 426 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 427 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 428 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 429 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 430 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 431 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 432 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 433 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 434 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 435 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 436 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 438 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 440 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 442 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 443 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 444 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 445 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 446 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 447 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 448 }; 449 450 static const ArchDefinition g_elf_arch_def = { 451 eArchTypeELF, 452 llvm::array_lengthof(g_elf_arch_entries), 453 g_elf_arch_entries, 454 "elf", 455 }; 456 457 static const ArchDefinitionEntry g_coff_arch_entries[] = { 458 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 459 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 460 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 461 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 462 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 463 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 464 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 465 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 466 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 467 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 468 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 469 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 470 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 472 }; 473 474 static const ArchDefinition g_coff_arch_def = { 475 eArchTypeCOFF, 476 llvm::array_lengthof(g_coff_arch_entries), 477 g_coff_arch_entries, 478 "pe-coff", 479 }; 480 481 //===----------------------------------------------------------------------===// 482 // Table of all ArchDefinitions 483 static const ArchDefinition *g_arch_definitions[] = { 484 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 485 486 static const size_t k_num_arch_definitions = 487 llvm::array_lengthof(g_arch_definitions); 488 489 //===----------------------------------------------------------------------===// 490 // Static helper functions. 491 492 // Get the architecture definition for a given object type. 493 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 494 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 495 const ArchDefinition *def = g_arch_definitions[i]; 496 if (def->type == arch_type) 497 return def; 498 } 499 return nullptr; 500 } 501 502 // Get an architecture definition by name. 503 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 504 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 505 if (name.equals_lower(g_core_definitions[i].name)) 506 return &g_core_definitions[i]; 507 } 508 return nullptr; 509 } 510 511 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 512 if (core < llvm::array_lengthof(g_core_definitions)) 513 return &g_core_definitions[core]; 514 return nullptr; 515 } 516 517 // Get a definition entry by cpu type and subtype. 518 static const ArchDefinitionEntry * 519 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 520 if (def == nullptr) 521 return nullptr; 522 523 const ArchDefinitionEntry *entries = def->entries; 524 for (size_t i = 0; i < def->num_entries; ++i) { 525 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 526 if (entries[i].sub == (sub & entries[i].sub_mask)) 527 return &entries[i]; 528 } 529 return nullptr; 530 } 531 532 static const ArchDefinitionEntry * 533 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 534 if (def == nullptr) 535 return nullptr; 536 537 const ArchDefinitionEntry *entries = def->entries; 538 for (size_t i = 0; i < def->num_entries; ++i) { 539 if (entries[i].core == core) 540 return &entries[i]; 541 } 542 return nullptr; 543 } 544 545 //===----------------------------------------------------------------------===// 546 // Constructors and destructors. 547 548 ArchSpec::ArchSpec() {} 549 550 ArchSpec::ArchSpec(const char *triple_cstr) { 551 if (triple_cstr) 552 SetTriple(triple_cstr); 553 } 554 555 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 556 557 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 558 559 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 560 SetArchitecture(arch_type, cpu, subtype); 561 } 562 563 ArchSpec::~ArchSpec() = default; 564 565 //===----------------------------------------------------------------------===// 566 // Assignment and initialization. 567 568 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 569 if (this != &rhs) { 570 m_triple = rhs.m_triple; 571 m_core = rhs.m_core; 572 m_byte_order = rhs.m_byte_order; 573 m_distribution_id = rhs.m_distribution_id; 574 m_flags = rhs.m_flags; 575 } 576 return *this; 577 } 578 579 void ArchSpec::Clear() { 580 m_triple = llvm::Triple(); 581 m_core = kCore_invalid; 582 m_byte_order = eByteOrderInvalid; 583 m_distribution_id.Clear(); 584 m_flags = 0; 585 } 586 587 //===----------------------------------------------------------------------===// 588 // Predicates. 589 590 const char *ArchSpec::GetArchitectureName() const { 591 const CoreDefinition *core_def = FindCoreDefinition(m_core); 592 if (core_def) 593 return core_def->name; 594 return "unknown"; 595 } 596 597 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 598 599 std::string ArchSpec::GetTargetABI() const { 600 601 std::string abi; 602 603 if (IsMIPS()) { 604 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 605 case ArchSpec::eMIPSABI_N64: 606 abi = "n64"; 607 return abi; 608 case ArchSpec::eMIPSABI_N32: 609 abi = "n32"; 610 return abi; 611 case ArchSpec::eMIPSABI_O32: 612 abi = "o32"; 613 return abi; 614 default: 615 return abi; 616 } 617 } 618 return abi; 619 } 620 621 void ArchSpec::SetFlags(std::string elf_abi) { 622 623 uint32_t flag = GetFlags(); 624 if (IsMIPS()) { 625 if (elf_abi == "n64") 626 flag |= ArchSpec::eMIPSABI_N64; 627 else if (elf_abi == "n32") 628 flag |= ArchSpec::eMIPSABI_N32; 629 else if (elf_abi == "o32") 630 flag |= ArchSpec::eMIPSABI_O32; 631 } 632 SetFlags(flag); 633 } 634 635 std::string ArchSpec::GetClangTargetCPU() const { 636 std::string cpu; 637 638 if (IsMIPS()) { 639 switch (m_core) { 640 case ArchSpec::eCore_mips32: 641 case ArchSpec::eCore_mips32el: 642 cpu = "mips32"; 643 break; 644 case ArchSpec::eCore_mips32r2: 645 case ArchSpec::eCore_mips32r2el: 646 cpu = "mips32r2"; 647 break; 648 case ArchSpec::eCore_mips32r3: 649 case ArchSpec::eCore_mips32r3el: 650 cpu = "mips32r3"; 651 break; 652 case ArchSpec::eCore_mips32r5: 653 case ArchSpec::eCore_mips32r5el: 654 cpu = "mips32r5"; 655 break; 656 case ArchSpec::eCore_mips32r6: 657 case ArchSpec::eCore_mips32r6el: 658 cpu = "mips32r6"; 659 break; 660 case ArchSpec::eCore_mips64: 661 case ArchSpec::eCore_mips64el: 662 cpu = "mips64"; 663 break; 664 case ArchSpec::eCore_mips64r2: 665 case ArchSpec::eCore_mips64r2el: 666 cpu = "mips64r2"; 667 break; 668 case ArchSpec::eCore_mips64r3: 669 case ArchSpec::eCore_mips64r3el: 670 cpu = "mips64r3"; 671 break; 672 case ArchSpec::eCore_mips64r5: 673 case ArchSpec::eCore_mips64r5el: 674 cpu = "mips64r5"; 675 break; 676 case ArchSpec::eCore_mips64r6: 677 case ArchSpec::eCore_mips64r6el: 678 cpu = "mips64r6"; 679 break; 680 default: 681 break; 682 } 683 } 684 return cpu; 685 } 686 687 uint32_t ArchSpec::GetMachOCPUType() const { 688 const CoreDefinition *core_def = FindCoreDefinition(m_core); 689 if (core_def) { 690 const ArchDefinitionEntry *arch_def = 691 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 692 if (arch_def) { 693 return arch_def->cpu; 694 } 695 } 696 return LLDB_INVALID_CPUTYPE; 697 } 698 699 uint32_t ArchSpec::GetMachOCPUSubType() const { 700 const CoreDefinition *core_def = FindCoreDefinition(m_core); 701 if (core_def) { 702 const ArchDefinitionEntry *arch_def = 703 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 704 if (arch_def) { 705 return arch_def->sub; 706 } 707 } 708 return LLDB_INVALID_CPUTYPE; 709 } 710 711 uint32_t ArchSpec::GetDataByteSize() const { 712 return 1; 713 } 714 715 uint32_t ArchSpec::GetCodeByteSize() const { 716 return 1; 717 } 718 719 llvm::Triple::ArchType ArchSpec::GetMachine() const { 720 const CoreDefinition *core_def = FindCoreDefinition(m_core); 721 if (core_def) 722 return core_def->machine; 723 724 return llvm::Triple::UnknownArch; 725 } 726 727 ConstString ArchSpec::GetDistributionId() const { 728 return m_distribution_id; 729 } 730 731 void ArchSpec::SetDistributionId(const char *distribution_id) { 732 m_distribution_id.SetCString(distribution_id); 733 } 734 735 uint32_t ArchSpec::GetAddressByteSize() const { 736 const CoreDefinition *core_def = FindCoreDefinition(m_core); 737 if (core_def) { 738 if (core_def->machine == llvm::Triple::mips64 || 739 core_def->machine == llvm::Triple::mips64el) { 740 // For N32/O32 applications Address size is 4 bytes. 741 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 742 return 4; 743 } 744 return core_def->addr_byte_size; 745 } 746 return 0; 747 } 748 749 ByteOrder ArchSpec::GetDefaultEndian() const { 750 const CoreDefinition *core_def = FindCoreDefinition(m_core); 751 if (core_def) 752 return core_def->default_byte_order; 753 return eByteOrderInvalid; 754 } 755 756 bool ArchSpec::CharIsSignedByDefault() const { 757 switch (m_triple.getArch()) { 758 default: 759 return true; 760 761 case llvm::Triple::aarch64: 762 case llvm::Triple::aarch64_be: 763 case llvm::Triple::arm: 764 case llvm::Triple::armeb: 765 case llvm::Triple::thumb: 766 case llvm::Triple::thumbeb: 767 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 768 769 case llvm::Triple::ppc: 770 case llvm::Triple::ppc64: 771 return m_triple.isOSDarwin(); 772 773 case llvm::Triple::ppc64le: 774 case llvm::Triple::systemz: 775 case llvm::Triple::xcore: 776 case llvm::Triple::arc: 777 return false; 778 } 779 } 780 781 lldb::ByteOrder ArchSpec::GetByteOrder() const { 782 if (m_byte_order == eByteOrderInvalid) 783 return GetDefaultEndian(); 784 return m_byte_order; 785 } 786 787 //===----------------------------------------------------------------------===// 788 // Mutators. 789 790 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 791 m_triple = triple; 792 UpdateCore(); 793 return IsValid(); 794 } 795 796 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 797 ArchSpec &arch) { 798 // Accept "12-10" or "12.10" as cpu type/subtype 799 if (triple_str.empty()) 800 return false; 801 802 size_t pos = triple_str.find_first_of("-."); 803 if (pos == llvm::StringRef::npos) 804 return false; 805 806 llvm::StringRef cpu_str = triple_str.substr(0, pos); 807 llvm::StringRef remainder = triple_str.substr(pos + 1); 808 if (cpu_str.empty() || remainder.empty()) 809 return false; 810 811 llvm::StringRef sub_str; 812 llvm::StringRef vendor; 813 llvm::StringRef os; 814 std::tie(sub_str, remainder) = remainder.split('-'); 815 std::tie(vendor, os) = remainder.split('-'); 816 817 uint32_t cpu = 0; 818 uint32_t sub = 0; 819 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 820 return false; 821 822 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 823 return false; 824 if (!vendor.empty() && !os.empty()) { 825 arch.GetTriple().setVendorName(vendor); 826 arch.GetTriple().setOSName(os); 827 } 828 829 return true; 830 } 831 832 bool ArchSpec::SetTriple(llvm::StringRef triple) { 833 if (triple.empty()) { 834 Clear(); 835 return false; 836 } 837 838 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 839 return true; 840 841 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 842 return IsValid(); 843 } 844 845 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 846 return !normalized_triple.getArchName().empty() && 847 normalized_triple.getOSName().empty() && 848 normalized_triple.getVendorName().empty() && 849 normalized_triple.getEnvironmentName().empty(); 850 } 851 852 void ArchSpec::MergeFrom(const ArchSpec &other) { 853 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 854 GetTriple().setVendor(other.GetTriple().getVendor()); 855 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 856 GetTriple().setOS(other.GetTriple().getOS()); 857 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 858 GetTriple().setArch(other.GetTriple().getArch()); 859 860 // MachO unknown64 isn't really invalid as the debugger can still obtain 861 // information from the binary, e.g. line tables. As such, we don't update 862 // the core here. 863 if (other.GetCore() != eCore_uknownMach64) 864 UpdateCore(); 865 } 866 if (!TripleEnvironmentWasSpecified() && 867 other.TripleEnvironmentWasSpecified()) { 868 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 869 } 870 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 871 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 872 // adopt the specific arm core. 873 if (GetTriple().getArch() == llvm::Triple::arm && 874 other.GetTriple().getArch() == llvm::Triple::arm && 875 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 876 other.GetCore() != ArchSpec::eCore_arm_generic) { 877 m_core = other.GetCore(); 878 CoreUpdated(true); 879 } 880 if (GetFlags() == 0) { 881 SetFlags(other.GetFlags()); 882 } 883 } 884 885 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 886 uint32_t sub, uint32_t os) { 887 m_core = kCore_invalid; 888 bool update_triple = true; 889 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 890 if (arch_def) { 891 const ArchDefinitionEntry *arch_def_entry = 892 FindArchDefinitionEntry(arch_def, cpu, sub); 893 if (arch_def_entry) { 894 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 895 if (core_def) { 896 m_core = core_def->core; 897 update_triple = false; 898 // Always use the architecture name because it might be more 899 // descriptive than the architecture enum ("armv7" -> 900 // llvm::Triple::arm). 901 m_triple.setArchName(llvm::StringRef(core_def->name)); 902 if (arch_type == eArchTypeMachO) { 903 m_triple.setVendor(llvm::Triple::Apple); 904 905 // Don't set the OS. It could be simulator, macosx, ios, watchos, 906 // tvos, bridgeos. We could get close with the cpu type - but we 907 // can't get it right all of the time. Better to leave this unset 908 // so other sections of code will set it when they have more 909 // information. NB: don't call m_triple.setOS 910 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 911 // the ArchSpec::TripleVendorWasSpecified() method says that any 912 // OSName setting means it was specified. 913 } else if (arch_type == eArchTypeELF) { 914 switch (os) { 915 case llvm::ELF::ELFOSABI_AIX: 916 m_triple.setOS(llvm::Triple::OSType::AIX); 917 break; 918 case llvm::ELF::ELFOSABI_FREEBSD: 919 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 920 break; 921 case llvm::ELF::ELFOSABI_GNU: 922 m_triple.setOS(llvm::Triple::OSType::Linux); 923 break; 924 case llvm::ELF::ELFOSABI_NETBSD: 925 m_triple.setOS(llvm::Triple::OSType::NetBSD); 926 break; 927 case llvm::ELF::ELFOSABI_OPENBSD: 928 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 929 break; 930 case llvm::ELF::ELFOSABI_SOLARIS: 931 m_triple.setOS(llvm::Triple::OSType::Solaris); 932 break; 933 } 934 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 935 m_triple.setVendor(llvm::Triple::PC); 936 m_triple.setOS(llvm::Triple::Win32); 937 } else { 938 m_triple.setVendor(llvm::Triple::UnknownVendor); 939 m_triple.setOS(llvm::Triple::UnknownOS); 940 } 941 // Fall back onto setting the machine type if the arch by name 942 // failed... 943 if (m_triple.getArch() == llvm::Triple::UnknownArch) 944 m_triple.setArch(core_def->machine); 945 } 946 } else { 947 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 948 LLDB_LOGF(log, 949 "Unable to find a core definition for cpu 0x%" PRIx32 950 " sub %" PRId32, 951 cpu, sub); 952 } 953 } 954 CoreUpdated(update_triple); 955 return IsValid(); 956 } 957 958 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 959 const CoreDefinition *core_def = FindCoreDefinition(m_core); 960 if (core_def) 961 return core_def->min_opcode_byte_size; 962 return 0; 963 } 964 965 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 966 const CoreDefinition *core_def = FindCoreDefinition(m_core); 967 if (core_def) 968 return core_def->max_opcode_byte_size; 969 return 0; 970 } 971 972 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 973 return IsEqualTo(rhs, true); 974 } 975 976 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 977 return IsEqualTo(rhs, false); 978 } 979 980 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 981 llvm::Triple::EnvironmentType rhs) { 982 if (lhs == rhs) 983 return true; 984 985 // If any of the environment is unknown then they are compatible 986 if (lhs == llvm::Triple::UnknownEnvironment || 987 rhs == llvm::Triple::UnknownEnvironment) 988 return true; 989 990 // If one of the environment is Android and the other one is EABI then they 991 // are considered to be compatible. This is required as a workaround for 992 // shared libraries compiled for Android without the NOTE section indicating 993 // that they are using the Android ABI. 994 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 995 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 996 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 997 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 998 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 999 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1000 return true; 1001 1002 return false; 1003 } 1004 1005 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1006 // explicitly ignoring m_distribution_id in this method. 1007 1008 if (GetByteOrder() != rhs.GetByteOrder()) 1009 return false; 1010 1011 const ArchSpec::Core lhs_core = GetCore(); 1012 const ArchSpec::Core rhs_core = rhs.GetCore(); 1013 1014 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1015 1016 if (core_match) { 1017 const llvm::Triple &lhs_triple = GetTriple(); 1018 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1019 1020 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1021 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1022 if (lhs_triple_vendor != rhs_triple_vendor) { 1023 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1024 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1025 // Both architectures had the vendor specified, so if they aren't equal 1026 // then we return false 1027 if (rhs_vendor_specified && lhs_vendor_specified) 1028 return false; 1029 1030 // Only fail if both vendor types are not unknown 1031 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1032 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1033 return false; 1034 } 1035 1036 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1037 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1038 if (lhs_triple_os != rhs_triple_os) { 1039 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1040 const bool lhs_os_specified = TripleOSWasSpecified(); 1041 // Both architectures had the OS specified, so if they aren't equal then 1042 // we return false 1043 if (rhs_os_specified && lhs_os_specified) 1044 return false; 1045 1046 // Only fail if both os types are not unknown 1047 if (lhs_triple_os != llvm::Triple::UnknownOS && 1048 rhs_triple_os != llvm::Triple::UnknownOS) 1049 return false; 1050 } 1051 1052 const llvm::Triple::EnvironmentType lhs_triple_env = 1053 lhs_triple.getEnvironment(); 1054 const llvm::Triple::EnvironmentType rhs_triple_env = 1055 rhs_triple.getEnvironment(); 1056 1057 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1058 } 1059 return false; 1060 } 1061 1062 void ArchSpec::UpdateCore() { 1063 llvm::StringRef arch_name(m_triple.getArchName()); 1064 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1065 if (core_def) { 1066 m_core = core_def->core; 1067 // Set the byte order to the default byte order for an architecture. This 1068 // can be modified if needed for cases when cores handle both big and 1069 // little endian 1070 m_byte_order = core_def->default_byte_order; 1071 } else { 1072 Clear(); 1073 } 1074 } 1075 1076 //===----------------------------------------------------------------------===// 1077 // Helper methods. 1078 1079 void ArchSpec::CoreUpdated(bool update_triple) { 1080 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1081 if (core_def) { 1082 if (update_triple) 1083 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1084 m_byte_order = core_def->default_byte_order; 1085 } else { 1086 if (update_triple) 1087 m_triple = llvm::Triple(); 1088 m_byte_order = eByteOrderInvalid; 1089 } 1090 } 1091 1092 //===----------------------------------------------------------------------===// 1093 // Operators. 1094 1095 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1096 bool try_inverse, bool enforce_exact_match) { 1097 if (core1 == core2) 1098 return true; 1099 1100 switch (core1) { 1101 case ArchSpec::kCore_any: 1102 return true; 1103 1104 case ArchSpec::eCore_arm_generic: 1105 if (enforce_exact_match) 1106 break; 1107 LLVM_FALLTHROUGH; 1108 case ArchSpec::kCore_arm_any: 1109 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1110 return true; 1111 if (core2 >= ArchSpec::kCore_thumb_first && 1112 core2 <= ArchSpec::kCore_thumb_last) 1113 return true; 1114 if (core2 == ArchSpec::kCore_arm_any) 1115 return true; 1116 break; 1117 1118 case ArchSpec::kCore_x86_32_any: 1119 if ((core2 >= ArchSpec::kCore_x86_32_first && 1120 core2 <= ArchSpec::kCore_x86_32_last) || 1121 (core2 == ArchSpec::kCore_x86_32_any)) 1122 return true; 1123 break; 1124 1125 case ArchSpec::kCore_x86_64_any: 1126 if ((core2 >= ArchSpec::kCore_x86_64_first && 1127 core2 <= ArchSpec::kCore_x86_64_last) || 1128 (core2 == ArchSpec::kCore_x86_64_any)) 1129 return true; 1130 break; 1131 1132 case ArchSpec::kCore_ppc_any: 1133 if ((core2 >= ArchSpec::kCore_ppc_first && 1134 core2 <= ArchSpec::kCore_ppc_last) || 1135 (core2 == ArchSpec::kCore_ppc_any)) 1136 return true; 1137 break; 1138 1139 case ArchSpec::kCore_ppc64_any: 1140 if ((core2 >= ArchSpec::kCore_ppc64_first && 1141 core2 <= ArchSpec::kCore_ppc64_last) || 1142 (core2 == ArchSpec::kCore_ppc64_any)) 1143 return true; 1144 break; 1145 1146 case ArchSpec::eCore_arm_armv6m: 1147 if (!enforce_exact_match) { 1148 if (core2 == ArchSpec::eCore_arm_generic) 1149 return true; 1150 try_inverse = false; 1151 if (core2 == ArchSpec::eCore_arm_armv7) 1152 return true; 1153 if (core2 == ArchSpec::eCore_arm_armv6m) 1154 return true; 1155 } 1156 break; 1157 1158 case ArchSpec::kCore_hexagon_any: 1159 if ((core2 >= ArchSpec::kCore_hexagon_first && 1160 core2 <= ArchSpec::kCore_hexagon_last) || 1161 (core2 == ArchSpec::kCore_hexagon_any)) 1162 return true; 1163 break; 1164 1165 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1166 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1167 // ARMv7E-M - armv7em 1168 case ArchSpec::eCore_arm_armv7em: 1169 if (!enforce_exact_match) { 1170 if (core2 == ArchSpec::eCore_arm_generic) 1171 return true; 1172 if (core2 == ArchSpec::eCore_arm_armv7m) 1173 return true; 1174 if (core2 == ArchSpec::eCore_arm_armv6m) 1175 return true; 1176 if (core2 == ArchSpec::eCore_arm_armv7) 1177 return true; 1178 try_inverse = true; 1179 } 1180 break; 1181 1182 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1183 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1184 // ARMv7E-M - armv7em 1185 case ArchSpec::eCore_arm_armv7m: 1186 if (!enforce_exact_match) { 1187 if (core2 == ArchSpec::eCore_arm_generic) 1188 return true; 1189 if (core2 == ArchSpec::eCore_arm_armv6m) 1190 return true; 1191 if (core2 == ArchSpec::eCore_arm_armv7) 1192 return true; 1193 if (core2 == ArchSpec::eCore_arm_armv7em) 1194 return true; 1195 try_inverse = true; 1196 } 1197 break; 1198 1199 case ArchSpec::eCore_arm_armv7f: 1200 case ArchSpec::eCore_arm_armv7k: 1201 case ArchSpec::eCore_arm_armv7s: 1202 if (!enforce_exact_match) { 1203 if (core2 == ArchSpec::eCore_arm_generic) 1204 return true; 1205 if (core2 == ArchSpec::eCore_arm_armv7) 1206 return true; 1207 try_inverse = false; 1208 } 1209 break; 1210 1211 case ArchSpec::eCore_x86_64_x86_64h: 1212 if (!enforce_exact_match) { 1213 try_inverse = false; 1214 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1215 return true; 1216 } 1217 break; 1218 1219 case ArchSpec::eCore_arm_armv8: 1220 if (!enforce_exact_match) { 1221 if (core2 == ArchSpec::eCore_arm_arm64) 1222 return true; 1223 if (core2 == ArchSpec::eCore_arm_aarch64) 1224 return true; 1225 try_inverse = false; 1226 } 1227 break; 1228 1229 case ArchSpec::eCore_arm_aarch64: 1230 if (!enforce_exact_match) { 1231 if (core2 == ArchSpec::eCore_arm_arm64) 1232 return true; 1233 if (core2 == ArchSpec::eCore_arm_armv8) 1234 return true; 1235 try_inverse = false; 1236 } 1237 break; 1238 1239 case ArchSpec::eCore_arm_arm64: 1240 if (!enforce_exact_match) { 1241 if (core2 == ArchSpec::eCore_arm_aarch64) 1242 return true; 1243 if (core2 == ArchSpec::eCore_arm_armv8) 1244 return true; 1245 try_inverse = false; 1246 } 1247 break; 1248 1249 case ArchSpec::eCore_mips32: 1250 if (!enforce_exact_match) { 1251 if (core2 >= ArchSpec::kCore_mips32_first && 1252 core2 <= ArchSpec::kCore_mips32_last) 1253 return true; 1254 try_inverse = false; 1255 } 1256 break; 1257 1258 case ArchSpec::eCore_mips32el: 1259 if (!enforce_exact_match) { 1260 if (core2 >= ArchSpec::kCore_mips32el_first && 1261 core2 <= ArchSpec::kCore_mips32el_last) 1262 return true; 1263 try_inverse = true; 1264 } 1265 break; 1266 1267 case ArchSpec::eCore_mips64: 1268 if (!enforce_exact_match) { 1269 if (core2 >= ArchSpec::kCore_mips32_first && 1270 core2 <= ArchSpec::kCore_mips32_last) 1271 return true; 1272 if (core2 >= ArchSpec::kCore_mips64_first && 1273 core2 <= ArchSpec::kCore_mips64_last) 1274 return true; 1275 try_inverse = false; 1276 } 1277 break; 1278 1279 case ArchSpec::eCore_mips64el: 1280 if (!enforce_exact_match) { 1281 if (core2 >= ArchSpec::kCore_mips32el_first && 1282 core2 <= ArchSpec::kCore_mips32el_last) 1283 return true; 1284 if (core2 >= ArchSpec::kCore_mips64el_first && 1285 core2 <= ArchSpec::kCore_mips64el_last) 1286 return true; 1287 try_inverse = false; 1288 } 1289 break; 1290 1291 case ArchSpec::eCore_mips64r2: 1292 case ArchSpec::eCore_mips64r3: 1293 case ArchSpec::eCore_mips64r5: 1294 if (!enforce_exact_match) { 1295 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1296 return true; 1297 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1298 return true; 1299 try_inverse = false; 1300 } 1301 break; 1302 1303 case ArchSpec::eCore_mips64r2el: 1304 case ArchSpec::eCore_mips64r3el: 1305 case ArchSpec::eCore_mips64r5el: 1306 if (!enforce_exact_match) { 1307 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1308 return true; 1309 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1310 return true; 1311 try_inverse = false; 1312 } 1313 break; 1314 1315 case ArchSpec::eCore_mips32r2: 1316 case ArchSpec::eCore_mips32r3: 1317 case ArchSpec::eCore_mips32r5: 1318 if (!enforce_exact_match) { 1319 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1320 return true; 1321 } 1322 break; 1323 1324 case ArchSpec::eCore_mips32r2el: 1325 case ArchSpec::eCore_mips32r3el: 1326 case ArchSpec::eCore_mips32r5el: 1327 if (!enforce_exact_match) { 1328 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1329 return true; 1330 } 1331 break; 1332 1333 case ArchSpec::eCore_mips32r6: 1334 if (!enforce_exact_match) { 1335 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1336 return true; 1337 } 1338 break; 1339 1340 case ArchSpec::eCore_mips32r6el: 1341 if (!enforce_exact_match) { 1342 if (core2 == ArchSpec::eCore_mips32el || 1343 core2 == ArchSpec::eCore_mips32r6el) 1344 return true; 1345 } 1346 break; 1347 1348 case ArchSpec::eCore_mips64r6: 1349 if (!enforce_exact_match) { 1350 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1351 return true; 1352 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1353 return true; 1354 } 1355 break; 1356 1357 case ArchSpec::eCore_mips64r6el: 1358 if (!enforce_exact_match) { 1359 if (core2 == ArchSpec::eCore_mips32el || 1360 core2 == ArchSpec::eCore_mips32r6el) 1361 return true; 1362 if (core2 == ArchSpec::eCore_mips64el || 1363 core2 == ArchSpec::eCore_mips64r6el) 1364 return true; 1365 } 1366 break; 1367 1368 default: 1369 break; 1370 } 1371 if (try_inverse) 1372 return cores_match(core2, core1, false, enforce_exact_match); 1373 return false; 1374 } 1375 1376 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1377 const ArchSpec::Core lhs_core = lhs.GetCore(); 1378 const ArchSpec::Core rhs_core = rhs.GetCore(); 1379 return lhs_core < rhs_core; 1380 } 1381 1382 1383 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1384 return lhs.GetCore() == rhs.GetCore(); 1385 } 1386 1387 bool ArchSpec::IsFullySpecifiedTriple() const { 1388 const auto &user_specified_triple = GetTriple(); 1389 1390 bool user_triple_fully_specified = false; 1391 1392 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1393 TripleOSWasSpecified()) { 1394 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1395 TripleVendorWasSpecified()) { 1396 const unsigned unspecified = 0; 1397 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1398 user_triple_fully_specified = true; 1399 } 1400 } 1401 } 1402 1403 return user_triple_fully_specified; 1404 } 1405 1406 void ArchSpec::PiecewiseTripleCompare( 1407 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1408 bool &os_different, bool &os_version_different, bool &env_different) const { 1409 const llvm::Triple &me(GetTriple()); 1410 const llvm::Triple &them(other.GetTriple()); 1411 1412 arch_different = (me.getArch() != them.getArch()); 1413 1414 vendor_different = (me.getVendor() != them.getVendor()); 1415 1416 os_different = (me.getOS() != them.getOS()); 1417 1418 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1419 1420 env_different = (me.getEnvironment() != them.getEnvironment()); 1421 } 1422 1423 bool ArchSpec::IsAlwaysThumbInstructions() const { 1424 std::string Status; 1425 if (GetTriple().getArch() == llvm::Triple::arm || 1426 GetTriple().getArch() == llvm::Triple::thumb) { 1427 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1428 // 1429 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1430 // execute thumb instructions. We map the cores to arch names like this: 1431 // 1432 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1433 // Cortex-M7: armv7em 1434 1435 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1436 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1437 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1438 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1439 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1440 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1441 return true; 1442 } 1443 } 1444 return false; 1445 } 1446 1447 void ArchSpec::DumpTriple(Stream &s) const { 1448 const llvm::Triple &triple = GetTriple(); 1449 llvm::StringRef arch_str = triple.getArchName(); 1450 llvm::StringRef vendor_str = triple.getVendorName(); 1451 llvm::StringRef os_str = triple.getOSName(); 1452 llvm::StringRef environ_str = triple.getEnvironmentName(); 1453 1454 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1455 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1456 os_str.empty() ? "*" : os_str.str().c_str()); 1457 1458 if (!environ_str.empty()) 1459 s.Printf("-%s", environ_str.str().c_str()); 1460 } 1461