1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 105 ArchSpec::eCore_arm_aarch64, "aarch64"}, 106 107 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 108 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 109 "mips"}, 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 111 "mipsr2"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 113 "mipsr3"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 115 "mipsr5"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 117 "mipsr6"}, 118 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 119 "mipsel"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 121 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 128 129 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 130 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 131 "mips64"}, 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 133 "mips64r2"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 135 "mips64r3"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 137 "mips64r5"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 139 "mips64r6"}, 140 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 141 ArchSpec::eCore_mips64el, "mips64el"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 150 151 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 152 "powerpc"}, 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 154 "ppc601"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 156 "ppc602"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 158 "ppc603"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 160 "ppc603e"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 162 "ppc603ev"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 164 "ppc604"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 166 "ppc604e"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 168 "ppc620"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 170 "ppc750"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 172 "ppc7400"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 174 "ppc7450"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 176 "ppc970"}, 177 178 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 179 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 180 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 181 "powerpc64"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 183 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 184 185 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 186 ArchSpec::eCore_s390x_generic, "s390x"}, 187 188 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 189 ArchSpec::eCore_sparc_generic, "sparc"}, 190 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 191 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 192 193 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 194 "i386"}, 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 196 "i486"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 198 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 200 "i686"}, 201 202 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 203 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 206 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 207 ArchSpec::eCore_hexagon_generic, "hexagon"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 212 213 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 214 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 215 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 217 218 {eByteOrderBig, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba3, 219 "kalimba3"}, 220 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba4, 221 "kalimba4"}, 222 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba5, 223 "kalimba5"}}; 224 225 // Ensure that we have an entry in the g_core_definitions for each core. If you 226 // comment out an entry above, you will need to comment out the corresponding 227 // ArchSpec::Core enumeration. 228 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 229 ArchSpec::kNumCores, 230 "make sure we have one core definition for each core"); 231 232 struct ArchDefinitionEntry { 233 ArchSpec::Core core; 234 uint32_t cpu; 235 uint32_t sub; 236 uint32_t cpu_mask; 237 uint32_t sub_mask; 238 }; 239 240 struct ArchDefinition { 241 ArchitectureType type; 242 size_t num_entries; 243 const ArchDefinitionEntry *entries; 244 const char *name; 245 }; 246 247 void ArchSpec::ListSupportedArchNames(StringList &list) { 248 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 249 list.AppendString(g_core_definitions[i].name); 250 } 251 252 size_t ArchSpec::AutoComplete(CompletionRequest &request) { 253 if (!request.GetCursorArgumentPrefix().empty()) { 254 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 255 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, 256 request.GetCursorArgumentPrefix())) 257 request.AddCompletion(g_core_definitions[i].name); 258 } 259 } else { 260 StringList matches; 261 ListSupportedArchNames(matches); 262 request.AddCompletions(matches); 263 } 264 return request.GetNumberOfMatches(); 265 } 266 267 #define CPU_ANY (UINT32_MAX) 268 269 //===----------------------------------------------------------------------===// 270 // A table that gets searched linearly for matches. This table is used to 271 // convert cpu type and subtypes to architecture names, and to convert 272 // architecture names to cpu types and subtypes. The ordering is important and 273 // allows the precedence to be set when the table is built. 274 #define SUBTYPE_MASK 0x00FFFFFFu 275 276 static const ArchDefinitionEntry g_macho_arch_entries[] = { 277 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 278 UINT32_MAX, UINT32_MAX}, 279 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 302 SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 306 SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 308 SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 310 SUBTYPE_MASK}, 311 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 312 SUBTYPE_MASK}, 313 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 314 SUBTYPE_MASK}, 315 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 316 UINT32_MAX, SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 336 SUBTYPE_MASK}, 337 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 340 SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 342 UINT32_MAX, UINT32_MAX}, 343 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 364 SUBTYPE_MASK}, 365 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 366 SUBTYPE_MASK}, 367 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 368 SUBTYPE_MASK}, 369 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 370 UINT32_MAX, SUBTYPE_MASK}, 371 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 372 UINT32_MAX, SUBTYPE_MASK}, 373 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 374 UINT32_MAX, SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 376 SUBTYPE_MASK}, 377 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 378 SUBTYPE_MASK}, 379 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 380 UINT32_MAX, SUBTYPE_MASK}, 381 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 382 UINT32_MAX, UINT32_MAX}, 383 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 384 SUBTYPE_MASK}, 385 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 386 SUBTYPE_MASK}, 387 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 388 UINT32_MAX, SUBTYPE_MASK}, 389 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 390 UINT32_MAX, UINT32_MAX}, 391 // Catch any unknown mach architectures so we can always use the object and 392 // symbol mach-o files 393 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 394 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 395 0x00000000u}}; 396 397 static const ArchDefinition g_macho_arch_def = { 398 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 399 g_macho_arch_entries, "mach-o"}; 400 401 //===----------------------------------------------------------------------===// 402 // A table that gets searched linearly for matches. This table is used to 403 // convert cpu type and subtypes to architecture names, and to convert 404 // architecture names to cpu types and subtypes. The ordering is important and 405 // allows the precedence to be set when the table is built. 406 static const ArchDefinitionEntry g_elf_arch_entries[] = { 407 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 409 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 411 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 413 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 415 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 416 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 417 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 419 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 420 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 421 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 422 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 423 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 424 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 425 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 426 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 427 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 428 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 429 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 430 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 431 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 433 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 435 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 436 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 437 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 438 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 439 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 440 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 441 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 442 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 443 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 444 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 445 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 446 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 447 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 448 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 449 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 450 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 451 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 452 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 453 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 454 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 455 {ArchSpec::eCore_kalimba3, llvm::ELF::EM_CSR_KALIMBA, 456 llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 457 {ArchSpec::eCore_kalimba4, llvm::ELF::EM_CSR_KALIMBA, 458 llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 459 {ArchSpec::eCore_kalimba5, llvm::ELF::EM_CSR_KALIMBA, 460 llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu} // KALIMBA 461 }; 462 463 static const ArchDefinition g_elf_arch_def = { 464 eArchTypeELF, 465 llvm::array_lengthof(g_elf_arch_entries), 466 g_elf_arch_entries, 467 "elf", 468 }; 469 470 static const ArchDefinitionEntry g_coff_arch_entries[] = { 471 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 472 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 473 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 474 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 475 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 476 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 477 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 478 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 479 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 480 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 481 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 482 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 483 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 484 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 485 }; 486 487 static const ArchDefinition g_coff_arch_def = { 488 eArchTypeCOFF, 489 llvm::array_lengthof(g_coff_arch_entries), 490 g_coff_arch_entries, 491 "pe-coff", 492 }; 493 494 //===----------------------------------------------------------------------===// 495 // Table of all ArchDefinitions 496 static const ArchDefinition *g_arch_definitions[] = { 497 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 498 499 static const size_t k_num_arch_definitions = 500 llvm::array_lengthof(g_arch_definitions); 501 502 //===----------------------------------------------------------------------===// 503 // Static helper functions. 504 505 // Get the architecture definition for a given object type. 506 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 507 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 508 const ArchDefinition *def = g_arch_definitions[i]; 509 if (def->type == arch_type) 510 return def; 511 } 512 return nullptr; 513 } 514 515 // Get an architecture definition by name. 516 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 517 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 518 if (name.equals_lower(g_core_definitions[i].name)) 519 return &g_core_definitions[i]; 520 } 521 return nullptr; 522 } 523 524 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 525 if (core < llvm::array_lengthof(g_core_definitions)) 526 return &g_core_definitions[core]; 527 return nullptr; 528 } 529 530 // Get a definition entry by cpu type and subtype. 531 static const ArchDefinitionEntry * 532 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 533 if (def == nullptr) 534 return nullptr; 535 536 const ArchDefinitionEntry *entries = def->entries; 537 for (size_t i = 0; i < def->num_entries; ++i) { 538 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 539 if (entries[i].sub == (sub & entries[i].sub_mask)) 540 return &entries[i]; 541 } 542 return nullptr; 543 } 544 545 static const ArchDefinitionEntry * 546 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 547 if (def == nullptr) 548 return nullptr; 549 550 const ArchDefinitionEntry *entries = def->entries; 551 for (size_t i = 0; i < def->num_entries; ++i) { 552 if (entries[i].core == core) 553 return &entries[i]; 554 } 555 return nullptr; 556 } 557 558 //===----------------------------------------------------------------------===// 559 // Constructors and destructors. 560 561 ArchSpec::ArchSpec() {} 562 563 ArchSpec::ArchSpec(const char *triple_cstr) { 564 if (triple_cstr) 565 SetTriple(triple_cstr); 566 } 567 568 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 569 570 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 571 572 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 573 SetArchitecture(arch_type, cpu, subtype); 574 } 575 576 ArchSpec::~ArchSpec() = default; 577 578 //===----------------------------------------------------------------------===// 579 // Assignment and initialization. 580 581 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 582 if (this != &rhs) { 583 m_triple = rhs.m_triple; 584 m_core = rhs.m_core; 585 m_byte_order = rhs.m_byte_order; 586 m_distribution_id = rhs.m_distribution_id; 587 m_flags = rhs.m_flags; 588 } 589 return *this; 590 } 591 592 void ArchSpec::Clear() { 593 m_triple = llvm::Triple(); 594 m_core = kCore_invalid; 595 m_byte_order = eByteOrderInvalid; 596 m_distribution_id.Clear(); 597 m_flags = 0; 598 } 599 600 //===----------------------------------------------------------------------===// 601 // Predicates. 602 603 const char *ArchSpec::GetArchitectureName() const { 604 const CoreDefinition *core_def = FindCoreDefinition(m_core); 605 if (core_def) 606 return core_def->name; 607 return "unknown"; 608 } 609 610 bool ArchSpec::IsMIPS() const { 611 const llvm::Triple::ArchType machine = GetMachine(); 612 return machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 613 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el; 614 } 615 616 std::string ArchSpec::GetTargetABI() const { 617 618 std::string abi; 619 620 if (IsMIPS()) { 621 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 622 case ArchSpec::eMIPSABI_N64: 623 abi = "n64"; 624 return abi; 625 case ArchSpec::eMIPSABI_N32: 626 abi = "n32"; 627 return abi; 628 case ArchSpec::eMIPSABI_O32: 629 abi = "o32"; 630 return abi; 631 default: 632 return abi; 633 } 634 } 635 return abi; 636 } 637 638 void ArchSpec::SetFlags(std::string elf_abi) { 639 640 uint32_t flag = GetFlags(); 641 if (IsMIPS()) { 642 if (elf_abi == "n64") 643 flag |= ArchSpec::eMIPSABI_N64; 644 else if (elf_abi == "n32") 645 flag |= ArchSpec::eMIPSABI_N32; 646 else if (elf_abi == "o32") 647 flag |= ArchSpec::eMIPSABI_O32; 648 } 649 SetFlags(flag); 650 } 651 652 std::string ArchSpec::GetClangTargetCPU() const { 653 std::string cpu; 654 const llvm::Triple::ArchType machine = GetMachine(); 655 656 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 657 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) { 658 switch (m_core) { 659 case ArchSpec::eCore_mips32: 660 case ArchSpec::eCore_mips32el: 661 cpu = "mips32"; 662 break; 663 case ArchSpec::eCore_mips32r2: 664 case ArchSpec::eCore_mips32r2el: 665 cpu = "mips32r2"; 666 break; 667 case ArchSpec::eCore_mips32r3: 668 case ArchSpec::eCore_mips32r3el: 669 cpu = "mips32r3"; 670 break; 671 case ArchSpec::eCore_mips32r5: 672 case ArchSpec::eCore_mips32r5el: 673 cpu = "mips32r5"; 674 break; 675 case ArchSpec::eCore_mips32r6: 676 case ArchSpec::eCore_mips32r6el: 677 cpu = "mips32r6"; 678 break; 679 case ArchSpec::eCore_mips64: 680 case ArchSpec::eCore_mips64el: 681 cpu = "mips64"; 682 break; 683 case ArchSpec::eCore_mips64r2: 684 case ArchSpec::eCore_mips64r2el: 685 cpu = "mips64r2"; 686 break; 687 case ArchSpec::eCore_mips64r3: 688 case ArchSpec::eCore_mips64r3el: 689 cpu = "mips64r3"; 690 break; 691 case ArchSpec::eCore_mips64r5: 692 case ArchSpec::eCore_mips64r5el: 693 cpu = "mips64r5"; 694 break; 695 case ArchSpec::eCore_mips64r6: 696 case ArchSpec::eCore_mips64r6el: 697 cpu = "mips64r6"; 698 break; 699 default: 700 break; 701 } 702 } 703 return cpu; 704 } 705 706 uint32_t ArchSpec::GetMachOCPUType() const { 707 const CoreDefinition *core_def = FindCoreDefinition(m_core); 708 if (core_def) { 709 const ArchDefinitionEntry *arch_def = 710 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 711 if (arch_def) { 712 return arch_def->cpu; 713 } 714 } 715 return LLDB_INVALID_CPUTYPE; 716 } 717 718 uint32_t ArchSpec::GetMachOCPUSubType() const { 719 const CoreDefinition *core_def = FindCoreDefinition(m_core); 720 if (core_def) { 721 const ArchDefinitionEntry *arch_def = 722 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 723 if (arch_def) { 724 return arch_def->sub; 725 } 726 } 727 return LLDB_INVALID_CPUTYPE; 728 } 729 730 uint32_t ArchSpec::GetDataByteSize() const { 731 switch (m_core) { 732 case eCore_kalimba3: 733 return 4; 734 case eCore_kalimba4: 735 return 1; 736 case eCore_kalimba5: 737 return 4; 738 default: 739 return 1; 740 } 741 return 1; 742 } 743 744 uint32_t ArchSpec::GetCodeByteSize() const { 745 switch (m_core) { 746 case eCore_kalimba3: 747 return 4; 748 case eCore_kalimba4: 749 return 1; 750 case eCore_kalimba5: 751 return 1; 752 default: 753 return 1; 754 } 755 return 1; 756 } 757 758 llvm::Triple::ArchType ArchSpec::GetMachine() const { 759 const CoreDefinition *core_def = FindCoreDefinition(m_core); 760 if (core_def) 761 return core_def->machine; 762 763 return llvm::Triple::UnknownArch; 764 } 765 766 const ConstString &ArchSpec::GetDistributionId() const { 767 return m_distribution_id; 768 } 769 770 void ArchSpec::SetDistributionId(const char *distribution_id) { 771 m_distribution_id.SetCString(distribution_id); 772 } 773 774 uint32_t ArchSpec::GetAddressByteSize() const { 775 const CoreDefinition *core_def = FindCoreDefinition(m_core); 776 if (core_def) { 777 if (core_def->machine == llvm::Triple::mips64 || 778 core_def->machine == llvm::Triple::mips64el) { 779 // For N32/O32 applications Address size is 4 bytes. 780 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 781 return 4; 782 } 783 return core_def->addr_byte_size; 784 } 785 return 0; 786 } 787 788 ByteOrder ArchSpec::GetDefaultEndian() const { 789 const CoreDefinition *core_def = FindCoreDefinition(m_core); 790 if (core_def) 791 return core_def->default_byte_order; 792 return eByteOrderInvalid; 793 } 794 795 bool ArchSpec::CharIsSignedByDefault() const { 796 switch (m_triple.getArch()) { 797 default: 798 return true; 799 800 case llvm::Triple::aarch64: 801 case llvm::Triple::aarch64_be: 802 case llvm::Triple::arm: 803 case llvm::Triple::armeb: 804 case llvm::Triple::thumb: 805 case llvm::Triple::thumbeb: 806 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 807 808 case llvm::Triple::ppc: 809 case llvm::Triple::ppc64: 810 return m_triple.isOSDarwin(); 811 812 case llvm::Triple::ppc64le: 813 case llvm::Triple::systemz: 814 case llvm::Triple::xcore: 815 case llvm::Triple::arc: 816 return false; 817 } 818 } 819 820 lldb::ByteOrder ArchSpec::GetByteOrder() const { 821 if (m_byte_order == eByteOrderInvalid) 822 return GetDefaultEndian(); 823 return m_byte_order; 824 } 825 826 //===----------------------------------------------------------------------===// 827 // Mutators. 828 829 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 830 m_triple = triple; 831 UpdateCore(); 832 return IsValid(); 833 } 834 835 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 836 ArchSpec &arch) { 837 // Accept "12-10" or "12.10" as cpu type/subtype 838 if (triple_str.empty()) 839 return false; 840 841 size_t pos = triple_str.find_first_of("-."); 842 if (pos == llvm::StringRef::npos) 843 return false; 844 845 llvm::StringRef cpu_str = triple_str.substr(0, pos); 846 llvm::StringRef remainder = triple_str.substr(pos + 1); 847 if (cpu_str.empty() || remainder.empty()) 848 return false; 849 850 llvm::StringRef sub_str; 851 llvm::StringRef vendor; 852 llvm::StringRef os; 853 std::tie(sub_str, remainder) = remainder.split('-'); 854 std::tie(vendor, os) = remainder.split('-'); 855 856 uint32_t cpu = 0; 857 uint32_t sub = 0; 858 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 859 return false; 860 861 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 862 return false; 863 if (!vendor.empty() && !os.empty()) { 864 arch.GetTriple().setVendorName(vendor); 865 arch.GetTriple().setOSName(os); 866 } 867 868 return true; 869 } 870 871 bool ArchSpec::SetTriple(llvm::StringRef triple) { 872 if (triple.empty()) { 873 Clear(); 874 return false; 875 } 876 877 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 878 return true; 879 880 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 881 return IsValid(); 882 } 883 884 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 885 return !normalized_triple.getArchName().empty() && 886 normalized_triple.getOSName().empty() && 887 normalized_triple.getVendorName().empty() && 888 normalized_triple.getEnvironmentName().empty(); 889 } 890 891 void ArchSpec::MergeFrom(const ArchSpec &other) { 892 if (TripleVendorIsUnspecifiedUnknown() && 893 !other.TripleVendorIsUnspecifiedUnknown()) 894 GetTriple().setVendor(other.GetTriple().getVendor()); 895 if (TripleOSIsUnspecifiedUnknown() && !other.TripleOSIsUnspecifiedUnknown()) 896 GetTriple().setOS(other.GetTriple().getOS()); 897 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 898 GetTriple().setArch(other.GetTriple().getArch()); 899 900 // MachO unknown64 isn't really invalid as the debugger can still obtain 901 // information from the binary, e.g. line tables. As such, we don't update 902 // the core here. 903 if (other.GetCore() != eCore_uknownMach64) 904 UpdateCore(); 905 } 906 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 907 !TripleVendorWasSpecified()) { 908 if (other.TripleVendorWasSpecified()) 909 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 910 } 911 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 912 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 913 // adopt the specific arm core. 914 if (GetTriple().getArch() == llvm::Triple::arm && 915 other.GetTriple().getArch() == llvm::Triple::arm && 916 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 917 other.GetCore() != ArchSpec::eCore_arm_generic) { 918 m_core = other.GetCore(); 919 CoreUpdated(true); 920 } 921 if (GetFlags() == 0) { 922 SetFlags(other.GetFlags()); 923 } 924 } 925 926 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 927 uint32_t sub, uint32_t os) { 928 m_core = kCore_invalid; 929 bool update_triple = true; 930 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 931 if (arch_def) { 932 const ArchDefinitionEntry *arch_def_entry = 933 FindArchDefinitionEntry(arch_def, cpu, sub); 934 if (arch_def_entry) { 935 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 936 if (core_def) { 937 m_core = core_def->core; 938 update_triple = false; 939 // Always use the architecture name because it might be more 940 // descriptive than the architecture enum ("armv7" -> 941 // llvm::Triple::arm). 942 m_triple.setArchName(llvm::StringRef(core_def->name)); 943 if (arch_type == eArchTypeMachO) { 944 m_triple.setVendor(llvm::Triple::Apple); 945 946 // Don't set the OS. It could be simulator, macosx, ios, watchos, 947 // tvos, bridgeos. We could get close with the cpu type - but we 948 // can't get it right all of the time. Better to leave this unset 949 // so other sections of code will set it when they have more 950 // information. NB: don't call m_triple.setOS (llvm::Triple::UnknownOS). 951 // That sets the OSName to "unknown" and the 952 // ArchSpec::TripleVendorWasSpecified() method says that any OSName 953 // setting means it was specified. 954 } else if (arch_type == eArchTypeELF) { 955 switch (os) { 956 case llvm::ELF::ELFOSABI_AIX: 957 m_triple.setOS(llvm::Triple::OSType::AIX); 958 break; 959 case llvm::ELF::ELFOSABI_FREEBSD: 960 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 961 break; 962 case llvm::ELF::ELFOSABI_GNU: 963 m_triple.setOS(llvm::Triple::OSType::Linux); 964 break; 965 case llvm::ELF::ELFOSABI_NETBSD: 966 m_triple.setOS(llvm::Triple::OSType::NetBSD); 967 break; 968 case llvm::ELF::ELFOSABI_OPENBSD: 969 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 970 break; 971 case llvm::ELF::ELFOSABI_SOLARIS: 972 m_triple.setOS(llvm::Triple::OSType::Solaris); 973 break; 974 } 975 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 976 m_triple.setVendor(llvm::Triple::PC); 977 m_triple.setOS(llvm::Triple::Win32); 978 } else { 979 m_triple.setVendor(llvm::Triple::UnknownVendor); 980 m_triple.setOS(llvm::Triple::UnknownOS); 981 } 982 // Fall back onto setting the machine type if the arch by name 983 // failed... 984 if (m_triple.getArch() == llvm::Triple::UnknownArch) 985 m_triple.setArch(core_def->machine); 986 } 987 } else { 988 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 989 if (log) 990 log->Printf("Unable to find a core definition for cpu 0x%" PRIx32 " sub %" PRId32, cpu, sub); 991 } 992 } 993 CoreUpdated(update_triple); 994 return IsValid(); 995 } 996 997 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 998 const CoreDefinition *core_def = FindCoreDefinition(m_core); 999 if (core_def) 1000 return core_def->min_opcode_byte_size; 1001 return 0; 1002 } 1003 1004 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 1005 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1006 if (core_def) 1007 return core_def->max_opcode_byte_size; 1008 return 0; 1009 } 1010 1011 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 1012 return IsEqualTo(rhs, true); 1013 } 1014 1015 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 1016 return IsEqualTo(rhs, false); 1017 } 1018 1019 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 1020 llvm::Triple::EnvironmentType rhs) { 1021 if (lhs == rhs) 1022 return true; 1023 1024 // If any of the environment is unknown then they are compatible 1025 if (lhs == llvm::Triple::UnknownEnvironment || 1026 rhs == llvm::Triple::UnknownEnvironment) 1027 return true; 1028 1029 // If one of the environment is Android and the other one is EABI then they 1030 // are considered to be compatible. This is required as a workaround for 1031 // shared libraries compiled for Android without the NOTE section indicating 1032 // that they are using the Android ABI. 1033 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 1034 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 1035 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1036 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1037 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1038 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1039 return true; 1040 1041 return false; 1042 } 1043 1044 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1045 // explicitly ignoring m_distribution_id in this method. 1046 1047 if (GetByteOrder() != rhs.GetByteOrder()) 1048 return false; 1049 1050 const ArchSpec::Core lhs_core = GetCore(); 1051 const ArchSpec::Core rhs_core = rhs.GetCore(); 1052 1053 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1054 1055 if (core_match) { 1056 const llvm::Triple &lhs_triple = GetTriple(); 1057 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1058 1059 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1060 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1061 if (lhs_triple_vendor != rhs_triple_vendor) { 1062 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1063 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1064 // Both architectures had the vendor specified, so if they aren't equal 1065 // then we return false 1066 if (rhs_vendor_specified && lhs_vendor_specified) 1067 return false; 1068 1069 // Only fail if both vendor types are not unknown 1070 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1071 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1072 return false; 1073 } 1074 1075 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1076 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1077 if (lhs_triple_os != rhs_triple_os) { 1078 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1079 const bool lhs_os_specified = TripleOSWasSpecified(); 1080 // Both architectures had the OS specified, so if they aren't equal then 1081 // we return false 1082 if (rhs_os_specified && lhs_os_specified) 1083 return false; 1084 1085 // Only fail if both os types are not unknown 1086 if (lhs_triple_os != llvm::Triple::UnknownOS && 1087 rhs_triple_os != llvm::Triple::UnknownOS) 1088 return false; 1089 } 1090 1091 const llvm::Triple::EnvironmentType lhs_triple_env = 1092 lhs_triple.getEnvironment(); 1093 const llvm::Triple::EnvironmentType rhs_triple_env = 1094 rhs_triple.getEnvironment(); 1095 1096 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1097 } 1098 return false; 1099 } 1100 1101 void ArchSpec::UpdateCore() { 1102 llvm::StringRef arch_name(m_triple.getArchName()); 1103 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1104 if (core_def) { 1105 m_core = core_def->core; 1106 // Set the byte order to the default byte order for an architecture. This 1107 // can be modified if needed for cases when cores handle both big and 1108 // little endian 1109 m_byte_order = core_def->default_byte_order; 1110 } else { 1111 Clear(); 1112 } 1113 } 1114 1115 //===----------------------------------------------------------------------===// 1116 // Helper methods. 1117 1118 void ArchSpec::CoreUpdated(bool update_triple) { 1119 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1120 if (core_def) { 1121 if (update_triple) 1122 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1123 m_byte_order = core_def->default_byte_order; 1124 } else { 1125 if (update_triple) 1126 m_triple = llvm::Triple(); 1127 m_byte_order = eByteOrderInvalid; 1128 } 1129 } 1130 1131 //===----------------------------------------------------------------------===// 1132 // Operators. 1133 1134 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1135 bool try_inverse, bool enforce_exact_match) { 1136 if (core1 == core2) 1137 return true; 1138 1139 switch (core1) { 1140 case ArchSpec::kCore_any: 1141 return true; 1142 1143 case ArchSpec::eCore_arm_generic: 1144 if (enforce_exact_match) 1145 break; 1146 LLVM_FALLTHROUGH; 1147 case ArchSpec::kCore_arm_any: 1148 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1149 return true; 1150 if (core2 >= ArchSpec::kCore_thumb_first && 1151 core2 <= ArchSpec::kCore_thumb_last) 1152 return true; 1153 if (core2 == ArchSpec::kCore_arm_any) 1154 return true; 1155 break; 1156 1157 case ArchSpec::kCore_x86_32_any: 1158 if ((core2 >= ArchSpec::kCore_x86_32_first && 1159 core2 <= ArchSpec::kCore_x86_32_last) || 1160 (core2 == ArchSpec::kCore_x86_32_any)) 1161 return true; 1162 break; 1163 1164 case ArchSpec::kCore_x86_64_any: 1165 if ((core2 >= ArchSpec::kCore_x86_64_first && 1166 core2 <= ArchSpec::kCore_x86_64_last) || 1167 (core2 == ArchSpec::kCore_x86_64_any)) 1168 return true; 1169 break; 1170 1171 case ArchSpec::kCore_ppc_any: 1172 if ((core2 >= ArchSpec::kCore_ppc_first && 1173 core2 <= ArchSpec::kCore_ppc_last) || 1174 (core2 == ArchSpec::kCore_ppc_any)) 1175 return true; 1176 break; 1177 1178 case ArchSpec::kCore_ppc64_any: 1179 if ((core2 >= ArchSpec::kCore_ppc64_first && 1180 core2 <= ArchSpec::kCore_ppc64_last) || 1181 (core2 == ArchSpec::kCore_ppc64_any)) 1182 return true; 1183 break; 1184 1185 case ArchSpec::eCore_arm_armv6m: 1186 if (!enforce_exact_match) { 1187 if (core2 == ArchSpec::eCore_arm_generic) 1188 return true; 1189 try_inverse = false; 1190 if (core2 == ArchSpec::eCore_arm_armv7) 1191 return true; 1192 if (core2 == ArchSpec::eCore_arm_armv6m) 1193 return true; 1194 } 1195 break; 1196 1197 case ArchSpec::kCore_hexagon_any: 1198 if ((core2 >= ArchSpec::kCore_hexagon_first && 1199 core2 <= ArchSpec::kCore_hexagon_last) || 1200 (core2 == ArchSpec::kCore_hexagon_any)) 1201 return true; 1202 break; 1203 1204 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1205 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1206 // ARMv7E-M - armv7em 1207 case ArchSpec::eCore_arm_armv7em: 1208 if (!enforce_exact_match) { 1209 if (core2 == ArchSpec::eCore_arm_generic) 1210 return true; 1211 if (core2 == ArchSpec::eCore_arm_armv7m) 1212 return true; 1213 if (core2 == ArchSpec::eCore_arm_armv6m) 1214 return true; 1215 if (core2 == ArchSpec::eCore_arm_armv7) 1216 return true; 1217 try_inverse = true; 1218 } 1219 break; 1220 1221 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1222 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1223 // ARMv7E-M - armv7em 1224 case ArchSpec::eCore_arm_armv7m: 1225 if (!enforce_exact_match) { 1226 if (core2 == ArchSpec::eCore_arm_generic) 1227 return true; 1228 if (core2 == ArchSpec::eCore_arm_armv6m) 1229 return true; 1230 if (core2 == ArchSpec::eCore_arm_armv7) 1231 return true; 1232 if (core2 == ArchSpec::eCore_arm_armv7em) 1233 return true; 1234 try_inverse = true; 1235 } 1236 break; 1237 1238 case ArchSpec::eCore_arm_armv7f: 1239 case ArchSpec::eCore_arm_armv7k: 1240 case ArchSpec::eCore_arm_armv7s: 1241 if (!enforce_exact_match) { 1242 if (core2 == ArchSpec::eCore_arm_generic) 1243 return true; 1244 if (core2 == ArchSpec::eCore_arm_armv7) 1245 return true; 1246 try_inverse = false; 1247 } 1248 break; 1249 1250 case ArchSpec::eCore_x86_64_x86_64h: 1251 if (!enforce_exact_match) { 1252 try_inverse = false; 1253 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1254 return true; 1255 } 1256 break; 1257 1258 case ArchSpec::eCore_arm_armv8: 1259 if (!enforce_exact_match) { 1260 if (core2 == ArchSpec::eCore_arm_arm64) 1261 return true; 1262 if (core2 == ArchSpec::eCore_arm_aarch64) 1263 return true; 1264 try_inverse = false; 1265 } 1266 break; 1267 1268 case ArchSpec::eCore_arm_aarch64: 1269 if (!enforce_exact_match) { 1270 if (core2 == ArchSpec::eCore_arm_arm64) 1271 return true; 1272 if (core2 == ArchSpec::eCore_arm_armv8) 1273 return true; 1274 try_inverse = false; 1275 } 1276 break; 1277 1278 case ArchSpec::eCore_arm_arm64: 1279 if (!enforce_exact_match) { 1280 if (core2 == ArchSpec::eCore_arm_aarch64) 1281 return true; 1282 if (core2 == ArchSpec::eCore_arm_armv8) 1283 return true; 1284 try_inverse = false; 1285 } 1286 break; 1287 1288 case ArchSpec::eCore_mips32: 1289 if (!enforce_exact_match) { 1290 if (core2 >= ArchSpec::kCore_mips32_first && 1291 core2 <= ArchSpec::kCore_mips32_last) 1292 return true; 1293 try_inverse = false; 1294 } 1295 break; 1296 1297 case ArchSpec::eCore_mips32el: 1298 if (!enforce_exact_match) { 1299 if (core2 >= ArchSpec::kCore_mips32el_first && 1300 core2 <= ArchSpec::kCore_mips32el_last) 1301 return true; 1302 try_inverse = true; 1303 } 1304 break; 1305 1306 case ArchSpec::eCore_mips64: 1307 if (!enforce_exact_match) { 1308 if (core2 >= ArchSpec::kCore_mips32_first && 1309 core2 <= ArchSpec::kCore_mips32_last) 1310 return true; 1311 if (core2 >= ArchSpec::kCore_mips64_first && 1312 core2 <= ArchSpec::kCore_mips64_last) 1313 return true; 1314 try_inverse = false; 1315 } 1316 break; 1317 1318 case ArchSpec::eCore_mips64el: 1319 if (!enforce_exact_match) { 1320 if (core2 >= ArchSpec::kCore_mips32el_first && 1321 core2 <= ArchSpec::kCore_mips32el_last) 1322 return true; 1323 if (core2 >= ArchSpec::kCore_mips64el_first && 1324 core2 <= ArchSpec::kCore_mips64el_last) 1325 return true; 1326 try_inverse = false; 1327 } 1328 break; 1329 1330 case ArchSpec::eCore_mips64r2: 1331 case ArchSpec::eCore_mips64r3: 1332 case ArchSpec::eCore_mips64r5: 1333 if (!enforce_exact_match) { 1334 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1335 return true; 1336 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1337 return true; 1338 try_inverse = false; 1339 } 1340 break; 1341 1342 case ArchSpec::eCore_mips64r2el: 1343 case ArchSpec::eCore_mips64r3el: 1344 case ArchSpec::eCore_mips64r5el: 1345 if (!enforce_exact_match) { 1346 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1347 return true; 1348 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1349 return true; 1350 try_inverse = false; 1351 } 1352 break; 1353 1354 case ArchSpec::eCore_mips32r2: 1355 case ArchSpec::eCore_mips32r3: 1356 case ArchSpec::eCore_mips32r5: 1357 if (!enforce_exact_match) { 1358 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1359 return true; 1360 } 1361 break; 1362 1363 case ArchSpec::eCore_mips32r2el: 1364 case ArchSpec::eCore_mips32r3el: 1365 case ArchSpec::eCore_mips32r5el: 1366 if (!enforce_exact_match) { 1367 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1368 return true; 1369 } 1370 break; 1371 1372 case ArchSpec::eCore_mips32r6: 1373 if (!enforce_exact_match) { 1374 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1375 return true; 1376 } 1377 break; 1378 1379 case ArchSpec::eCore_mips32r6el: 1380 if (!enforce_exact_match) { 1381 if (core2 == ArchSpec::eCore_mips32el || 1382 core2 == ArchSpec::eCore_mips32r6el) 1383 return true; 1384 } 1385 break; 1386 1387 case ArchSpec::eCore_mips64r6: 1388 if (!enforce_exact_match) { 1389 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1390 return true; 1391 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1392 return true; 1393 } 1394 break; 1395 1396 case ArchSpec::eCore_mips64r6el: 1397 if (!enforce_exact_match) { 1398 if (core2 == ArchSpec::eCore_mips32el || 1399 core2 == ArchSpec::eCore_mips32r6el) 1400 return true; 1401 if (core2 == ArchSpec::eCore_mips64el || 1402 core2 == ArchSpec::eCore_mips64r6el) 1403 return true; 1404 } 1405 break; 1406 1407 default: 1408 break; 1409 } 1410 if (try_inverse) 1411 return cores_match(core2, core1, false, enforce_exact_match); 1412 return false; 1413 } 1414 1415 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1416 const ArchSpec::Core lhs_core = lhs.GetCore(); 1417 const ArchSpec::Core rhs_core = rhs.GetCore(); 1418 return lhs_core < rhs_core; 1419 } 1420 1421 1422 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1423 return lhs.GetCore() == rhs.GetCore(); 1424 } 1425 1426 bool ArchSpec::IsFullySpecifiedTriple() const { 1427 const auto &user_specified_triple = GetTriple(); 1428 1429 bool user_triple_fully_specified = false; 1430 1431 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1432 TripleOSWasSpecified()) { 1433 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1434 TripleVendorWasSpecified()) { 1435 const unsigned unspecified = 0; 1436 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1437 user_triple_fully_specified = true; 1438 } 1439 } 1440 } 1441 1442 return user_triple_fully_specified; 1443 } 1444 1445 void ArchSpec::PiecewiseTripleCompare( 1446 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1447 bool &os_different, bool &os_version_different, bool &env_different) const { 1448 const llvm::Triple &me(GetTriple()); 1449 const llvm::Triple &them(other.GetTriple()); 1450 1451 arch_different = (me.getArch() != them.getArch()); 1452 1453 vendor_different = (me.getVendor() != them.getVendor()); 1454 1455 os_different = (me.getOS() != them.getOS()); 1456 1457 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1458 1459 env_different = (me.getEnvironment() != them.getEnvironment()); 1460 } 1461 1462 bool ArchSpec::IsAlwaysThumbInstructions() const { 1463 std::string Status; 1464 if (GetTriple().getArch() == llvm::Triple::arm || 1465 GetTriple().getArch() == llvm::Triple::thumb) { 1466 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1467 // 1468 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1469 // execute thumb instructions. We map the cores to arch names like this: 1470 // 1471 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1472 // Cortex-M7: armv7em 1473 1474 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1475 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1476 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1477 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1478 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1479 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1480 return true; 1481 } 1482 } 1483 return false; 1484 } 1485 1486 void ArchSpec::DumpTriple(Stream &s) const { 1487 const llvm::Triple &triple = GetTriple(); 1488 llvm::StringRef arch_str = triple.getArchName(); 1489 llvm::StringRef vendor_str = triple.getVendorName(); 1490 llvm::StringRef os_str = triple.getOSName(); 1491 llvm::StringRef environ_str = triple.getEnvironmentName(); 1492 1493 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1494 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1495 os_str.empty() ? "*" : os_str.str().c_str()); 1496 1497 if (!environ_str.empty()) 1498 s.Printf("-%s", environ_str.str().c_str()); 1499 } 1500