1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/StringList.h" 13 #include "lldb/lldb-defines.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/BinaryFormat/COFF.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Compiler.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26 namespace lldb_private { 27 28 struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36 }; 37 38 } // namespace lldb_private 39 40 // This core information can be looked using the ArchSpec::Core as the index 41 static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 103 ArchSpec::eCore_arm_armv8l, "armv8l"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_generic, "hexagon"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 214 215 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32, 216 "riscv32"}, 217 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64, 218 "riscv64"}, 219 220 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 221 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 222 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 223 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 224 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 225 226 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"}, 227 228 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 229 "wasm32"}, 230 }; 231 232 // Ensure that we have an entry in the g_core_definitions for each core. If you 233 // comment out an entry above, you will need to comment out the corresponding 234 // ArchSpec::Core enumeration. 235 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 236 ArchSpec::kNumCores, 237 "make sure we have one core definition for each core"); 238 239 struct ArchDefinitionEntry { 240 ArchSpec::Core core; 241 uint32_t cpu; 242 uint32_t sub; 243 uint32_t cpu_mask; 244 uint32_t sub_mask; 245 }; 246 247 struct ArchDefinition { 248 ArchitectureType type; 249 size_t num_entries; 250 const ArchDefinitionEntry *entries; 251 const char *name; 252 }; 253 254 void ArchSpec::ListSupportedArchNames(StringList &list) { 255 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 256 list.AppendString(g_core_definitions[i].name); 257 } 258 259 void ArchSpec::AutoComplete(CompletionRequest &request) { 260 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 261 request.TryCompleteCurrentArg(g_core_definitions[i].name); 262 } 263 264 #define CPU_ANY (UINT32_MAX) 265 266 //===----------------------------------------------------------------------===// 267 // A table that gets searched linearly for matches. This table is used to 268 // convert cpu type and subtypes to architecture names, and to convert 269 // architecture names to cpu types and subtypes. The ordering is important and 270 // allows the precedence to be set when the table is built. 271 #define SUBTYPE_MASK 0x00FFFFFFu 272 273 // clang-format off 274 static const ArchDefinitionEntry g_macho_arch_entries[] = { 275 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX}, 276 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 278 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 291 // FIXME: This should be arm64e once the triple exists. 292 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 299 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 300 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 301 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 302 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 303 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 304 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 305 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 306 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 307 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 309 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX}, 312 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 313 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK}, 314 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK}, 315 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK}, 316 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK}, 317 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK}, 318 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK}, 319 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK}, 320 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK}, 321 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK}, 322 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK}, 323 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK}, 324 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK}, 325 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 326 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 327 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK}, 328 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK}, 329 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK}, 330 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK}, 331 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX}, 332 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK}, 333 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK}, 334 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK}, 335 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX}, 336 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files 337 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 338 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}}; 339 // clang-format on 340 341 static const ArchDefinition g_macho_arch_def = { 342 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 343 g_macho_arch_entries, "mach-o"}; 344 345 //===----------------------------------------------------------------------===// 346 // A table that gets searched linearly for matches. This table is used to 347 // convert cpu type and subtypes to architecture names, and to convert 348 // architecture names to cpu types and subtypes. The ordering is important and 349 // allows the precedence to be set when the table is built. 350 static const ArchDefinitionEntry g_elf_arch_entries[] = { 351 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 352 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 353 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 354 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 355 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 356 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 357 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 358 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 359 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 360 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 361 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 362 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 363 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 364 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 365 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 366 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 367 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 368 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 369 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 370 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 371 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 372 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 373 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 374 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 375 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 376 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 377 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 378 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 379 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 380 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 381 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 382 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 383 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 384 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 385 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 386 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 387 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 388 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 389 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 390 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 391 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 392 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 393 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 394 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 395 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 396 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 397 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 398 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 399 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 400 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 401 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 402 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR 403 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, 404 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32 405 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, 406 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64 407 }; 408 409 static const ArchDefinition g_elf_arch_def = { 410 eArchTypeELF, 411 llvm::array_lengthof(g_elf_arch_entries), 412 g_elf_arch_entries, 413 "elf", 414 }; 415 416 static const ArchDefinitionEntry g_coff_arch_entries[] = { 417 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 418 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 419 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 420 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 421 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 422 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 423 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 424 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 425 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 426 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 427 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 428 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 429 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 430 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 431 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 432 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 433 }; 434 435 static const ArchDefinition g_coff_arch_def = { 436 eArchTypeCOFF, 437 llvm::array_lengthof(g_coff_arch_entries), 438 g_coff_arch_entries, 439 "pe-coff", 440 }; 441 442 //===----------------------------------------------------------------------===// 443 // Table of all ArchDefinitions 444 static const ArchDefinition *g_arch_definitions[] = { 445 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 446 447 static const size_t k_num_arch_definitions = 448 llvm::array_lengthof(g_arch_definitions); 449 450 //===----------------------------------------------------------------------===// 451 // Static helper functions. 452 453 // Get the architecture definition for a given object type. 454 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 455 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 456 const ArchDefinition *def = g_arch_definitions[i]; 457 if (def->type == arch_type) 458 return def; 459 } 460 return nullptr; 461 } 462 463 // Get an architecture definition by name. 464 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 465 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 466 if (name.equals_lower(g_core_definitions[i].name)) 467 return &g_core_definitions[i]; 468 } 469 return nullptr; 470 } 471 472 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 473 if (core < llvm::array_lengthof(g_core_definitions)) 474 return &g_core_definitions[core]; 475 return nullptr; 476 } 477 478 // Get a definition entry by cpu type and subtype. 479 static const ArchDefinitionEntry * 480 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 481 if (def == nullptr) 482 return nullptr; 483 484 const ArchDefinitionEntry *entries = def->entries; 485 for (size_t i = 0; i < def->num_entries; ++i) { 486 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 487 if (entries[i].sub == (sub & entries[i].sub_mask)) 488 return &entries[i]; 489 } 490 return nullptr; 491 } 492 493 static const ArchDefinitionEntry * 494 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 495 if (def == nullptr) 496 return nullptr; 497 498 const ArchDefinitionEntry *entries = def->entries; 499 for (size_t i = 0; i < def->num_entries; ++i) { 500 if (entries[i].core == core) 501 return &entries[i]; 502 } 503 return nullptr; 504 } 505 506 //===----------------------------------------------------------------------===// 507 // Constructors and destructors. 508 509 ArchSpec::ArchSpec() {} 510 511 ArchSpec::ArchSpec(const char *triple_cstr) { 512 if (triple_cstr) 513 SetTriple(triple_cstr); 514 } 515 516 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 517 518 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 519 520 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 521 SetArchitecture(arch_type, cpu, subtype); 522 } 523 524 ArchSpec::~ArchSpec() = default; 525 526 void ArchSpec::Clear() { 527 m_triple = llvm::Triple(); 528 m_core = kCore_invalid; 529 m_byte_order = eByteOrderInvalid; 530 m_distribution_id.Clear(); 531 m_flags = 0; 532 } 533 534 //===----------------------------------------------------------------------===// 535 // Predicates. 536 537 const char *ArchSpec::GetArchitectureName() const { 538 const CoreDefinition *core_def = FindCoreDefinition(m_core); 539 if (core_def) 540 return core_def->name; 541 return "unknown"; 542 } 543 544 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 545 546 std::string ArchSpec::GetTargetABI() const { 547 548 std::string abi; 549 550 if (IsMIPS()) { 551 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 552 case ArchSpec::eMIPSABI_N64: 553 abi = "n64"; 554 return abi; 555 case ArchSpec::eMIPSABI_N32: 556 abi = "n32"; 557 return abi; 558 case ArchSpec::eMIPSABI_O32: 559 abi = "o32"; 560 return abi; 561 default: 562 return abi; 563 } 564 } 565 return abi; 566 } 567 568 void ArchSpec::SetFlags(const std::string &elf_abi) { 569 570 uint32_t flag = GetFlags(); 571 if (IsMIPS()) { 572 if (elf_abi == "n64") 573 flag |= ArchSpec::eMIPSABI_N64; 574 else if (elf_abi == "n32") 575 flag |= ArchSpec::eMIPSABI_N32; 576 else if (elf_abi == "o32") 577 flag |= ArchSpec::eMIPSABI_O32; 578 } 579 SetFlags(flag); 580 } 581 582 std::string ArchSpec::GetClangTargetCPU() const { 583 std::string cpu; 584 585 if (IsMIPS()) { 586 switch (m_core) { 587 case ArchSpec::eCore_mips32: 588 case ArchSpec::eCore_mips32el: 589 cpu = "mips32"; 590 break; 591 case ArchSpec::eCore_mips32r2: 592 case ArchSpec::eCore_mips32r2el: 593 cpu = "mips32r2"; 594 break; 595 case ArchSpec::eCore_mips32r3: 596 case ArchSpec::eCore_mips32r3el: 597 cpu = "mips32r3"; 598 break; 599 case ArchSpec::eCore_mips32r5: 600 case ArchSpec::eCore_mips32r5el: 601 cpu = "mips32r5"; 602 break; 603 case ArchSpec::eCore_mips32r6: 604 case ArchSpec::eCore_mips32r6el: 605 cpu = "mips32r6"; 606 break; 607 case ArchSpec::eCore_mips64: 608 case ArchSpec::eCore_mips64el: 609 cpu = "mips64"; 610 break; 611 case ArchSpec::eCore_mips64r2: 612 case ArchSpec::eCore_mips64r2el: 613 cpu = "mips64r2"; 614 break; 615 case ArchSpec::eCore_mips64r3: 616 case ArchSpec::eCore_mips64r3el: 617 cpu = "mips64r3"; 618 break; 619 case ArchSpec::eCore_mips64r5: 620 case ArchSpec::eCore_mips64r5el: 621 cpu = "mips64r5"; 622 break; 623 case ArchSpec::eCore_mips64r6: 624 case ArchSpec::eCore_mips64r6el: 625 cpu = "mips64r6"; 626 break; 627 default: 628 break; 629 } 630 } 631 return cpu; 632 } 633 634 uint32_t ArchSpec::GetMachOCPUType() const { 635 const CoreDefinition *core_def = FindCoreDefinition(m_core); 636 if (core_def) { 637 const ArchDefinitionEntry *arch_def = 638 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 639 if (arch_def) { 640 return arch_def->cpu; 641 } 642 } 643 return LLDB_INVALID_CPUTYPE; 644 } 645 646 uint32_t ArchSpec::GetMachOCPUSubType() const { 647 const CoreDefinition *core_def = FindCoreDefinition(m_core); 648 if (core_def) { 649 const ArchDefinitionEntry *arch_def = 650 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 651 if (arch_def) { 652 return arch_def->sub; 653 } 654 } 655 return LLDB_INVALID_CPUTYPE; 656 } 657 658 uint32_t ArchSpec::GetDataByteSize() const { 659 return 1; 660 } 661 662 uint32_t ArchSpec::GetCodeByteSize() const { 663 return 1; 664 } 665 666 llvm::Triple::ArchType ArchSpec::GetMachine() const { 667 const CoreDefinition *core_def = FindCoreDefinition(m_core); 668 if (core_def) 669 return core_def->machine; 670 671 return llvm::Triple::UnknownArch; 672 } 673 674 ConstString ArchSpec::GetDistributionId() const { 675 return m_distribution_id; 676 } 677 678 void ArchSpec::SetDistributionId(const char *distribution_id) { 679 m_distribution_id.SetCString(distribution_id); 680 } 681 682 uint32_t ArchSpec::GetAddressByteSize() const { 683 const CoreDefinition *core_def = FindCoreDefinition(m_core); 684 if (core_def) { 685 if (core_def->machine == llvm::Triple::mips64 || 686 core_def->machine == llvm::Triple::mips64el) { 687 // For N32/O32 applications Address size is 4 bytes. 688 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 689 return 4; 690 } 691 return core_def->addr_byte_size; 692 } 693 return 0; 694 } 695 696 ByteOrder ArchSpec::GetDefaultEndian() const { 697 const CoreDefinition *core_def = FindCoreDefinition(m_core); 698 if (core_def) 699 return core_def->default_byte_order; 700 return eByteOrderInvalid; 701 } 702 703 bool ArchSpec::CharIsSignedByDefault() const { 704 switch (m_triple.getArch()) { 705 default: 706 return true; 707 708 case llvm::Triple::aarch64: 709 case llvm::Triple::aarch64_32: 710 case llvm::Triple::aarch64_be: 711 case llvm::Triple::arm: 712 case llvm::Triple::armeb: 713 case llvm::Triple::thumb: 714 case llvm::Triple::thumbeb: 715 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 716 717 case llvm::Triple::ppc: 718 case llvm::Triple::ppc64: 719 return m_triple.isOSDarwin(); 720 721 case llvm::Triple::ppc64le: 722 case llvm::Triple::systemz: 723 case llvm::Triple::xcore: 724 case llvm::Triple::arc: 725 return false; 726 } 727 } 728 729 lldb::ByteOrder ArchSpec::GetByteOrder() const { 730 if (m_byte_order == eByteOrderInvalid) 731 return GetDefaultEndian(); 732 return m_byte_order; 733 } 734 735 //===----------------------------------------------------------------------===// 736 // Mutators. 737 738 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 739 m_triple = triple; 740 UpdateCore(); 741 return IsValid(); 742 } 743 744 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 745 ArchSpec &arch) { 746 // Accept "12-10" or "12.10" as cpu type/subtype 747 if (triple_str.empty()) 748 return false; 749 750 size_t pos = triple_str.find_first_of("-."); 751 if (pos == llvm::StringRef::npos) 752 return false; 753 754 llvm::StringRef cpu_str = triple_str.substr(0, pos); 755 llvm::StringRef remainder = triple_str.substr(pos + 1); 756 if (cpu_str.empty() || remainder.empty()) 757 return false; 758 759 llvm::StringRef sub_str; 760 llvm::StringRef vendor; 761 llvm::StringRef os; 762 std::tie(sub_str, remainder) = remainder.split('-'); 763 std::tie(vendor, os) = remainder.split('-'); 764 765 uint32_t cpu = 0; 766 uint32_t sub = 0; 767 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 768 return false; 769 770 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 771 return false; 772 if (!vendor.empty() && !os.empty()) { 773 arch.GetTriple().setVendorName(vendor); 774 arch.GetTriple().setOSName(os); 775 } 776 777 return true; 778 } 779 780 bool ArchSpec::SetTriple(llvm::StringRef triple) { 781 if (triple.empty()) { 782 Clear(); 783 return false; 784 } 785 786 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 787 return true; 788 789 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 790 return IsValid(); 791 } 792 793 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 794 return !normalized_triple.getArchName().empty() && 795 normalized_triple.getOSName().empty() && 796 normalized_triple.getVendorName().empty() && 797 normalized_triple.getEnvironmentName().empty(); 798 } 799 800 void ArchSpec::MergeFrom(const ArchSpec &other) { 801 // ios-macabi always wins over macosx. 802 if ((GetTriple().getOS() == llvm::Triple::MacOSX || 803 GetTriple().getOS() == llvm::Triple::UnknownOS) && 804 other.GetTriple().getOS() == llvm::Triple::IOS && 805 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) { 806 (*this) = other; 807 return; 808 } 809 810 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 811 GetTriple().setVendor(other.GetTriple().getVendor()); 812 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 813 GetTriple().setOS(other.GetTriple().getOS()); 814 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 815 GetTriple().setArch(other.GetTriple().getArch()); 816 817 // MachO unknown64 isn't really invalid as the debugger can still obtain 818 // information from the binary, e.g. line tables. As such, we don't update 819 // the core here. 820 if (other.GetCore() != eCore_uknownMach64) 821 UpdateCore(); 822 } 823 if (!TripleEnvironmentWasSpecified() && 824 other.TripleEnvironmentWasSpecified()) { 825 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 826 } 827 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 828 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 829 // adopt the specific arm core. 830 if (GetTriple().getArch() == llvm::Triple::arm && 831 other.GetTriple().getArch() == llvm::Triple::arm && 832 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 833 other.GetCore() != ArchSpec::eCore_arm_generic) { 834 m_core = other.GetCore(); 835 CoreUpdated(false); 836 } 837 if (GetFlags() == 0) { 838 SetFlags(other.GetFlags()); 839 } 840 } 841 842 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 843 uint32_t sub, uint32_t os) { 844 m_core = kCore_invalid; 845 bool update_triple = true; 846 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 847 if (arch_def) { 848 const ArchDefinitionEntry *arch_def_entry = 849 FindArchDefinitionEntry(arch_def, cpu, sub); 850 if (arch_def_entry) { 851 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 852 if (core_def) { 853 m_core = core_def->core; 854 update_triple = false; 855 // Always use the architecture name because it might be more 856 // descriptive than the architecture enum ("armv7" -> 857 // llvm::Triple::arm). 858 m_triple.setArchName(llvm::StringRef(core_def->name)); 859 if (arch_type == eArchTypeMachO) { 860 m_triple.setVendor(llvm::Triple::Apple); 861 862 // Don't set the OS. It could be simulator, macosx, ios, watchos, 863 // tvos, bridgeos. We could get close with the cpu type - but we 864 // can't get it right all of the time. Better to leave this unset 865 // so other sections of code will set it when they have more 866 // information. NB: don't call m_triple.setOS 867 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 868 // the ArchSpec::TripleVendorWasSpecified() method says that any 869 // OSName setting means it was specified. 870 } else if (arch_type == eArchTypeELF) { 871 switch (os) { 872 case llvm::ELF::ELFOSABI_AIX: 873 m_triple.setOS(llvm::Triple::OSType::AIX); 874 break; 875 case llvm::ELF::ELFOSABI_FREEBSD: 876 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 877 break; 878 case llvm::ELF::ELFOSABI_GNU: 879 m_triple.setOS(llvm::Triple::OSType::Linux); 880 break; 881 case llvm::ELF::ELFOSABI_NETBSD: 882 m_triple.setOS(llvm::Triple::OSType::NetBSD); 883 break; 884 case llvm::ELF::ELFOSABI_OPENBSD: 885 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 886 break; 887 case llvm::ELF::ELFOSABI_SOLARIS: 888 m_triple.setOS(llvm::Triple::OSType::Solaris); 889 break; 890 } 891 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 892 m_triple.setVendor(llvm::Triple::PC); 893 m_triple.setOS(llvm::Triple::Win32); 894 } else { 895 m_triple.setVendor(llvm::Triple::UnknownVendor); 896 m_triple.setOS(llvm::Triple::UnknownOS); 897 } 898 // Fall back onto setting the machine type if the arch by name 899 // failed... 900 if (m_triple.getArch() == llvm::Triple::UnknownArch) 901 m_triple.setArch(core_def->machine); 902 } 903 } else { 904 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 905 LLDB_LOGF(log, 906 "Unable to find a core definition for cpu 0x%" PRIx32 907 " sub %" PRId32, 908 cpu, sub); 909 } 910 } 911 CoreUpdated(update_triple); 912 return IsValid(); 913 } 914 915 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 916 const CoreDefinition *core_def = FindCoreDefinition(m_core); 917 if (core_def) 918 return core_def->min_opcode_byte_size; 919 return 0; 920 } 921 922 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 923 const CoreDefinition *core_def = FindCoreDefinition(m_core); 924 if (core_def) 925 return core_def->max_opcode_byte_size; 926 return 0; 927 } 928 929 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 930 return IsEqualTo(rhs, true); 931 } 932 933 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 934 return IsEqualTo(rhs, false); 935 } 936 937 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 938 llvm::Triple::EnvironmentType rhs) { 939 if (lhs == rhs) 940 return true; 941 942 // Apple simulators are a different platform than what they simulate. 943 // As the environments are different at this point, if one of them is a 944 // simulator, then they are different. 945 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator) 946 return false; 947 948 // If any of the environment is unknown then they are compatible 949 if (lhs == llvm::Triple::UnknownEnvironment || 950 rhs == llvm::Triple::UnknownEnvironment) 951 return true; 952 953 // If one of the environment is Android and the other one is EABI then they 954 // are considered to be compatible. This is required as a workaround for 955 // shared libraries compiled for Android without the NOTE section indicating 956 // that they are using the Android ABI. 957 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 958 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 959 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 960 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 961 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 962 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 963 return true; 964 965 return false; 966 } 967 968 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 969 // explicitly ignoring m_distribution_id in this method. 970 971 if (GetByteOrder() != rhs.GetByteOrder() || 972 !cores_match(GetCore(), rhs.GetCore(), true, exact_match)) 973 return false; 974 975 const llvm::Triple &lhs_triple = GetTriple(); 976 const llvm::Triple &rhs_triple = rhs.GetTriple(); 977 978 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 979 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 980 if (lhs_triple_vendor != rhs_triple_vendor) { 981 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 982 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 983 // Both architectures had the vendor specified, so if they aren't equal 984 // then we return false 985 if (rhs_vendor_specified && lhs_vendor_specified) 986 return false; 987 988 // Only fail if both vendor types are not unknown 989 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 990 rhs_triple_vendor != llvm::Triple::UnknownVendor) 991 return false; 992 } 993 994 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 995 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 996 const llvm::Triple::EnvironmentType lhs_triple_env = 997 lhs_triple.getEnvironment(); 998 const llvm::Triple::EnvironmentType rhs_triple_env = 999 rhs_triple.getEnvironment(); 1000 1001 if (!exact_match) { 1002 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match. 1003 if ((lhs_triple_os == llvm::Triple::IOS && 1004 lhs_triple_env == llvm::Triple::MacABI && 1005 rhs_triple_os == llvm::Triple::MacOSX) || 1006 (lhs_triple_os == llvm::Triple::MacOSX && 1007 rhs_triple_os == llvm::Triple::IOS && 1008 rhs_triple_env == llvm::Triple::MacABI)) 1009 return true; 1010 } 1011 1012 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible. 1013 if (lhs_triple_os == llvm::Triple::IOS && 1014 rhs_triple_os == llvm::Triple::IOS && 1015 (lhs_triple_env == llvm::Triple::MacABI || 1016 rhs_triple_env == llvm::Triple::MacABI) && 1017 lhs_triple_env != rhs_triple_env) 1018 return false; 1019 1020 if (lhs_triple_os != rhs_triple_os) { 1021 const bool lhs_os_specified = TripleOSWasSpecified(); 1022 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1023 // If both OS types are specified and different, fail. 1024 if (lhs_os_specified && rhs_os_specified) 1025 return false; 1026 1027 // If the pair of os+env is both unspecified, match any other os+env combo. 1028 if (!exact_match && ((!lhs_os_specified && !lhs_triple.hasEnvironment()) || 1029 (!rhs_os_specified && !rhs_triple.hasEnvironment()))) 1030 return true; 1031 } 1032 1033 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1034 } 1035 1036 void ArchSpec::UpdateCore() { 1037 llvm::StringRef arch_name(m_triple.getArchName()); 1038 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1039 if (core_def) { 1040 m_core = core_def->core; 1041 // Set the byte order to the default byte order for an architecture. This 1042 // can be modified if needed for cases when cores handle both big and 1043 // little endian 1044 m_byte_order = core_def->default_byte_order; 1045 } else { 1046 Clear(); 1047 } 1048 } 1049 1050 //===----------------------------------------------------------------------===// 1051 // Helper methods. 1052 1053 void ArchSpec::CoreUpdated(bool update_triple) { 1054 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1055 if (core_def) { 1056 if (update_triple) 1057 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1058 m_byte_order = core_def->default_byte_order; 1059 } else { 1060 if (update_triple) 1061 m_triple = llvm::Triple(); 1062 m_byte_order = eByteOrderInvalid; 1063 } 1064 } 1065 1066 //===----------------------------------------------------------------------===// 1067 // Operators. 1068 1069 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1070 bool try_inverse, bool enforce_exact_match) { 1071 if (core1 == core2) 1072 return true; 1073 1074 switch (core1) { 1075 case ArchSpec::kCore_any: 1076 return true; 1077 1078 case ArchSpec::eCore_arm_generic: 1079 if (enforce_exact_match) 1080 break; 1081 LLVM_FALLTHROUGH; 1082 case ArchSpec::kCore_arm_any: 1083 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1084 return true; 1085 if (core2 >= ArchSpec::kCore_thumb_first && 1086 core2 <= ArchSpec::kCore_thumb_last) 1087 return true; 1088 if (core2 == ArchSpec::kCore_arm_any) 1089 return true; 1090 break; 1091 1092 case ArchSpec::kCore_x86_32_any: 1093 if ((core2 >= ArchSpec::kCore_x86_32_first && 1094 core2 <= ArchSpec::kCore_x86_32_last) || 1095 (core2 == ArchSpec::kCore_x86_32_any)) 1096 return true; 1097 break; 1098 1099 case ArchSpec::kCore_x86_64_any: 1100 if ((core2 >= ArchSpec::kCore_x86_64_first && 1101 core2 <= ArchSpec::kCore_x86_64_last) || 1102 (core2 == ArchSpec::kCore_x86_64_any)) 1103 return true; 1104 break; 1105 1106 case ArchSpec::kCore_ppc_any: 1107 if ((core2 >= ArchSpec::kCore_ppc_first && 1108 core2 <= ArchSpec::kCore_ppc_last) || 1109 (core2 == ArchSpec::kCore_ppc_any)) 1110 return true; 1111 break; 1112 1113 case ArchSpec::kCore_ppc64_any: 1114 if ((core2 >= ArchSpec::kCore_ppc64_first && 1115 core2 <= ArchSpec::kCore_ppc64_last) || 1116 (core2 == ArchSpec::kCore_ppc64_any)) 1117 return true; 1118 break; 1119 1120 case ArchSpec::eCore_arm_armv6m: 1121 if (!enforce_exact_match) { 1122 if (core2 == ArchSpec::eCore_arm_generic) 1123 return true; 1124 try_inverse = false; 1125 if (core2 == ArchSpec::eCore_arm_armv7) 1126 return true; 1127 if (core2 == ArchSpec::eCore_arm_armv6m) 1128 return true; 1129 } 1130 break; 1131 1132 case ArchSpec::kCore_hexagon_any: 1133 if ((core2 >= ArchSpec::kCore_hexagon_first && 1134 core2 <= ArchSpec::kCore_hexagon_last) || 1135 (core2 == ArchSpec::kCore_hexagon_any)) 1136 return true; 1137 break; 1138 1139 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1140 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1141 // ARMv7E-M - armv7em 1142 case ArchSpec::eCore_arm_armv7em: 1143 if (!enforce_exact_match) { 1144 if (core2 == ArchSpec::eCore_arm_generic) 1145 return true; 1146 if (core2 == ArchSpec::eCore_arm_armv7m) 1147 return true; 1148 if (core2 == ArchSpec::eCore_arm_armv6m) 1149 return true; 1150 if (core2 == ArchSpec::eCore_arm_armv7) 1151 return true; 1152 try_inverse = true; 1153 } 1154 break; 1155 1156 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1157 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1158 // ARMv7E-M - armv7em 1159 case ArchSpec::eCore_arm_armv7m: 1160 if (!enforce_exact_match) { 1161 if (core2 == ArchSpec::eCore_arm_generic) 1162 return true; 1163 if (core2 == ArchSpec::eCore_arm_armv6m) 1164 return true; 1165 if (core2 == ArchSpec::eCore_arm_armv7) 1166 return true; 1167 if (core2 == ArchSpec::eCore_arm_armv7em) 1168 return true; 1169 try_inverse = true; 1170 } 1171 break; 1172 1173 case ArchSpec::eCore_arm_armv7f: 1174 case ArchSpec::eCore_arm_armv7k: 1175 case ArchSpec::eCore_arm_armv7s: 1176 case ArchSpec::eCore_arm_armv7l: 1177 case ArchSpec::eCore_arm_armv8l: 1178 if (!enforce_exact_match) { 1179 if (core2 == ArchSpec::eCore_arm_generic) 1180 return true; 1181 if (core2 == ArchSpec::eCore_arm_armv7) 1182 return true; 1183 try_inverse = false; 1184 } 1185 break; 1186 1187 case ArchSpec::eCore_x86_64_x86_64h: 1188 if (!enforce_exact_match) { 1189 try_inverse = false; 1190 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1191 return true; 1192 } 1193 break; 1194 1195 case ArchSpec::eCore_arm_armv8: 1196 if (!enforce_exact_match) { 1197 if (core2 == ArchSpec::eCore_arm_arm64) 1198 return true; 1199 if (core2 == ArchSpec::eCore_arm_aarch64) 1200 return true; 1201 try_inverse = false; 1202 } 1203 break; 1204 1205 case ArchSpec::eCore_arm_aarch64: 1206 if (!enforce_exact_match) { 1207 if (core2 == ArchSpec::eCore_arm_arm64) 1208 return true; 1209 if (core2 == ArchSpec::eCore_arm_armv8) 1210 return true; 1211 try_inverse = false; 1212 } 1213 break; 1214 1215 case ArchSpec::eCore_arm_arm64: 1216 if (!enforce_exact_match) { 1217 if (core2 == ArchSpec::eCore_arm_aarch64) 1218 return true; 1219 if (core2 == ArchSpec::eCore_arm_armv8) 1220 return true; 1221 try_inverse = false; 1222 } 1223 break; 1224 1225 case ArchSpec::eCore_arm_arm64_32: 1226 if (!enforce_exact_match) { 1227 if (core2 == ArchSpec::eCore_arm_generic) 1228 return true; 1229 try_inverse = false; 1230 } 1231 break; 1232 1233 case ArchSpec::eCore_mips32: 1234 if (!enforce_exact_match) { 1235 if (core2 >= ArchSpec::kCore_mips32_first && 1236 core2 <= ArchSpec::kCore_mips32_last) 1237 return true; 1238 try_inverse = false; 1239 } 1240 break; 1241 1242 case ArchSpec::eCore_mips32el: 1243 if (!enforce_exact_match) { 1244 if (core2 >= ArchSpec::kCore_mips32el_first && 1245 core2 <= ArchSpec::kCore_mips32el_last) 1246 return true; 1247 try_inverse = true; 1248 } 1249 break; 1250 1251 case ArchSpec::eCore_mips64: 1252 if (!enforce_exact_match) { 1253 if (core2 >= ArchSpec::kCore_mips32_first && 1254 core2 <= ArchSpec::kCore_mips32_last) 1255 return true; 1256 if (core2 >= ArchSpec::kCore_mips64_first && 1257 core2 <= ArchSpec::kCore_mips64_last) 1258 return true; 1259 try_inverse = false; 1260 } 1261 break; 1262 1263 case ArchSpec::eCore_mips64el: 1264 if (!enforce_exact_match) { 1265 if (core2 >= ArchSpec::kCore_mips32el_first && 1266 core2 <= ArchSpec::kCore_mips32el_last) 1267 return true; 1268 if (core2 >= ArchSpec::kCore_mips64el_first && 1269 core2 <= ArchSpec::kCore_mips64el_last) 1270 return true; 1271 try_inverse = false; 1272 } 1273 break; 1274 1275 case ArchSpec::eCore_mips64r2: 1276 case ArchSpec::eCore_mips64r3: 1277 case ArchSpec::eCore_mips64r5: 1278 if (!enforce_exact_match) { 1279 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1280 return true; 1281 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1282 return true; 1283 try_inverse = false; 1284 } 1285 break; 1286 1287 case ArchSpec::eCore_mips64r2el: 1288 case ArchSpec::eCore_mips64r3el: 1289 case ArchSpec::eCore_mips64r5el: 1290 if (!enforce_exact_match) { 1291 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1292 return true; 1293 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1294 return true; 1295 try_inverse = false; 1296 } 1297 break; 1298 1299 case ArchSpec::eCore_mips32r2: 1300 case ArchSpec::eCore_mips32r3: 1301 case ArchSpec::eCore_mips32r5: 1302 if (!enforce_exact_match) { 1303 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1304 return true; 1305 } 1306 break; 1307 1308 case ArchSpec::eCore_mips32r2el: 1309 case ArchSpec::eCore_mips32r3el: 1310 case ArchSpec::eCore_mips32r5el: 1311 if (!enforce_exact_match) { 1312 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1313 return true; 1314 } 1315 break; 1316 1317 case ArchSpec::eCore_mips32r6: 1318 if (!enforce_exact_match) { 1319 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1320 return true; 1321 } 1322 break; 1323 1324 case ArchSpec::eCore_mips32r6el: 1325 if (!enforce_exact_match) { 1326 if (core2 == ArchSpec::eCore_mips32el || 1327 core2 == ArchSpec::eCore_mips32r6el) 1328 return true; 1329 } 1330 break; 1331 1332 case ArchSpec::eCore_mips64r6: 1333 if (!enforce_exact_match) { 1334 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1335 return true; 1336 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1337 return true; 1338 } 1339 break; 1340 1341 case ArchSpec::eCore_mips64r6el: 1342 if (!enforce_exact_match) { 1343 if (core2 == ArchSpec::eCore_mips32el || 1344 core2 == ArchSpec::eCore_mips32r6el) 1345 return true; 1346 if (core2 == ArchSpec::eCore_mips64el || 1347 core2 == ArchSpec::eCore_mips64r6el) 1348 return true; 1349 } 1350 break; 1351 1352 default: 1353 break; 1354 } 1355 if (try_inverse) 1356 return cores_match(core2, core1, false, enforce_exact_match); 1357 return false; 1358 } 1359 1360 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1361 const ArchSpec::Core lhs_core = lhs.GetCore(); 1362 const ArchSpec::Core rhs_core = rhs.GetCore(); 1363 return lhs_core < rhs_core; 1364 } 1365 1366 1367 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1368 return lhs.GetCore() == rhs.GetCore(); 1369 } 1370 1371 bool ArchSpec::IsFullySpecifiedTriple() const { 1372 const auto &user_specified_triple = GetTriple(); 1373 1374 bool user_triple_fully_specified = false; 1375 1376 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1377 TripleOSWasSpecified()) { 1378 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1379 TripleVendorWasSpecified()) { 1380 const unsigned unspecified = 0; 1381 if (!user_specified_triple.isOSDarwin() || 1382 user_specified_triple.getOSMajorVersion() != unspecified) { 1383 user_triple_fully_specified = true; 1384 } 1385 } 1386 } 1387 1388 return user_triple_fully_specified; 1389 } 1390 1391 void ArchSpec::PiecewiseTripleCompare( 1392 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1393 bool &os_different, bool &os_version_different, bool &env_different) const { 1394 const llvm::Triple &me(GetTriple()); 1395 const llvm::Triple &them(other.GetTriple()); 1396 1397 arch_different = (me.getArch() != them.getArch()); 1398 1399 vendor_different = (me.getVendor() != them.getVendor()); 1400 1401 os_different = (me.getOS() != them.getOS()); 1402 1403 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1404 1405 env_different = (me.getEnvironment() != them.getEnvironment()); 1406 } 1407 1408 bool ArchSpec::IsAlwaysThumbInstructions() const { 1409 std::string Status; 1410 if (GetTriple().getArch() == llvm::Triple::arm || 1411 GetTriple().getArch() == llvm::Triple::thumb) { 1412 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1413 // 1414 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1415 // execute thumb instructions. We map the cores to arch names like this: 1416 // 1417 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1418 // Cortex-M7: armv7em 1419 1420 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1421 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1422 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1423 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1424 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1425 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1426 return true; 1427 } 1428 // Windows on ARM is always thumb. 1429 if (GetTriple().isOSWindows()) 1430 return true; 1431 } 1432 return false; 1433 } 1434 1435 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1436 const llvm::Triple &triple = GetTriple(); 1437 llvm::StringRef arch_str = triple.getArchName(); 1438 llvm::StringRef vendor_str = triple.getVendorName(); 1439 llvm::StringRef os_str = triple.getOSName(); 1440 llvm::StringRef environ_str = triple.getEnvironmentName(); 1441 1442 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1443 vendor_str.empty() ? "*" : vendor_str, 1444 os_str.empty() ? "*" : os_str); 1445 1446 if (!environ_str.empty()) 1447 s << "-" << environ_str; 1448 } 1449 1450 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *, 1451 raw_ostream &Out) { 1452 Val.DumpTriple(Out); 1453 } 1454 1455 llvm::StringRef 1456 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *, 1457 ArchSpec &Val) { 1458 Val = ArchSpec(Scalar); 1459 return {}; 1460 } 1461