1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "lldb/Utility/ArchSpec.h" 11 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" // for Stream 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" // for LLDB_INVALID_C... 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" // for Twine 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" // for CPUType::CPU_T... 21 #include "llvm/Support/Compiler.h" // for LLVM_FALLTHROUGH 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 105 ArchSpec::eCore_arm_aarch64, "aarch64"}, 106 107 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 108 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 109 "mips"}, 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 111 "mipsr2"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 113 "mipsr3"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 115 "mipsr5"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 117 "mipsr6"}, 118 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 119 "mipsel"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 121 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 128 129 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 130 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 131 "mips64"}, 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 133 "mips64r2"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 135 "mips64r3"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 137 "mips64r5"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 139 "mips64r6"}, 140 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 141 ArchSpec::eCore_mips64el, "mips64el"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 150 151 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 152 "powerpc"}, 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 154 "ppc601"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 156 "ppc602"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 158 "ppc603"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 160 "ppc603e"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 162 "ppc603ev"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 164 "ppc604"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 166 "ppc604e"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 168 "ppc620"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 170 "ppc750"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 172 "ppc7400"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 174 "ppc7450"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 176 "ppc970"}, 177 178 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 179 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 180 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 181 "powerpc64"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 183 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 184 185 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 186 ArchSpec::eCore_s390x_generic, "s390x"}, 187 188 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 189 ArchSpec::eCore_sparc_generic, "sparc"}, 190 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 191 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 192 193 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 194 "i386"}, 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 196 "i486"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 198 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 200 "i686"}, 201 202 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 203 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 206 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 207 ArchSpec::eCore_hexagon_generic, "hexagon"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 212 213 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 214 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 215 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 217 218 {eByteOrderBig, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba3, 219 "kalimba3"}, 220 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba4, 221 "kalimba4"}, 222 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba5, 223 "kalimba5"}}; 224 225 // Ensure that we have an entry in the g_core_definitions for each core. If you 226 // comment out an entry above, you will need to comment out the corresponding 227 // ArchSpec::Core enumeration. 228 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 229 ArchSpec::kNumCores, 230 "make sure we have one core definition for each core"); 231 232 struct ArchDefinitionEntry { 233 ArchSpec::Core core; 234 uint32_t cpu; 235 uint32_t sub; 236 uint32_t cpu_mask; 237 uint32_t sub_mask; 238 }; 239 240 struct ArchDefinition { 241 ArchitectureType type; 242 size_t num_entries; 243 const ArchDefinitionEntry *entries; 244 const char *name; 245 }; 246 247 size_t ArchSpec::AutoComplete(llvm::StringRef name, StringList &matches) { 248 if (!name.empty()) { 249 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 250 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, name)) 251 matches.AppendString(g_core_definitions[i].name); 252 } 253 } else { 254 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 255 matches.AppendString(g_core_definitions[i].name); 256 } 257 return matches.GetSize(); 258 } 259 260 #define CPU_ANY (UINT32_MAX) 261 262 //===----------------------------------------------------------------------===// 263 // A table that gets searched linearly for matches. This table is used to 264 // convert cpu type and subtypes to architecture names, and to convert 265 // architecture names to cpu types and subtypes. The ordering is important and 266 // allows the precedence to be set when the table is built. 267 #define SUBTYPE_MASK 0x00FFFFFFu 268 269 static const ArchDefinitionEntry g_macho_arch_entries[] = { 270 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 271 UINT32_MAX, UINT32_MAX}, 272 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 273 SUBTYPE_MASK}, 274 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 275 SUBTYPE_MASK}, 276 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 277 SUBTYPE_MASK}, 278 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 279 SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 303 SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 305 SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 307 SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 309 UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 317 SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 333 SUBTYPE_MASK}, 334 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 335 UINT32_MAX, UINT32_MAX}, 336 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 343 SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 361 SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 363 UINT32_MAX, SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 365 UINT32_MAX, SUBTYPE_MASK}, 366 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 367 UINT32_MAX, SUBTYPE_MASK}, 368 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 369 SUBTYPE_MASK}, 370 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 371 SUBTYPE_MASK}, 372 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 373 UINT32_MAX, SUBTYPE_MASK}, 374 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 375 UINT32_MAX, UINT32_MAX}, 376 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 379 SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 381 UINT32_MAX, SUBTYPE_MASK}, 382 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 383 UINT32_MAX, UINT32_MAX}, 384 // Catch any unknown mach architectures so we can always use the object and 385 // symbol mach-o files 386 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 387 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 388 0x00000000u}}; 389 390 static const ArchDefinition g_macho_arch_def = { 391 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 392 g_macho_arch_entries, "mach-o"}; 393 394 //===----------------------------------------------------------------------===// 395 // A table that gets searched linearly for matches. This table is used to 396 // convert cpu type and subtypes to architecture names, and to convert 397 // architecture names to cpu types and subtypes. The ordering is important and 398 // allows the precedence to be set when the table is built. 399 static const ArchDefinitionEntry g_elf_arch_entries[] = { 400 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 401 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 402 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 403 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 404 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 405 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 406 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 407 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 408 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 410 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 412 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 414 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 416 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 417 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 418 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 419 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 420 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 422 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 423 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 424 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 425 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 426 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 427 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 428 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 429 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 430 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 431 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 432 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 433 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 434 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 435 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 436 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 438 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 440 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 442 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 443 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 444 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 445 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 446 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 447 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 448 {ArchSpec::eCore_kalimba3, llvm::ELF::EM_CSR_KALIMBA, 449 llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 450 {ArchSpec::eCore_kalimba4, llvm::ELF::EM_CSR_KALIMBA, 451 llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 452 {ArchSpec::eCore_kalimba5, llvm::ELF::EM_CSR_KALIMBA, 453 llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu} // KALIMBA 454 }; 455 456 static const ArchDefinition g_elf_arch_def = { 457 eArchTypeELF, 458 llvm::array_lengthof(g_elf_arch_entries), 459 g_elf_arch_entries, 460 "elf", 461 }; 462 463 static const ArchDefinitionEntry g_coff_arch_entries[] = { 464 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 465 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 466 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 467 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 468 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 469 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 470 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 472 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 474 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 475 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 476 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 477 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 478 }; 479 480 static const ArchDefinition g_coff_arch_def = { 481 eArchTypeCOFF, 482 llvm::array_lengthof(g_coff_arch_entries), 483 g_coff_arch_entries, 484 "pe-coff", 485 }; 486 487 //===----------------------------------------------------------------------===// 488 // Table of all ArchDefinitions 489 static const ArchDefinition *g_arch_definitions[] = { 490 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 491 492 static const size_t k_num_arch_definitions = 493 llvm::array_lengthof(g_arch_definitions); 494 495 //===----------------------------------------------------------------------===// 496 // Static helper functions. 497 498 // Get the architecture definition for a given object type. 499 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 500 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 501 const ArchDefinition *def = g_arch_definitions[i]; 502 if (def->type == arch_type) 503 return def; 504 } 505 return nullptr; 506 } 507 508 // Get an architecture definition by name. 509 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 510 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 511 if (name.equals_lower(g_core_definitions[i].name)) 512 return &g_core_definitions[i]; 513 } 514 return nullptr; 515 } 516 517 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 518 if (core < llvm::array_lengthof(g_core_definitions)) 519 return &g_core_definitions[core]; 520 return nullptr; 521 } 522 523 // Get a definition entry by cpu type and subtype. 524 static const ArchDefinitionEntry * 525 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 526 if (def == nullptr) 527 return nullptr; 528 529 const ArchDefinitionEntry *entries = def->entries; 530 for (size_t i = 0; i < def->num_entries; ++i) { 531 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 532 if (entries[i].sub == (sub & entries[i].sub_mask)) 533 return &entries[i]; 534 } 535 return nullptr; 536 } 537 538 static const ArchDefinitionEntry * 539 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 540 if (def == nullptr) 541 return nullptr; 542 543 const ArchDefinitionEntry *entries = def->entries; 544 for (size_t i = 0; i < def->num_entries; ++i) { 545 if (entries[i].core == core) 546 return &entries[i]; 547 } 548 return nullptr; 549 } 550 551 //===----------------------------------------------------------------------===// 552 // Constructors and destructors. 553 554 ArchSpec::ArchSpec() {} 555 556 ArchSpec::ArchSpec(const char *triple_cstr) { 557 if (triple_cstr) 558 SetTriple(triple_cstr); 559 } 560 561 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 562 563 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 564 565 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 566 SetArchitecture(arch_type, cpu, subtype); 567 } 568 569 ArchSpec::~ArchSpec() = default; 570 571 //===----------------------------------------------------------------------===// 572 // Assignment and initialization. 573 574 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 575 if (this != &rhs) { 576 m_triple = rhs.m_triple; 577 m_core = rhs.m_core; 578 m_byte_order = rhs.m_byte_order; 579 m_distribution_id = rhs.m_distribution_id; 580 m_flags = rhs.m_flags; 581 } 582 return *this; 583 } 584 585 void ArchSpec::Clear() { 586 m_triple = llvm::Triple(); 587 m_core = kCore_invalid; 588 m_byte_order = eByteOrderInvalid; 589 m_distribution_id.Clear(); 590 m_flags = 0; 591 } 592 593 //===----------------------------------------------------------------------===// 594 // Predicates. 595 596 const char *ArchSpec::GetArchitectureName() const { 597 const CoreDefinition *core_def = FindCoreDefinition(m_core); 598 if (core_def) 599 return core_def->name; 600 return "unknown"; 601 } 602 603 bool ArchSpec::IsMIPS() const { 604 const llvm::Triple::ArchType machine = GetMachine(); 605 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 606 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) 607 return true; 608 return false; 609 } 610 611 std::string ArchSpec::GetTargetABI() const { 612 613 std::string abi; 614 615 if (IsMIPS()) { 616 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 617 case ArchSpec::eMIPSABI_N64: 618 abi = "n64"; 619 return abi; 620 case ArchSpec::eMIPSABI_N32: 621 abi = "n32"; 622 return abi; 623 case ArchSpec::eMIPSABI_O32: 624 abi = "o32"; 625 return abi; 626 default: 627 return abi; 628 } 629 } 630 return abi; 631 } 632 633 void ArchSpec::SetFlags(std::string elf_abi) { 634 635 uint32_t flag = GetFlags(); 636 if (IsMIPS()) { 637 if (elf_abi == "n64") 638 flag |= ArchSpec::eMIPSABI_N64; 639 else if (elf_abi == "n32") 640 flag |= ArchSpec::eMIPSABI_N32; 641 else if (elf_abi == "o32") 642 flag |= ArchSpec::eMIPSABI_O32; 643 } 644 SetFlags(flag); 645 } 646 647 std::string ArchSpec::GetClangTargetCPU() const { 648 std::string cpu; 649 const llvm::Triple::ArchType machine = GetMachine(); 650 651 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 652 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) { 653 switch (m_core) { 654 case ArchSpec::eCore_mips32: 655 case ArchSpec::eCore_mips32el: 656 cpu = "mips32"; 657 break; 658 case ArchSpec::eCore_mips32r2: 659 case ArchSpec::eCore_mips32r2el: 660 cpu = "mips32r2"; 661 break; 662 case ArchSpec::eCore_mips32r3: 663 case ArchSpec::eCore_mips32r3el: 664 cpu = "mips32r3"; 665 break; 666 case ArchSpec::eCore_mips32r5: 667 case ArchSpec::eCore_mips32r5el: 668 cpu = "mips32r5"; 669 break; 670 case ArchSpec::eCore_mips32r6: 671 case ArchSpec::eCore_mips32r6el: 672 cpu = "mips32r6"; 673 break; 674 case ArchSpec::eCore_mips64: 675 case ArchSpec::eCore_mips64el: 676 cpu = "mips64"; 677 break; 678 case ArchSpec::eCore_mips64r2: 679 case ArchSpec::eCore_mips64r2el: 680 cpu = "mips64r2"; 681 break; 682 case ArchSpec::eCore_mips64r3: 683 case ArchSpec::eCore_mips64r3el: 684 cpu = "mips64r3"; 685 break; 686 case ArchSpec::eCore_mips64r5: 687 case ArchSpec::eCore_mips64r5el: 688 cpu = "mips64r5"; 689 break; 690 case ArchSpec::eCore_mips64r6: 691 case ArchSpec::eCore_mips64r6el: 692 cpu = "mips64r6"; 693 break; 694 default: 695 break; 696 } 697 } 698 return cpu; 699 } 700 701 uint32_t ArchSpec::GetMachOCPUType() const { 702 const CoreDefinition *core_def = FindCoreDefinition(m_core); 703 if (core_def) { 704 const ArchDefinitionEntry *arch_def = 705 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 706 if (arch_def) { 707 return arch_def->cpu; 708 } 709 } 710 return LLDB_INVALID_CPUTYPE; 711 } 712 713 uint32_t ArchSpec::GetMachOCPUSubType() const { 714 const CoreDefinition *core_def = FindCoreDefinition(m_core); 715 if (core_def) { 716 const ArchDefinitionEntry *arch_def = 717 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 718 if (arch_def) { 719 return arch_def->sub; 720 } 721 } 722 return LLDB_INVALID_CPUTYPE; 723 } 724 725 uint32_t ArchSpec::GetDataByteSize() const { 726 switch (m_core) { 727 case eCore_kalimba3: 728 return 4; 729 case eCore_kalimba4: 730 return 1; 731 case eCore_kalimba5: 732 return 4; 733 default: 734 return 1; 735 } 736 return 1; 737 } 738 739 uint32_t ArchSpec::GetCodeByteSize() const { 740 switch (m_core) { 741 case eCore_kalimba3: 742 return 4; 743 case eCore_kalimba4: 744 return 1; 745 case eCore_kalimba5: 746 return 1; 747 default: 748 return 1; 749 } 750 return 1; 751 } 752 753 llvm::Triple::ArchType ArchSpec::GetMachine() const { 754 const CoreDefinition *core_def = FindCoreDefinition(m_core); 755 if (core_def) 756 return core_def->machine; 757 758 return llvm::Triple::UnknownArch; 759 } 760 761 const ConstString &ArchSpec::GetDistributionId() const { 762 return m_distribution_id; 763 } 764 765 void ArchSpec::SetDistributionId(const char *distribution_id) { 766 m_distribution_id.SetCString(distribution_id); 767 } 768 769 uint32_t ArchSpec::GetAddressByteSize() const { 770 const CoreDefinition *core_def = FindCoreDefinition(m_core); 771 if (core_def) { 772 if (core_def->machine == llvm::Triple::mips64 || 773 core_def->machine == llvm::Triple::mips64el) { 774 // For N32/O32 applications Address size is 4 bytes. 775 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 776 return 4; 777 } 778 return core_def->addr_byte_size; 779 } 780 return 0; 781 } 782 783 ByteOrder ArchSpec::GetDefaultEndian() const { 784 const CoreDefinition *core_def = FindCoreDefinition(m_core); 785 if (core_def) 786 return core_def->default_byte_order; 787 return eByteOrderInvalid; 788 } 789 790 bool ArchSpec::CharIsSignedByDefault() const { 791 switch (m_triple.getArch()) { 792 default: 793 return true; 794 795 case llvm::Triple::aarch64: 796 case llvm::Triple::aarch64_be: 797 case llvm::Triple::arm: 798 case llvm::Triple::armeb: 799 case llvm::Triple::thumb: 800 case llvm::Triple::thumbeb: 801 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 802 803 case llvm::Triple::ppc: 804 case llvm::Triple::ppc64: 805 return m_triple.isOSDarwin(); 806 807 case llvm::Triple::ppc64le: 808 case llvm::Triple::systemz: 809 case llvm::Triple::xcore: 810 return false; 811 } 812 } 813 814 lldb::ByteOrder ArchSpec::GetByteOrder() const { 815 if (m_byte_order == eByteOrderInvalid) 816 return GetDefaultEndian(); 817 return m_byte_order; 818 } 819 820 //===----------------------------------------------------------------------===// 821 // Mutators. 822 823 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 824 m_triple = triple; 825 UpdateCore(); 826 return IsValid(); 827 } 828 829 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 830 ArchSpec &arch) { 831 // Accept "12-10" or "12.10" as cpu type/subtype 832 if (triple_str.empty()) 833 return false; 834 835 size_t pos = triple_str.find_first_of("-."); 836 if (pos == llvm::StringRef::npos) 837 return false; 838 839 llvm::StringRef cpu_str = triple_str.substr(0, pos); 840 llvm::StringRef remainder = triple_str.substr(pos + 1); 841 if (cpu_str.empty() || remainder.empty()) 842 return false; 843 844 llvm::StringRef sub_str; 845 llvm::StringRef vendor; 846 llvm::StringRef os; 847 std::tie(sub_str, remainder) = remainder.split('-'); 848 std::tie(vendor, os) = remainder.split('-'); 849 850 uint32_t cpu = 0; 851 uint32_t sub = 0; 852 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 853 return false; 854 855 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 856 return false; 857 if (!vendor.empty() && !os.empty()) { 858 arch.GetTriple().setVendorName(vendor); 859 arch.GetTriple().setOSName(os); 860 } 861 862 return true; 863 } 864 865 bool ArchSpec::SetTriple(llvm::StringRef triple) { 866 if (triple.empty()) { 867 Clear(); 868 return false; 869 } 870 871 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 872 return true; 873 874 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 875 return IsValid(); 876 } 877 878 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 879 return !normalized_triple.getArchName().empty() && 880 normalized_triple.getOSName().empty() && 881 normalized_triple.getVendorName().empty() && 882 normalized_triple.getEnvironmentName().empty(); 883 } 884 885 void ArchSpec::MergeFrom(const ArchSpec &other) { 886 if (TripleVendorIsUnspecifiedUnknown() && 887 !other.TripleVendorIsUnspecifiedUnknown()) 888 GetTriple().setVendor(other.GetTriple().getVendor()); 889 if (TripleOSIsUnspecifiedUnknown() && !other.TripleOSIsUnspecifiedUnknown()) 890 GetTriple().setOS(other.GetTriple().getOS()); 891 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 892 GetTriple().setArch(other.GetTriple().getArch()); 893 894 // MachO unknown64 isn't really invalid as the debugger can still obtain 895 // information from the binary, e.g. line tables. As such, we don't update 896 // the core here. 897 if (other.GetCore() != eCore_uknownMach64) 898 UpdateCore(); 899 } 900 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 901 !TripleVendorWasSpecified()) { 902 if (other.TripleVendorWasSpecified()) 903 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 904 } 905 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 906 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 907 // adopt the specific arm core. 908 if (GetTriple().getArch() == llvm::Triple::arm && 909 other.GetTriple().getArch() == llvm::Triple::arm && 910 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 911 other.GetCore() != ArchSpec::eCore_arm_generic) { 912 m_core = other.GetCore(); 913 CoreUpdated(true); 914 } 915 if (GetFlags() == 0) { 916 SetFlags(other.GetFlags()); 917 } 918 } 919 920 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 921 uint32_t sub, uint32_t os) { 922 m_core = kCore_invalid; 923 bool update_triple = true; 924 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 925 if (arch_def) { 926 const ArchDefinitionEntry *arch_def_entry = 927 FindArchDefinitionEntry(arch_def, cpu, sub); 928 if (arch_def_entry) { 929 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 930 if (core_def) { 931 m_core = core_def->core; 932 update_triple = false; 933 // Always use the architecture name because it might be more 934 // descriptive than the architecture enum ("armv7" -> 935 // llvm::Triple::arm). 936 m_triple.setArchName(llvm::StringRef(core_def->name)); 937 if (arch_type == eArchTypeMachO) { 938 m_triple.setVendor(llvm::Triple::Apple); 939 940 // Don't set the OS. It could be simulator, macosx, ios, watchos, 941 // tvos. We could get close with the cpu type - but we can't get it 942 // right all of the time. Better to leave this unset so other 943 // sections of code will set it when they have more information. 944 // NB: don't call m_triple.setOS (llvm::Triple::UnknownOS). That sets 945 // the OSName to 946 // "unknown" and the ArchSpec::TripleVendorWasSpecified() method says 947 // that any OSName setting means it was specified. 948 } else if (arch_type == eArchTypeELF) { 949 switch (os) { 950 case llvm::ELF::ELFOSABI_AIX: 951 m_triple.setOS(llvm::Triple::OSType::AIX); 952 break; 953 case llvm::ELF::ELFOSABI_FREEBSD: 954 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 955 break; 956 case llvm::ELF::ELFOSABI_GNU: 957 m_triple.setOS(llvm::Triple::OSType::Linux); 958 break; 959 case llvm::ELF::ELFOSABI_NETBSD: 960 m_triple.setOS(llvm::Triple::OSType::NetBSD); 961 break; 962 case llvm::ELF::ELFOSABI_OPENBSD: 963 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 964 break; 965 case llvm::ELF::ELFOSABI_SOLARIS: 966 m_triple.setOS(llvm::Triple::OSType::Solaris); 967 break; 968 } 969 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 970 m_triple.setVendor(llvm::Triple::PC); 971 m_triple.setOS(llvm::Triple::Win32); 972 } else { 973 m_triple.setVendor(llvm::Triple::UnknownVendor); 974 m_triple.setOS(llvm::Triple::UnknownOS); 975 } 976 // Fall back onto setting the machine type if the arch by name 977 // failed... 978 if (m_triple.getArch() == llvm::Triple::UnknownArch) 979 m_triple.setArch(core_def->machine); 980 } 981 } 982 } 983 CoreUpdated(update_triple); 984 return IsValid(); 985 } 986 987 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 988 const CoreDefinition *core_def = FindCoreDefinition(m_core); 989 if (core_def) 990 return core_def->min_opcode_byte_size; 991 return 0; 992 } 993 994 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 995 const CoreDefinition *core_def = FindCoreDefinition(m_core); 996 if (core_def) 997 return core_def->max_opcode_byte_size; 998 return 0; 999 } 1000 1001 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 1002 return IsEqualTo(rhs, true); 1003 } 1004 1005 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 1006 return IsEqualTo(rhs, false); 1007 } 1008 1009 static bool isCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 1010 llvm::Triple::EnvironmentType rhs) { 1011 if (lhs == rhs) 1012 return true; 1013 1014 // If any of the environment is unknown then they are compatible 1015 if (lhs == llvm::Triple::UnknownEnvironment || 1016 rhs == llvm::Triple::UnknownEnvironment) 1017 return true; 1018 1019 // If one of the environment is Android and the other one is EABI then they 1020 // are considered to be compatible. This is required as a workaround for 1021 // shared libraries compiled for Android without the NOTE section indicating 1022 // that they are using the Android ABI. 1023 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 1024 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 1025 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1026 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1027 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1028 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1029 return true; 1030 1031 return false; 1032 } 1033 1034 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1035 // explicitly ignoring m_distribution_id in this method. 1036 1037 if (GetByteOrder() != rhs.GetByteOrder()) 1038 return false; 1039 1040 const ArchSpec::Core lhs_core = GetCore(); 1041 const ArchSpec::Core rhs_core = rhs.GetCore(); 1042 1043 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1044 1045 if (core_match) { 1046 const llvm::Triple &lhs_triple = GetTriple(); 1047 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1048 1049 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1050 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1051 if (lhs_triple_vendor != rhs_triple_vendor) { 1052 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1053 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1054 // Both architectures had the vendor specified, so if they aren't equal 1055 // then we return false 1056 if (rhs_vendor_specified && lhs_vendor_specified) 1057 return false; 1058 1059 // Only fail if both vendor types are not unknown 1060 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1061 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1062 return false; 1063 } 1064 1065 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1066 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1067 if (lhs_triple_os != rhs_triple_os) { 1068 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1069 const bool lhs_os_specified = TripleOSWasSpecified(); 1070 // Both architectures had the OS specified, so if they aren't equal then 1071 // we return false 1072 if (rhs_os_specified && lhs_os_specified) 1073 return false; 1074 1075 // Only fail if both os types are not unknown 1076 if (lhs_triple_os != llvm::Triple::UnknownOS && 1077 rhs_triple_os != llvm::Triple::UnknownOS) 1078 return false; 1079 } 1080 1081 const llvm::Triple::EnvironmentType lhs_triple_env = 1082 lhs_triple.getEnvironment(); 1083 const llvm::Triple::EnvironmentType rhs_triple_env = 1084 rhs_triple.getEnvironment(); 1085 1086 if (!isCompatibleEnvironment(lhs_triple_env, rhs_triple_env)) 1087 return false; 1088 return true; 1089 } 1090 return false; 1091 } 1092 1093 void ArchSpec::UpdateCore() { 1094 llvm::StringRef arch_name(m_triple.getArchName()); 1095 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1096 if (core_def) { 1097 m_core = core_def->core; 1098 // Set the byte order to the default byte order for an architecture. This 1099 // can be modified if needed for cases when cores handle both big and 1100 // little endian 1101 m_byte_order = core_def->default_byte_order; 1102 } else { 1103 Clear(); 1104 } 1105 } 1106 1107 //===----------------------------------------------------------------------===// 1108 // Helper methods. 1109 1110 void ArchSpec::CoreUpdated(bool update_triple) { 1111 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1112 if (core_def) { 1113 if (update_triple) 1114 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1115 m_byte_order = core_def->default_byte_order; 1116 } else { 1117 if (update_triple) 1118 m_triple = llvm::Triple(); 1119 m_byte_order = eByteOrderInvalid; 1120 } 1121 } 1122 1123 //===----------------------------------------------------------------------===// 1124 // Operators. 1125 1126 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1127 bool try_inverse, bool enforce_exact_match) { 1128 if (core1 == core2) 1129 return true; 1130 1131 switch (core1) { 1132 case ArchSpec::kCore_any: 1133 return true; 1134 1135 case ArchSpec::eCore_arm_generic: 1136 if (enforce_exact_match) 1137 break; 1138 LLVM_FALLTHROUGH; 1139 case ArchSpec::kCore_arm_any: 1140 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1141 return true; 1142 if (core2 >= ArchSpec::kCore_thumb_first && 1143 core2 <= ArchSpec::kCore_thumb_last) 1144 return true; 1145 if (core2 == ArchSpec::kCore_arm_any) 1146 return true; 1147 break; 1148 1149 case ArchSpec::kCore_x86_32_any: 1150 if ((core2 >= ArchSpec::kCore_x86_32_first && 1151 core2 <= ArchSpec::kCore_x86_32_last) || 1152 (core2 == ArchSpec::kCore_x86_32_any)) 1153 return true; 1154 break; 1155 1156 case ArchSpec::kCore_x86_64_any: 1157 if ((core2 >= ArchSpec::kCore_x86_64_first && 1158 core2 <= ArchSpec::kCore_x86_64_last) || 1159 (core2 == ArchSpec::kCore_x86_64_any)) 1160 return true; 1161 break; 1162 1163 case ArchSpec::kCore_ppc_any: 1164 if ((core2 >= ArchSpec::kCore_ppc_first && 1165 core2 <= ArchSpec::kCore_ppc_last) || 1166 (core2 == ArchSpec::kCore_ppc_any)) 1167 return true; 1168 break; 1169 1170 case ArchSpec::kCore_ppc64_any: 1171 if ((core2 >= ArchSpec::kCore_ppc64_first && 1172 core2 <= ArchSpec::kCore_ppc64_last) || 1173 (core2 == ArchSpec::kCore_ppc64_any)) 1174 return true; 1175 break; 1176 1177 case ArchSpec::eCore_arm_armv6m: 1178 if (!enforce_exact_match) { 1179 if (core2 == ArchSpec::eCore_arm_generic) 1180 return true; 1181 try_inverse = false; 1182 if (core2 == ArchSpec::eCore_arm_armv7) 1183 return true; 1184 if (core2 == ArchSpec::eCore_arm_armv6m) 1185 return true; 1186 } 1187 break; 1188 1189 case ArchSpec::kCore_hexagon_any: 1190 if ((core2 >= ArchSpec::kCore_hexagon_first && 1191 core2 <= ArchSpec::kCore_hexagon_last) || 1192 (core2 == ArchSpec::kCore_hexagon_any)) 1193 return true; 1194 break; 1195 1196 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1197 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1198 // ARMv7E-M - armv7em 1199 case ArchSpec::eCore_arm_armv7em: 1200 if (!enforce_exact_match) { 1201 if (core2 == ArchSpec::eCore_arm_generic) 1202 return true; 1203 if (core2 == ArchSpec::eCore_arm_armv7m) 1204 return true; 1205 if (core2 == ArchSpec::eCore_arm_armv6m) 1206 return true; 1207 if (core2 == ArchSpec::eCore_arm_armv7) 1208 return true; 1209 try_inverse = true; 1210 } 1211 break; 1212 1213 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1214 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1215 // ARMv7E-M - armv7em 1216 case ArchSpec::eCore_arm_armv7m: 1217 if (!enforce_exact_match) { 1218 if (core2 == ArchSpec::eCore_arm_generic) 1219 return true; 1220 if (core2 == ArchSpec::eCore_arm_armv6m) 1221 return true; 1222 if (core2 == ArchSpec::eCore_arm_armv7) 1223 return true; 1224 if (core2 == ArchSpec::eCore_arm_armv7em) 1225 return true; 1226 try_inverse = true; 1227 } 1228 break; 1229 1230 case ArchSpec::eCore_arm_armv7f: 1231 case ArchSpec::eCore_arm_armv7k: 1232 case ArchSpec::eCore_arm_armv7s: 1233 if (!enforce_exact_match) { 1234 if (core2 == ArchSpec::eCore_arm_generic) 1235 return true; 1236 if (core2 == ArchSpec::eCore_arm_armv7) 1237 return true; 1238 try_inverse = false; 1239 } 1240 break; 1241 1242 case ArchSpec::eCore_x86_64_x86_64h: 1243 if (!enforce_exact_match) { 1244 try_inverse = false; 1245 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1246 return true; 1247 } 1248 break; 1249 1250 case ArchSpec::eCore_arm_armv8: 1251 if (!enforce_exact_match) { 1252 if (core2 == ArchSpec::eCore_arm_arm64) 1253 return true; 1254 if (core2 == ArchSpec::eCore_arm_aarch64) 1255 return true; 1256 try_inverse = false; 1257 } 1258 break; 1259 1260 case ArchSpec::eCore_arm_aarch64: 1261 if (!enforce_exact_match) { 1262 if (core2 == ArchSpec::eCore_arm_arm64) 1263 return true; 1264 if (core2 == ArchSpec::eCore_arm_armv8) 1265 return true; 1266 try_inverse = false; 1267 } 1268 break; 1269 1270 case ArchSpec::eCore_arm_arm64: 1271 if (!enforce_exact_match) { 1272 if (core2 == ArchSpec::eCore_arm_aarch64) 1273 return true; 1274 if (core2 == ArchSpec::eCore_arm_armv8) 1275 return true; 1276 try_inverse = false; 1277 } 1278 break; 1279 1280 case ArchSpec::eCore_mips32: 1281 if (!enforce_exact_match) { 1282 if (core2 >= ArchSpec::kCore_mips32_first && 1283 core2 <= ArchSpec::kCore_mips32_last) 1284 return true; 1285 try_inverse = false; 1286 } 1287 break; 1288 1289 case ArchSpec::eCore_mips32el: 1290 if (!enforce_exact_match) { 1291 if (core2 >= ArchSpec::kCore_mips32el_first && 1292 core2 <= ArchSpec::kCore_mips32el_last) 1293 return true; 1294 try_inverse = true; 1295 } 1296 break; 1297 1298 case ArchSpec::eCore_mips64: 1299 if (!enforce_exact_match) { 1300 if (core2 >= ArchSpec::kCore_mips32_first && 1301 core2 <= ArchSpec::kCore_mips32_last) 1302 return true; 1303 if (core2 >= ArchSpec::kCore_mips64_first && 1304 core2 <= ArchSpec::kCore_mips64_last) 1305 return true; 1306 try_inverse = false; 1307 } 1308 break; 1309 1310 case ArchSpec::eCore_mips64el: 1311 if (!enforce_exact_match) { 1312 if (core2 >= ArchSpec::kCore_mips32el_first && 1313 core2 <= ArchSpec::kCore_mips32el_last) 1314 return true; 1315 if (core2 >= ArchSpec::kCore_mips64el_first && 1316 core2 <= ArchSpec::kCore_mips64el_last) 1317 return true; 1318 try_inverse = false; 1319 } 1320 break; 1321 1322 case ArchSpec::eCore_mips64r2: 1323 case ArchSpec::eCore_mips64r3: 1324 case ArchSpec::eCore_mips64r5: 1325 if (!enforce_exact_match) { 1326 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1327 return true; 1328 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1329 return true; 1330 try_inverse = false; 1331 } 1332 break; 1333 1334 case ArchSpec::eCore_mips64r2el: 1335 case ArchSpec::eCore_mips64r3el: 1336 case ArchSpec::eCore_mips64r5el: 1337 if (!enforce_exact_match) { 1338 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1339 return true; 1340 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1341 return true; 1342 try_inverse = false; 1343 } 1344 break; 1345 1346 case ArchSpec::eCore_mips32r2: 1347 case ArchSpec::eCore_mips32r3: 1348 case ArchSpec::eCore_mips32r5: 1349 if (!enforce_exact_match) { 1350 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1351 return true; 1352 } 1353 break; 1354 1355 case ArchSpec::eCore_mips32r2el: 1356 case ArchSpec::eCore_mips32r3el: 1357 case ArchSpec::eCore_mips32r5el: 1358 if (!enforce_exact_match) { 1359 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1360 return true; 1361 } 1362 break; 1363 1364 case ArchSpec::eCore_mips32r6: 1365 if (!enforce_exact_match) { 1366 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1367 return true; 1368 } 1369 break; 1370 1371 case ArchSpec::eCore_mips32r6el: 1372 if (!enforce_exact_match) { 1373 if (core2 == ArchSpec::eCore_mips32el || 1374 core2 == ArchSpec::eCore_mips32r6el) 1375 return true; 1376 } 1377 break; 1378 1379 case ArchSpec::eCore_mips64r6: 1380 if (!enforce_exact_match) { 1381 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1382 return true; 1383 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1384 return true; 1385 } 1386 break; 1387 1388 case ArchSpec::eCore_mips64r6el: 1389 if (!enforce_exact_match) { 1390 if (core2 == ArchSpec::eCore_mips32el || 1391 core2 == ArchSpec::eCore_mips32r6el) 1392 return true; 1393 if (core2 == ArchSpec::eCore_mips64el || 1394 core2 == ArchSpec::eCore_mips64r6el) 1395 return true; 1396 } 1397 break; 1398 1399 default: 1400 break; 1401 } 1402 if (try_inverse) 1403 return cores_match(core2, core1, false, enforce_exact_match); 1404 return false; 1405 } 1406 1407 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1408 const ArchSpec::Core lhs_core = lhs.GetCore(); 1409 const ArchSpec::Core rhs_core = rhs.GetCore(); 1410 return lhs_core < rhs_core; 1411 } 1412 1413 1414 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1415 return lhs.GetCore() == rhs.GetCore(); 1416 } 1417 1418 bool ArchSpec::IsFullySpecifiedTriple() const { 1419 const auto &user_specified_triple = GetTriple(); 1420 1421 bool user_triple_fully_specified = false; 1422 1423 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1424 TripleOSWasSpecified()) { 1425 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1426 TripleVendorWasSpecified()) { 1427 const unsigned unspecified = 0; 1428 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1429 user_triple_fully_specified = true; 1430 } 1431 } 1432 } 1433 1434 return user_triple_fully_specified; 1435 } 1436 1437 void ArchSpec::PiecewiseTripleCompare( 1438 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1439 bool &os_different, bool &os_version_different, bool &env_different) const { 1440 const llvm::Triple &me(GetTriple()); 1441 const llvm::Triple &them(other.GetTriple()); 1442 1443 arch_different = (me.getArch() != them.getArch()); 1444 1445 vendor_different = (me.getVendor() != them.getVendor()); 1446 1447 os_different = (me.getOS() != them.getOS()); 1448 1449 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1450 1451 env_different = (me.getEnvironment() != them.getEnvironment()); 1452 } 1453 1454 bool ArchSpec::IsAlwaysThumbInstructions() const { 1455 std::string Status; 1456 if (GetTriple().getArch() == llvm::Triple::arm || 1457 GetTriple().getArch() == llvm::Triple::thumb) { 1458 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1459 // 1460 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1461 // execute thumb instructions. We map the cores to arch names like this: 1462 // 1463 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1464 // Cortex-M7: armv7em 1465 1466 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1467 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1468 GetCore() == ArchSpec::Core::eCore_arm_armv6m) { 1469 return true; 1470 } 1471 } 1472 return false; 1473 } 1474 1475 void ArchSpec::DumpTriple(Stream &s) const { 1476 const llvm::Triple &triple = GetTriple(); 1477 llvm::StringRef arch_str = triple.getArchName(); 1478 llvm::StringRef vendor_str = triple.getVendorName(); 1479 llvm::StringRef os_str = triple.getOSName(); 1480 llvm::StringRef environ_str = triple.getEnvironmentName(); 1481 1482 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1483 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1484 os_str.empty() ? "*" : os_str.str().c_str()); 1485 1486 if (!environ_str.empty()) 1487 s.Printf("-%s", environ_str.str().c_str()); 1488 } 1489