1 //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 9 #include <cassert> 10 #include <stddef.h> 11 #include <vector> 12 13 #include "lldb/lldb-defines.h" 14 #include "llvm/Support/Compiler.h" 15 16 #include "RegisterInfoPOSIX_arm64.h" 17 18 // Based on RegisterContextDarwin_arm64.cpp 19 #define GPR_OFFSET(idx) ((idx)*8) 20 #define GPR_OFFSET_NAME(reg) \ 21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg)) 22 23 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR)) 24 #define FPU_OFFSET_NAME(reg) \ 25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \ 26 sizeof(RegisterInfoPOSIX_arm64::GPR)) 27 28 // This information is based on AArch64 with SVE architecture reference manual. 29 // AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR 30 // (First Fault) register and a VG (Vector Granule) pseudo register. 31 32 // SVE 16-byte quad word is the basic unit of expansion in vector length. 33 #define SVE_QUAD_WORD_BYTES 16 34 35 // Vector length is the multiplier which decides the no of quad words, 36 // (multiples of 128-bits or 16-bytes) present in a Z register. Vector length 37 // is decided during execution and can change at runtime. SVE AArch64 register 38 // infos have modes one for each valid value of vector length. A change in 39 // vector length requires register context to update sizes of SVE Z, P and FFR. 40 // Also register context needs to update byte offsets of all registers affected 41 // by the change in vector length. 42 #define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR) 43 44 #define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX 45 46 #define EXC_OFFSET_NAME(reg) \ 47 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \ 48 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 49 sizeof(RegisterInfoPOSIX_arm64::FPU)) 50 #define DBG_OFFSET_NAME(reg) \ 51 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \ 52 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 54 sizeof(RegisterInfoPOSIX_arm64::EXC)) 55 56 #define DEFINE_DBG(reg, i) \ 57 #reg, NULL, \ 58 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \ 59 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \ 60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 62 dbg_##reg##i }, \ 63 NULL, NULL, NULL, 0 64 #define REG_CONTEXT_SIZE \ 65 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 67 sizeof(RegisterInfoPOSIX_arm64::EXC)) 68 69 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 70 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 71 #include "RegisterInfos_arm64.h" 72 #include "RegisterInfos_arm64_sve.h" 73 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 74 75 // Number of register sets provided by this context. 76 enum { 77 k_num_gpr_registers = gpr_w28 - gpr_x0 + 1, 78 k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1, 79 k_num_sve_registers = sve_ffr - sve_vg + 1, 80 k_num_register_sets_default = 2, 81 k_num_register_sets = 3 82 }; 83 84 // ARM64 general purpose registers. 85 static const uint32_t g_gpr_regnums_arm64[] = { 86 gpr_x0, gpr_x1, gpr_x2, gpr_x3, 87 gpr_x4, gpr_x5, gpr_x6, gpr_x7, 88 gpr_x8, gpr_x9, gpr_x10, gpr_x11, 89 gpr_x12, gpr_x13, gpr_x14, gpr_x15, 90 gpr_x16, gpr_x17, gpr_x18, gpr_x19, 91 gpr_x20, gpr_x21, gpr_x22, gpr_x23, 92 gpr_x24, gpr_x25, gpr_x26, gpr_x27, 93 gpr_x28, gpr_fp, gpr_lr, gpr_sp, 94 gpr_pc, gpr_cpsr, gpr_w0, gpr_w1, 95 gpr_w2, gpr_w3, gpr_w4, gpr_w5, 96 gpr_w6, gpr_w7, gpr_w8, gpr_w9, 97 gpr_w10, gpr_w11, gpr_w12, gpr_w13, 98 gpr_w14, gpr_w15, gpr_w16, gpr_w17, 99 gpr_w18, gpr_w19, gpr_w20, gpr_w21, 100 gpr_w22, gpr_w23, gpr_w24, gpr_w25, 101 gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM}; 102 103 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 104 1) == k_num_gpr_registers, 105 "g_gpr_regnums_arm64 has wrong number of register infos"); 106 107 // ARM64 floating point registers. 108 static const uint32_t g_fpu_regnums_arm64[] = { 109 fpu_v0, fpu_v1, fpu_v2, 110 fpu_v3, fpu_v4, fpu_v5, 111 fpu_v6, fpu_v7, fpu_v8, 112 fpu_v9, fpu_v10, fpu_v11, 113 fpu_v12, fpu_v13, fpu_v14, 114 fpu_v15, fpu_v16, fpu_v17, 115 fpu_v18, fpu_v19, fpu_v20, 116 fpu_v21, fpu_v22, fpu_v23, 117 fpu_v24, fpu_v25, fpu_v26, 118 fpu_v27, fpu_v28, fpu_v29, 119 fpu_v30, fpu_v31, fpu_s0, 120 fpu_s1, fpu_s2, fpu_s3, 121 fpu_s4, fpu_s5, fpu_s6, 122 fpu_s7, fpu_s8, fpu_s9, 123 fpu_s10, fpu_s11, fpu_s12, 124 fpu_s13, fpu_s14, fpu_s15, 125 fpu_s16, fpu_s17, fpu_s18, 126 fpu_s19, fpu_s20, fpu_s21, 127 fpu_s22, fpu_s23, fpu_s24, 128 fpu_s25, fpu_s26, fpu_s27, 129 fpu_s28, fpu_s29, fpu_s30, 130 fpu_s31, fpu_d0, fpu_d1, 131 fpu_d2, fpu_d3, fpu_d4, 132 fpu_d5, fpu_d6, fpu_d7, 133 fpu_d8, fpu_d9, fpu_d10, 134 fpu_d11, fpu_d12, fpu_d13, 135 fpu_d14, fpu_d15, fpu_d16, 136 fpu_d17, fpu_d18, fpu_d19, 137 fpu_d20, fpu_d21, fpu_d22, 138 fpu_d23, fpu_d24, fpu_d25, 139 fpu_d26, fpu_d27, fpu_d28, 140 fpu_d29, fpu_d30, fpu_d31, 141 fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM}; 142 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 143 1) == k_num_fpr_registers, 144 "g_fpu_regnums_arm64 has wrong number of register infos"); 145 146 // ARM64 SVE registers. 147 static const uint32_t g_sve_regnums_arm64[] = { 148 sve_vg, sve_z0, sve_z1, 149 sve_z2, sve_z3, sve_z4, 150 sve_z5, sve_z6, sve_z7, 151 sve_z8, sve_z9, sve_z10, 152 sve_z11, sve_z12, sve_z13, 153 sve_z14, sve_z15, sve_z16, 154 sve_z17, sve_z18, sve_z19, 155 sve_z20, sve_z21, sve_z22, 156 sve_z23, sve_z24, sve_z25, 157 sve_z26, sve_z27, sve_z28, 158 sve_z29, sve_z30, sve_z31, 159 sve_p0, sve_p1, sve_p2, 160 sve_p3, sve_p4, sve_p5, 161 sve_p6, sve_p7, sve_p8, 162 sve_p9, sve_p10, sve_p11, 163 sve_p12, sve_p13, sve_p14, 164 sve_p15, sve_ffr, LLDB_INVALID_REGNUM}; 165 static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) - 166 1) == k_num_sve_registers, 167 "g_sve_regnums_arm64 has wrong number of register infos"); 168 169 // Register sets for ARM64. 170 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 171 {"General Purpose Registers", "gpr", k_num_gpr_registers, 172 g_gpr_regnums_arm64}, 173 {"Floating Point Registers", "fpu", k_num_fpr_registers, 174 g_fpu_regnums_arm64}, 175 {"Scalable Vector Extension Registers", "sve", k_num_sve_registers, 176 g_sve_regnums_arm64}}; 177 178 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64( 179 const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets) 180 : lldb_private::RegisterInfoAndSetInterface(target_arch), 181 m_opt_regsets(opt_regsets) { 182 switch (target_arch.GetMachine()) { 183 case llvm::Triple::aarch64: 184 case llvm::Triple::aarch64_32: { 185 m_register_set_p = g_reg_sets_arm64; 186 m_register_set_count = k_num_register_sets_default; 187 m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1); 188 m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1); 189 190 // Now configure register sets supported by current target. If we have a 191 // dynamic register set like MTE, Pointer Authentication regset then we need 192 // to create dynamic register infos and regset array. Push back all optional 193 // register infos and regset and calculate register offsets accordingly. 194 if (m_opt_regsets.AllSet(eRegsetMaskSVE)) { 195 m_register_info_p = g_register_infos_arm64_sve_le; 196 m_register_info_count = sve_ffr + 1; 197 m_per_regset_regnum_range[m_register_set_count++] = 198 std::make_pair(sve_vg, sve_ffr + 1); 199 } else { 200 m_register_info_p = g_register_infos_arm64_le; 201 m_register_info_count = fpu_fpcr + 1; 202 } 203 204 if (m_opt_regsets.AnySet(eRegsetMaskDynamic)) { 205 llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref = 206 llvm::makeArrayRef(m_register_info_p, m_register_info_count); 207 llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref = 208 llvm::makeArrayRef(m_register_set_p, m_register_set_count); 209 llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos)); 210 llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets)); 211 212 m_register_info_count = m_dynamic_reg_infos.size(); 213 m_register_info_p = m_dynamic_reg_infos.data(); 214 m_register_set_p = m_dynamic_reg_sets.data(); 215 m_register_set_count = m_dynamic_reg_sets.size(); 216 } 217 break; 218 } 219 default: 220 assert(false && "Unhandled target architecture."); 221 } 222 } 223 224 uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const { 225 return m_register_info_count; 226 } 227 228 size_t RegisterInfoPOSIX_arm64::GetGPRSize() const { 229 return sizeof(struct RegisterInfoPOSIX_arm64::GPR); 230 } 231 232 size_t RegisterInfoPOSIX_arm64::GetFPRSize() const { 233 return sizeof(struct RegisterInfoPOSIX_arm64::FPU); 234 } 235 236 const lldb_private::RegisterInfo * 237 RegisterInfoPOSIX_arm64::GetRegisterInfo() const { 238 return m_register_info_p; 239 } 240 241 size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const { 242 return m_register_set_count; 243 } 244 245 size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex( 246 uint32_t reg_index) const { 247 for (const auto ®set_range : m_per_regset_regnum_range) { 248 if (reg_index >= regset_range.second.first && 249 reg_index < regset_range.second.second) 250 return regset_range.first; 251 } 252 return LLDB_INVALID_REGNUM; 253 } 254 255 const lldb_private::RegisterSet * 256 RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const { 257 if (set_index < GetRegisterSetCount()) 258 return &m_register_set_p[set_index]; 259 return nullptr; 260 } 261 262 uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLength(uint32_t sve_vq) { 263 // sve_vq contains SVE Quad vector length in context of AArch64 SVE. 264 // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0. 265 // Also if an invalid or previously set vector length is passed to this 266 // function then it will exit immediately with previously set vector length. 267 if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq) 268 return m_vector_reg_vq; 269 270 // We cannot enable AArch64 only mode if SVE was enabled. 271 if (sve_vq == eVectorQuadwordAArch64 && 272 m_vector_reg_vq > eVectorQuadwordAArch64) 273 sve_vq = eVectorQuadwordAArch64SVE; 274 275 m_vector_reg_vq = sve_vq; 276 277 if (sve_vq == eVectorQuadwordAArch64) 278 return m_vector_reg_vq; 279 std::vector<lldb_private::RegisterInfo> ®_info_ref = 280 m_per_vq_reg_infos[sve_vq]; 281 282 if (reg_info_ref.empty()) { 283 reg_info_ref = llvm::makeArrayRef(m_register_info_p, m_register_info_count); 284 285 uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX; 286 reg_info_ref[fpu_fpsr].byte_offset = offset; 287 reg_info_ref[fpu_fpcr].byte_offset = offset + 4; 288 reg_info_ref[sve_vg].byte_offset = offset + 8; 289 offset += 16; 290 291 // Update Z registers size and offset 292 uint32_t s_reg_base = fpu_s0; 293 uint32_t d_reg_base = fpu_d0; 294 uint32_t v_reg_base = fpu_v0; 295 uint32_t z_reg_base = sve_z0; 296 297 for (uint32_t index = 0; index < 32; index++) { 298 reg_info_ref[s_reg_base + index].byte_offset = offset; 299 reg_info_ref[d_reg_base + index].byte_offset = offset; 300 reg_info_ref[v_reg_base + index].byte_offset = offset; 301 reg_info_ref[z_reg_base + index].byte_offset = offset; 302 303 reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES; 304 offset += reg_info_ref[z_reg_base + index].byte_size; 305 } 306 307 // Update P registers and FFR size and offset 308 for (uint32_t it = sve_p0; it <= sve_ffr; it++) { 309 reg_info_ref[it].byte_offset = offset; 310 reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8; 311 offset += reg_info_ref[it].byte_size; 312 } 313 314 for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) { 315 reg_info_ref[it].byte_offset = offset; 316 offset += reg_info_ref[it].byte_size; 317 } 318 319 m_per_vq_reg_infos[sve_vq] = reg_info_ref; 320 } 321 322 m_register_info_p = m_per_vq_reg_infos[sve_vq].data(); 323 return m_vector_reg_vq; 324 } 325 326 bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const { 327 if (m_vector_reg_vq > eVectorQuadwordAArch64) 328 return (sve_vg <= reg && reg <= sve_ffr); 329 else 330 return false; 331 } 332 333 bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const { 334 return (sve_z0 <= reg && reg <= sve_z31); 335 } 336 337 bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const { 338 return (sve_p0 <= reg && reg <= sve_p15); 339 } 340 341 bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const { 342 return sve_vg == reg; 343 } 344 345 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; } 346 347 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; } 348 349 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; } 350 351 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; } 352 353 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; } 354