1 //===-- RegisterContextPOSIX_x86.cpp ----------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include <cstring> 11 #include <errno.h> 12 #include <stdint.h> 13 14 #include "lldb/Core/DataBufferHeap.h" 15 #include "lldb/Core/DataExtractor.h" 16 #include "lldb/Core/RegisterValue.h" 17 #include "lldb/Core/Scalar.h" 18 #include "lldb/Target/Target.h" 19 #include "lldb/Target/Thread.h" 20 #include "lldb/Host/Endian.h" 21 #include "llvm/Support/Compiler.h" 22 23 #include "RegisterContext_x86.h" 24 #include "RegisterContextPOSIX_x86.h" 25 #include "Plugins/Process/elf-core/ProcessElfCore.h" 26 27 using namespace lldb_private; 28 using namespace lldb; 29 30 const uint32_t 31 g_gpr_regnums_i386[] = 32 { 33 gpr_eax_i386, 34 gpr_ebx_i386, 35 gpr_ecx_i386, 36 gpr_edx_i386, 37 gpr_edi_i386, 38 gpr_esi_i386, 39 gpr_ebp_i386, 40 gpr_esp_i386, 41 gpr_eip_i386, 42 gpr_eflags_i386, 43 gpr_cs_i386, 44 gpr_fs_i386, 45 gpr_gs_i386, 46 gpr_ss_i386, 47 gpr_ds_i386, 48 gpr_es_i386, 49 gpr_ax_i386, 50 gpr_bx_i386, 51 gpr_cx_i386, 52 gpr_dx_i386, 53 gpr_di_i386, 54 gpr_si_i386, 55 gpr_bp_i386, 56 gpr_sp_i386, 57 gpr_ah_i386, 58 gpr_bh_i386, 59 gpr_ch_i386, 60 gpr_dh_i386, 61 gpr_al_i386, 62 gpr_bl_i386, 63 gpr_cl_i386, 64 gpr_dl_i386, 65 LLDB_INVALID_REGNUM, // Register sets must be terminated with LLDB_INVALID_REGNUM. 66 }; 67 static_assert((sizeof(g_gpr_regnums_i386) / sizeof(g_gpr_regnums_i386[0])) - 1 == k_num_gpr_registers_i386, 68 "g_gpr_regnums_i386 has wrong number of register infos"); 69 70 const uint32_t 71 g_fpu_regnums_i386[] = 72 { 73 fpu_fctrl_i386, 74 fpu_fstat_i386, 75 fpu_ftag_i386, 76 fpu_fop_i386, 77 fpu_fiseg_i386, 78 fpu_fioff_i386, 79 fpu_foseg_i386, 80 fpu_fooff_i386, 81 fpu_mxcsr_i386, 82 fpu_mxcsrmask_i386, 83 fpu_st0_i386, 84 fpu_st1_i386, 85 fpu_st2_i386, 86 fpu_st3_i386, 87 fpu_st4_i386, 88 fpu_st5_i386, 89 fpu_st6_i386, 90 fpu_st7_i386, 91 fpu_mm0_i386, 92 fpu_mm1_i386, 93 fpu_mm2_i386, 94 fpu_mm3_i386, 95 fpu_mm4_i386, 96 fpu_mm5_i386, 97 fpu_mm6_i386, 98 fpu_mm7_i386, 99 fpu_xmm0_i386, 100 fpu_xmm1_i386, 101 fpu_xmm2_i386, 102 fpu_xmm3_i386, 103 fpu_xmm4_i386, 104 fpu_xmm5_i386, 105 fpu_xmm6_i386, 106 fpu_xmm7_i386, 107 LLDB_INVALID_REGNUM // Register sets must be terminated with LLDB_INVALID_REGNUM. 108 }; 109 static_assert((sizeof(g_fpu_regnums_i386) / sizeof(g_fpu_regnums_i386[0])) - 1 == k_num_fpr_registers_i386, 110 "g_fpu_regnums_i386 has wrong number of register infos"); 111 112 const uint32_t 113 g_avx_regnums_i386[] = 114 { 115 fpu_ymm0_i386, 116 fpu_ymm1_i386, 117 fpu_ymm2_i386, 118 fpu_ymm3_i386, 119 fpu_ymm4_i386, 120 fpu_ymm5_i386, 121 fpu_ymm6_i386, 122 fpu_ymm7_i386, 123 LLDB_INVALID_REGNUM // Register sets must be terminated with LLDB_INVALID_REGNUM. 124 }; 125 static_assert((sizeof(g_avx_regnums_i386) / sizeof(g_avx_regnums_i386[0])) - 1 == k_num_avx_registers_i386, 126 " g_avx_regnums_i386 has wrong number of register infos"); 127 128 static const 129 uint32_t g_gpr_regnums_x86_64[] = 130 { 131 gpr_rax_x86_64, 132 gpr_rbx_x86_64, 133 gpr_rcx_x86_64, 134 gpr_rdx_x86_64, 135 gpr_rdi_x86_64, 136 gpr_rsi_x86_64, 137 gpr_rbp_x86_64, 138 gpr_rsp_x86_64, 139 gpr_r8_x86_64, 140 gpr_r9_x86_64, 141 gpr_r10_x86_64, 142 gpr_r11_x86_64, 143 gpr_r12_x86_64, 144 gpr_r13_x86_64, 145 gpr_r14_x86_64, 146 gpr_r15_x86_64, 147 gpr_rip_x86_64, 148 gpr_rflags_x86_64, 149 gpr_cs_x86_64, 150 gpr_fs_x86_64, 151 gpr_gs_x86_64, 152 gpr_ss_x86_64, 153 gpr_ds_x86_64, 154 gpr_es_x86_64, 155 gpr_eax_x86_64, 156 gpr_ebx_x86_64, 157 gpr_ecx_x86_64, 158 gpr_edx_x86_64, 159 gpr_edi_x86_64, 160 gpr_esi_x86_64, 161 gpr_ebp_x86_64, 162 gpr_esp_x86_64, 163 gpr_r8d_x86_64, // Low 32 bits or r8 164 gpr_r9d_x86_64, // Low 32 bits or r9 165 gpr_r10d_x86_64, // Low 32 bits or r10 166 gpr_r11d_x86_64, // Low 32 bits or r11 167 gpr_r12d_x86_64, // Low 32 bits or r12 168 gpr_r13d_x86_64, // Low 32 bits or r13 169 gpr_r14d_x86_64, // Low 32 bits or r14 170 gpr_r15d_x86_64, // Low 32 bits or r15 171 gpr_ax_x86_64, 172 gpr_bx_x86_64, 173 gpr_cx_x86_64, 174 gpr_dx_x86_64, 175 gpr_di_x86_64, 176 gpr_si_x86_64, 177 gpr_bp_x86_64, 178 gpr_sp_x86_64, 179 gpr_r8w_x86_64, // Low 16 bits or r8 180 gpr_r9w_x86_64, // Low 16 bits or r9 181 gpr_r10w_x86_64, // Low 16 bits or r10 182 gpr_r11w_x86_64, // Low 16 bits or r11 183 gpr_r12w_x86_64, // Low 16 bits or r12 184 gpr_r13w_x86_64, // Low 16 bits or r13 185 gpr_r14w_x86_64, // Low 16 bits or r14 186 gpr_r15w_x86_64, // Low 16 bits or r15 187 gpr_ah_x86_64, 188 gpr_bh_x86_64, 189 gpr_ch_x86_64, 190 gpr_dh_x86_64, 191 gpr_al_x86_64, 192 gpr_bl_x86_64, 193 gpr_cl_x86_64, 194 gpr_dl_x86_64, 195 gpr_dil_x86_64, 196 gpr_sil_x86_64, 197 gpr_bpl_x86_64, 198 gpr_spl_x86_64, 199 gpr_r8l_x86_64, // Low 8 bits or r8 200 gpr_r9l_x86_64, // Low 8 bits or r9 201 gpr_r10l_x86_64, // Low 8 bits or r10 202 gpr_r11l_x86_64, // Low 8 bits or r11 203 gpr_r12l_x86_64, // Low 8 bits or r12 204 gpr_r13l_x86_64, // Low 8 bits or r13 205 gpr_r14l_x86_64, // Low 8 bits or r14 206 gpr_r15l_x86_64, // Low 8 bits or r15 207 LLDB_INVALID_REGNUM // Register sets must be terminated with LLDB_INVALID_REGNUM. 208 }; 209 static_assert((sizeof(g_gpr_regnums_x86_64) / sizeof(g_gpr_regnums_x86_64[0])) - 1 == k_num_gpr_registers_x86_64, 210 "g_gpr_regnums_x86_64 has wrong number of register infos"); 211 212 static const uint32_t 213 g_fpu_regnums_x86_64[] = 214 { 215 fpu_fctrl_x86_64, 216 fpu_fstat_x86_64, 217 fpu_ftag_x86_64, 218 fpu_fop_x86_64, 219 fpu_fiseg_x86_64, 220 fpu_fioff_x86_64, 221 fpu_foseg_x86_64, 222 fpu_fooff_x86_64, 223 fpu_mxcsr_x86_64, 224 fpu_mxcsrmask_x86_64, 225 fpu_st0_x86_64, 226 fpu_st1_x86_64, 227 fpu_st2_x86_64, 228 fpu_st3_x86_64, 229 fpu_st4_x86_64, 230 fpu_st5_x86_64, 231 fpu_st6_x86_64, 232 fpu_st7_x86_64, 233 fpu_mm0_x86_64, 234 fpu_mm1_x86_64, 235 fpu_mm2_x86_64, 236 fpu_mm3_x86_64, 237 fpu_mm4_x86_64, 238 fpu_mm5_x86_64, 239 fpu_mm6_x86_64, 240 fpu_mm7_x86_64, 241 fpu_xmm0_x86_64, 242 fpu_xmm1_x86_64, 243 fpu_xmm2_x86_64, 244 fpu_xmm3_x86_64, 245 fpu_xmm4_x86_64, 246 fpu_xmm5_x86_64, 247 fpu_xmm6_x86_64, 248 fpu_xmm7_x86_64, 249 fpu_xmm8_x86_64, 250 fpu_xmm9_x86_64, 251 fpu_xmm10_x86_64, 252 fpu_xmm11_x86_64, 253 fpu_xmm12_x86_64, 254 fpu_xmm13_x86_64, 255 fpu_xmm14_x86_64, 256 fpu_xmm15_x86_64, 257 LLDB_INVALID_REGNUM // Register sets must be terminated with LLDB_INVALID_REGNUM. 258 }; 259 static_assert((sizeof(g_fpu_regnums_x86_64) / sizeof(g_fpu_regnums_x86_64[0])) - 1 == k_num_fpr_registers_x86_64, 260 "g_fpu_regnums_x86_64 has wrong number of register infos"); 261 262 static const uint32_t 263 g_avx_regnums_x86_64[] = 264 { 265 fpu_ymm0_x86_64, 266 fpu_ymm1_x86_64, 267 fpu_ymm2_x86_64, 268 fpu_ymm3_x86_64, 269 fpu_ymm4_x86_64, 270 fpu_ymm5_x86_64, 271 fpu_ymm6_x86_64, 272 fpu_ymm7_x86_64, 273 fpu_ymm8_x86_64, 274 fpu_ymm9_x86_64, 275 fpu_ymm10_x86_64, 276 fpu_ymm11_x86_64, 277 fpu_ymm12_x86_64, 278 fpu_ymm13_x86_64, 279 fpu_ymm14_x86_64, 280 fpu_ymm15_x86_64, 281 LLDB_INVALID_REGNUM // Register sets must be terminated with LLDB_INVALID_REGNUM. 282 }; 283 static_assert((sizeof(g_avx_regnums_x86_64) / sizeof(g_avx_regnums_x86_64[0])) - 1 == k_num_avx_registers_x86_64, 284 "g_avx_regnums_x86_64 has wrong number of register infos"); 285 286 uint32_t RegisterContextPOSIX_x86::g_contained_eax[] = { gpr_eax_i386, LLDB_INVALID_REGNUM }; 287 uint32_t RegisterContextPOSIX_x86::g_contained_ebx[] = { gpr_ebx_i386, LLDB_INVALID_REGNUM }; 288 uint32_t RegisterContextPOSIX_x86::g_contained_ecx[] = { gpr_ecx_i386, LLDB_INVALID_REGNUM }; 289 uint32_t RegisterContextPOSIX_x86::g_contained_edx[] = { gpr_edx_i386, LLDB_INVALID_REGNUM }; 290 uint32_t RegisterContextPOSIX_x86::g_contained_edi[] = { gpr_edi_i386, LLDB_INVALID_REGNUM }; 291 uint32_t RegisterContextPOSIX_x86::g_contained_esi[] = { gpr_esi_i386, LLDB_INVALID_REGNUM }; 292 uint32_t RegisterContextPOSIX_x86::g_contained_ebp[] = { gpr_ebp_i386, LLDB_INVALID_REGNUM }; 293 uint32_t RegisterContextPOSIX_x86::g_contained_esp[] = { gpr_esp_i386, LLDB_INVALID_REGNUM }; 294 295 uint32_t RegisterContextPOSIX_x86::g_invalidate_eax[] = { gpr_eax_i386, gpr_ax_i386, gpr_ah_i386, gpr_al_i386, LLDB_INVALID_REGNUM }; 296 uint32_t RegisterContextPOSIX_x86::g_invalidate_ebx[] = { gpr_ebx_i386, gpr_bx_i386, gpr_bh_i386, gpr_bl_i386, LLDB_INVALID_REGNUM }; 297 uint32_t RegisterContextPOSIX_x86::g_invalidate_ecx[] = { gpr_ecx_i386, gpr_cx_i386, gpr_ch_i386, gpr_cl_i386, LLDB_INVALID_REGNUM }; 298 uint32_t RegisterContextPOSIX_x86::g_invalidate_edx[] = { gpr_edx_i386, gpr_dx_i386, gpr_dh_i386, gpr_dl_i386, LLDB_INVALID_REGNUM }; 299 uint32_t RegisterContextPOSIX_x86::g_invalidate_edi[] = { gpr_edi_i386, gpr_di_i386, LLDB_INVALID_REGNUM }; 300 uint32_t RegisterContextPOSIX_x86::g_invalidate_esi[] = { gpr_esi_i386, gpr_si_i386, LLDB_INVALID_REGNUM }; 301 uint32_t RegisterContextPOSIX_x86::g_invalidate_ebp[] = { gpr_ebp_i386, gpr_bp_i386, LLDB_INVALID_REGNUM }; 302 uint32_t RegisterContextPOSIX_x86::g_invalidate_esp[] = { gpr_esp_i386, gpr_sp_i386, LLDB_INVALID_REGNUM }; 303 304 uint32_t RegisterContextPOSIX_x86::g_contained_rax[] = { gpr_rax_x86_64, LLDB_INVALID_REGNUM }; 305 uint32_t RegisterContextPOSIX_x86::g_contained_rbx[] = { gpr_rbx_x86_64, LLDB_INVALID_REGNUM }; 306 uint32_t RegisterContextPOSIX_x86::g_contained_rcx[] = { gpr_rcx_x86_64, LLDB_INVALID_REGNUM }; 307 uint32_t RegisterContextPOSIX_x86::g_contained_rdx[] = { gpr_rdx_x86_64, LLDB_INVALID_REGNUM }; 308 uint32_t RegisterContextPOSIX_x86::g_contained_rdi[] = { gpr_rdi_x86_64, LLDB_INVALID_REGNUM }; 309 uint32_t RegisterContextPOSIX_x86::g_contained_rsi[] = { gpr_rsi_x86_64, LLDB_INVALID_REGNUM }; 310 uint32_t RegisterContextPOSIX_x86::g_contained_rbp[] = { gpr_rbp_x86_64, LLDB_INVALID_REGNUM }; 311 uint32_t RegisterContextPOSIX_x86::g_contained_rsp[] = { gpr_rsp_x86_64, LLDB_INVALID_REGNUM }; 312 uint32_t RegisterContextPOSIX_x86::g_contained_r8[] = { gpr_r8_x86_64, LLDB_INVALID_REGNUM }; 313 uint32_t RegisterContextPOSIX_x86::g_contained_r9[] = { gpr_r9_x86_64, LLDB_INVALID_REGNUM }; 314 uint32_t RegisterContextPOSIX_x86::g_contained_r10[] = { gpr_r10_x86_64, LLDB_INVALID_REGNUM }; 315 uint32_t RegisterContextPOSIX_x86::g_contained_r11[] = { gpr_r11_x86_64, LLDB_INVALID_REGNUM }; 316 uint32_t RegisterContextPOSIX_x86::g_contained_r12[] = { gpr_r12_x86_64, LLDB_INVALID_REGNUM }; 317 uint32_t RegisterContextPOSIX_x86::g_contained_r13[] = { gpr_r13_x86_64, LLDB_INVALID_REGNUM }; 318 uint32_t RegisterContextPOSIX_x86::g_contained_r14[] = { gpr_r14_x86_64, LLDB_INVALID_REGNUM }; 319 uint32_t RegisterContextPOSIX_x86::g_contained_r15[] = { gpr_r15_x86_64, LLDB_INVALID_REGNUM }; 320 321 uint32_t RegisterContextPOSIX_x86::g_invalidate_rax[] = { gpr_rax_x86_64, gpr_eax_x86_64, gpr_ax_x86_64, gpr_ah_x86_64, gpr_al_x86_64, LLDB_INVALID_REGNUM }; 322 uint32_t RegisterContextPOSIX_x86::g_invalidate_rbx[] = { gpr_rbx_x86_64, gpr_ebx_x86_64, gpr_bx_x86_64, gpr_bh_x86_64, gpr_bl_x86_64, LLDB_INVALID_REGNUM }; 323 uint32_t RegisterContextPOSIX_x86::g_invalidate_rcx[] = { gpr_rcx_x86_64, gpr_ecx_x86_64, gpr_cx_x86_64, gpr_ch_x86_64, gpr_cl_x86_64, LLDB_INVALID_REGNUM }; 324 uint32_t RegisterContextPOSIX_x86::g_invalidate_rdx[] = { gpr_rdx_x86_64, gpr_edx_x86_64, gpr_dx_x86_64, gpr_dh_x86_64, gpr_dl_x86_64, LLDB_INVALID_REGNUM }; 325 uint32_t RegisterContextPOSIX_x86::g_invalidate_rdi[] = { gpr_rdi_x86_64, gpr_edi_x86_64, gpr_di_x86_64, gpr_dil_x86_64, LLDB_INVALID_REGNUM }; 326 uint32_t RegisterContextPOSIX_x86::g_invalidate_rsi[] = { gpr_rsi_x86_64, gpr_esi_x86_64, gpr_si_x86_64, gpr_sil_x86_64, LLDB_INVALID_REGNUM }; 327 uint32_t RegisterContextPOSIX_x86::g_invalidate_rbp[] = { gpr_rbp_x86_64, gpr_ebp_x86_64, gpr_bp_x86_64, gpr_bpl_x86_64, LLDB_INVALID_REGNUM }; 328 uint32_t RegisterContextPOSIX_x86::g_invalidate_rsp[] = { gpr_rsp_x86_64, gpr_esp_x86_64, gpr_sp_x86_64, gpr_spl_x86_64, LLDB_INVALID_REGNUM }; 329 uint32_t RegisterContextPOSIX_x86::g_invalidate_r8[] = { gpr_r8_x86_64, gpr_r8d_x86_64, gpr_r8w_x86_64, gpr_r8l_x86_64, LLDB_INVALID_REGNUM }; 330 uint32_t RegisterContextPOSIX_x86::g_invalidate_r9[] = { gpr_r9_x86_64, gpr_r9d_x86_64, gpr_r9w_x86_64, gpr_r9l_x86_64, LLDB_INVALID_REGNUM }; 331 uint32_t RegisterContextPOSIX_x86::g_invalidate_r10[] = { gpr_r10_x86_64, gpr_r10d_x86_64, gpr_r10w_x86_64, gpr_r10l_x86_64, LLDB_INVALID_REGNUM }; 332 uint32_t RegisterContextPOSIX_x86::g_invalidate_r11[] = { gpr_r11_x86_64, gpr_r11d_x86_64, gpr_r11w_x86_64, gpr_r11l_x86_64, LLDB_INVALID_REGNUM }; 333 uint32_t RegisterContextPOSIX_x86::g_invalidate_r12[] = { gpr_r12_x86_64, gpr_r12d_x86_64, gpr_r12w_x86_64, gpr_r12l_x86_64, LLDB_INVALID_REGNUM }; 334 uint32_t RegisterContextPOSIX_x86::g_invalidate_r13[] = { gpr_r13_x86_64, gpr_r13d_x86_64, gpr_r13w_x86_64, gpr_r13l_x86_64, LLDB_INVALID_REGNUM }; 335 uint32_t RegisterContextPOSIX_x86::g_invalidate_r14[] = { gpr_r14_x86_64, gpr_r14d_x86_64, gpr_r14w_x86_64, gpr_r14l_x86_64, LLDB_INVALID_REGNUM }; 336 uint32_t RegisterContextPOSIX_x86::g_invalidate_r15[] = { gpr_r15_x86_64, gpr_r15d_x86_64, gpr_r15w_x86_64, gpr_r15l_x86_64, LLDB_INVALID_REGNUM }; 337 338 // Number of register sets provided by this context. 339 enum 340 { 341 k_num_extended_register_sets = 1, 342 k_num_register_sets = 3 343 }; 344 345 static const RegisterSet 346 g_reg_sets_i386[k_num_register_sets] = 347 { 348 { "General Purpose Registers", "gpr", k_num_gpr_registers_i386, g_gpr_regnums_i386 }, 349 { "Floating Point Registers", "fpu", k_num_fpr_registers_i386, g_fpu_regnums_i386 }, 350 { "Advanced Vector Extensions", "avx", k_num_avx_registers_i386, g_avx_regnums_i386 } 351 }; 352 353 static const RegisterSet 354 g_reg_sets_x86_64[k_num_register_sets] = 355 { 356 { "General Purpose Registers", "gpr", k_num_gpr_registers_x86_64, g_gpr_regnums_x86_64 }, 357 { "Floating Point Registers", "fpu", k_num_fpr_registers_x86_64, g_fpu_regnums_x86_64 }, 358 { "Advanced Vector Extensions", "avx", k_num_avx_registers_x86_64, g_avx_regnums_x86_64 } 359 }; 360 361 bool RegisterContextPOSIX_x86::IsGPR(unsigned reg) 362 { 363 return reg <= m_reg_info.last_gpr; // GPR's come first. 364 } 365 366 bool RegisterContextPOSIX_x86::IsFPR(unsigned reg) 367 { 368 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); 369 } 370 371 bool RegisterContextPOSIX_x86::IsAVX(unsigned reg) 372 { 373 return (m_reg_info.first_ymm <= reg && reg <= m_reg_info.last_ymm); 374 } 375 376 bool RegisterContextPOSIX_x86::IsFPR(unsigned reg, FPRType fpr_type) 377 { 378 bool generic_fpr = IsFPR(reg); 379 380 if (fpr_type == eXSAVE) 381 return generic_fpr || IsAVX(reg); 382 return generic_fpr; 383 } 384 385 RegisterContextPOSIX_x86::RegisterContextPOSIX_x86(Thread &thread, 386 uint32_t concrete_frame_idx, 387 RegisterInfoInterface *register_info) 388 : RegisterContext(thread, concrete_frame_idx) 389 { 390 m_register_info_ap.reset(register_info); 391 392 switch (register_info->m_target_arch.GetMachine()) 393 { 394 case llvm::Triple::x86: 395 m_reg_info.num_registers = k_num_registers_i386; 396 m_reg_info.num_gpr_registers = k_num_gpr_registers_i386; 397 m_reg_info.num_fpr_registers = k_num_fpr_registers_i386; 398 m_reg_info.num_avx_registers = k_num_avx_registers_i386; 399 m_reg_info.last_gpr = k_last_gpr_i386; 400 m_reg_info.first_fpr = k_first_fpr_i386; 401 m_reg_info.last_fpr = k_last_fpr_i386; 402 m_reg_info.first_st = fpu_st0_i386; 403 m_reg_info.last_st = fpu_st7_i386; 404 m_reg_info.first_mm = fpu_mm0_i386; 405 m_reg_info.last_mm = fpu_mm7_i386; 406 m_reg_info.first_xmm = fpu_xmm0_i386; 407 m_reg_info.last_xmm = fpu_xmm7_i386; 408 m_reg_info.first_ymm = fpu_ymm0_i386; 409 m_reg_info.last_ymm = fpu_ymm7_i386; 410 m_reg_info.first_dr = dr0_i386; 411 m_reg_info.gpr_flags = gpr_eflags_i386; 412 break; 413 case llvm::Triple::x86_64: 414 m_reg_info.num_registers = k_num_registers_x86_64; 415 m_reg_info.num_gpr_registers = k_num_gpr_registers_x86_64; 416 m_reg_info.num_fpr_registers = k_num_fpr_registers_x86_64; 417 m_reg_info.num_avx_registers = k_num_avx_registers_x86_64; 418 m_reg_info.last_gpr = k_last_gpr_x86_64; 419 m_reg_info.first_fpr = k_first_fpr_x86_64; 420 m_reg_info.last_fpr = k_last_fpr_x86_64; 421 m_reg_info.first_st = fpu_st0_x86_64; 422 m_reg_info.last_st = fpu_st7_x86_64; 423 m_reg_info.first_mm = fpu_mm0_x86_64; 424 m_reg_info.last_mm = fpu_mm7_x86_64; 425 m_reg_info.first_xmm = fpu_xmm0_x86_64; 426 m_reg_info.last_xmm = fpu_xmm15_x86_64; 427 m_reg_info.first_ymm = fpu_ymm0_x86_64; 428 m_reg_info.last_ymm = fpu_ymm15_x86_64; 429 m_reg_info.first_dr = dr0_x86_64; 430 m_reg_info.gpr_flags = gpr_rflags_x86_64; 431 break; 432 default: 433 assert(false && "Unhandled target architecture."); 434 break; 435 } 436 437 // Initialize m_iovec to point to the buffer and buffer size 438 // using the conventions of Berkeley style UIO structures, as required 439 // by PTRACE extensions. 440 m_iovec.iov_base = &m_fpr.xstate.xsave; 441 m_iovec.iov_len = sizeof(m_fpr.xstate.xsave); 442 443 ::memset(&m_fpr, 0, sizeof(FPR)); 444 445 // elf-core yet to support ReadFPR() 446 ProcessSP base = CalculateProcess(); 447 if (base.get()->GetPluginName() == ProcessElfCore::GetPluginNameStatic()) 448 return; 449 450 m_fpr_type = eNotValid; 451 } 452 453 RegisterContextPOSIX_x86::~RegisterContextPOSIX_x86() 454 { 455 } 456 457 RegisterContextPOSIX_x86::FPRType RegisterContextPOSIX_x86::GetFPRType() 458 { 459 if (m_fpr_type == eNotValid) 460 { 461 // TODO: Use assembly to call cpuid on the inferior and query ebx or ecx 462 m_fpr_type = eXSAVE; // extended floating-point registers, if available 463 if (false == ReadFPR()) 464 m_fpr_type = eFXSAVE; // assume generic floating-point registers 465 } 466 return m_fpr_type; 467 } 468 469 void 470 RegisterContextPOSIX_x86::Invalidate() 471 { 472 } 473 474 void 475 RegisterContextPOSIX_x86::InvalidateAllRegisters() 476 { 477 } 478 479 unsigned 480 RegisterContextPOSIX_x86::GetRegisterOffset(unsigned reg) 481 { 482 assert(reg < m_reg_info.num_registers && "Invalid register number."); 483 return GetRegisterInfo()[reg].byte_offset; 484 } 485 486 unsigned 487 RegisterContextPOSIX_x86::GetRegisterSize(unsigned reg) 488 { 489 assert(reg < m_reg_info.num_registers && "Invalid register number."); 490 return GetRegisterInfo()[reg].byte_size; 491 } 492 493 size_t 494 RegisterContextPOSIX_x86::GetRegisterCount() 495 { 496 size_t num_registers = m_reg_info.num_gpr_registers + m_reg_info.num_fpr_registers; 497 if (GetFPRType() == eXSAVE) 498 return num_registers + m_reg_info.num_avx_registers; 499 return num_registers; 500 } 501 502 size_t 503 RegisterContextPOSIX_x86::GetGPRSize() 504 { 505 return m_register_info_ap->GetGPRSize (); 506 } 507 508 const RegisterInfo * 509 RegisterContextPOSIX_x86::GetRegisterInfo() 510 { 511 // Commonly, this method is overridden and g_register_infos is copied and specialized. 512 // So, use GetRegisterInfo() rather than g_register_infos in this scope. 513 return m_register_info_ap->GetRegisterInfo (); 514 } 515 516 const RegisterInfo * 517 RegisterContextPOSIX_x86::GetRegisterInfoAtIndex(size_t reg) 518 { 519 if (reg < m_reg_info.num_registers) 520 return &GetRegisterInfo()[reg]; 521 else 522 return NULL; 523 } 524 525 size_t 526 RegisterContextPOSIX_x86::GetRegisterSetCount() 527 { 528 size_t sets = 0; 529 for (size_t set = 0; set < k_num_register_sets; ++set) 530 { 531 if (IsRegisterSetAvailable(set)) 532 ++sets; 533 } 534 535 return sets; 536 } 537 538 const RegisterSet * 539 RegisterContextPOSIX_x86::GetRegisterSet(size_t set) 540 { 541 if (IsRegisterSetAvailable(set)) 542 { 543 switch (m_register_info_ap->m_target_arch.GetMachine()) 544 { 545 case llvm::Triple::x86: 546 return &g_reg_sets_i386[set]; 547 case llvm::Triple::x86_64: 548 return &g_reg_sets_x86_64[set]; 549 default: 550 assert(false && "Unhandled target architecture."); 551 return NULL; 552 } 553 } 554 return NULL; 555 } 556 557 const char * 558 RegisterContextPOSIX_x86::GetRegisterName(unsigned reg) 559 { 560 assert(reg < m_reg_info.num_registers && "Invalid register offset."); 561 return GetRegisterInfo()[reg].name; 562 } 563 564 lldb::ByteOrder 565 RegisterContextPOSIX_x86::GetByteOrder() 566 { 567 // Get the target process whose privileged thread was used for the register read. 568 lldb::ByteOrder byte_order = eByteOrderInvalid; 569 Process *process = CalculateProcess().get(); 570 571 if (process) 572 byte_order = process->GetByteOrder(); 573 return byte_order; 574 } 575 576 // Parse ymm registers and into xmm.bytes and ymmh.bytes. 577 bool RegisterContextPOSIX_x86::CopyYMMtoXSTATE(uint32_t reg, lldb::ByteOrder byte_order) 578 { 579 if (!IsAVX(reg)) 580 return false; 581 582 if (byte_order == eByteOrderLittle) 583 { 584 ::memcpy(m_fpr.xstate.fxsave.xmm[reg - m_reg_info.first_ymm].bytes, 585 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes, 586 sizeof(XMMReg)); 587 ::memcpy(m_fpr.xstate.xsave.ymmh[reg - m_reg_info.first_ymm].bytes, 588 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes + sizeof(XMMReg), 589 sizeof(YMMHReg)); 590 return true; 591 } 592 593 if (byte_order == eByteOrderBig) 594 { 595 ::memcpy(m_fpr.xstate.fxsave.xmm[reg - m_reg_info.first_ymm].bytes, 596 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes + sizeof(XMMReg), 597 sizeof(XMMReg)); 598 ::memcpy(m_fpr.xstate.xsave.ymmh[reg - m_reg_info.first_ymm].bytes, 599 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes, 600 sizeof(YMMHReg)); 601 return true; 602 } 603 return false; // unsupported or invalid byte order 604 } 605 606 // Concatenate xmm.bytes with ymmh.bytes 607 bool RegisterContextPOSIX_x86::CopyXSTATEtoYMM(uint32_t reg, lldb::ByteOrder byte_order) 608 { 609 if (!IsAVX(reg)) 610 return false; 611 612 if (byte_order == eByteOrderLittle) 613 { 614 ::memcpy(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes, 615 m_fpr.xstate.fxsave.xmm[reg - m_reg_info.first_ymm].bytes, 616 sizeof(XMMReg)); 617 ::memcpy(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes + sizeof(XMMReg), 618 m_fpr.xstate.xsave.ymmh[reg - m_reg_info.first_ymm].bytes, 619 sizeof(YMMHReg)); 620 return true; 621 } 622 623 if (byte_order == eByteOrderBig) 624 { 625 ::memcpy(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes + sizeof(XMMReg), 626 m_fpr.xstate.fxsave.xmm[reg - m_reg_info.first_ymm].bytes, 627 sizeof(XMMReg)); 628 ::memcpy(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes, 629 m_fpr.xstate.xsave.ymmh[reg - m_reg_info.first_ymm].bytes, 630 sizeof(YMMHReg)); 631 return true; 632 } 633 return false; // unsupported or invalid byte order 634 } 635 636 bool 637 RegisterContextPOSIX_x86::IsRegisterSetAvailable(size_t set_index) 638 { 639 // Note: Extended register sets are assumed to be at the end of g_reg_sets... 640 size_t num_sets = k_num_register_sets - k_num_extended_register_sets; 641 642 if (GetFPRType() == eXSAVE) // ...and to start with AVX registers. 643 ++num_sets; 644 return (set_index < num_sets); 645 } 646 647 648 // Used when parsing DWARF and EH frame information and any other 649 // object file sections that contain register numbers in them. 650 uint32_t 651 RegisterContextPOSIX_x86::ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, 652 uint32_t num) 653 { 654 const uint32_t num_regs = GetRegisterCount(); 655 656 assert (kind < kNumRegisterKinds); 657 for (uint32_t reg_idx = 0; reg_idx < num_regs; ++reg_idx) 658 { 659 const RegisterInfo *reg_info = GetRegisterInfoAtIndex (reg_idx); 660 661 if (reg_info->kinds[kind] == num) 662 return reg_idx; 663 } 664 665 return LLDB_INVALID_REGNUM; 666 } 667 668