1 //===-- RegisterContextLinux_i386.cpp --------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===---------------------------------------------------------------------===// 9 10 #include "RegisterContextPOSIX_x86.h" 11 #include "RegisterContextLinux_i386.h" 12 13 using namespace lldb_private; 14 using namespace lldb; 15 16 struct GPR 17 { 18 uint32_t ebx; 19 uint32_t ecx; 20 uint32_t edx; 21 uint32_t esi; 22 uint32_t edi; 23 uint32_t ebp; 24 uint32_t eax; 25 uint32_t ds; 26 uint32_t es; 27 uint32_t fs; 28 uint32_t gs; 29 uint32_t orig_ax; 30 uint32_t eip; 31 uint32_t cs; 32 uint32_t eflags; 33 uint32_t esp; 34 uint32_t ss; 35 }; 36 37 struct FPR_i386 38 { 39 uint16_t fctrl; // FPU Control Word (fcw) 40 uint16_t fstat; // FPU Status Word (fsw) 41 uint16_t ftag; // FPU Tag Word (ftw) 42 uint16_t fop; // Last Instruction Opcode (fop) 43 union 44 { 45 struct 46 { 47 uint64_t fip; // Instruction Pointer 48 uint64_t fdp; // Data Pointer 49 } x86_64; 50 struct 51 { 52 uint32_t fioff; // FPU IP Offset (fip) 53 uint32_t fiseg; // FPU IP Selector (fcs) 54 uint32_t fooff; // FPU Operand Pointer Offset (foo) 55 uint32_t foseg; // FPU Operand Pointer Selector (fos) 56 } i386; 57 } ptr; 58 uint32_t mxcsr; // MXCSR Register State 59 uint32_t mxcsrmask; // MXCSR Mask 60 MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes 61 XMMReg xmm[8]; // 8*16 bytes for each XMM-reg = 128 bytes 62 uint32_t padding[56]; 63 }; 64 65 struct UserArea 66 { 67 GPR regs; // General purpose registers. 68 int32_t fpvalid; // True if FPU is being used. 69 FPR_i386 i387; // FPU registers. 70 uint32_t tsize; // Text segment size. 71 uint32_t dsize; // Data segment size. 72 uint32_t ssize; // Stack segment size. 73 uint32_t start_code; // VM address of text. 74 uint32_t start_stack; // VM address of stack bottom (top in rsp). 75 int32_t signal; // Signal causing core dump. 76 int32_t reserved; // Unused. 77 uint32_t ar0; // Location of GPR's. 78 uint32_t fpstate; // Location of FPR's. Should be a FXSTATE *, but this 79 // has to be 32-bits even on 64-bit systems. 80 uint32_t magic; // Identifier for core dumps. 81 char u_comm[32]; // Command causing core dump. 82 uint32_t u_debugreg[8]; // Debug registers (DR0 - DR7). 83 }; 84 85 #define DR_SIZE sizeof(((UserArea*)NULL)->u_debugreg[0]) 86 #define DR_0_OFFSET 0xFC 87 #define DR_OFFSET(reg_index) \ 88 (DR_0_OFFSET + (reg_index * 4)) 89 #define FPR_SIZE(reg) sizeof(((FPR_i386*)NULL)->reg) 90 91 //--------------------------------------------------------------------------- 92 // Include RegisterInfos_i386 to declare our g_register_infos_i386 structure. 93 //--------------------------------------------------------------------------- 94 #define DECLARE_REGISTER_INFOS_I386_STRUCT 95 #include "RegisterInfos_i386.h" 96 #undef DECLARE_REGISTER_INFOS_I386_STRUCT 97 98 RegisterContextLinux_i386::RegisterContextLinux_i386(const ArchSpec &target_arch) : 99 RegisterInfoInterface(target_arch) 100 { 101 } 102 103 RegisterContextLinux_i386::~RegisterContextLinux_i386() 104 { 105 } 106 107 size_t 108 RegisterContextLinux_i386::GetGPRSize() 109 { 110 return sizeof(GPR); 111 } 112 113 const RegisterInfo * 114 RegisterContextLinux_i386::GetRegisterInfo() 115 { 116 switch (m_target_arch.GetCore()) 117 { 118 case ArchSpec::eCore_x86_32_i386: 119 case ArchSpec::eCore_x86_32_i486: 120 case ArchSpec::eCore_x86_32_i486sx: 121 return g_register_infos_i386; 122 default: 123 assert(false && "Unhandled target architecture."); 124 return NULL; 125 } 126 } 127