1 //===- ARM64.cpp ----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 14 #include "lld/Common/ErrorHandler.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Endian.h" 19 #include "llvm/Support/MathExtras.h" 20 21 using namespace llvm::MachO; 22 using namespace llvm::support::endian; 23 using namespace lld; 24 using namespace lld::macho; 25 26 namespace { 27 28 struct ARM64 : TargetInfo { 29 ARM64(); 30 31 uint64_t getEmbeddedAddend(MemoryBufferRef, const section_64 &, 32 const relocation_info) const override; 33 void relocateOne(uint8_t *loc, const Reloc &, uint64_t va, 34 uint64_t pc) const override; 35 36 void writeStub(uint8_t *buf, const macho::Symbol &) const override; 37 void writeStubHelperHeader(uint8_t *buf) const override; 38 void writeStubHelperEntry(uint8_t *buf, const DylibSymbol &, 39 uint64_t entryAddr) const override; 40 41 void relaxGotLoad(uint8_t *loc, uint8_t type) const override; 42 const TargetInfo::RelocAttrs &getRelocAttrs(uint8_t type) const override; 43 uint64_t getPageSize() const override { return 16 * 1024; } 44 }; 45 46 } // namespace 47 48 // Random notes on reloc types: 49 // ADDEND always pairs with BRANCH26, PAGE21, or PAGEOFF12 50 // SUBTRACTOR always pairs with UNSIGNED (a delta between two sections) 51 // POINTER_TO_GOT: 4-byte is pc-relative, 8-byte is absolute 52 53 const TargetInfo::RelocAttrs &ARM64::getRelocAttrs(uint8_t type) const { 54 static const std::array<TargetInfo::RelocAttrs, 11> relocAttrsArray{{ 55 #define B(x) RelocAttrBits::x 56 {"UNSIGNED", B(ABSOLUTE) | B(EXTERN) | B(LOCAL) | B(TLV) | B(DYSYM8) | 57 B(BYTE4) | B(BYTE8)}, 58 {"SUBTRACTOR", B(SUBTRAHEND) | B(BYTE8)}, 59 {"BRANCH26", B(PCREL) | B(EXTERN) | B(BRANCH) | B(BYTE4)}, 60 {"PAGE21", B(PCREL) | B(EXTERN) | B(BYTE4)}, 61 {"PAGEOFF12", B(ABSOLUTE) | B(EXTERN) | B(BYTE4)}, 62 {"GOT_LOAD_PAGE21", B(PCREL) | B(EXTERN) | B(GOT) | B(BYTE4)}, 63 {"GOT_LOAD_PAGEOFF12", 64 B(ABSOLUTE) | B(EXTERN) | B(GOT) | B(LOAD) | B(BYTE4)}, 65 {"POINTER_TO_GOT", B(PCREL) | B(EXTERN) | B(GOT) | B(BYTE4) | B(BYTE8)}, 66 {"TLVP_LOAD_PAGE21", B(PCREL) | B(EXTERN) | B(TLV) | B(BYTE4)}, 67 {"TLVP_LOAD_PAGEOFF12", 68 B(ABSOLUTE) | B(EXTERN) | B(TLV) | B(LOAD) | B(BYTE4)}, 69 {"ADDEND", B(ADDEND)}, 70 #undef B 71 }}; 72 assert(type >= 0 && type < relocAttrsArray.size() && 73 "invalid relocation type"); 74 if (type < 0 || type >= relocAttrsArray.size()) 75 return TargetInfo::invalidRelocAttrs; 76 return relocAttrsArray[type]; 77 } 78 79 uint64_t ARM64::getEmbeddedAddend(MemoryBufferRef mb, const section_64 &sec, 80 const relocation_info rel) const { 81 // TODO(gkm): extract embedded addend just so we can assert that it is 0 82 return 0; 83 } 84 85 inline uint64_t bitField(uint64_t value, int right, int width, int left) { 86 return ((value >> right) & ((1 << width) - 1)) << left; 87 } 88 89 // 25 0 90 // +-----------+---------------------------------------------------+ 91 // | | imm26 | 92 // +-----------+---------------------------------------------------+ 93 94 inline uint64_t encodeBranch26(uint64_t base, uint64_t va) { 95 // Since branch destinations are 4-byte aligned, the 2 least- 96 // significant bits are 0. They are right shifted off the end. 97 return (base | bitField(va, 2, 26, 0)); 98 } 99 100 // 30 29 23 5 101 // +-+---+---------+-------------------------------------+---------+ 102 // | |ilo| | immhi | | 103 // +-+---+---------+-------------------------------------+---------+ 104 105 inline uint64_t encodePage21(uint64_t base, uint64_t va) { 106 return (base | bitField(va, 12, 2, 29) | bitField(va, 14, 19, 5)); 107 } 108 109 // 21 10 110 // +-------------------+-----------------------+-------------------+ 111 // | | imm12 | | 112 // +-------------------+-----------------------+-------------------+ 113 114 inline uint64_t encodePageOff12(uint64_t base, uint64_t va) { 115 int scale = ((base & 0x3b000000) == 0x39000000) ? base >> 30 : 0; 116 // TODO(gkm): extract embedded addend and warn if != 0 117 // uint64_t addend = ((base & 0x003FFC00) >> 10); 118 return (base | bitField(va, scale, 12 - scale, 10)); 119 } 120 121 inline uint64_t pageBits(uint64_t address) { 122 const uint64_t pageMask = ~0xfffull; 123 return address & pageMask; 124 } 125 126 // For instruction relocations (load, store, add), the base 127 // instruction is pre-populated in the text section. A pre-populated 128 // instruction has opcode & register-operand bits set, with immediate 129 // operands zeroed. We read it from text, OR-in the immediate 130 // operands, then write-back the completed instruction. 131 132 void ARM64::relocateOne(uint8_t *loc, const Reloc &r, uint64_t value, 133 uint64_t pc) const { 134 uint32_t base = ((r.length == 2) ? read32le(loc) : 0); 135 value += r.addend; 136 switch (r.type) { 137 case ARM64_RELOC_BRANCH26: 138 value = encodeBranch26(base, value - pc); 139 break; 140 case ARM64_RELOC_UNSIGNED: 141 break; 142 case ARM64_RELOC_POINTER_TO_GOT: 143 if (r.pcrel) 144 value -= pc; 145 break; 146 case ARM64_RELOC_PAGE21: 147 case ARM64_RELOC_GOT_LOAD_PAGE21: 148 case ARM64_RELOC_TLVP_LOAD_PAGE21: 149 assert(r.pcrel); 150 value = encodePage21(base, pageBits(value) - pageBits(pc)); 151 break; 152 case ARM64_RELOC_PAGEOFF12: 153 case ARM64_RELOC_GOT_LOAD_PAGEOFF12: 154 case ARM64_RELOC_TLVP_LOAD_PAGEOFF12: 155 assert(!r.pcrel); 156 value = encodePageOff12(base, value); 157 break; 158 default: 159 llvm_unreachable("unexpected relocation type"); 160 } 161 162 switch (r.length) { 163 case 2: 164 write32le(loc, value); 165 break; 166 case 3: 167 write64le(loc, value); 168 break; 169 default: 170 llvm_unreachable("invalid r_length"); 171 } 172 } 173 174 static constexpr uint32_t stubCode[] = { 175 0x90000010, // 00: adrp x16, __la_symbol_ptr@page 176 0xf9400210, // 04: ldr x16, [x16, __la_symbol_ptr@pageoff] 177 0xd61f0200, // 08: br x16 178 }; 179 180 void ARM64::writeStub(uint8_t *buf8, const macho::Symbol &sym) const { 181 auto *buf32 = reinterpret_cast<uint32_t *>(buf8); 182 uint64_t pcPageBits = 183 pageBits(in.stubs->addr + sym.stubsIndex * sizeof(stubCode)); 184 uint64_t lazyPointerVA = in.lazyPointers->addr + sym.stubsIndex * WordSize; 185 buf32[0] = encodePage21(stubCode[0], pageBits(lazyPointerVA) - pcPageBits); 186 buf32[1] = encodePageOff12(stubCode[1], lazyPointerVA); 187 buf32[2] = stubCode[2]; 188 } 189 190 static constexpr uint32_t stubHelperHeaderCode[] = { 191 0x90000011, // 00: adrp x17, _dyld_private@page 192 0x91000231, // 04: add x17, x17, _dyld_private@pageoff 193 0xa9bf47f0, // 08: stp x16/x17, [sp, #-16]! 194 0x90000010, // 0c: adrp x16, dyld_stub_binder@page 195 0xf9400210, // 10: ldr x16, [x16, dyld_stub_binder@pageoff] 196 0xd61f0200, // 14: br x16 197 }; 198 199 void ARM64::writeStubHelperHeader(uint8_t *buf8) const { 200 auto *buf32 = reinterpret_cast<uint32_t *>(buf8); 201 auto pcPageBits = [](int i) { 202 return pageBits(in.stubHelper->addr + i * sizeof(uint32_t)); 203 }; 204 uint64_t loaderVA = in.imageLoaderCache->getVA(); 205 buf32[0] = 206 encodePage21(stubHelperHeaderCode[0], pageBits(loaderVA) - pcPageBits(0)); 207 buf32[1] = encodePageOff12(stubHelperHeaderCode[1], loaderVA); 208 buf32[2] = stubHelperHeaderCode[2]; 209 uint64_t binderVA = 210 in.got->addr + in.stubHelper->stubBinder->gotIndex * WordSize; 211 buf32[3] = 212 encodePage21(stubHelperHeaderCode[3], pageBits(binderVA) - pcPageBits(3)); 213 buf32[4] = encodePageOff12(stubHelperHeaderCode[4], binderVA); 214 buf32[5] = stubHelperHeaderCode[5]; 215 } 216 217 static constexpr uint32_t stubHelperEntryCode[] = { 218 0x18000050, // 00: ldr w16, l0 219 0x14000000, // 04: b stubHelperHeader 220 0x00000000, // 08: l0: .long 0 221 }; 222 223 void ARM64::writeStubHelperEntry(uint8_t *buf8, const DylibSymbol &sym, 224 uint64_t entryVA) const { 225 auto *buf32 = reinterpret_cast<uint32_t *>(buf8); 226 auto pcVA = [entryVA](int i) { return entryVA + i * sizeof(uint32_t); }; 227 uint64_t stubHelperHeaderVA = in.stubHelper->addr; 228 buf32[0] = stubHelperEntryCode[0]; 229 buf32[1] = 230 encodeBranch26(stubHelperEntryCode[1], stubHelperHeaderVA - pcVA(1)); 231 buf32[2] = sym.lazyBindOffset; 232 } 233 234 void ARM64::relaxGotLoad(uint8_t *loc, uint8_t type) const { 235 // The instruction format comments below are quoted from 236 // Arm® Architecture Reference Manual 237 // Armv8, for Armv8-A architecture profile 238 // ARM DDI 0487G.a (ID011921) 239 uint32_t instruction = read32le(loc); 240 // C6.2.132 LDR (immediate) 241 // LDR <Xt>, [<Xn|SP>{, #<pimm>}] 242 if ((instruction & 0xffc00000) != 0xf9400000) 243 error(getRelocAttrs(type).name + " reloc requires LDR instruction"); 244 assert(((instruction >> 10) & 0xfff) == 0 && 245 "non-zero embedded LDR immediate"); 246 // C6.2.4 ADD (immediate) 247 // ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} 248 instruction = ((instruction & 0x001fffff) | 0x91000000); 249 write32le(loc, instruction); 250 } 251 252 ARM64::ARM64() { 253 cpuType = CPU_TYPE_ARM64; 254 cpuSubtype = CPU_SUBTYPE_ARM64_ALL; 255 256 stubSize = sizeof(stubCode); 257 stubHelperHeaderSize = sizeof(stubHelperHeaderCode); 258 stubHelperEntrySize = sizeof(stubHelperEntryCode); 259 } 260 261 TargetInfo *macho::createARM64TargetInfo() { 262 static ARM64 t; 263 return &t; 264 } 265