1 //===- ARM64.cpp ----------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "InputFiles.h"
10 #include "Symbols.h"
11 #include "SyntheticSections.h"
12 #include "Target.h"
13 
14 #include "lld/Common/ErrorHandler.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/BinaryFormat/MachO.h"
18 #include "llvm/Support/Endian.h"
19 #include "llvm/Support/MathExtras.h"
20 
21 using namespace llvm::MachO;
22 using namespace llvm::support::endian;
23 using namespace lld;
24 using namespace lld::macho;
25 
26 namespace {
27 
28 struct ARM64 : TargetInfo {
29   ARM64();
30 
31   uint64_t getEmbeddedAddend(MemoryBufferRef, const section_64 &,
32                              const relocation_info) const override;
33   void relocateOne(uint8_t *loc, const Reloc &, uint64_t va,
34                    uint64_t pc) const override;
35 
36   void writeStub(uint8_t *buf, const macho::Symbol &) const override;
37   void writeStubHelperHeader(uint8_t *buf) const override;
38   void writeStubHelperEntry(uint8_t *buf, const DylibSymbol &,
39                             uint64_t entryAddr) const override;
40 
41   void relaxGotLoad(uint8_t *loc, uint8_t type) const override;
42   const TargetInfo::RelocAttrs &getRelocAttrs(uint8_t type) const override;
43   uint64_t getPageSize() const override { return 16 * 1024; }
44 };
45 
46 } // namespace
47 
48 // Random notes on reloc types:
49 // ADDEND always pairs with BRANCH26, PAGE21, or PAGEOFF12
50 // POINTER_TO_GOT: ld64 supports a 4-byte pc-relative form as well as an 8-byte
51 // absolute version of this relocation. The semantics of the absolute relocation
52 // are weird -- it results in the value of the GOT slot being written, instead
53 // of the address. Let's not support it unless we find a real-world use case.
54 
55 const TargetInfo::RelocAttrs &ARM64::getRelocAttrs(uint8_t type) const {
56   static const std::array<TargetInfo::RelocAttrs, 11> relocAttrsArray{{
57 #define B(x) RelocAttrBits::x
58       {"UNSIGNED", B(UNSIGNED) | B(ABSOLUTE) | B(EXTERN) | B(LOCAL) |
59                        B(DYSYM8) | B(BYTE4) | B(BYTE8)},
60       {"SUBTRACTOR", B(SUBTRAHEND) | B(BYTE4) | B(BYTE8)},
61       {"BRANCH26", B(PCREL) | B(EXTERN) | B(BRANCH) | B(BYTE4)},
62       {"PAGE21", B(PCREL) | B(EXTERN) | B(BYTE4)},
63       {"PAGEOFF12", B(ABSOLUTE) | B(EXTERN) | B(BYTE4)},
64       {"GOT_LOAD_PAGE21", B(PCREL) | B(EXTERN) | B(GOT) | B(BYTE4)},
65       {"GOT_LOAD_PAGEOFF12",
66        B(ABSOLUTE) | B(EXTERN) | B(GOT) | B(LOAD) | B(BYTE4)},
67       {"POINTER_TO_GOT", B(PCREL) | B(EXTERN) | B(GOT) | B(POINTER) | B(BYTE4)},
68       {"TLVP_LOAD_PAGE21", B(PCREL) | B(EXTERN) | B(TLV) | B(BYTE4)},
69       {"TLVP_LOAD_PAGEOFF12",
70        B(ABSOLUTE) | B(EXTERN) | B(TLV) | B(LOAD) | B(BYTE4)},
71       {"ADDEND", B(ADDEND)},
72 #undef B
73   }};
74   assert(type < relocAttrsArray.size() && "invalid relocation type");
75   if (type >= relocAttrsArray.size())
76     return TargetInfo::invalidRelocAttrs;
77   return relocAttrsArray[type];
78 }
79 
80 uint64_t ARM64::getEmbeddedAddend(MemoryBufferRef mb, const section_64 &sec,
81                                   const relocation_info rel) const {
82   if (rel.r_type != ARM64_RELOC_UNSIGNED) {
83     // All other reloc types should use the ADDEND relocation to store their
84     // addends.
85     // TODO(gkm): extract embedded addend just so we can assert that it is 0
86     return 0;
87   }
88 
89   auto *buf = reinterpret_cast<const uint8_t *>(mb.getBufferStart());
90   const uint8_t *loc = buf + sec.offset + rel.r_address;
91   switch (rel.r_length) {
92   case 2:
93     return read32le(loc);
94   case 3:
95     return read64le(loc);
96   default:
97     llvm_unreachable("invalid r_length");
98   }
99 }
100 
101 inline uint64_t bitField(uint64_t value, int right, int width, int left) {
102   return ((value >> right) & ((1 << width) - 1)) << left;
103 }
104 
105 //              25                                                0
106 // +-----------+---------------------------------------------------+
107 // |           |                       imm26                       |
108 // +-----------+---------------------------------------------------+
109 
110 inline uint64_t encodeBranch26(uint64_t base, uint64_t va) {
111   // Since branch destinations are 4-byte aligned, the 2 least-
112   // significant bits are 0. They are right shifted off the end.
113   return (base | bitField(va, 2, 26, 0));
114 }
115 
116 //   30 29          23                                  5
117 // +-+---+---------+-------------------------------------+---------+
118 // | |ilo|         |                immhi                |         |
119 // +-+---+---------+-------------------------------------+---------+
120 
121 inline uint64_t encodePage21(uint64_t base, uint64_t va) {
122   return (base | bitField(va, 12, 2, 29) | bitField(va, 14, 19, 5));
123 }
124 
125 //                      21                   10
126 // +-------------------+-----------------------+-------------------+
127 // |                   |         imm12         |                   |
128 // +-------------------+-----------------------+-------------------+
129 
130 inline uint64_t encodePageOff12(uint64_t base, uint64_t va) {
131   int scale = ((base & 0x3b000000) == 0x39000000) ? base >> 30 : 0;
132   // TODO(gkm): extract embedded addend and warn if != 0
133   // uint64_t addend = ((base & 0x003FFC00) >> 10);
134   return (base | bitField(va, scale, 12 - scale, 10));
135 }
136 
137 inline uint64_t pageBits(uint64_t address) {
138   const uint64_t pageMask = ~0xfffull;
139   return address & pageMask;
140 }
141 
142 // For instruction relocations (load, store, add), the base
143 // instruction is pre-populated in the text section. A pre-populated
144 // instruction has opcode & register-operand bits set, with immediate
145 // operands zeroed. We read it from text, OR-in the immediate
146 // operands, then write-back the completed instruction.
147 
148 void ARM64::relocateOne(uint8_t *loc, const Reloc &r, uint64_t value,
149                         uint64_t pc) const {
150   uint32_t base = ((r.length == 2) ? read32le(loc) : 0);
151   value += r.addend;
152   switch (r.type) {
153   case ARM64_RELOC_BRANCH26:
154     value = encodeBranch26(base, value - pc);
155     break;
156   case ARM64_RELOC_UNSIGNED:
157     break;
158   case ARM64_RELOC_POINTER_TO_GOT:
159     if (r.pcrel)
160       value -= pc;
161     break;
162   case ARM64_RELOC_PAGE21:
163   case ARM64_RELOC_GOT_LOAD_PAGE21:
164   case ARM64_RELOC_TLVP_LOAD_PAGE21:
165     assert(r.pcrel);
166     value = encodePage21(base, pageBits(value) - pageBits(pc));
167     break;
168   case ARM64_RELOC_PAGEOFF12:
169   case ARM64_RELOC_GOT_LOAD_PAGEOFF12:
170   case ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
171     assert(!r.pcrel);
172     value = encodePageOff12(base, value);
173     break;
174   default:
175     llvm_unreachable("unexpected relocation type");
176   }
177 
178   switch (r.length) {
179   case 2:
180     write32le(loc, value);
181     break;
182   case 3:
183     write64le(loc, value);
184     break;
185   default:
186     llvm_unreachable("invalid r_length");
187   }
188 }
189 
190 static constexpr uint32_t stubCode[] = {
191     0x90000010, // 00: adrp  x16, __la_symbol_ptr@page
192     0xf9400210, // 04: ldr   x16, [x16, __la_symbol_ptr@pageoff]
193     0xd61f0200, // 08: br    x16
194 };
195 
196 void ARM64::writeStub(uint8_t *buf8, const macho::Symbol &sym) const {
197   auto *buf32 = reinterpret_cast<uint32_t *>(buf8);
198   uint64_t pcPageBits =
199       pageBits(in.stubs->addr + sym.stubsIndex * sizeof(stubCode));
200   uint64_t lazyPointerVA = in.lazyPointers->addr + sym.stubsIndex * WordSize;
201   buf32[0] = encodePage21(stubCode[0], pageBits(lazyPointerVA) - pcPageBits);
202   buf32[1] = encodePageOff12(stubCode[1], lazyPointerVA);
203   buf32[2] = stubCode[2];
204 }
205 
206 static constexpr uint32_t stubHelperHeaderCode[] = {
207     0x90000011, // 00: adrp  x17, _dyld_private@page
208     0x91000231, // 04: add   x17, x17, _dyld_private@pageoff
209     0xa9bf47f0, // 08: stp   x16/x17, [sp, #-16]!
210     0x90000010, // 0c: adrp  x16, dyld_stub_binder@page
211     0xf9400210, // 10: ldr   x16, [x16, dyld_stub_binder@pageoff]
212     0xd61f0200, // 14: br    x16
213 };
214 
215 void ARM64::writeStubHelperHeader(uint8_t *buf8) const {
216   auto *buf32 = reinterpret_cast<uint32_t *>(buf8);
217   auto pcPageBits = [](int i) {
218     return pageBits(in.stubHelper->addr + i * sizeof(uint32_t));
219   };
220   uint64_t loaderVA = in.imageLoaderCache->getVA();
221   buf32[0] =
222       encodePage21(stubHelperHeaderCode[0], pageBits(loaderVA) - pcPageBits(0));
223   buf32[1] = encodePageOff12(stubHelperHeaderCode[1], loaderVA);
224   buf32[2] = stubHelperHeaderCode[2];
225   uint64_t binderVA =
226       in.got->addr + in.stubHelper->stubBinder->gotIndex * WordSize;
227   buf32[3] =
228       encodePage21(stubHelperHeaderCode[3], pageBits(binderVA) - pcPageBits(3));
229   buf32[4] = encodePageOff12(stubHelperHeaderCode[4], binderVA);
230   buf32[5] = stubHelperHeaderCode[5];
231 }
232 
233 static constexpr uint32_t stubHelperEntryCode[] = {
234     0x18000050, // 00: ldr  w16, l0
235     0x14000000, // 04: b    stubHelperHeader
236     0x00000000, // 08: l0: .long 0
237 };
238 
239 void ARM64::writeStubHelperEntry(uint8_t *buf8, const DylibSymbol &sym,
240                                  uint64_t entryVA) const {
241   auto *buf32 = reinterpret_cast<uint32_t *>(buf8);
242   auto pcVA = [entryVA](int i) { return entryVA + i * sizeof(uint32_t); };
243   uint64_t stubHelperHeaderVA = in.stubHelper->addr;
244   buf32[0] = stubHelperEntryCode[0];
245   buf32[1] =
246       encodeBranch26(stubHelperEntryCode[1], stubHelperHeaderVA - pcVA(1));
247   buf32[2] = sym.lazyBindOffset;
248 }
249 
250 void ARM64::relaxGotLoad(uint8_t *loc, uint8_t type) const {
251   // The instruction format comments below are quoted from
252   // Arm® Architecture Reference Manual
253   // Armv8, for Armv8-A architecture profile
254   // ARM DDI 0487G.a (ID011921)
255   uint32_t instruction = read32le(loc);
256   // C6.2.132 LDR (immediate)
257   // LDR <Xt>, [<Xn|SP>{, #<pimm>}]
258   if ((instruction & 0xffc00000) != 0xf9400000)
259     error(getRelocAttrs(type).name + " reloc requires LDR instruction");
260   assert(((instruction >> 10) & 0xfff) == 0 &&
261          "non-zero embedded LDR immediate");
262   // C6.2.4 ADD (immediate)
263   // ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
264   instruction = ((instruction & 0x001fffff) | 0x91000000);
265   write32le(loc, instruction);
266 }
267 
268 ARM64::ARM64() {
269   cpuType = CPU_TYPE_ARM64;
270   cpuSubtype = CPU_SUBTYPE_ARM64_ALL;
271 
272   stubSize = sizeof(stubCode);
273   stubHelperHeaderSize = sizeof(stubHelperHeaderCode);
274   stubHelperEntrySize = sizeof(stubHelperEntryCode);
275 }
276 
277 TargetInfo *macho::createARM64TargetInfo() {
278   static ARM64 t;
279   return &t;
280 }
281