1 //===- ARM.cpp ------------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "Thunks.h" 14 #include "lld/Common/ErrorHandler.h" 15 #include "llvm/Object/ELF.h" 16 #include "llvm/Support/Endian.h" 17 18 using namespace llvm; 19 using namespace llvm::support::endian; 20 using namespace llvm::ELF; 21 using namespace lld; 22 using namespace lld::elf; 23 24 namespace { 25 class ARM final : public TargetInfo { 26 public: 27 ARM(); 28 uint32_t calcEFlags() const override; 29 RelExpr getRelExpr(RelType Type, const Symbol &S, 30 const uint8_t *Loc) const override; 31 RelType getDynRel(RelType Type) const override; 32 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 33 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; 34 void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override; 35 void writePltHeader(uint8_t *Buf) const override; 36 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 37 int32_t Index, unsigned RelOff) const override; 38 void addPltSymbols(InputSection &IS, uint64_t Off) const override; 39 void addPltHeaderSymbols(InputSection &ISD) const override; 40 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 41 uint64_t BranchAddr, const Symbol &S) const override; 42 uint32_t getThunkSectionSpacing() const override; 43 bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override; 44 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 45 }; 46 } // namespace 47 48 ARM::ARM() { 49 CopyRel = R_ARM_COPY; 50 RelativeRel = R_ARM_RELATIVE; 51 IRelativeRel = R_ARM_IRELATIVE; 52 GotRel = R_ARM_GLOB_DAT; 53 NoneRel = R_ARM_NONE; 54 PltRel = R_ARM_JUMP_SLOT; 55 SymbolicRel = R_ARM_ABS32; 56 TlsGotRel = R_ARM_TLS_TPOFF32; 57 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 58 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 59 GotBaseSymInGotPlt = false; 60 PltEntrySize = 16; 61 PltHeaderSize = 32; 62 TrapInstr = {0xd4, 0xd4, 0xd4, 0xd4}; 63 NeedsThunks = true; 64 } 65 66 uint32_t ARM::calcEFlags() const { 67 // The ABIFloatType is used by loaders to detect the floating point calling 68 // convention. 69 uint32_t ABIFloatType = 0; 70 if (Config->ARMVFPArgs == ARMVFPArgKind::Base || 71 Config->ARMVFPArgs == ARMVFPArgKind::Default) 72 ABIFloatType = EF_ARM_ABI_FLOAT_SOFT; 73 else if (Config->ARMVFPArgs == ARMVFPArgKind::VFP) 74 ABIFloatType = EF_ARM_ABI_FLOAT_HARD; 75 76 // We don't currently use any features incompatible with EF_ARM_EABI_VER5, 77 // but we don't have any firm guarantees of conformance. Linux AArch64 78 // kernels (as of 2016) require an EABI version to be set. 79 return EF_ARM_EABI_VER5 | ABIFloatType; 80 } 81 82 RelExpr ARM::getRelExpr(RelType Type, const Symbol &S, 83 const uint8_t *Loc) const { 84 switch (Type) { 85 case R_ARM_THM_JUMP11: 86 return R_PC; 87 case R_ARM_CALL: 88 case R_ARM_JUMP24: 89 case R_ARM_PC24: 90 case R_ARM_PLT32: 91 case R_ARM_PREL31: 92 case R_ARM_THM_JUMP19: 93 case R_ARM_THM_JUMP24: 94 case R_ARM_THM_CALL: 95 return R_PLT_PC; 96 case R_ARM_GOTOFF32: 97 // (S + A) - GOT_ORG 98 return R_GOTREL; 99 case R_ARM_GOT_BREL: 100 // GOT(S) + A - GOT_ORG 101 return R_GOT_OFF; 102 case R_ARM_GOT_PREL: 103 case R_ARM_TLS_IE32: 104 // GOT(S) + A - P 105 return R_GOT_PC; 106 case R_ARM_SBREL32: 107 return R_ARM_SBREL; 108 case R_ARM_TARGET1: 109 return Config->Target1Rel ? R_PC : R_ABS; 110 case R_ARM_TARGET2: 111 if (Config->Target2 == Target2Policy::Rel) 112 return R_PC; 113 if (Config->Target2 == Target2Policy::Abs) 114 return R_ABS; 115 return R_GOT_PC; 116 case R_ARM_TLS_GD32: 117 return R_TLSGD_PC; 118 case R_ARM_TLS_LDM32: 119 return R_TLSLD_PC; 120 case R_ARM_BASE_PREL: 121 // B(S) + A - P 122 // FIXME: currently B(S) assumed to be .got, this may not hold for all 123 // platforms. 124 return R_GOTONLY_PC; 125 case R_ARM_MOVW_PREL_NC: 126 case R_ARM_MOVT_PREL: 127 case R_ARM_REL32: 128 case R_ARM_THM_MOVW_PREL_NC: 129 case R_ARM_THM_MOVT_PREL: 130 return R_PC; 131 case R_ARM_NONE: 132 return R_NONE; 133 case R_ARM_TLS_LE32: 134 return R_TLS; 135 case R_ARM_V4BX: 136 // V4BX is just a marker to indicate there's a "bx rN" instruction at the 137 // given address. It can be used to implement a special linker mode which 138 // rewrites ARMv4T inputs to ARMv4. Since we support only ARMv4 input and 139 // not ARMv4 output, we can just ignore it. 140 return R_HINT; 141 default: 142 return R_ABS; 143 } 144 } 145 146 RelType ARM::getDynRel(RelType Type) const { 147 if ((Type == R_ARM_ABS32) || (Type == R_ARM_TARGET1 && !Config->Target1Rel)) 148 return R_ARM_ABS32; 149 return R_ARM_NONE; 150 } 151 152 void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const { 153 write32le(Buf, In.Plt->getVA()); 154 } 155 156 void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const { 157 // An ARM entry is the address of the ifunc resolver function. 158 write32le(Buf, S.getVA()); 159 } 160 161 // Long form PLT Header that does not have any restrictions on the displacement 162 // of the .plt from the .plt.got. 163 static void writePltHeaderLong(uint8_t *Buf) { 164 const uint8_t PltData[] = { 165 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 166 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 167 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 168 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 169 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 170 0xd4, 0xd4, 0xd4, 0xd4, // Pad to 32-byte boundary 171 0xd4, 0xd4, 0xd4, 0xd4, // Pad to 32-byte boundary 172 0xd4, 0xd4, 0xd4, 0xd4}; 173 memcpy(Buf, PltData, sizeof(PltData)); 174 uint64_t GotPlt = In.GotPlt->getVA(); 175 uint64_t L1 = In.Plt->getVA() + 8; 176 write32le(Buf + 16, GotPlt - L1 - 8); 177 } 178 179 // The default PLT header requires the .plt.got to be within 128 Mb of the 180 // .plt in the positive direction. 181 void ARM::writePltHeader(uint8_t *Buf) const { 182 // Use a similar sequence to that in writePlt(), the difference is the calling 183 // conventions mean we use lr instead of ip. The PLT entry is responsible for 184 // saving lr on the stack, the dynamic loader is responsible for reloading 185 // it. 186 const uint32_t PltData[] = { 187 0xe52de004, // L1: str lr, [sp,#-4]! 188 0xe28fe600, // add lr, pc, #0x0NN00000 &(.got.plt - L1 - 4) 189 0xe28eea00, // add lr, lr, #0x000NN000 &(.got.plt - L1 - 4) 190 0xe5bef000, // ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4) 191 }; 192 193 uint64_t Offset = In.GotPlt->getVA() - In.Plt->getVA() - 4; 194 if (!llvm::isUInt<27>(Offset)) { 195 // We cannot encode the Offset, use the long form. 196 writePltHeaderLong(Buf); 197 return; 198 } 199 write32le(Buf + 0, PltData[0]); 200 write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff)); 201 write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff)); 202 write32le(Buf + 12, PltData[3] | (Offset & 0xfff)); 203 memcpy(Buf + 16, TrapInstr.data(), 4); // Pad to 32-byte boundary 204 memcpy(Buf + 20, TrapInstr.data(), 4); 205 memcpy(Buf + 24, TrapInstr.data(), 4); 206 memcpy(Buf + 28, TrapInstr.data(), 4); 207 } 208 209 void ARM::addPltHeaderSymbols(InputSection &IS) const { 210 addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS); 211 addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS); 212 } 213 214 // Long form PLT entries that do not have any restrictions on the displacement 215 // of the .plt from the .plt.got. 216 static void writePltLong(uint8_t *Buf, uint64_t GotPltEntryAddr, 217 uint64_t PltEntryAddr, int32_t Index, 218 unsigned RelOff) { 219 const uint8_t PltData[] = { 220 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 221 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 222 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 223 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 224 }; 225 memcpy(Buf, PltData, sizeof(PltData)); 226 uint64_t L1 = PltEntryAddr + 4; 227 write32le(Buf + 12, GotPltEntryAddr - L1 - 8); 228 } 229 230 // The default PLT entries require the .plt.got to be within 128 Mb of the 231 // .plt in the positive direction. 232 void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 233 uint64_t PltEntryAddr, int32_t Index, 234 unsigned RelOff) const { 235 // The PLT entry is similar to the example given in Appendix A of ELF for 236 // the Arm Architecture. Instead of using the Group Relocations to find the 237 // optimal rotation for the 8-bit immediate used in the add instructions we 238 // hard code the most compact rotations for simplicity. This saves a load 239 // instruction over the long plt sequences. 240 const uint32_t PltData[] = { 241 0xe28fc600, // L1: add ip, pc, #0x0NN00000 Offset(&(.plt.got) - L1 - 8 242 0xe28cca00, // add ip, ip, #0x000NN000 Offset(&(.plt.got) - L1 - 8 243 0xe5bcf000, // ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8 244 }; 245 246 uint64_t Offset = GotPltEntryAddr - PltEntryAddr - 8; 247 if (!llvm::isUInt<27>(Offset)) { 248 // We cannot encode the Offset, use the long form. 249 writePltLong(Buf, GotPltEntryAddr, PltEntryAddr, Index, RelOff); 250 return; 251 } 252 write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff)); 253 write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff)); 254 write32le(Buf + 8, PltData[2] | (Offset & 0xfff)); 255 memcpy(Buf + 12, TrapInstr.data(), 4); // Pad to 16-byte boundary 256 } 257 258 void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const { 259 addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS); 260 addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS); 261 } 262 263 bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 264 uint64_t BranchAddr, const Symbol &S) const { 265 // If S is an undefined weak symbol and does not have a PLT entry then it 266 // will be resolved as a branch to the next instruction. 267 if (S.isUndefWeak() && !S.isInPlt()) 268 return false; 269 // A state change from ARM to Thumb and vice versa must go through an 270 // interworking thunk if the relocation type is not R_ARM_CALL or 271 // R_ARM_THM_CALL. 272 switch (Type) { 273 case R_ARM_PC24: 274 case R_ARM_PLT32: 275 case R_ARM_JUMP24: 276 // Source is ARM, all PLT entries are ARM so no interworking required. 277 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 278 if (Expr == R_PC && ((S.getVA() & 1) == 1)) 279 return true; 280 LLVM_FALLTHROUGH; 281 case R_ARM_CALL: { 282 uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA(); 283 return !inBranchRange(Type, BranchAddr, Dst); 284 } 285 case R_ARM_THM_JUMP19: 286 case R_ARM_THM_JUMP24: 287 // Source is Thumb, all PLT entries are ARM so interworking is required. 288 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 289 if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0)) 290 return true; 291 LLVM_FALLTHROUGH; 292 case R_ARM_THM_CALL: { 293 uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA(); 294 return !inBranchRange(Type, BranchAddr, Dst); 295 } 296 } 297 return false; 298 } 299 300 uint32_t ARM::getThunkSectionSpacing() const { 301 // The placing of pre-created ThunkSections is controlled by the value 302 // ThunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to 303 // place the ThunkSection such that all branches from the InputSections 304 // prior to the ThunkSection can reach a Thunk placed at the end of the 305 // ThunkSection. Graphically: 306 // | up to ThunkSectionSpacing .text input sections | 307 // | ThunkSection | 308 // | up to ThunkSectionSpacing .text input sections | 309 // | ThunkSection | 310 311 // Pre-created ThunkSections are spaced roughly 16MiB apart on ARMv7. This 312 // is to match the most common expected case of a Thumb 2 encoded BL, BLX or 313 // B.W: 314 // ARM B, BL, BLX range +/- 32MiB 315 // Thumb B.W, BL, BLX range +/- 16MiB 316 // Thumb B<cc>.W range +/- 1MiB 317 // If a branch cannot reach a pre-created ThunkSection a new one will be 318 // created so we can handle the rare cases of a Thumb 2 conditional branch. 319 // We intentionally use a lower size for ThunkSectionSpacing than the maximum 320 // branch range so the end of the ThunkSection is more likely to be within 321 // range of the branch instruction that is furthest away. The value we shorten 322 // ThunkSectionSpacing by is set conservatively to allow us to create 16,384 323 // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to 324 // one of the Thunks going out of range. 325 326 // On Arm the ThunkSectionSpacing depends on the range of the Thumb Branch 327 // range. On earlier Architectures such as ARMv4, ARMv5 and ARMv6 (except 328 // ARMv6T2) the range is +/- 4MiB. 329 330 return (Config->ARMJ1J2BranchEncoding) ? 0x1000000 - 0x30000 331 : 0x400000 - 0x7500; 332 } 333 334 bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const { 335 uint64_t Range; 336 uint64_t InstrSize; 337 338 switch (Type) { 339 case R_ARM_PC24: 340 case R_ARM_PLT32: 341 case R_ARM_JUMP24: 342 case R_ARM_CALL: 343 Range = 0x2000000; 344 InstrSize = 4; 345 break; 346 case R_ARM_THM_JUMP19: 347 Range = 0x100000; 348 InstrSize = 2; 349 break; 350 case R_ARM_THM_JUMP24: 351 case R_ARM_THM_CALL: 352 Range = Config->ARMJ1J2BranchEncoding ? 0x1000000 : 0x400000; 353 InstrSize = 2; 354 break; 355 default: 356 return true; 357 } 358 // PC at Src is 2 instructions ahead, immediate of branch is signed 359 if (Src > Dst) 360 Range -= 2 * InstrSize; 361 else 362 Range += InstrSize; 363 364 if ((Dst & 0x1) == 0) 365 // Destination is ARM, if ARM caller then Src is already 4-byte aligned. 366 // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure 367 // destination will be 4 byte aligned. 368 Src &= ~0x3; 369 else 370 // Bit 0 == 1 denotes Thumb state, it is not part of the range 371 Dst &= ~0x1; 372 373 uint64_t Distance = (Src > Dst) ? Src - Dst : Dst - Src; 374 return Distance <= Range; 375 } 376 377 void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 378 switch (Type) { 379 case R_ARM_ABS32: 380 case R_ARM_BASE_PREL: 381 case R_ARM_GOTOFF32: 382 case R_ARM_GOT_BREL: 383 case R_ARM_GOT_PREL: 384 case R_ARM_REL32: 385 case R_ARM_RELATIVE: 386 case R_ARM_SBREL32: 387 case R_ARM_TARGET1: 388 case R_ARM_TARGET2: 389 case R_ARM_TLS_GD32: 390 case R_ARM_TLS_IE32: 391 case R_ARM_TLS_LDM32: 392 case R_ARM_TLS_LDO32: 393 case R_ARM_TLS_LE32: 394 case R_ARM_TLS_TPOFF32: 395 case R_ARM_TLS_DTPOFF32: 396 write32le(Loc, Val); 397 break; 398 case R_ARM_PREL31: 399 checkInt(Loc, Val, 31, Type); 400 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 401 break; 402 case R_ARM_CALL: 403 // R_ARM_CALL is used for BL and BLX instructions, depending on the 404 // value of bit 0 of Val, we must select a BL or BLX instruction 405 if (Val & 1) { 406 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 407 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 408 checkInt(Loc, Val, 26, Type); 409 write32le(Loc, 0xfa000000 | // opcode 410 ((Val & 2) << 23) | // H 411 ((Val >> 2) & 0x00ffffff)); // imm24 412 break; 413 } 414 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 415 // BLX (always unconditional) instruction to an ARM Target, select an 416 // unconditional BL. 417 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 418 // fall through as BL encoding is shared with B 419 LLVM_FALLTHROUGH; 420 case R_ARM_JUMP24: 421 case R_ARM_PC24: 422 case R_ARM_PLT32: 423 checkInt(Loc, Val, 26, Type); 424 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 425 break; 426 case R_ARM_THM_JUMP11: 427 checkInt(Loc, Val, 12, Type); 428 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 429 break; 430 case R_ARM_THM_JUMP19: 431 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 432 checkInt(Loc, Val, 21, Type); 433 write16le(Loc, 434 (read16le(Loc) & 0xfbc0) | // opcode cond 435 ((Val >> 10) & 0x0400) | // S 436 ((Val >> 12) & 0x003f)); // imm6 437 write16le(Loc + 2, 438 0x8000 | // opcode 439 ((Val >> 8) & 0x0800) | // J2 440 ((Val >> 5) & 0x2000) | // J1 441 ((Val >> 1) & 0x07ff)); // imm11 442 break; 443 case R_ARM_THM_CALL: 444 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 445 // value of bit 0 of Val, we must select a BL or BLX instruction 446 if ((Val & 1) == 0) { 447 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 448 // only be two byte aligned. This must be done before overflow check 449 Val = alignTo(Val, 4); 450 } 451 // Bit 12 is 0 for BLX, 1 for BL 452 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 453 if (!Config->ARMJ1J2BranchEncoding) { 454 // Older Arm architectures do not support R_ARM_THM_JUMP24 and have 455 // different encoding rules and range due to J1 and J2 always being 1. 456 checkInt(Loc, Val, 23, Type); 457 write16le(Loc, 458 0xf000 | // opcode 459 ((Val >> 12) & 0x07ff)); // imm11 460 write16le(Loc + 2, 461 (read16le(Loc + 2) & 0xd000) | // opcode 462 0x2800 | // J1 == J2 == 1 463 ((Val >> 1) & 0x07ff)); // imm11 464 break; 465 } 466 // Fall through as rest of encoding is the same as B.W 467 LLVM_FALLTHROUGH; 468 case R_ARM_THM_JUMP24: 469 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 470 checkInt(Loc, Val, 25, Type); 471 write16le(Loc, 472 0xf000 | // opcode 473 ((Val >> 14) & 0x0400) | // S 474 ((Val >> 12) & 0x03ff)); // imm10 475 write16le(Loc + 2, 476 (read16le(Loc + 2) & 0xd000) | // opcode 477 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 478 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 479 ((Val >> 1) & 0x07ff)); // imm11 480 break; 481 case R_ARM_MOVW_ABS_NC: 482 case R_ARM_MOVW_PREL_NC: 483 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 484 (Val & 0x0fff)); 485 break; 486 case R_ARM_MOVT_ABS: 487 case R_ARM_MOVT_PREL: 488 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 489 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 490 break; 491 case R_ARM_THM_MOVT_ABS: 492 case R_ARM_THM_MOVT_PREL: 493 // Encoding T1: A = imm4:i:imm3:imm8 494 write16le(Loc, 495 0xf2c0 | // opcode 496 ((Val >> 17) & 0x0400) | // i 497 ((Val >> 28) & 0x000f)); // imm4 498 write16le(Loc + 2, 499 (read16le(Loc + 2) & 0x8f00) | // opcode 500 ((Val >> 12) & 0x7000) | // imm3 501 ((Val >> 16) & 0x00ff)); // imm8 502 break; 503 case R_ARM_THM_MOVW_ABS_NC: 504 case R_ARM_THM_MOVW_PREL_NC: 505 // Encoding T3: A = imm4:i:imm3:imm8 506 write16le(Loc, 507 0xf240 | // opcode 508 ((Val >> 1) & 0x0400) | // i 509 ((Val >> 12) & 0x000f)); // imm4 510 write16le(Loc + 2, 511 (read16le(Loc + 2) & 0x8f00) | // opcode 512 ((Val << 4) & 0x7000) | // imm3 513 (Val & 0x00ff)); // imm8 514 break; 515 default: 516 error(getErrorLocation(Loc) + "unrecognized relocation " + toString(Type)); 517 } 518 } 519 520 int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 521 switch (Type) { 522 default: 523 return 0; 524 case R_ARM_ABS32: 525 case R_ARM_BASE_PREL: 526 case R_ARM_GOTOFF32: 527 case R_ARM_GOT_BREL: 528 case R_ARM_GOT_PREL: 529 case R_ARM_REL32: 530 case R_ARM_TARGET1: 531 case R_ARM_TARGET2: 532 case R_ARM_TLS_GD32: 533 case R_ARM_TLS_LDM32: 534 case R_ARM_TLS_LDO32: 535 case R_ARM_TLS_IE32: 536 case R_ARM_TLS_LE32: 537 return SignExtend64<32>(read32le(Buf)); 538 case R_ARM_PREL31: 539 return SignExtend64<31>(read32le(Buf)); 540 case R_ARM_CALL: 541 case R_ARM_JUMP24: 542 case R_ARM_PC24: 543 case R_ARM_PLT32: 544 return SignExtend64<26>(read32le(Buf) << 2); 545 case R_ARM_THM_JUMP11: 546 return SignExtend64<12>(read16le(Buf) << 1); 547 case R_ARM_THM_JUMP19: { 548 // Encoding T3: A = S:J2:J1:imm10:imm6:0 549 uint16_t Hi = read16le(Buf); 550 uint16_t Lo = read16le(Buf + 2); 551 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 552 ((Lo & 0x0800) << 8) | // J2 553 ((Lo & 0x2000) << 5) | // J1 554 ((Hi & 0x003f) << 12) | // imm6 555 ((Lo & 0x07ff) << 1)); // imm11:0 556 } 557 case R_ARM_THM_CALL: 558 if (!Config->ARMJ1J2BranchEncoding) { 559 // Older Arm architectures do not support R_ARM_THM_JUMP24 and have 560 // different encoding rules and range due to J1 and J2 always being 1. 561 uint16_t Hi = read16le(Buf); 562 uint16_t Lo = read16le(Buf + 2); 563 return SignExtend64<22>(((Hi & 0x7ff) << 12) | // imm11 564 ((Lo & 0x7ff) << 1)); // imm11:0 565 break; 566 } 567 LLVM_FALLTHROUGH; 568 case R_ARM_THM_JUMP24: { 569 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 570 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 571 uint16_t Hi = read16le(Buf); 572 uint16_t Lo = read16le(Buf + 2); 573 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 574 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 575 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 576 ((Hi & 0x003ff) << 12) | // imm0 577 ((Lo & 0x007ff) << 1)); // imm11:0 578 } 579 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 580 // MOVT is in the range -32768 <= A < 32768 581 case R_ARM_MOVW_ABS_NC: 582 case R_ARM_MOVT_ABS: 583 case R_ARM_MOVW_PREL_NC: 584 case R_ARM_MOVT_PREL: { 585 uint64_t Val = read32le(Buf) & 0x000f0fff; 586 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 587 } 588 case R_ARM_THM_MOVW_ABS_NC: 589 case R_ARM_THM_MOVT_ABS: 590 case R_ARM_THM_MOVW_PREL_NC: 591 case R_ARM_THM_MOVT_PREL: { 592 // Encoding T3: A = imm4:i:imm3:imm8 593 uint16_t Hi = read16le(Buf); 594 uint16_t Lo = read16le(Buf + 2); 595 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 596 ((Hi & 0x0400) << 1) | // i 597 ((Lo & 0x7000) >> 4) | // imm3 598 (Lo & 0x00ff)); // imm8 599 } 600 } 601 } 602 603 TargetInfo *elf::getARMTargetInfo() { 604 static ARM Target; 605 return &Target; 606 } 607