1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 22 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 26 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 28 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // expected-no-diagnostics 30 #ifndef HEADER 31 #define HEADER 32 template <class T> 33 struct S { 34 T f; 35 S(T a) : f(a) {} 36 S() : f() {} 37 operator T() { return T(); } 38 ~S() {} 39 }; 40 41 volatile int g __attribute__((aligned(128))) = 1212; 42 43 struct SS { 44 int a; 45 int b : 4; 46 int &c; 47 SS(int &d) : a(0), b(0), c(d) { 48 #pragma omp target 49 #pragma omp teams private(a, b, c) 50 #ifdef LAMBDA 51 [&]() { 52 ++this->a, --b, (this)->c /= 1; 53 }(); 54 #else 55 ++this->a, --b, c /= 1; 56 #endif 57 } 58 }; 59 60 template<typename T> 61 struct SST { 62 T a; 63 SST() : a(T()) { 64 #pragma omp target 65 #pragma omp teams private(a) 66 #ifdef LAMBDA 67 [&]() { 68 [&]() { 69 ++this->a; 70 }(); 71 }(); 72 #else 73 ++(this)->a; 74 #endif 75 } 76 }; 77 78 template <typename T> 79 T tmain() { 80 S<T> test; 81 SST<T> sst; 82 T t_var __attribute__((aligned(128))) = T(); 83 T vec[] __attribute__((aligned(128))) = {1, 2}; 84 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 85 S<T> var __attribute__((aligned(128))) (3); 86 #pragma omp target 87 #pragma omp teams private(t_var, vec, s_arr, var) 88 { 89 vec[0] = t_var; 90 s_arr[0] = var; 91 } 92 return T(); 93 } 94 95 int main() { 96 static int sivar; 97 SS ss(sivar); 98 #ifdef LAMBDA 99 100 101 // lambda and target region in main 102 103 // target region in struct constructor 104 105 // offloading function in struct constructor 106 107 // outlined teams region in struct constructor 108 // call void [[INNER_LAMBDA_CONSTR:@.+]]([[CAP_0_TY]]* 109 110 // inner lambda in struct constructor 111 // define{{.*}} void [[INNER_LAMBDA_CONSTR]]([[CAP_0_TY]]* 112 113 114 // ret 115 116 [&]() { 117 #pragma omp target 118 #pragma omp teams private(g, sivar) 119 { 120 121 g = 1; 122 sivar = 2; 123 [&]() { 124 g = 2; 125 sivar = 4; 126 }(); 127 } 128 }(); 129 return 0; 130 #else 131 S<float> test; 132 int t_var = 0; 133 int vec[] = {1, 2}; 134 S<float> s_arr[] = {1, 2}; 135 S<float> var(3); 136 #pragma omp target 137 #pragma omp teams private(t_var, vec, s_arr, var, sivar) 138 { 139 vec[0] = t_var; 140 s_arr[0] = var; 141 sivar = 3; 142 } 143 return tmain<int>(); 144 #endif 145 } 146 147 148 // target region in main function 149 150 151 // template tmain 152 153 // target in SS constructor 154 155 156 // target in tmain template 157 158 159 // SST constructor 160 161 // target in SST constructor 162 163 164 #endif 165 166 // CHECK1-LABEL: define {{[^@]+}}@main 167 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 168 // CHECK1-NEXT: entry: 169 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 170 // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 171 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 172 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 173 // CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 174 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 175 // CHECK1-NEXT: ret i32 0 176 // 177 // 178 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 179 // CHECK1-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 180 // CHECK1-NEXT: entry: 181 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 182 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 183 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 184 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 185 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 186 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 187 // CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 192 // CHECK1-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 195 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 196 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 197 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 198 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 199 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 200 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 201 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 202 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 203 // CHECK1-NEXT: store i32 0, i32* [[A]], align 8 204 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 205 // CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 206 // CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 207 // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 208 // CHECK1-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 209 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 210 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 211 // CHECK1-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 212 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 213 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 214 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 215 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 216 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 217 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 218 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 219 // CHECK1-NEXT: store i8* null, i8** [[TMP5]], align 8 220 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 221 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 222 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 223 // CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 224 // CHECK1-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 225 // CHECK1: omp_offload.failed: 226 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4:[0-9]+]] 227 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 228 // CHECK1: omp_offload.cont: 229 // CHECK1-NEXT: ret void 230 // 231 // 232 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 233 // CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { 234 // CHECK1-NEXT: entry: 235 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 236 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 237 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 238 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 239 // CHECK1-NEXT: ret void 240 // 241 // 242 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 243 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 244 // CHECK1-NEXT: entry: 245 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 246 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 247 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 248 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 249 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8 250 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 251 // CHECK1-NEXT: [[C:%.*]] = alloca i32, align 4 252 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 253 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 254 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 255 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 256 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 257 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 258 // CHECK1-NEXT: store i32* [[A]], i32** [[TMP]], align 8 259 // CHECK1-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 260 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 261 // CHECK1-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP1]], align 8 262 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 263 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 264 // CHECK1-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 265 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 266 // CHECK1-NEXT: store i32* [[B]], i32** [[TMP4]], align 8 267 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 268 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 8 269 // CHECK1-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 270 // CHECK1-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 271 // CHECK1-NEXT: ret void 272 // 273 // 274 // CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 275 // CHECK1-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { 276 // CHECK1-NEXT: entry: 277 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 278 // CHECK1-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 279 // CHECK1-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 280 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 281 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 282 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 283 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 284 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 285 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 286 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 287 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 288 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 289 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 290 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 291 // CHECK1-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 292 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 293 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 294 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 295 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 296 // CHECK1-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 297 // CHECK1-NEXT: ret void 298 // 299 // 300 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 301 // CHECK1-SAME: () #[[ATTR3]] { 302 // CHECK1-NEXT: entry: 303 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 304 // CHECK1-NEXT: ret void 305 // 306 // 307 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 308 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 309 // CHECK1-NEXT: entry: 310 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 311 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 312 // CHECK1-NEXT: [[G:%.*]] = alloca i32, align 128 313 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 315 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 316 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 317 // CHECK1-NEXT: store i32 1, i32* [[G]], align 128 318 // CHECK1-NEXT: store i32 2, i32* [[SIVAR]], align 4 319 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 320 // CHECK1-NEXT: store i32* [[G]], i32** [[TMP0]], align 8 321 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 322 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 8 323 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) 324 // CHECK1-NEXT: ret void 325 // 326 // 327 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 328 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] { 329 // CHECK1-NEXT: entry: 330 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 331 // CHECK1-NEXT: ret void 332 // 333 // 334 // CHECK2-LABEL: define {{[^@]+}}@main 335 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 336 // CHECK2-NEXT: entry: 337 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 338 // CHECK2-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 339 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 340 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 341 // CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 342 // CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 343 // CHECK2-NEXT: ret i32 0 344 // 345 // 346 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 347 // CHECK2-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 348 // CHECK2-NEXT: entry: 349 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 350 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 351 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 352 // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 353 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 354 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 355 // CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 356 // CHECK2-NEXT: ret void 357 // 358 // 359 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 360 // CHECK2-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 361 // CHECK2-NEXT: entry: 362 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 363 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 364 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 365 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 366 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 367 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 368 // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 369 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 370 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 371 // CHECK2-NEXT: store i32 0, i32* [[A]], align 8 372 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 373 // CHECK2-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 374 // CHECK2-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 375 // CHECK2-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 376 // CHECK2-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 377 // CHECK2-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 378 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 379 // CHECK2-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 380 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 381 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 382 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 383 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 384 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 385 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 386 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 387 // CHECK2-NEXT: store i8* null, i8** [[TMP5]], align 8 388 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 389 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 390 // CHECK2-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 391 // CHECK2-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 392 // CHECK2-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 393 // CHECK2: omp_offload.failed: 394 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4:[0-9]+]] 395 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 396 // CHECK2: omp_offload.cont: 397 // CHECK2-NEXT: ret void 398 // 399 // 400 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 401 // CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { 402 // CHECK2-NEXT: entry: 403 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 404 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 405 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 406 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 407 // CHECK2-NEXT: ret void 408 // 409 // 410 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 411 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 412 // CHECK2-NEXT: entry: 413 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 414 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 415 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 416 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 417 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8 418 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 419 // CHECK2-NEXT: [[C:%.*]] = alloca i32, align 4 420 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 421 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 422 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 423 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 424 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 425 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 426 // CHECK2-NEXT: store i32* [[A]], i32** [[TMP]], align 8 427 // CHECK2-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 428 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 429 // CHECK2-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP1]], align 8 430 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 431 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 432 // CHECK2-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 433 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 434 // CHECK2-NEXT: store i32* [[B]], i32** [[TMP4]], align 8 435 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 436 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 8 437 // CHECK2-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 438 // CHECK2-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 439 // CHECK2-NEXT: ret void 440 // 441 // 442 // CHECK2-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 443 // CHECK2-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { 444 // CHECK2-NEXT: entry: 445 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 446 // CHECK2-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 447 // CHECK2-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 448 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 449 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 450 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 451 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 452 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 453 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 454 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 455 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 456 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 457 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 458 // CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 459 // CHECK2-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 460 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 461 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 462 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 463 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 464 // CHECK2-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 465 // CHECK2-NEXT: ret void 466 // 467 // 468 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 469 // CHECK2-SAME: () #[[ATTR3]] { 470 // CHECK2-NEXT: entry: 471 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 472 // CHECK2-NEXT: ret void 473 // 474 // 475 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 476 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 477 // CHECK2-NEXT: entry: 478 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 479 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 480 // CHECK2-NEXT: [[G:%.*]] = alloca i32, align 128 481 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 482 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 483 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 484 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 485 // CHECK2-NEXT: store i32 1, i32* [[G]], align 128 486 // CHECK2-NEXT: store i32 2, i32* [[SIVAR]], align 4 487 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 488 // CHECK2-NEXT: store i32* [[G]], i32** [[TMP0]], align 8 489 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 490 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 8 491 // CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) 492 // CHECK2-NEXT: ret void 493 // 494 // 495 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 496 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] { 497 // CHECK2-NEXT: entry: 498 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 499 // CHECK2-NEXT: ret void 500 // 501 // 502 // CHECK3-LABEL: define {{[^@]+}}@main 503 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 504 // CHECK3-NEXT: entry: 505 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 506 // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 507 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 508 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 509 // CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 510 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 511 // CHECK3-NEXT: ret i32 0 512 // 513 // 514 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 515 // CHECK3-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 516 // CHECK3-NEXT: entry: 517 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 518 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 519 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 520 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 521 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 522 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 523 // CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 524 // CHECK3-NEXT: ret void 525 // 526 // 527 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 528 // CHECK3-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 529 // CHECK3-NEXT: entry: 530 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 531 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 532 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 533 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 534 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 535 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 536 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 537 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 538 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 539 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 540 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 541 // CHECK3-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 542 // CHECK3-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 543 // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 544 // CHECK3-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 545 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 546 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 547 // CHECK3-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 548 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 549 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 550 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 551 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 552 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 553 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 554 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 555 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4 556 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 557 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 558 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 559 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 560 // CHECK3-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 561 // CHECK3: omp_offload.failed: 562 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4:[0-9]+]] 563 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 564 // CHECK3: omp_offload.cont: 565 // CHECK3-NEXT: ret void 566 // 567 // 568 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 569 // CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { 570 // CHECK3-NEXT: entry: 571 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 572 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 573 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 574 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 575 // CHECK3-NEXT: ret void 576 // 577 // 578 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 579 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 580 // CHECK3-NEXT: entry: 581 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 582 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 583 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 584 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 585 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4 586 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 587 // CHECK3-NEXT: [[C:%.*]] = alloca i32, align 4 588 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 589 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 590 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 591 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 592 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 593 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 594 // CHECK3-NEXT: store i32* [[A]], i32** [[TMP]], align 4 595 // CHECK3-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 596 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 597 // CHECK3-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP1]], align 4 598 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 599 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 600 // CHECK3-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 4 601 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 602 // CHECK3-NEXT: store i32* [[B]], i32** [[TMP4]], align 4 603 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 604 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 4 605 // CHECK3-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 606 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]) 607 // CHECK3-NEXT: ret void 608 // 609 // 610 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 611 // CHECK3-SAME: (%class.anon.0* noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { 612 // CHECK3-NEXT: entry: 613 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 614 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 615 // CHECK3-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 616 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 617 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 618 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 619 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 620 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 621 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 622 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 623 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 624 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 625 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 626 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 627 // CHECK3-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 628 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 629 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 630 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 631 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 632 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 633 // CHECK3-NEXT: ret void 634 // 635 // 636 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 637 // CHECK3-SAME: () #[[ATTR3]] { 638 // CHECK3-NEXT: entry: 639 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 640 // CHECK3-NEXT: ret void 641 // 642 // 643 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 644 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 645 // CHECK3-NEXT: entry: 646 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 647 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 648 // CHECK3-NEXT: [[G:%.*]] = alloca i32, align 128 649 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 650 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 4 651 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 652 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 653 // CHECK3-NEXT: store i32 1, i32* [[G]], align 128 654 // CHECK3-NEXT: store i32 2, i32* [[SIVAR]], align 4 655 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 656 // CHECK3-NEXT: store i32* [[G]], i32** [[TMP0]], align 4 657 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 658 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 4 659 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) 660 // CHECK3-NEXT: ret void 661 // 662 // 663 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 664 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] { 665 // CHECK3-NEXT: entry: 666 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 667 // CHECK3-NEXT: ret void 668 // 669 // 670 // CHECK4-LABEL: define {{[^@]+}}@main 671 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 672 // CHECK4-NEXT: entry: 673 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 674 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 675 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 676 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 677 // CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 678 // CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 679 // CHECK4-NEXT: ret i32 0 680 // 681 // 682 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 683 // CHECK4-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 684 // CHECK4-NEXT: entry: 685 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 686 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 687 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 688 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 689 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 690 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 691 // CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 692 // CHECK4-NEXT: ret void 693 // 694 // 695 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 696 // CHECK4-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 697 // CHECK4-NEXT: entry: 698 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 699 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 700 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 701 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 702 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 703 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 704 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 705 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 706 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 707 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 708 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 709 // CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 710 // CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 711 // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 712 // CHECK4-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 713 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 714 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 715 // CHECK4-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 716 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 717 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 718 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 719 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 720 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 721 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 722 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 723 // CHECK4-NEXT: store i8* null, i8** [[TMP5]], align 4 724 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 725 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 726 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 727 // CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 728 // CHECK4-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 729 // CHECK4: omp_offload.failed: 730 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4:[0-9]+]] 731 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 732 // CHECK4: omp_offload.cont: 733 // CHECK4-NEXT: ret void 734 // 735 // 736 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 737 // CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { 738 // CHECK4-NEXT: entry: 739 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 740 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 741 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 742 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 743 // CHECK4-NEXT: ret void 744 // 745 // 746 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 747 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 748 // CHECK4-NEXT: entry: 749 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 750 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 751 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 752 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 753 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4 754 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 755 // CHECK4-NEXT: [[C:%.*]] = alloca i32, align 4 756 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 757 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 758 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 759 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 760 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 761 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 762 // CHECK4-NEXT: store i32* [[A]], i32** [[TMP]], align 4 763 // CHECK4-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 764 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 765 // CHECK4-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP1]], align 4 766 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 767 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 768 // CHECK4-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 4 769 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 770 // CHECK4-NEXT: store i32* [[B]], i32** [[TMP4]], align 4 771 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 772 // CHECK4-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 4 773 // CHECK4-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 774 // CHECK4-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]) 775 // CHECK4-NEXT: ret void 776 // 777 // 778 // CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 779 // CHECK4-SAME: (%class.anon.0* noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { 780 // CHECK4-NEXT: entry: 781 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 782 // CHECK4-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 783 // CHECK4-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 784 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 785 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 786 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 787 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 788 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 789 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 790 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 791 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 792 // CHECK4-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 793 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 794 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 795 // CHECK4-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 796 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 797 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 798 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 799 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 800 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 801 // CHECK4-NEXT: ret void 802 // 803 // 804 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 805 // CHECK4-SAME: () #[[ATTR3]] { 806 // CHECK4-NEXT: entry: 807 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 808 // CHECK4-NEXT: ret void 809 // 810 // 811 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 812 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 813 // CHECK4-NEXT: entry: 814 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 815 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 816 // CHECK4-NEXT: [[G:%.*]] = alloca i32, align 128 817 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 818 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 4 819 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 820 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 821 // CHECK4-NEXT: store i32 1, i32* [[G]], align 128 822 // CHECK4-NEXT: store i32 2, i32* [[SIVAR]], align 4 823 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 824 // CHECK4-NEXT: store i32* [[G]], i32** [[TMP0]], align 4 825 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 826 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 4 827 // CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) 828 // CHECK4-NEXT: ret void 829 // 830 // 831 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 832 // CHECK4-SAME: () #[[ATTR5:[0-9]+]] { 833 // CHECK4-NEXT: entry: 834 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 835 // CHECK4-NEXT: ret void 836 // 837 // 838 // CHECK9-LABEL: define {{[^@]+}}@main 839 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 840 // CHECK9-NEXT: entry: 841 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 842 // CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 843 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 844 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 845 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 846 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 847 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 848 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 849 // CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 850 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 851 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 852 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 853 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 854 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 855 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) 856 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 857 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 858 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00) 859 // CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 860 // CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 861 // CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 862 // CHECK9: omp_offload.failed: 863 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] 864 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 865 // CHECK9: omp_offload.cont: 866 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 867 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 868 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 869 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 870 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 871 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 872 // CHECK9: arraydestroy.body: 873 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 874 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 875 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 876 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 877 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 878 // CHECK9: arraydestroy.done1: 879 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 880 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 881 // CHECK9-NEXT: ret i32 [[TMP4]] 882 // 883 // 884 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 885 // CHECK9-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 886 // CHECK9-NEXT: entry: 887 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 888 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 889 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 890 // CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 891 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 892 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 893 // CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 894 // CHECK9-NEXT: ret void 895 // 896 // 897 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 898 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 899 // CHECK9-NEXT: entry: 900 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 901 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 902 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 903 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 904 // CHECK9-NEXT: ret void 905 // 906 // 907 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 908 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 909 // CHECK9-NEXT: entry: 910 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 911 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 912 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 913 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 914 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 915 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 916 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 917 // CHECK9-NEXT: ret void 918 // 919 // 920 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 921 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 922 // CHECK9-NEXT: entry: 923 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 924 // CHECK9-NEXT: ret void 925 // 926 // 927 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 928 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 929 // CHECK9-NEXT: entry: 930 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 931 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 932 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 933 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 934 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 935 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 936 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 937 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 938 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 939 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 940 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 941 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 942 // CHECK9: arrayctor.loop: 943 // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 944 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 945 // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 946 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 947 // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 948 // CHECK9: arrayctor.cont: 949 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 950 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 951 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 952 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 953 // CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 954 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 955 // CHECK9-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* 956 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) 957 // CHECK9-NEXT: store i32 3, i32* [[SIVAR]], align 4 958 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 959 // CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 960 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 961 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 962 // CHECK9: arraydestroy.body: 963 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 964 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 965 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 966 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 967 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 968 // CHECK9: arraydestroy.done3: 969 // CHECK9-NEXT: ret void 970 // 971 // 972 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 973 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 974 // CHECK9-NEXT: entry: 975 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 976 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 977 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 978 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 979 // CHECK9-NEXT: ret void 980 // 981 // 982 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 983 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { 984 // CHECK9-NEXT: entry: 985 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 986 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 987 // CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 988 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 989 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 990 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 991 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 992 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 993 // CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[SST]]) 994 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 995 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 996 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 997 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 998 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 999 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1000 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1001 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef signext 3) 1002 // CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1003 // CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1004 // CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1005 // CHECK9: omp_offload.failed: 1006 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] 1007 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1008 // CHECK9: omp_offload.cont: 1009 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1010 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1011 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1012 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1013 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1014 // CHECK9: arraydestroy.body: 1015 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1016 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1017 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1018 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1019 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1020 // CHECK9: arraydestroy.done1: 1021 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1022 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1023 // CHECK9-NEXT: ret i32 [[TMP4]] 1024 // 1025 // 1026 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1027 // CHECK9-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1028 // CHECK9-NEXT: entry: 1029 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1030 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 1031 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1032 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1033 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1034 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1035 // CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 1036 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1037 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 1038 // CHECK9-NEXT: store i32 0, i32* [[A]], align 8 1039 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1040 // CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 1041 // CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 1042 // CHECK9-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 1043 // CHECK9-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 1044 // CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1045 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 1046 // CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 1047 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1048 // CHECK9-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 1049 // CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 1050 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1051 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 1052 // CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 1053 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1054 // CHECK9-NEXT: store i8* null, i8** [[TMP5]], align 8 1055 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1056 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1057 // CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1058 // CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 1059 // CHECK9-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1060 // CHECK9: omp_offload.failed: 1061 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] 1062 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1063 // CHECK9: omp_offload.cont: 1064 // CHECK9-NEXT: ret void 1065 // 1066 // 1067 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 1068 // CHECK9-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 1069 // CHECK9-NEXT: entry: 1070 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1071 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1072 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1073 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 1074 // CHECK9-NEXT: ret void 1075 // 1076 // 1077 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 1078 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 1079 // CHECK9-NEXT: entry: 1080 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1081 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1082 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1083 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 1084 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1085 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 1086 // CHECK9-NEXT: [[C:%.*]] = alloca i32, align 4 1087 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 1088 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1089 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1090 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1091 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1092 // CHECK9-NEXT: store i32* [[A]], i32** [[TMP]], align 8 1093 // CHECK9-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 1094 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 1095 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1096 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 1097 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 1098 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 1099 // CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 1100 // CHECK9-NEXT: store i32 [[DEC]], i32* [[B]], align 4 1101 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 8 1102 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1103 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 1104 // CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 1105 // CHECK9-NEXT: ret void 1106 // 1107 // 1108 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1109 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1110 // CHECK9-NEXT: entry: 1111 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1112 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1113 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1114 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1115 // CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 1116 // CHECK9-NEXT: ret void 1117 // 1118 // 1119 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1120 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1121 // CHECK9-NEXT: entry: 1122 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1123 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1124 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1125 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1126 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1127 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1128 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1129 // CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 1130 // CHECK9-NEXT: ret void 1131 // 1132 // 1133 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1134 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1135 // CHECK9-NEXT: entry: 1136 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1137 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1138 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1139 // CHECK9-NEXT: ret void 1140 // 1141 // 1142 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1143 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1144 // CHECK9-NEXT: entry: 1145 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1146 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1147 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1148 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1149 // CHECK9-NEXT: ret void 1150 // 1151 // 1152 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 1153 // CHECK9-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1154 // CHECK9-NEXT: entry: 1155 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1156 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1157 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1158 // CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1159 // CHECK9-NEXT: ret void 1160 // 1161 // 1162 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1163 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1164 // CHECK9-NEXT: entry: 1165 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1166 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1167 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1168 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1169 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1170 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1171 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1172 // CHECK9-NEXT: ret void 1173 // 1174 // 1175 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 1176 // CHECK9-SAME: () #[[ATTR3]] { 1177 // CHECK9-NEXT: entry: 1178 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 1179 // CHECK9-NEXT: ret void 1180 // 1181 // 1182 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 1183 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1184 // CHECK9-NEXT: entry: 1185 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1186 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1187 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1188 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1189 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1190 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1191 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1192 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1193 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1194 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1195 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1196 // CHECK9: arrayctor.loop: 1197 // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1198 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1199 // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 1200 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1201 // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1202 // CHECK9: arrayctor.cont: 1203 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1204 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 1205 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 1206 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 1207 // CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1208 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 1209 // CHECK9-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 1210 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) 1211 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1212 // CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1213 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 1214 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1215 // CHECK9: arraydestroy.body: 1216 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1217 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1218 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1219 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1220 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1221 // CHECK9: arraydestroy.done3: 1222 // CHECK9-NEXT: ret void 1223 // 1224 // 1225 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1226 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1227 // CHECK9-NEXT: entry: 1228 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1229 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1230 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1231 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1232 // CHECK9-NEXT: ret void 1233 // 1234 // 1235 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1236 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1237 // CHECK9-NEXT: entry: 1238 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1239 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1240 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1241 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1242 // CHECK9-NEXT: store i32 0, i32* [[F]], align 4 1243 // CHECK9-NEXT: ret void 1244 // 1245 // 1246 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 1247 // CHECK9-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1248 // CHECK9-NEXT: entry: 1249 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1250 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1251 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1252 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1253 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1254 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1255 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 1256 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 1257 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1258 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** 1259 // CHECK9-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 8 1260 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1261 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** 1262 // CHECK9-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 8 1263 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1264 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 1265 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1266 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1267 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1268 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1269 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1270 // CHECK9: omp_offload.failed: 1271 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] 1272 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1273 // CHECK9: omp_offload.cont: 1274 // CHECK9-NEXT: ret void 1275 // 1276 // 1277 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 1278 // CHECK9-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 1279 // CHECK9-NEXT: entry: 1280 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1281 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1282 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1283 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) 1284 // CHECK9-NEXT: ret void 1285 // 1286 // 1287 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 1288 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 1289 // CHECK9-NEXT: entry: 1290 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1291 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1292 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1293 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 1294 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1295 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1296 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1297 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1298 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1299 // CHECK9-NEXT: store i32* [[A]], i32** [[TMP]], align 8 1300 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 1301 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1302 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 1303 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 1304 // CHECK9-NEXT: ret void 1305 // 1306 // 1307 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1308 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1309 // CHECK9-NEXT: entry: 1310 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1311 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1312 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1313 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1314 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1315 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1316 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1317 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1318 // CHECK9-NEXT: ret void 1319 // 1320 // 1321 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1322 // CHECK9-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1323 // CHECK9-NEXT: entry: 1324 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1325 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1326 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1327 // CHECK9-NEXT: ret void 1328 // 1329 // 1330 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1331 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1332 // CHECK9-NEXT: entry: 1333 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1334 // CHECK9-NEXT: ret void 1335 // 1336 // 1337 // CHECK10-LABEL: define {{[^@]+}}@main 1338 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 1339 // CHECK10-NEXT: entry: 1340 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1341 // CHECK10-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 1342 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1343 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1344 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1345 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1346 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1347 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1348 // CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 1349 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1350 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 1351 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1352 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 1353 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 1354 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) 1355 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 1356 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 1357 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00) 1358 // CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1359 // CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1360 // CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1361 // CHECK10: omp_offload.failed: 1362 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] 1363 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1364 // CHECK10: omp_offload.cont: 1365 // CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1366 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1367 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1368 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1369 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1370 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1371 // CHECK10: arraydestroy.body: 1372 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1373 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1374 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1375 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1376 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1377 // CHECK10: arraydestroy.done1: 1378 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1379 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1380 // CHECK10-NEXT: ret i32 [[TMP4]] 1381 // 1382 // 1383 // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 1384 // CHECK10-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1385 // CHECK10-NEXT: entry: 1386 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1387 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 1388 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1389 // CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 1390 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1391 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 1392 // CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 1393 // CHECK10-NEXT: ret void 1394 // 1395 // 1396 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1397 // CHECK10-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1398 // CHECK10-NEXT: entry: 1399 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1400 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1401 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1402 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1403 // CHECK10-NEXT: ret void 1404 // 1405 // 1406 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1407 // CHECK10-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1408 // CHECK10-NEXT: entry: 1409 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1410 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1411 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1412 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1413 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1414 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1415 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1416 // CHECK10-NEXT: ret void 1417 // 1418 // 1419 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 1420 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 1421 // CHECK10-NEXT: entry: 1422 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1423 // CHECK10-NEXT: ret void 1424 // 1425 // 1426 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 1427 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1428 // CHECK10-NEXT: entry: 1429 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1430 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1431 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1432 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1433 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1434 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1435 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1436 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1437 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1438 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1439 // CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1440 // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1441 // CHECK10: arrayctor.loop: 1442 // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1443 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1444 // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 1445 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1446 // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1447 // CHECK10: arrayctor.cont: 1448 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1449 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 1450 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 1451 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 1452 // CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 1453 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 1454 // CHECK10-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1455 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) 1456 // CHECK10-NEXT: store i32 3, i32* [[SIVAR]], align 4 1457 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1458 // CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1459 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 1460 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1461 // CHECK10: arraydestroy.body: 1462 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1463 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1464 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1465 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1466 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1467 // CHECK10: arraydestroy.done3: 1468 // CHECK10-NEXT: ret void 1469 // 1470 // 1471 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1472 // CHECK10-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1473 // CHECK10-NEXT: entry: 1474 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1475 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1476 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1477 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1478 // CHECK10-NEXT: ret void 1479 // 1480 // 1481 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1482 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { 1483 // CHECK10-NEXT: entry: 1484 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1485 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1486 // CHECK10-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 1487 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1488 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1489 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1490 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1491 // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1492 // CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[SST]]) 1493 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 1494 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1495 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1496 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1497 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 1498 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1499 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1500 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef signext 3) 1501 // CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1502 // CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1503 // CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1504 // CHECK10: omp_offload.failed: 1505 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] 1506 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1507 // CHECK10: omp_offload.cont: 1508 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1509 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1510 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1511 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1512 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1513 // CHECK10: arraydestroy.body: 1514 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1515 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1516 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1517 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1518 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1519 // CHECK10: arraydestroy.done1: 1520 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1521 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1522 // CHECK10-NEXT: ret i32 [[TMP4]] 1523 // 1524 // 1525 // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1526 // CHECK10-SAME: (%struct.SS* noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1527 // CHECK10-NEXT: entry: 1528 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1529 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 1530 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1531 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1532 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1533 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1534 // CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 1535 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1536 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 1537 // CHECK10-NEXT: store i32 0, i32* [[A]], align 8 1538 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1539 // CHECK10-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 1540 // CHECK10-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 1541 // CHECK10-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 1542 // CHECK10-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 1543 // CHECK10-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1544 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 1545 // CHECK10-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 1546 // CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1547 // CHECK10-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 1548 // CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 8 1549 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1550 // CHECK10-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 1551 // CHECK10-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 1552 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1553 // CHECK10-NEXT: store i8* null, i8** [[TMP5]], align 8 1554 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1555 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1556 // CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1557 // CHECK10-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 1558 // CHECK10-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1559 // CHECK10: omp_offload.failed: 1560 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] 1561 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1562 // CHECK10: omp_offload.cont: 1563 // CHECK10-NEXT: ret void 1564 // 1565 // 1566 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 1567 // CHECK10-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 1568 // CHECK10-NEXT: entry: 1569 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1570 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1571 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1572 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 1573 // CHECK10-NEXT: ret void 1574 // 1575 // 1576 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 1577 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 1578 // CHECK10-NEXT: entry: 1579 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1580 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1581 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 1582 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 1583 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1584 // CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4 1585 // CHECK10-NEXT: [[C:%.*]] = alloca i32, align 4 1586 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 1587 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1588 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1589 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 1590 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 1591 // CHECK10-NEXT: store i32* [[A]], i32** [[TMP]], align 8 1592 // CHECK10-NEXT: store i32* [[C]], i32** [[_TMP1]], align 8 1593 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 1594 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1595 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 1596 // CHECK10-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 1597 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 1598 // CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 1599 // CHECK10-NEXT: store i32 [[DEC]], i32* [[B]], align 4 1600 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 8 1601 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1602 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 1603 // CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 1604 // CHECK10-NEXT: ret void 1605 // 1606 // 1607 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1608 // CHECK10-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1609 // CHECK10-NEXT: entry: 1610 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1611 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1612 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1613 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1614 // CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 1615 // CHECK10-NEXT: ret void 1616 // 1617 // 1618 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1619 // CHECK10-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1620 // CHECK10-NEXT: entry: 1621 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1622 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1623 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1624 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1625 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1626 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1627 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1628 // CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 1629 // CHECK10-NEXT: ret void 1630 // 1631 // 1632 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1633 // CHECK10-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1634 // CHECK10-NEXT: entry: 1635 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1636 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1637 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1638 // CHECK10-NEXT: ret void 1639 // 1640 // 1641 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1642 // CHECK10-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1643 // CHECK10-NEXT: entry: 1644 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1645 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1646 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1647 // CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1648 // CHECK10-NEXT: ret void 1649 // 1650 // 1651 // CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 1652 // CHECK10-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1653 // CHECK10-NEXT: entry: 1654 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1655 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1656 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1657 // CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1658 // CHECK10-NEXT: ret void 1659 // 1660 // 1661 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1662 // CHECK10-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1663 // CHECK10-NEXT: entry: 1664 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1665 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1666 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1667 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1668 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1669 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1670 // CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1671 // CHECK10-NEXT: ret void 1672 // 1673 // 1674 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 1675 // CHECK10-SAME: () #[[ATTR3]] { 1676 // CHECK10-NEXT: entry: 1677 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 1678 // CHECK10-NEXT: ret void 1679 // 1680 // 1681 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 1682 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1683 // CHECK10-NEXT: entry: 1684 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1685 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1686 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1687 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1688 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1689 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1690 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1691 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1692 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1693 // CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1694 // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1695 // CHECK10: arrayctor.loop: 1696 // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1697 // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1698 // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 1699 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1700 // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1701 // CHECK10: arrayctor.cont: 1702 // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1703 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 1704 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 1705 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 1706 // CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1707 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 1708 // CHECK10-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 1709 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) 1710 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1711 // CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1712 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 1713 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1714 // CHECK10: arraydestroy.body: 1715 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1716 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1717 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1718 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1719 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1720 // CHECK10: arraydestroy.done3: 1721 // CHECK10-NEXT: ret void 1722 // 1723 // 1724 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1725 // CHECK10-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1726 // CHECK10-NEXT: entry: 1727 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1728 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1729 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1730 // CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1731 // CHECK10-NEXT: ret void 1732 // 1733 // 1734 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1735 // CHECK10-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1736 // CHECK10-NEXT: entry: 1737 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1738 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1739 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1740 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1741 // CHECK10-NEXT: store i32 0, i32* [[F]], align 4 1742 // CHECK10-NEXT: ret void 1743 // 1744 // 1745 // CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 1746 // CHECK10-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1747 // CHECK10-NEXT: entry: 1748 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1749 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1750 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1751 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1752 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1753 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1754 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 1755 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 1756 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1757 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** 1758 // CHECK10-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 8 1759 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1760 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** 1761 // CHECK10-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 8 1762 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1763 // CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 1764 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1765 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1766 // CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1767 // CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1768 // CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1769 // CHECK10: omp_offload.failed: 1770 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] 1771 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1772 // CHECK10: omp_offload.cont: 1773 // CHECK10-NEXT: ret void 1774 // 1775 // 1776 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 1777 // CHECK10-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 1778 // CHECK10-NEXT: entry: 1779 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1780 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1781 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1782 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) 1783 // CHECK10-NEXT: ret void 1784 // 1785 // 1786 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 1787 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 1788 // CHECK10-NEXT: entry: 1789 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1790 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1791 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 1792 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 1793 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1794 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1795 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1796 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 1797 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 1798 // CHECK10-NEXT: store i32* [[A]], i32** [[TMP]], align 8 1799 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 1800 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1801 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 1802 // CHECK10-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 1803 // CHECK10-NEXT: ret void 1804 // 1805 // 1806 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1807 // CHECK10-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1808 // CHECK10-NEXT: entry: 1809 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1810 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1811 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1812 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1813 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1814 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1815 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1816 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1817 // CHECK10-NEXT: ret void 1818 // 1819 // 1820 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1821 // CHECK10-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1822 // CHECK10-NEXT: entry: 1823 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1824 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1825 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1826 // CHECK10-NEXT: ret void 1827 // 1828 // 1829 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1830 // CHECK10-SAME: () #[[ATTR6:[0-9]+]] { 1831 // CHECK10-NEXT: entry: 1832 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 1833 // CHECK10-NEXT: ret void 1834 // 1835 // 1836 // CHECK11-LABEL: define {{[^@]+}}@main 1837 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1838 // CHECK11-NEXT: entry: 1839 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1840 // CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 1841 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1842 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1843 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1844 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1845 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1846 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1847 // CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 1848 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1849 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 1850 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1851 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 1852 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1853 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) 1854 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 1855 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 1856 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00) 1857 // CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1858 // CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1859 // CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1860 // CHECK11: omp_offload.failed: 1861 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] 1862 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1863 // CHECK11: omp_offload.cont: 1864 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1865 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1866 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1867 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1868 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1869 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1870 // CHECK11: arraydestroy.body: 1871 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1872 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1873 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1874 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1875 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1876 // CHECK11: arraydestroy.done1: 1877 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1878 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1879 // CHECK11-NEXT: ret i32 [[TMP4]] 1880 // 1881 // 1882 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 1883 // CHECK11-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1884 // CHECK11-NEXT: entry: 1885 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1886 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 1887 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1888 // CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 1889 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1890 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 1891 // CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 1892 // CHECK11-NEXT: ret void 1893 // 1894 // 1895 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1896 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1897 // CHECK11-NEXT: entry: 1898 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1899 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1900 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1901 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1902 // CHECK11-NEXT: ret void 1903 // 1904 // 1905 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1906 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1907 // CHECK11-NEXT: entry: 1908 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1909 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1910 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1911 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1912 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1913 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1914 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1915 // CHECK11-NEXT: ret void 1916 // 1917 // 1918 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 1919 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 1920 // CHECK11-NEXT: entry: 1921 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1922 // CHECK11-NEXT: ret void 1923 // 1924 // 1925 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 1926 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 1927 // CHECK11-NEXT: entry: 1928 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1929 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1930 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1931 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1932 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1933 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1934 // CHECK11-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1935 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1936 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1937 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1938 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1939 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1940 // CHECK11: arrayctor.loop: 1941 // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1942 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1943 // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1944 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1945 // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1946 // CHECK11: arrayctor.cont: 1947 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1948 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 1949 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 1950 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 1951 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1952 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 1953 // CHECK11-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1954 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) 1955 // CHECK11-NEXT: store i32 3, i32* [[SIVAR]], align 4 1956 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1957 // CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1958 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 1959 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1960 // CHECK11: arraydestroy.body: 1961 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1962 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1963 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1964 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1965 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1966 // CHECK11: arraydestroy.done3: 1967 // CHECK11-NEXT: ret void 1968 // 1969 // 1970 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1971 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1972 // CHECK11-NEXT: entry: 1973 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1974 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1975 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1976 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1977 // CHECK11-NEXT: ret void 1978 // 1979 // 1980 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1981 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { 1982 // CHECK11-NEXT: entry: 1983 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1984 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1985 // CHECK11-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 1986 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1987 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1988 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1989 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1990 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1991 // CHECK11-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[SST]]) 1992 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 128 1993 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1994 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1995 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1996 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 1997 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1998 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1999 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) 2000 // CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 2001 // CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 2002 // CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2003 // CHECK11: omp_offload.failed: 2004 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] 2005 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2006 // CHECK11: omp_offload.cont: 2007 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2008 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2009 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2010 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2011 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2012 // CHECK11: arraydestroy.body: 2013 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2014 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2015 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2016 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2017 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2018 // CHECK11: arraydestroy.done1: 2019 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2020 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 2021 // CHECK11-NEXT: ret i32 [[TMP4]] 2022 // 2023 // 2024 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 2025 // CHECK11-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2026 // CHECK11-NEXT: entry: 2027 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2028 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 2029 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2030 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2031 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2032 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2033 // CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 2034 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2035 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 2036 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 2037 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 2038 // CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 2039 // CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 2040 // CHECK11-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 2041 // CHECK11-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 2042 // CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 2043 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 2044 // CHECK11-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 2045 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2046 // CHECK11-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 2047 // CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 2048 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2049 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 2050 // CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 2051 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2052 // CHECK11-NEXT: store i8* null, i8** [[TMP5]], align 4 2053 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2054 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2055 // CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2056 // CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 2057 // CHECK11-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2058 // CHECK11: omp_offload.failed: 2059 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] 2060 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2061 // CHECK11: omp_offload.cont: 2062 // CHECK11-NEXT: ret void 2063 // 2064 // 2065 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 2066 // CHECK11-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 2067 // CHECK11-NEXT: entry: 2068 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2069 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2070 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2071 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 2072 // CHECK11-NEXT: ret void 2073 // 2074 // 2075 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2076 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 2077 // CHECK11-NEXT: entry: 2078 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2079 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2080 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2081 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 2082 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2083 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 2084 // CHECK11-NEXT: [[C:%.*]] = alloca i32, align 4 2085 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 2086 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2087 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2088 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2089 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2090 // CHECK11-NEXT: store i32* [[A]], i32** [[TMP]], align 4 2091 // CHECK11-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 2092 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 2093 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2094 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 2095 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 2096 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 2097 // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 2098 // CHECK11-NEXT: store i32 [[DEC]], i32* [[B]], align 4 2099 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 2100 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2101 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 2102 // CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 2103 // CHECK11-NEXT: ret void 2104 // 2105 // 2106 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2107 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2108 // CHECK11-NEXT: entry: 2109 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2110 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2111 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2112 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2113 // CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 2114 // CHECK11-NEXT: ret void 2115 // 2116 // 2117 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2118 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2119 // CHECK11-NEXT: entry: 2120 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2121 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2122 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2123 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2124 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2125 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2126 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2127 // CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 2128 // CHECK11-NEXT: ret void 2129 // 2130 // 2131 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2132 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2133 // CHECK11-NEXT: entry: 2134 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2135 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2136 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2137 // CHECK11-NEXT: ret void 2138 // 2139 // 2140 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2141 // CHECK11-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2142 // CHECK11-NEXT: entry: 2143 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2144 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2145 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2146 // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2147 // CHECK11-NEXT: ret void 2148 // 2149 // 2150 // CHECK11-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 2151 // CHECK11-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2152 // CHECK11-NEXT: entry: 2153 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2154 // CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2155 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2156 // CHECK11-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2157 // CHECK11-NEXT: ret void 2158 // 2159 // 2160 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2161 // CHECK11-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2162 // CHECK11-NEXT: entry: 2163 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2164 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2165 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2166 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2167 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2168 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2169 // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2170 // CHECK11-NEXT: ret void 2171 // 2172 // 2173 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 2174 // CHECK11-SAME: () #[[ATTR3]] { 2175 // CHECK11-NEXT: entry: 2176 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 2177 // CHECK11-NEXT: ret void 2178 // 2179 // 2180 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 2181 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2182 // CHECK11-NEXT: entry: 2183 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2184 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2185 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2186 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2187 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2188 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 2189 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2190 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2191 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2192 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2193 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2194 // CHECK11: arrayctor.loop: 2195 // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2196 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2197 // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 2198 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2199 // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2200 // CHECK11: arrayctor.cont: 2201 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 2202 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 2203 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 2204 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 2205 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2206 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 2207 // CHECK11-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 2208 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) 2209 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2210 // CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2211 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 2212 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2213 // CHECK11: arraydestroy.body: 2214 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2215 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2216 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2217 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 2218 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 2219 // CHECK11: arraydestroy.done3: 2220 // CHECK11-NEXT: ret void 2221 // 2222 // 2223 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2224 // CHECK11-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2225 // CHECK11-NEXT: entry: 2226 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2227 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2228 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2229 // CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2230 // CHECK11-NEXT: ret void 2231 // 2232 // 2233 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2234 // CHECK11-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2235 // CHECK11-NEXT: entry: 2236 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2237 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2238 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2239 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2240 // CHECK11-NEXT: store i32 0, i32* [[F]], align 4 2241 // CHECK11-NEXT: ret void 2242 // 2243 // 2244 // CHECK11-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 2245 // CHECK11-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2246 // CHECK11-NEXT: entry: 2247 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2248 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2249 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2250 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2251 // CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2252 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2253 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 2254 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 2255 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2256 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** 2257 // CHECK11-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 4 2258 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2259 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** 2260 // CHECK11-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 4 2261 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2262 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 2263 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2264 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2265 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2266 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2267 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2268 // CHECK11: omp_offload.failed: 2269 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] 2270 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2271 // CHECK11: omp_offload.cont: 2272 // CHECK11-NEXT: ret void 2273 // 2274 // 2275 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 2276 // CHECK11-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 2277 // CHECK11-NEXT: entry: 2278 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2279 // CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2280 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2281 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) 2282 // CHECK11-NEXT: ret void 2283 // 2284 // 2285 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 2286 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 2287 // CHECK11-NEXT: entry: 2288 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2289 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2290 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2291 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 2292 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2293 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2294 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2295 // CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2296 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2297 // CHECK11-NEXT: store i32* [[A]], i32** [[TMP]], align 4 2298 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 2299 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2300 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 2301 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 2302 // CHECK11-NEXT: ret void 2303 // 2304 // 2305 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2306 // CHECK11-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2307 // CHECK11-NEXT: entry: 2308 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2309 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2310 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2311 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2312 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2313 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2314 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2315 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2316 // CHECK11-NEXT: ret void 2317 // 2318 // 2319 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2320 // CHECK11-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2321 // CHECK11-NEXT: entry: 2322 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2323 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2324 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2325 // CHECK11-NEXT: ret void 2326 // 2327 // 2328 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2329 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { 2330 // CHECK11-NEXT: entry: 2331 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 2332 // CHECK11-NEXT: ret void 2333 // 2334 // 2335 // CHECK12-LABEL: define {{[^@]+}}@main 2336 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 2337 // CHECK12-NEXT: entry: 2338 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2339 // CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 2340 // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2341 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2342 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2343 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2344 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 2345 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2346 // CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 2347 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2348 // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 2349 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2350 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 2351 // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2352 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) 2353 // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 2354 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 2355 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00) 2356 // CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 2357 // CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 2358 // CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2359 // CHECK12: omp_offload.failed: 2360 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] 2361 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2362 // CHECK12: omp_offload.cont: 2363 // CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2364 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2365 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2366 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2367 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2368 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2369 // CHECK12: arraydestroy.body: 2370 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2371 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2372 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2373 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2374 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2375 // CHECK12: arraydestroy.done1: 2376 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2377 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 2378 // CHECK12-NEXT: ret i32 [[TMP4]] 2379 // 2380 // 2381 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 2382 // CHECK12-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2383 // CHECK12-NEXT: entry: 2384 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2385 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 2386 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2387 // CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 2388 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2389 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 2390 // CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) 2391 // CHECK12-NEXT: ret void 2392 // 2393 // 2394 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2395 // CHECK12-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2396 // CHECK12-NEXT: entry: 2397 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2398 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2399 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2400 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2401 // CHECK12-NEXT: ret void 2402 // 2403 // 2404 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2405 // CHECK12-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2406 // CHECK12-NEXT: entry: 2407 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2408 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2409 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2410 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2411 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2412 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2413 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2414 // CHECK12-NEXT: ret void 2415 // 2416 // 2417 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136 2418 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 2419 // CHECK12-NEXT: entry: 2420 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2421 // CHECK12-NEXT: ret void 2422 // 2423 // 2424 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2425 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2426 // CHECK12-NEXT: entry: 2427 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2428 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2429 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2430 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2431 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2432 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2433 // CHECK12-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2434 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2435 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2436 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2437 // CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2438 // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2439 // CHECK12: arrayctor.loop: 2440 // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2441 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2442 // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 2443 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2444 // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2445 // CHECK12: arrayctor.cont: 2446 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 2447 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 2448 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 2449 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 2450 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2451 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 2452 // CHECK12-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* 2453 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) 2454 // CHECK12-NEXT: store i32 3, i32* [[SIVAR]], align 4 2455 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2456 // CHECK12-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2457 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 2458 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2459 // CHECK12: arraydestroy.body: 2460 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2461 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2462 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2463 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 2464 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 2465 // CHECK12: arraydestroy.done3: 2466 // CHECK12-NEXT: ret void 2467 // 2468 // 2469 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2470 // CHECK12-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2471 // CHECK12-NEXT: entry: 2472 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2473 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2474 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2475 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2476 // CHECK12-NEXT: ret void 2477 // 2478 // 2479 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2480 // CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { 2481 // CHECK12-NEXT: entry: 2482 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2483 // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2484 // CHECK12-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 2485 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2486 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2487 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2488 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 2489 // CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2490 // CHECK12-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[SST]]) 2491 // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 128 2492 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2493 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2494 // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2495 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 2496 // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2497 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2498 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) 2499 // CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 2500 // CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 2501 // CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2502 // CHECK12: omp_offload.failed: 2503 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86() #[[ATTR4]] 2504 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2505 // CHECK12: omp_offload.cont: 2506 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2507 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2508 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2509 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2510 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2511 // CHECK12: arraydestroy.body: 2512 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2513 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2514 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2515 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2516 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2517 // CHECK12: arraydestroy.done1: 2518 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2519 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 2520 // CHECK12-NEXT: ret i32 [[TMP4]] 2521 // 2522 // 2523 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 2524 // CHECK12-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2525 // CHECK12-NEXT: entry: 2526 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2527 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 2528 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2529 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2530 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2531 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2532 // CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 2533 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2534 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 2535 // CHECK12-NEXT: store i32 0, i32* [[A]], align 4 2536 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 2537 // CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 2538 // CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 2539 // CHECK12-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 2540 // CHECK12-NEXT: store i8 [[BF_SET]], i8* [[B]], align 4 2541 // CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 2542 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 2543 // CHECK12-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 2544 // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2545 // CHECK12-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to %struct.SS** 2546 // CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP2]], align 4 2547 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2548 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to %struct.SS** 2549 // CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 4 2550 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2551 // CHECK12-NEXT: store i8* null, i8** [[TMP5]], align 4 2552 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2553 // CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2554 // CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2555 // CHECK12-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 2556 // CHECK12-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2557 // CHECK12: omp_offload.failed: 2558 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48(%struct.SS* [[THIS1]]) #[[ATTR4]] 2559 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2560 // CHECK12: omp_offload.cont: 2561 // CHECK12-NEXT: ret void 2562 // 2563 // 2564 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 2565 // CHECK12-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 2566 // CHECK12-NEXT: entry: 2567 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2568 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2569 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2570 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 2571 // CHECK12-NEXT: ret void 2572 // 2573 // 2574 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2575 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { 2576 // CHECK12-NEXT: entry: 2577 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2578 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2579 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2580 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 2581 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2582 // CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 2583 // CHECK12-NEXT: [[C:%.*]] = alloca i32, align 4 2584 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 2585 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2586 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2587 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2588 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2589 // CHECK12-NEXT: store i32* [[A]], i32** [[TMP]], align 4 2590 // CHECK12-NEXT: store i32* [[C]], i32** [[_TMP1]], align 4 2591 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 2592 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2593 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 2594 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 2595 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B]], align 4 2596 // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 2597 // CHECK12-NEXT: store i32 [[DEC]], i32* [[B]], align 4 2598 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 2599 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2600 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 2601 // CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 2602 // CHECK12-NEXT: ret void 2603 // 2604 // 2605 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2606 // CHECK12-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2607 // CHECK12-NEXT: entry: 2608 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2609 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2610 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2611 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2612 // CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 2613 // CHECK12-NEXT: ret void 2614 // 2615 // 2616 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2617 // CHECK12-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2618 // CHECK12-NEXT: entry: 2619 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2620 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2621 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2622 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2623 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2624 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2625 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2626 // CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 2627 // CHECK12-NEXT: ret void 2628 // 2629 // 2630 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2631 // CHECK12-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2632 // CHECK12-NEXT: entry: 2633 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2634 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2635 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2636 // CHECK12-NEXT: ret void 2637 // 2638 // 2639 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2640 // CHECK12-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2641 // CHECK12-NEXT: entry: 2642 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2643 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2644 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2645 // CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2646 // CHECK12-NEXT: ret void 2647 // 2648 // 2649 // CHECK12-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 2650 // CHECK12-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2651 // CHECK12-NEXT: entry: 2652 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2653 // CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2654 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2655 // CHECK12-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2656 // CHECK12-NEXT: ret void 2657 // 2658 // 2659 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2660 // CHECK12-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2661 // CHECK12-NEXT: entry: 2662 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2663 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2664 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2665 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2666 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2667 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2668 // CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2669 // CHECK12-NEXT: ret void 2670 // 2671 // 2672 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86 2673 // CHECK12-SAME: () #[[ATTR3]] { 2674 // CHECK12-NEXT: entry: 2675 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 2676 // CHECK12-NEXT: ret void 2677 // 2678 // 2679 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 2680 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 2681 // CHECK12-NEXT: entry: 2682 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2683 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2684 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2685 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2686 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2687 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 2688 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2689 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2690 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2691 // CHECK12-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2692 // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2693 // CHECK12: arrayctor.loop: 2694 // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2695 // CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2696 // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 2697 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2698 // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2699 // CHECK12: arrayctor.cont: 2700 // CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 2701 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 2702 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 2703 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 2704 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2705 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 2706 // CHECK12-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 2707 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) 2708 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2709 // CHECK12-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2710 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 2711 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2712 // CHECK12: arraydestroy.body: 2713 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2714 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2715 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2716 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 2717 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 2718 // CHECK12: arraydestroy.done3: 2719 // CHECK12-NEXT: ret void 2720 // 2721 // 2722 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2723 // CHECK12-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2724 // CHECK12-NEXT: entry: 2725 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2726 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2727 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2728 // CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2729 // CHECK12-NEXT: ret void 2730 // 2731 // 2732 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2733 // CHECK12-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2734 // CHECK12-NEXT: entry: 2735 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2736 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2737 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2738 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2739 // CHECK12-NEXT: store i32 0, i32* [[F]], align 4 2740 // CHECK12-NEXT: ret void 2741 // 2742 // 2743 // CHECK12-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 2744 // CHECK12-SAME: (%struct.SST* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2745 // CHECK12-NEXT: entry: 2746 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2747 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2748 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2749 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2750 // CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2751 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2752 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 2753 // CHECK12-NEXT: store i32 0, i32* [[A]], align 4 2754 // CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2755 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SST** 2756 // CHECK12-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP1]], align 4 2757 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2758 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SST** 2759 // CHECK12-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP3]], align 4 2760 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2761 // CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 2762 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2763 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2764 // CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2765 // CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2766 // CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2767 // CHECK12: omp_offload.failed: 2768 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64(%struct.SST* [[THIS1]]) #[[ATTR4]] 2769 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2770 // CHECK12: omp_offload.cont: 2771 // CHECK12-NEXT: ret void 2772 // 2773 // 2774 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 2775 // CHECK12-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 2776 // CHECK12-NEXT: entry: 2777 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2778 // CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2779 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2780 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SST* [[TMP0]]) 2781 // CHECK12-NEXT: ret void 2782 // 2783 // 2784 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 2785 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { 2786 // CHECK12-NEXT: entry: 2787 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2788 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2789 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 2790 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 2791 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2792 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2793 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2794 // CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 2795 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 2796 // CHECK12-NEXT: store i32* [[A]], i32** [[TMP]], align 4 2797 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 2798 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2799 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 2800 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 2801 // CHECK12-NEXT: ret void 2802 // 2803 // 2804 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2805 // CHECK12-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2806 // CHECK12-NEXT: entry: 2807 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2808 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2809 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2810 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2811 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2812 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2813 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2814 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2815 // CHECK12-NEXT: ret void 2816 // 2817 // 2818 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2819 // CHECK12-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2820 // CHECK12-NEXT: entry: 2821 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2822 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2823 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2824 // CHECK12-NEXT: ret void 2825 // 2826 // 2827 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2828 // CHECK12-SAME: () #[[ATTR6:[0-9]+]] { 2829 // CHECK12-NEXT: entry: 2830 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 2831 // CHECK12-NEXT: ret void 2832 // 2833