1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target 33 #pragma omp teams distribute simd reduction(+: t_var) 34 for (int i = 0; i < 2; ++i) { 35 t_var += (T) i; 36 } 37 return T(); 38 } 39 40 int main() { 41 static int sivar; 42 #ifdef LAMBDA 43 44 [&]() { 45 #pragma omp target 46 #pragma omp teams distribute simd reduction(+: sivar) 47 for (int i = 0; i < 2; ++i) { 48 49 // Skip global and bound tid vars 50 51 52 sivar += i; 53 54 [&]() { 55 56 sivar += 4; 57 58 }(); 59 } 60 }(); 61 return 0; 62 #else 63 #pragma omp target 64 #pragma omp teams distribute simd reduction(+: sivar) 65 for (int i = 0; i < 2; ++i) { 66 sivar += i; 67 } 68 return tmain<int>(); 69 #endif 70 } 71 72 73 74 75 // Skip global and bound tid vars 76 77 78 79 80 81 // Skip global and bound tid vars 82 83 84 #endif 85 // CHECK1-LABEL: define {{[^@]+}}@main 86 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 87 // CHECK1-NEXT: entry: 88 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 89 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 90 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 91 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 92 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 93 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 94 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 95 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 96 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 97 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 98 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 99 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 100 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 101 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 102 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 103 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 104 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 105 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 106 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 107 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 108 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 109 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 110 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 111 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 112 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 113 // CHECK1: omp_offload.failed: 114 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 115 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 116 // CHECK1: omp_offload.cont: 117 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 118 // CHECK1-NEXT: ret i32 [[CALL]] 119 // 120 // 121 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 122 // CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 123 // CHECK1-NEXT: entry: 124 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 125 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 126 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 127 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 128 // CHECK1-NEXT: ret void 129 // 130 // 131 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 132 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 133 // CHECK1-NEXT: entry: 134 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 135 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 136 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 137 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 138 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 139 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 140 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 141 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 142 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 143 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 144 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 145 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 146 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 147 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 148 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 149 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 150 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4 151 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 152 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 153 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 154 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 155 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 156 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 157 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 158 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 159 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 160 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 161 // CHECK1: cond.true: 162 // CHECK1-NEXT: br label [[COND_END:%.*]] 163 // CHECK1: cond.false: 164 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 165 // CHECK1-NEXT: br label [[COND_END]] 166 // CHECK1: cond.end: 167 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 168 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 169 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 170 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 171 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 172 // CHECK1: omp.inner.for.cond: 173 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 174 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 175 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 176 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 177 // CHECK1: omp.inner.for.body: 178 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 179 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 180 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 181 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 182 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 183 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 184 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 185 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 186 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 187 // CHECK1: omp.body.continue: 188 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 189 // CHECK1: omp.inner.for.inc: 190 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 191 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 192 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 193 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 194 // CHECK1: omp.inner.for.end: 195 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 196 // CHECK1: omp.loop.exit: 197 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 198 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 199 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 200 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 201 // CHECK1: .omp.final.then: 202 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 203 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 204 // CHECK1: .omp.final.done: 205 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 206 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 207 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 208 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 209 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 210 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 211 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 212 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 213 // CHECK1-NEXT: ] 214 // CHECK1: .omp.reduction.case1: 215 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 216 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 217 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 218 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 219 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 220 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 221 // CHECK1: .omp.reduction.case2: 222 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 223 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 224 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 225 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 226 // CHECK1: .omp.reduction.default: 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 231 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 234 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 235 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 236 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 237 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 238 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 239 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 240 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 241 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 242 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 243 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 244 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 245 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 246 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 247 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 248 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 249 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 250 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 251 // CHECK1-NEXT: ret void 252 // 253 // 254 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 255 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat { 256 // CHECK1-NEXT: entry: 257 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 258 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 259 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 260 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 261 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 262 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 263 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 264 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 265 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 266 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 267 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 268 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 269 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 271 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 272 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 273 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 274 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 275 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 276 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 277 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 278 // CHECK1-NEXT: store i8* null, i8** [[TMP7]], align 8 279 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 280 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 281 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 282 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 283 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 284 // CHECK1-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 285 // CHECK1: omp_offload.failed: 286 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP2]]) #[[ATTR2]] 287 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 288 // CHECK1: omp_offload.cont: 289 // CHECK1-NEXT: ret i32 0 290 // 291 // 292 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 293 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { 294 // CHECK1-NEXT: entry: 295 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 296 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 297 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 298 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 299 // CHECK1-NEXT: ret void 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 303 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 306 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 307 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 308 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 309 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 311 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 312 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 313 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 315 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 316 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 317 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 318 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 319 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 320 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 321 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4 322 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 323 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 324 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 325 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 326 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 327 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 328 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 329 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 330 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 331 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 332 // CHECK1: cond.true: 333 // CHECK1-NEXT: br label [[COND_END:%.*]] 334 // CHECK1: cond.false: 335 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 336 // CHECK1-NEXT: br label [[COND_END]] 337 // CHECK1: cond.end: 338 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 339 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 340 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 341 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 342 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 343 // CHECK1: omp.inner.for.cond: 344 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 345 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 346 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 347 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 348 // CHECK1: omp.inner.for.body: 349 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 350 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 352 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 353 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 354 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 355 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 356 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 357 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 358 // CHECK1: omp.body.continue: 359 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 360 // CHECK1: omp.inner.for.inc: 361 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 362 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 363 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 364 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 365 // CHECK1: omp.inner.for.end: 366 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 367 // CHECK1: omp.loop.exit: 368 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 369 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 370 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 371 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 372 // CHECK1: .omp.final.then: 373 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 374 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 375 // CHECK1: .omp.final.done: 376 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 377 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 378 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 379 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 380 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 381 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 382 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 383 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 384 // CHECK1-NEXT: ] 385 // CHECK1: .omp.reduction.case1: 386 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 387 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 388 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 389 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 390 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 391 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 392 // CHECK1: .omp.reduction.case2: 393 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 394 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 395 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 396 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 397 // CHECK1: .omp.reduction.default: 398 // CHECK1-NEXT: ret void 399 // 400 // 401 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 402 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { 403 // CHECK1-NEXT: entry: 404 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 405 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 406 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 407 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 408 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 409 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 410 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 411 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 412 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 413 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 414 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 415 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 416 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 417 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 418 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 419 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 420 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 421 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 422 // CHECK1-NEXT: ret void 423 // 424 // 425 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 426 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] { 427 // CHECK1-NEXT: entry: 428 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 429 // CHECK1-NEXT: ret void 430 // 431 // 432 // CHECK3-LABEL: define {{[^@]+}}@main 433 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 434 // CHECK3-NEXT: entry: 435 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 436 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 437 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 438 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 439 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 440 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 441 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 442 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 443 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4 444 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 445 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 446 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 447 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 448 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 449 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 450 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 451 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 452 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 453 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 454 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 455 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 456 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 457 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 458 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 459 // CHECK3: omp_offload.failed: 460 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 461 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 462 // CHECK3: omp_offload.cont: 463 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 464 // CHECK3-NEXT: ret i32 [[CALL]] 465 // 466 // 467 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 468 // CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 469 // CHECK3-NEXT: entry: 470 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 471 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 472 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[SIVAR_ADDR]]) 473 // CHECK3-NEXT: ret void 474 // 475 // 476 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 477 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 478 // CHECK3-NEXT: entry: 479 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 480 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 481 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 482 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 483 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 484 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 485 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 486 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 487 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 488 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 489 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 490 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 491 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 492 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 493 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 494 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 495 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4 496 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 497 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 498 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 499 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 500 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 501 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 502 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 503 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 504 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 505 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 506 // CHECK3: cond.true: 507 // CHECK3-NEXT: br label [[COND_END:%.*]] 508 // CHECK3: cond.false: 509 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 510 // CHECK3-NEXT: br label [[COND_END]] 511 // CHECK3: cond.end: 512 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 513 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 514 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 515 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 516 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 517 // CHECK3: omp.inner.for.cond: 518 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 519 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 520 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 521 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 522 // CHECK3: omp.inner.for.body: 523 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 524 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 525 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 526 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 527 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 528 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 529 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 530 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 531 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 532 // CHECK3: omp.body.continue: 533 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 534 // CHECK3: omp.inner.for.inc: 535 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 536 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 537 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 538 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 539 // CHECK3: omp.inner.for.end: 540 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 541 // CHECK3: omp.loop.exit: 542 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 543 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 544 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 545 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 546 // CHECK3: .omp.final.then: 547 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 548 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 549 // CHECK3: .omp.final.done: 550 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 551 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 552 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 553 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 554 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 555 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 556 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 557 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 558 // CHECK3-NEXT: ] 559 // CHECK3: .omp.reduction.case1: 560 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 561 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 562 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 563 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 564 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 565 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 566 // CHECK3: .omp.reduction.case2: 567 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 568 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 569 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 570 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 571 // CHECK3: .omp.reduction.default: 572 // CHECK3-NEXT: ret void 573 // 574 // 575 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 576 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 577 // CHECK3-NEXT: entry: 578 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 579 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 580 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 581 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 582 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 583 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 584 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 585 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 586 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 587 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 588 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 589 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 590 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 591 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 592 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 593 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 594 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 595 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 596 // CHECK3-NEXT: ret void 597 // 598 // 599 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 600 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat { 601 // CHECK3-NEXT: entry: 602 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 603 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 604 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 605 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 606 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 607 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 608 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 609 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 610 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 611 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 612 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 613 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 614 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 615 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 616 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 617 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 618 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 619 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 620 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 621 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 622 // CHECK3-NEXT: store i8* null, i8** [[TMP7]], align 4 623 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 624 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 625 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 626 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 627 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 628 // CHECK3-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 629 // CHECK3: omp_offload.failed: 630 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP2]]) #[[ATTR2]] 631 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 632 // CHECK3: omp_offload.cont: 633 // CHECK3-NEXT: ret i32 0 634 // 635 // 636 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 637 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { 638 // CHECK3-NEXT: entry: 639 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 640 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 641 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]]) 642 // CHECK3-NEXT: ret void 643 // 644 // 645 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 646 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 647 // CHECK3-NEXT: entry: 648 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 649 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 650 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 651 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 652 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 653 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 654 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 655 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 656 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 657 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 658 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 659 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 660 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 661 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 662 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 663 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 664 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4 665 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 666 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 667 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 668 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 669 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 670 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 671 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 672 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 673 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 674 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 675 // CHECK3: cond.true: 676 // CHECK3-NEXT: br label [[COND_END:%.*]] 677 // CHECK3: cond.false: 678 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 679 // CHECK3-NEXT: br label [[COND_END]] 680 // CHECK3: cond.end: 681 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 682 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 683 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 684 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 685 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 686 // CHECK3: omp.inner.for.cond: 687 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 688 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 689 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 690 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 691 // CHECK3: omp.inner.for.body: 692 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 693 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 694 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 695 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 696 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 697 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 698 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 699 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 700 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 701 // CHECK3: omp.body.continue: 702 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 703 // CHECK3: omp.inner.for.inc: 704 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 705 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 706 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 707 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 708 // CHECK3: omp.inner.for.end: 709 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 710 // CHECK3: omp.loop.exit: 711 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 712 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 713 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 714 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 715 // CHECK3: .omp.final.then: 716 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 717 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 718 // CHECK3: .omp.final.done: 719 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 720 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 721 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 722 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 723 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 724 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 725 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 726 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 727 // CHECK3-NEXT: ] 728 // CHECK3: .omp.reduction.case1: 729 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 730 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 731 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 732 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 733 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 734 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 735 // CHECK3: .omp.reduction.case2: 736 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 737 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 738 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 739 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 740 // CHECK3: .omp.reduction.default: 741 // CHECK3-NEXT: ret void 742 // 743 // 744 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 745 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { 746 // CHECK3-NEXT: entry: 747 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 748 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 749 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 750 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 751 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 752 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 753 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 754 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 755 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 756 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 757 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 758 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 759 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 760 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 761 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 762 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 763 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 764 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 765 // CHECK3-NEXT: ret void 766 // 767 // 768 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 769 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] { 770 // CHECK3-NEXT: entry: 771 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 772 // CHECK3-NEXT: ret void 773 // 774 // 775 // CHECK5-LABEL: define {{[^@]+}}@main 776 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 777 // CHECK5-NEXT: entry: 778 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 779 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 780 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 781 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 782 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 783 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 784 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 785 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 786 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 787 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 788 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 789 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 790 // CHECK5-NEXT: store i32 0, i32* [[SIVAR]], align 4 791 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 792 // CHECK5: omp.inner.for.cond: 793 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 794 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 795 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 796 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 797 // CHECK5: omp.inner.for.body: 798 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 799 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 800 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 801 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 802 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 803 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 804 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 805 // CHECK5-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2 806 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 807 // CHECK5: omp.body.continue: 808 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 809 // CHECK5: omp.inner.for.inc: 810 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 811 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 812 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 813 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 814 // CHECK5: omp.inner.for.end: 815 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 816 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 817 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 818 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 819 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 820 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 821 // CHECK5-NEXT: ret i32 [[CALL]] 822 // 823 // 824 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 825 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { 826 // CHECK5-NEXT: entry: 827 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 828 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 829 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 830 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 831 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 832 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 833 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 834 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 835 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 836 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 837 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 838 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 839 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 840 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 841 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 842 // CHECK5-NEXT: store i32 0, i32* [[T_VAR1]], align 4 843 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 844 // CHECK5: omp.inner.for.cond: 845 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 846 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 847 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 848 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 849 // CHECK5: omp.inner.for.body: 850 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 851 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 852 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 853 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 854 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 855 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6 856 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 857 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6 858 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 859 // CHECK5: omp.body.continue: 860 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 861 // CHECK5: omp.inner.for.inc: 862 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 863 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 864 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 865 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 866 // CHECK5: omp.inner.for.end: 867 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 868 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 869 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 870 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 871 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 872 // CHECK5-NEXT: ret i32 0 873 // 874 // 875 // CHECK7-LABEL: define {{[^@]+}}@main 876 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 877 // CHECK7-NEXT: entry: 878 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 879 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 880 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 881 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 882 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 883 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 884 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 885 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 886 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 887 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 888 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 889 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 890 // CHECK7-NEXT: store i32 0, i32* [[SIVAR]], align 4 891 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 892 // CHECK7: omp.inner.for.cond: 893 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 894 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 895 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 896 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 897 // CHECK7: omp.inner.for.body: 898 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 899 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 900 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 901 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 902 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 903 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 904 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 905 // CHECK7-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3 906 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 907 // CHECK7: omp.body.continue: 908 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 909 // CHECK7: omp.inner.for.inc: 910 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 911 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 912 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 913 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 914 // CHECK7: omp.inner.for.end: 915 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 916 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 917 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 918 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 919 // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 920 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 921 // CHECK7-NEXT: ret i32 [[CALL]] 922 // 923 // 924 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 925 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 926 // CHECK7-NEXT: entry: 927 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 928 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 929 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 930 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 931 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 932 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 933 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 934 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 935 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 936 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 937 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 938 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 939 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 940 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 941 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 942 // CHECK7-NEXT: store i32 0, i32* [[T_VAR1]], align 4 943 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 944 // CHECK7: omp.inner.for.cond: 945 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 946 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 947 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 948 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 949 // CHECK7: omp.inner.for.body: 950 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 951 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 952 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 953 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 954 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 955 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7 956 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 957 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7 958 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 959 // CHECK7: omp.body.continue: 960 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 961 // CHECK7: omp.inner.for.inc: 962 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 963 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 964 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 965 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 966 // CHECK7: omp.inner.for.end: 967 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 968 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 969 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 970 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 971 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 972 // CHECK7-NEXT: ret i32 0 973 // 974 // 975 // CHECK9-LABEL: define {{[^@]+}}@main 976 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 977 // CHECK9-NEXT: entry: 978 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 979 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 980 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 981 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 982 // CHECK9-NEXT: ret i32 0 983 // 984 // 985 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 986 // CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 987 // CHECK9-NEXT: entry: 988 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 989 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 990 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 991 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 992 // CHECK9-NEXT: ret void 993 // 994 // 995 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 996 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 997 // CHECK9-NEXT: entry: 998 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 999 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1000 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 1001 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1002 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1003 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1004 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1005 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1006 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1007 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1008 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1009 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1010 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 1011 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1012 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1013 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 1014 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 1015 // CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 1016 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1017 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1018 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1019 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1020 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1021 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1022 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1023 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1024 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1025 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1026 // CHECK9: cond.true: 1027 // CHECK9-NEXT: br label [[COND_END:%.*]] 1028 // CHECK9: cond.false: 1029 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1030 // CHECK9-NEXT: br label [[COND_END]] 1031 // CHECK9: cond.end: 1032 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1033 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1034 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1035 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1036 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1037 // CHECK9: omp.inner.for.cond: 1038 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1039 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 1040 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1041 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1042 // CHECK9: omp.inner.for.body: 1043 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1044 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1045 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1046 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 1047 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 1048 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 1049 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1050 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 1051 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1052 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 1053 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 1054 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1055 // CHECK9: omp.body.continue: 1056 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1057 // CHECK9: omp.inner.for.inc: 1058 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1059 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 1060 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1061 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1062 // CHECK9: omp.inner.for.end: 1063 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1064 // CHECK9: omp.loop.exit: 1065 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1066 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1067 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1068 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1069 // CHECK9: .omp.final.then: 1070 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 1071 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1072 // CHECK9: .omp.final.done: 1073 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1074 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR1]] to i8* 1075 // CHECK9-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 1076 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1077 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 1078 // CHECK9-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1079 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1080 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1081 // CHECK9-NEXT: ] 1082 // CHECK9: .omp.reduction.case1: 1083 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 1084 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 1085 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1086 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1087 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1088 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1089 // CHECK9: .omp.reduction.case2: 1090 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4 1091 // CHECK9-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 1092 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1093 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1094 // CHECK9: .omp.reduction.default: 1095 // CHECK9-NEXT: ret void 1096 // 1097 // 1098 // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 1099 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 1100 // CHECK9-NEXT: entry: 1101 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1102 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1103 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1104 // CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1105 // CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1106 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1107 // CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1108 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1109 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 1110 // CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1111 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1112 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 1113 // CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1114 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1115 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1116 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1117 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1118 // CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1119 // CHECK9-NEXT: ret void 1120 // 1121 // 1122 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1123 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1124 // CHECK9-NEXT: entry: 1125 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1126 // CHECK9-NEXT: ret void 1127 // 1128 // 1129 // CHECK11-LABEL: define {{[^@]+}}@main 1130 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1131 // CHECK11-NEXT: entry: 1132 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1133 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1134 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1135 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1136 // CHECK11-NEXT: ret i32 0 1137 // 1138