1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
15
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 template <typename T>
tmain()29 T tmain() {
30 T t_var = T();
31 T vec[] = {1, 2};
32 #pragma omp target
33 #pragma omp teams distribute simd reduction(+: t_var)
34 for (int i = 0; i < 2; ++i) {
35 t_var += (T) i;
36 }
37 return T();
38 }
39
main()40 int main() {
41 static int sivar;
42 #ifdef LAMBDA
43
44 [&]() {
45 #pragma omp target
46 #pragma omp teams distribute simd reduction(+: sivar)
47 for (int i = 0; i < 2; ++i) {
48
49 // Skip global and bound tid vars
50
51
52 sivar += i;
53
54 [&]() {
55
56 sivar += 4;
57
58 }();
59 }
60 }();
61 return 0;
62 #else
63 #pragma omp target
64 #pragma omp teams distribute simd reduction(+: sivar)
65 for (int i = 0; i < 2; ++i) {
66 sivar += i;
67 }
68 return tmain<int>();
69 #endif
70 }
71
72
73
74
75 // Skip global and bound tid vars
76
77
78
79
80
81 // Skip global and bound tid vars
82
83
84 #endif
85 // CHECK1-LABEL: define {{[^@]+}}@main
86 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
87 // CHECK1-NEXT: entry:
88 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
89 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
90 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
91 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
92 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
93 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
94 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
95 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
96 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
97 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
98 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
99 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
100 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
101 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
102 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
103 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
104 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
105 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
106 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8
107 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
108 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
109 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
110 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
111 // CHECK1-NEXT: store i32 1, i32* [[TMP9]], align 4
112 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
113 // CHECK1-NEXT: store i32 1, i32* [[TMP10]], align 4
114 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
115 // CHECK1-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 8
116 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
117 // CHECK1-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 8
118 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
119 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP13]], align 8
120 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
121 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP14]], align 8
122 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
123 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8
124 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
125 // CHECK1-NEXT: store i8** null, i8*** [[TMP16]], align 8
126 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
127 // CHECK1-NEXT: store i64 2, i64* [[TMP17]], align 8
128 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
129 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
130 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
131 // CHECK1: omp_offload.failed:
132 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
133 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
134 // CHECK1: omp_offload.cont:
135 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
136 // CHECK1-NEXT: ret i32 [[CALL]]
137 //
138 //
139 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63
140 // CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
141 // CHECK1-NEXT: entry:
142 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
143 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
144 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
145 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
146 // CHECK1-NEXT: ret void
147 //
148 //
149 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
150 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
151 // CHECK1-NEXT: entry:
152 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
153 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
154 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
155 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
156 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
157 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
158 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
159 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
160 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
161 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
162 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
163 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
164 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
165 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
166 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
167 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
168 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4
169 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
170 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
171 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
172 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
173 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
174 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
175 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
176 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
177 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
178 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
179 // CHECK1: cond.true:
180 // CHECK1-NEXT: br label [[COND_END:%.*]]
181 // CHECK1: cond.false:
182 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
183 // CHECK1-NEXT: br label [[COND_END]]
184 // CHECK1: cond.end:
185 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
186 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
187 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
188 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
189 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
190 // CHECK1: omp.inner.for.cond:
191 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
192 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
193 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
194 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
195 // CHECK1: omp.inner.for.body:
196 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
197 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
198 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
199 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
200 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
201 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5
202 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
203 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5
204 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
205 // CHECK1: omp.body.continue:
206 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
207 // CHECK1: omp.inner.for.inc:
208 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
209 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
210 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
211 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
212 // CHECK1: omp.inner.for.end:
213 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
214 // CHECK1: omp.loop.exit:
215 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
216 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
217 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
218 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
219 // CHECK1: .omp.final.then:
220 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
221 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
222 // CHECK1: .omp.final.done:
223 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
224 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8*
225 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8
226 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
227 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
228 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
229 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
230 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
231 // CHECK1-NEXT: ]
232 // CHECK1: .omp.reduction.case1:
233 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
234 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4
235 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
236 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
237 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
238 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
239 // CHECK1: .omp.reduction.case2:
240 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4
241 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
242 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
243 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
244 // CHECK1: .omp.reduction.default:
245 // CHECK1-NEXT: ret void
246 //
247 //
248 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
249 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
250 // CHECK1-NEXT: entry:
251 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
252 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
253 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
254 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
255 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
256 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
257 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
258 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
259 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
260 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
261 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
262 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
263 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
264 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
265 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
266 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
267 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
268 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
269 // CHECK1-NEXT: ret void
270 //
271 //
272 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
273 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat {
274 // CHECK1-NEXT: entry:
275 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
276 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
277 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
278 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
279 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
280 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
281 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
282 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
283 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
284 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
285 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
286 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
287 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
288 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
289 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
290 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64*
291 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8
292 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
293 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
294 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8
295 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
296 // CHECK1-NEXT: store i8* null, i8** [[TMP7]], align 8
297 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
298 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
299 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
300 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
301 // CHECK1-NEXT: store i32 1, i32* [[TMP10]], align 4
302 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
303 // CHECK1-NEXT: store i32 1, i32* [[TMP11]], align 4
304 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
305 // CHECK1-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 8
306 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
307 // CHECK1-NEXT: store i8** [[TMP9]], i8*** [[TMP13]], align 8
308 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
309 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP14]], align 8
310 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
311 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP15]], align 8
312 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
313 // CHECK1-NEXT: store i8** null, i8*** [[TMP16]], align 8
314 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
315 // CHECK1-NEXT: store i8** null, i8*** [[TMP17]], align 8
316 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
317 // CHECK1-NEXT: store i64 2, i64* [[TMP18]], align 8
318 // CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
319 // CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
320 // CHECK1-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
321 // CHECK1: omp_offload.failed:
322 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP2]]) #[[ATTR2]]
323 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
324 // CHECK1: omp_offload.cont:
325 // CHECK1-NEXT: ret i32 0
326 //
327 //
328 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
329 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
330 // CHECK1-NEXT: entry:
331 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
332 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
333 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
334 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
335 // CHECK1-NEXT: ret void
336 //
337 //
338 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
339 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
340 // CHECK1-NEXT: entry:
341 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
342 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
343 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
344 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
345 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
346 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
347 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
348 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
349 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
350 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
351 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
352 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
353 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
354 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
355 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
356 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
357 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4
358 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
359 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
360 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
361 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
362 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
363 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
364 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
365 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
366 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
367 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
368 // CHECK1: cond.true:
369 // CHECK1-NEXT: br label [[COND_END:%.*]]
370 // CHECK1: cond.false:
371 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
372 // CHECK1-NEXT: br label [[COND_END]]
373 // CHECK1: cond.end:
374 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
375 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
376 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
377 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
378 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
379 // CHECK1: omp.inner.for.cond:
380 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
381 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
382 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
383 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
384 // CHECK1: omp.inner.for.body:
385 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
386 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
387 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
388 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
389 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
390 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11
391 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
392 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11
393 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
394 // CHECK1: omp.body.continue:
395 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
396 // CHECK1: omp.inner.for.inc:
397 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
398 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
399 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
400 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
401 // CHECK1: omp.inner.for.end:
402 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
403 // CHECK1: omp.loop.exit:
404 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
405 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
406 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
407 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
408 // CHECK1: .omp.final.then:
409 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
410 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
411 // CHECK1: .omp.final.done:
412 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
413 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8*
414 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8
415 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
416 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
417 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
418 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
419 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
420 // CHECK1-NEXT: ]
421 // CHECK1: .omp.reduction.case1:
422 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
423 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4
424 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
425 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
426 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
427 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
428 // CHECK1: .omp.reduction.case2:
429 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4
430 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
431 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
432 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
433 // CHECK1: .omp.reduction.default:
434 // CHECK1-NEXT: ret void
435 //
436 //
437 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
438 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
439 // CHECK1-NEXT: entry:
440 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
441 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
442 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
443 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
444 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
445 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
446 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
447 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
448 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
449 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
450 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
451 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
452 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
453 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
454 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
455 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
456 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
457 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
458 // CHECK1-NEXT: ret void
459 //
460 //
461 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
462 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] {
463 // CHECK1-NEXT: entry:
464 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
465 // CHECK1-NEXT: ret void
466 //
467 //
468 // CHECK3-LABEL: define {{[^@]+}}@main
469 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
470 // CHECK3-NEXT: entry:
471 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
472 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
473 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
474 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
475 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
476 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
477 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
478 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
479 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4
480 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
481 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
482 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
483 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
484 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
485 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
486 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
487 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
488 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4
489 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
490 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
491 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
492 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
493 // CHECK3-NEXT: store i32 1, i32* [[TMP9]], align 4
494 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
495 // CHECK3-NEXT: store i32 1, i32* [[TMP10]], align 4
496 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
497 // CHECK3-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 4
498 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
499 // CHECK3-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 4
500 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
501 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP13]], align 4
502 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
503 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP14]], align 4
504 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
505 // CHECK3-NEXT: store i8** null, i8*** [[TMP15]], align 4
506 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
507 // CHECK3-NEXT: store i8** null, i8*** [[TMP16]], align 4
508 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
509 // CHECK3-NEXT: store i64 2, i64* [[TMP17]], align 8
510 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
511 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
512 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
513 // CHECK3: omp_offload.failed:
514 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
515 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
516 // CHECK3: omp_offload.cont:
517 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
518 // CHECK3-NEXT: ret i32 [[CALL]]
519 //
520 //
521 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63
522 // CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
523 // CHECK3-NEXT: entry:
524 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
525 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
526 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[SIVAR_ADDR]])
527 // CHECK3-NEXT: ret void
528 //
529 //
530 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
531 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
532 // CHECK3-NEXT: entry:
533 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
534 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
535 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4
536 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
537 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
538 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
539 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
540 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
541 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
542 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
543 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
544 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
545 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
546 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
547 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4
548 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4
549 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4
550 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
551 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
552 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
553 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
554 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
555 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
556 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
557 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
558 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
559 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
560 // CHECK3: cond.true:
561 // CHECK3-NEXT: br label [[COND_END:%.*]]
562 // CHECK3: cond.false:
563 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
564 // CHECK3-NEXT: br label [[COND_END]]
565 // CHECK3: cond.end:
566 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
567 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
568 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
569 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
570 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
571 // CHECK3: omp.inner.for.cond:
572 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
573 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
574 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
575 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
576 // CHECK3: omp.inner.for.body:
577 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
578 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
579 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
580 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
581 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
582 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6
583 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
584 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6
585 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
586 // CHECK3: omp.body.continue:
587 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
588 // CHECK3: omp.inner.for.inc:
589 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
590 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
591 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
592 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
593 // CHECK3: omp.inner.for.end:
594 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
595 // CHECK3: omp.loop.exit:
596 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
597 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
598 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
599 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
600 // CHECK3: .omp.final.then:
601 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
602 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
603 // CHECK3: .omp.final.done:
604 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
605 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8*
606 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4
607 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
608 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
609 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
610 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
611 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
612 // CHECK3-NEXT: ]
613 // CHECK3: .omp.reduction.case1:
614 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
615 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4
616 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
617 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
618 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
619 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
620 // CHECK3: .omp.reduction.case2:
621 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4
622 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
623 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
624 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
625 // CHECK3: .omp.reduction.default:
626 // CHECK3-NEXT: ret void
627 //
628 //
629 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
630 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
631 // CHECK3-NEXT: entry:
632 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
633 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
634 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
635 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
636 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
637 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
638 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
639 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
640 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
641 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
642 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
643 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
644 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
645 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
646 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
647 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
648 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
649 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
650 // CHECK3-NEXT: ret void
651 //
652 //
653 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
654 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat {
655 // CHECK3-NEXT: entry:
656 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
657 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
658 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
659 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
660 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
661 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
662 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
663 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
664 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
665 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
666 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
667 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4
668 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
669 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
670 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
671 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4
672 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
673 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
674 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4
675 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
676 // CHECK3-NEXT: store i8* null, i8** [[TMP7]], align 4
677 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
678 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
679 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
680 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
681 // CHECK3-NEXT: store i32 1, i32* [[TMP10]], align 4
682 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
683 // CHECK3-NEXT: store i32 1, i32* [[TMP11]], align 4
684 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
685 // CHECK3-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 4
686 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
687 // CHECK3-NEXT: store i8** [[TMP9]], i8*** [[TMP13]], align 4
688 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
689 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP14]], align 4
690 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
691 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP15]], align 4
692 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
693 // CHECK3-NEXT: store i8** null, i8*** [[TMP16]], align 4
694 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
695 // CHECK3-NEXT: store i8** null, i8*** [[TMP17]], align 4
696 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
697 // CHECK3-NEXT: store i64 2, i64* [[TMP18]], align 8
698 // CHECK3-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
699 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
700 // CHECK3-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
701 // CHECK3: omp_offload.failed:
702 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP2]]) #[[ATTR2]]
703 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
704 // CHECK3: omp_offload.cont:
705 // CHECK3-NEXT: ret i32 0
706 //
707 //
708 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
709 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
710 // CHECK3-NEXT: entry:
711 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
712 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
713 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]])
714 // CHECK3-NEXT: ret void
715 //
716 //
717 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
718 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
719 // CHECK3-NEXT: entry:
720 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
721 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
722 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4
723 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
724 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
725 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
726 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
727 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
728 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
729 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
730 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
731 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4
732 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
733 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
734 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4
735 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4
736 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4
737 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
738 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
739 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
740 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
741 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
742 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
743 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
744 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
745 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
746 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
747 // CHECK3: cond.true:
748 // CHECK3-NEXT: br label [[COND_END:%.*]]
749 // CHECK3: cond.false:
750 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
751 // CHECK3-NEXT: br label [[COND_END]]
752 // CHECK3: cond.end:
753 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
754 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
755 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
756 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
757 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
758 // CHECK3: omp.inner.for.cond:
759 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
760 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
761 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
762 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
763 // CHECK3: omp.inner.for.body:
764 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
765 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
766 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
767 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
768 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
769 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12
770 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
771 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12
772 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
773 // CHECK3: omp.body.continue:
774 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
775 // CHECK3: omp.inner.for.inc:
776 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
777 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
778 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
779 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
780 // CHECK3: omp.inner.for.end:
781 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
782 // CHECK3: omp.loop.exit:
783 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
784 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
785 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
786 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
787 // CHECK3: .omp.final.then:
788 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
789 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
790 // CHECK3: .omp.final.done:
791 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
792 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8*
793 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4
794 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
795 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var)
796 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
797 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
798 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
799 // CHECK3-NEXT: ]
800 // CHECK3: .omp.reduction.case1:
801 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4
802 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4
803 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
804 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
805 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
806 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
807 // CHECK3: .omp.reduction.case2:
808 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4
809 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4
810 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
811 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
812 // CHECK3: .omp.reduction.default:
813 // CHECK3-NEXT: ret void
814 //
815 //
816 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
817 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] {
818 // CHECK3-NEXT: entry:
819 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
820 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4
821 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
822 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4
823 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4
824 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
825 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4
826 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
827 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0
828 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
829 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
830 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0
831 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4
832 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
833 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
834 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
835 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
836 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
837 // CHECK3-NEXT: ret void
838 //
839 //
840 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
841 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] {
842 // CHECK3-NEXT: entry:
843 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
844 // CHECK3-NEXT: ret void
845 //
846 //
847 // CHECK5-LABEL: define {{[^@]+}}@main
848 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
849 // CHECK5-NEXT: entry:
850 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
851 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
852 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
853 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
854 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
855 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
856 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
857 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
858 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
859 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
860 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
861 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
862 // CHECK5-NEXT: store i32 0, i32* [[SIVAR]], align 4
863 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
864 // CHECK5: omp.inner.for.cond:
865 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
866 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
867 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
868 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
869 // CHECK5: omp.inner.for.body:
870 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
871 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
872 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
873 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
874 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
875 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
876 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
877 // CHECK5-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2
878 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
879 // CHECK5: omp.body.continue:
880 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
881 // CHECK5: omp.inner.for.inc:
882 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
883 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
884 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
885 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
886 // CHECK5: omp.inner.for.end:
887 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
888 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
889 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4
890 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
891 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4
892 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
893 // CHECK5-NEXT: ret i32 [[CALL]]
894 //
895 //
896 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
897 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat {
898 // CHECK5-NEXT: entry:
899 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
900 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
901 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
902 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
903 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
904 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
905 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
906 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
907 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
908 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
909 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
910 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
911 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
912 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
913 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
914 // CHECK5-NEXT: store i32 0, i32* [[T_VAR1]], align 4
915 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
916 // CHECK5: omp.inner.for.cond:
917 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
918 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
919 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
920 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
921 // CHECK5: omp.inner.for.body:
922 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
923 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
924 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
925 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
926 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
927 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6
928 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
929 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6
930 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
931 // CHECK5: omp.body.continue:
932 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
933 // CHECK5: omp.inner.for.inc:
934 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
935 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1
936 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
937 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
938 // CHECK5: omp.inner.for.end:
939 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
940 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
941 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4
942 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
943 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4
944 // CHECK5-NEXT: ret i32 0
945 //
946 //
947 // CHECK7-LABEL: define {{[^@]+}}@main
948 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
949 // CHECK7-NEXT: entry:
950 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
951 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
952 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
953 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
954 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
955 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
956 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
957 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
958 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
959 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
960 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
961 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
962 // CHECK7-NEXT: store i32 0, i32* [[SIVAR]], align 4
963 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
964 // CHECK7: omp.inner.for.cond:
965 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
966 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
967 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
968 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
969 // CHECK7: omp.inner.for.body:
970 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
971 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
972 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
973 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
974 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
975 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
976 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
977 // CHECK7-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3
978 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
979 // CHECK7: omp.body.continue:
980 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
981 // CHECK7: omp.inner.for.inc:
982 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
983 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
984 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
985 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
986 // CHECK7: omp.inner.for.end:
987 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
988 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
989 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4
990 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
991 // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4
992 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
993 // CHECK7-NEXT: ret i32 [[CALL]]
994 //
995 //
996 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
997 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat {
998 // CHECK7-NEXT: entry:
999 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1000 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1001 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1002 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1003 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1004 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1005 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1006 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
1007 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
1008 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1009 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1010 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1011 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1012 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1013 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1014 // CHECK7-NEXT: store i32 0, i32* [[T_VAR1]], align 4
1015 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1016 // CHECK7: omp.inner.for.cond:
1017 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1018 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
1019 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1020 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1021 // CHECK7: omp.inner.for.body:
1022 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1023 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1024 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1025 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
1026 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
1027 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7
1028 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
1029 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7
1030 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1031 // CHECK7: omp.body.continue:
1032 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1033 // CHECK7: omp.inner.for.inc:
1034 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1035 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1
1036 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1037 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1038 // CHECK7: omp.inner.for.end:
1039 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
1040 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1041 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4
1042 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
1043 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4
1044 // CHECK7-NEXT: ret i32 0
1045 //
1046 //
1047 // CHECK9-LABEL: define {{[^@]+}}@main
1048 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1049 // CHECK9-NEXT: entry:
1050 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1051 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1052 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
1053 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1054 // CHECK9-NEXT: ret i32 0
1055 //
1056 //
1057 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45
1058 // CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
1059 // CHECK9-NEXT: entry:
1060 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1061 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1062 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1063 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
1064 // CHECK9-NEXT: ret void
1065 //
1066 //
1067 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
1068 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {
1069 // CHECK9-NEXT: entry:
1070 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1071 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1072 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
1073 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4
1074 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1075 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1076 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1077 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1078 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1079 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1080 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1081 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
1082 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8
1083 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1084 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1085 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
1086 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
1087 // CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4
1088 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1089 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1090 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1091 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1092 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1093 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1094 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1095 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1096 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
1097 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1098 // CHECK9: cond.true:
1099 // CHECK9-NEXT: br label [[COND_END:%.*]]
1100 // CHECK9: cond.false:
1101 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1102 // CHECK9-NEXT: br label [[COND_END]]
1103 // CHECK9: cond.end:
1104 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1105 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1106 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1107 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1108 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1109 // CHECK9: omp.inner.for.cond:
1110 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
1111 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
1112 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1113 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1114 // CHECK9: omp.inner.for.body:
1115 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
1116 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
1117 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1118 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
1119 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4
1120 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4
1121 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
1122 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4
1123 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
1124 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4
1125 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4
1126 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1127 // CHECK9: omp.body.continue:
1128 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1129 // CHECK9: omp.inner.for.inc:
1130 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
1131 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
1132 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
1133 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
1134 // CHECK9: omp.inner.for.end:
1135 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1136 // CHECK9: omp.loop.exit:
1137 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1138 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1139 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1140 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1141 // CHECK9: .omp.final.then:
1142 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
1143 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
1144 // CHECK9: .omp.final.done:
1145 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
1146 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR1]] to i8*
1147 // CHECK9-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8
1148 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
1149 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var)
1150 // CHECK9-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1151 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1152 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1153 // CHECK9-NEXT: ]
1154 // CHECK9: .omp.reduction.case1:
1155 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4
1156 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4
1157 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
1158 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4
1159 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1160 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1161 // CHECK9: .omp.reduction.case2:
1162 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4
1163 // CHECK9-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4
1164 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var)
1165 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
1166 // CHECK9: .omp.reduction.default:
1167 // CHECK9-NEXT: ret void
1168 //
1169 //
1170 // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
1171 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
1172 // CHECK9-NEXT: entry:
1173 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1174 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8
1175 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1176 // CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8
1177 // CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1178 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]*
1179 // CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8
1180 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]*
1181 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0
1182 // CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1183 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1184 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0
1185 // CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
1186 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32*
1187 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1188 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4
1189 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1190 // CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4
1191 // CHECK9-NEXT: ret void
1192 //
1193 //
1194 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1195 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] {
1196 // CHECK9-NEXT: entry:
1197 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
1198 // CHECK9-NEXT: ret void
1199 //
1200 //
1201 // CHECK11-LABEL: define {{[^@]+}}@main
1202 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
1203 // CHECK11-NEXT: entry:
1204 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1205 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1206 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
1207 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1208 // CHECK11-NEXT: ret i32 0
1209 //
1210