1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute simd private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute simd private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 [&]() { 85 g = 2; 86 g1 = 2; 87 sivar = 4; 88 89 }(); 90 } 91 }(); 92 return 0; 93 #else 94 #pragma omp target 95 #pragma omp teams distribute simd private(t_var, vec, s_arr, var, sivar) 96 for (int i = 0; i < 2; ++i) { 97 vec[i] = t_var; 98 s_arr[i] = var; 99 sivar += i; 100 } 101 return tmain<int>(); 102 #endif 103 } 104 105 106 107 // Skip global, bound tid and loop vars 108 109 // private(s_arr) 110 111 // private(var) 112 113 114 115 116 117 // Skip global, bound tid and loop vars 118 119 // private(s_arr) 120 121 122 // private(var) 123 124 125 #endif 126 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 127 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 128 // CHECK1-NEXT: entry: 129 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 130 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 131 // CHECK1-NEXT: ret void 132 // 133 // 134 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 135 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 136 // CHECK1-NEXT: entry: 137 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 138 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 139 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 140 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 141 // CHECK1-NEXT: ret void 142 // 143 // 144 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 145 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 146 // CHECK1-NEXT: entry: 147 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 148 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 149 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 150 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 151 // CHECK1-NEXT: ret void 152 // 153 // 154 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 155 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 156 // CHECK1-NEXT: entry: 157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 158 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 160 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 161 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 162 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 163 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 164 // CHECK1-NEXT: ret void 165 // 166 // 167 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 168 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 169 // CHECK1-NEXT: entry: 170 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 171 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 172 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 173 // CHECK1-NEXT: ret void 174 // 175 // 176 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 177 // CHECK1-SAME: () #[[ATTR0]] { 178 // CHECK1-NEXT: entry: 179 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 180 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 181 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 182 // CHECK1-NEXT: ret void 183 // 184 // 185 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 186 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 187 // CHECK1-NEXT: entry: 188 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 189 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 192 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 193 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 194 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 195 // CHECK1-NEXT: ret void 196 // 197 // 198 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 199 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 200 // CHECK1-NEXT: entry: 201 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 202 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 203 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 204 // CHECK1: arraydestroy.body: 205 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 206 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 207 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 208 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 209 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 210 // CHECK1: arraydestroy.done1: 211 // CHECK1-NEXT: ret void 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 215 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 218 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 219 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 220 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 221 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 222 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 223 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 224 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 225 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 226 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 227 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 228 // CHECK1-NEXT: ret void 229 // 230 // 231 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 232 // CHECK1-SAME: () #[[ATTR0]] { 233 // CHECK1-NEXT: entry: 234 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 235 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 236 // CHECK1-NEXT: ret void 237 // 238 // 239 // CHECK1-LABEL: define {{[^@]+}}@main 240 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 241 // CHECK1-NEXT: entry: 242 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 243 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 244 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 245 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 246 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 247 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 248 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 249 // CHECK1: omp_offload.failed: 250 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] 251 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 252 // CHECK1: omp_offload.cont: 253 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 254 // CHECK1-NEXT: ret i32 [[CALL]] 255 // 256 // 257 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 258 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 259 // CHECK1-NEXT: entry: 260 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 261 // CHECK1-NEXT: ret void 262 // 263 // 264 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 265 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 266 // CHECK1-NEXT: entry: 267 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 268 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 269 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 274 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 275 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 277 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 278 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 279 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 280 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 281 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 282 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 283 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 284 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 285 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 286 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 287 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 288 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 289 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 290 // CHECK1: arrayctor.loop: 291 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 292 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 293 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 294 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 295 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 296 // CHECK1: arrayctor.cont: 297 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 298 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 299 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 300 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 301 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 302 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 303 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 304 // CHECK1: cond.true: 305 // CHECK1-NEXT: br label [[COND_END:%.*]] 306 // CHECK1: cond.false: 307 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 308 // CHECK1-NEXT: br label [[COND_END]] 309 // CHECK1: cond.end: 310 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 311 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 312 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 313 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 314 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 315 // CHECK1: omp.inner.for.cond: 316 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 317 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 318 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 319 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 320 // CHECK1: omp.inner.for.cond.cleanup: 321 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 322 // CHECK1: omp.inner.for.body: 323 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 324 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 325 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 326 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 327 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5 328 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 329 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 330 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 331 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 332 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 333 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 334 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 335 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 336 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 337 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5 338 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 339 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5 340 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 341 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5 342 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 343 // CHECK1: omp.body.continue: 344 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 345 // CHECK1: omp.inner.for.inc: 346 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 347 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 348 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 349 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 350 // CHECK1: omp.inner.for.end: 351 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 352 // CHECK1: omp.loop.exit: 353 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 354 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 355 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 356 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 357 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 358 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 359 // CHECK1: .omp.final.then: 360 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 361 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 362 // CHECK1: .omp.final.done: 363 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 364 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 365 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 366 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 367 // CHECK1: arraydestroy.body: 368 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 369 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 370 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 371 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 372 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 373 // CHECK1: arraydestroy.done7: 374 // CHECK1-NEXT: ret void 375 // 376 // 377 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 378 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 379 // CHECK1-NEXT: entry: 380 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 381 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 382 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 384 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 385 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 386 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 387 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 388 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 389 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 390 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 391 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 392 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 393 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 394 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 395 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 396 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 397 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 398 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 399 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 400 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 401 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 402 // CHECK1: omp_offload.failed: 403 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 404 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 405 // CHECK1: omp_offload.cont: 406 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 407 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 409 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 410 // CHECK1: arraydestroy.body: 411 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 412 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 413 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 414 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 415 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 416 // CHECK1: arraydestroy.done2: 417 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 418 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 419 // CHECK1-NEXT: ret i32 [[TMP4]] 420 // 421 // 422 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 423 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 424 // CHECK1-NEXT: entry: 425 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 426 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 427 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 428 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 429 // CHECK1-NEXT: ret void 430 // 431 // 432 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 433 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 434 // CHECK1-NEXT: entry: 435 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 436 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 437 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 438 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 439 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 440 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 441 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 442 // CHECK1-NEXT: ret void 443 // 444 // 445 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 446 // CHECK1-SAME: () #[[ATTR4]] { 447 // CHECK1-NEXT: entry: 448 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 449 // CHECK1-NEXT: ret void 450 // 451 // 452 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 453 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 454 // CHECK1-NEXT: entry: 455 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 456 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 457 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 458 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 459 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 460 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 461 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 462 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 463 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 464 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 465 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 466 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 467 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 468 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 469 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 470 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 471 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 472 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 473 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 474 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 475 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 476 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 477 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 478 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 479 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 480 // CHECK1: arrayctor.loop: 481 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 482 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 483 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 484 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 485 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 486 // CHECK1: arrayctor.cont: 487 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 488 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 489 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 490 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 491 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 492 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 493 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 494 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 495 // CHECK1: cond.true: 496 // CHECK1-NEXT: br label [[COND_END:%.*]] 497 // CHECK1: cond.false: 498 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 499 // CHECK1-NEXT: br label [[COND_END]] 500 // CHECK1: cond.end: 501 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 502 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 503 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 504 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 505 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 506 // CHECK1: omp.inner.for.cond: 507 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 508 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 509 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 510 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 511 // CHECK1: omp.inner.for.cond.cleanup: 512 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 513 // CHECK1: omp.inner.for.body: 514 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 515 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 516 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 517 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 518 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 519 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 520 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 521 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 522 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 523 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11 524 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 525 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 526 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] 527 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 528 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 529 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11 530 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 531 // CHECK1: omp.body.continue: 532 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 533 // CHECK1: omp.inner.for.inc: 534 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 535 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 536 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 537 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 538 // CHECK1: omp.inner.for.end: 539 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 540 // CHECK1: omp.loop.exit: 541 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 542 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 543 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 544 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 545 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 546 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 547 // CHECK1: .omp.final.then: 548 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 549 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 550 // CHECK1: .omp.final.done: 551 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 552 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 553 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 554 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 555 // CHECK1: arraydestroy.body: 556 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 557 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 558 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 559 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 560 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 561 // CHECK1: arraydestroy.done8: 562 // CHECK1-NEXT: ret void 563 // 564 // 565 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 566 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 567 // CHECK1-NEXT: entry: 568 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 569 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 570 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 571 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 572 // CHECK1-NEXT: ret void 573 // 574 // 575 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 576 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 577 // CHECK1-NEXT: entry: 578 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 579 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 580 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 581 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 582 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 583 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 584 // CHECK1-NEXT: ret void 585 // 586 // 587 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 588 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 589 // CHECK1-NEXT: entry: 590 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 591 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 592 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 593 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 594 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 595 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 596 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 597 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 598 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 599 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 600 // CHECK1-NEXT: ret void 601 // 602 // 603 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 604 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 605 // CHECK1-NEXT: entry: 606 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 607 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 608 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 609 // CHECK1-NEXT: ret void 610 // 611 // 612 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 613 // CHECK1-SAME: () #[[ATTR0]] { 614 // CHECK1-NEXT: entry: 615 // CHECK1-NEXT: call void @__cxx_global_var_init() 616 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 617 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 618 // CHECK1-NEXT: ret void 619 // 620 // 621 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 622 // CHECK1-SAME: () #[[ATTR0]] { 623 // CHECK1-NEXT: entry: 624 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 625 // CHECK1-NEXT: ret void 626 // 627 // 628 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 629 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 630 // CHECK3-NEXT: entry: 631 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 632 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 633 // CHECK3-NEXT: ret void 634 // 635 // 636 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 637 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 638 // CHECK3-NEXT: entry: 639 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 640 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 641 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 642 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 643 // CHECK3-NEXT: ret void 644 // 645 // 646 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 647 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 648 // CHECK3-NEXT: entry: 649 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 650 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 651 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 652 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 653 // CHECK3-NEXT: ret void 654 // 655 // 656 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 657 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 658 // CHECK3-NEXT: entry: 659 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 660 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 661 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 662 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 663 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 664 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 665 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 666 // CHECK3-NEXT: ret void 667 // 668 // 669 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 670 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 671 // CHECK3-NEXT: entry: 672 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 673 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 674 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 675 // CHECK3-NEXT: ret void 676 // 677 // 678 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 679 // CHECK3-SAME: () #[[ATTR0]] { 680 // CHECK3-NEXT: entry: 681 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 682 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 683 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 684 // CHECK3-NEXT: ret void 685 // 686 // 687 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 688 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 689 // CHECK3-NEXT: entry: 690 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 691 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 692 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 693 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 694 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 695 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 696 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 697 // CHECK3-NEXT: ret void 698 // 699 // 700 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 701 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 702 // CHECK3-NEXT: entry: 703 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 704 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 705 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 706 // CHECK3: arraydestroy.body: 707 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 708 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 709 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 710 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 711 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 712 // CHECK3: arraydestroy.done1: 713 // CHECK3-NEXT: ret void 714 // 715 // 716 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 717 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 718 // CHECK3-NEXT: entry: 719 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 720 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 721 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 722 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 723 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 724 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 725 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 726 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 727 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 728 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 729 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 730 // CHECK3-NEXT: ret void 731 // 732 // 733 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 734 // CHECK3-SAME: () #[[ATTR0]] { 735 // CHECK3-NEXT: entry: 736 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 737 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 738 // CHECK3-NEXT: ret void 739 // 740 // 741 // CHECK3-LABEL: define {{[^@]+}}@main 742 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 743 // CHECK3-NEXT: entry: 744 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 745 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 746 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 747 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 748 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 749 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 750 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 751 // CHECK3: omp_offload.failed: 752 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] 753 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 754 // CHECK3: omp_offload.cont: 755 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 756 // CHECK3-NEXT: ret i32 [[CALL]] 757 // 758 // 759 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 760 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 761 // CHECK3-NEXT: entry: 762 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 763 // CHECK3-NEXT: ret void 764 // 765 // 766 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 767 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 768 // CHECK3-NEXT: entry: 769 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 770 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 771 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 772 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 773 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 774 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 775 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 776 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 777 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 778 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 779 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 780 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 781 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 782 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 783 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 784 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 785 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 786 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 787 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 788 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 789 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 790 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 791 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 792 // CHECK3: arrayctor.loop: 793 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 794 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 795 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 796 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 797 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 798 // CHECK3: arrayctor.cont: 799 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 800 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 801 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 802 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 803 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 804 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 805 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 806 // CHECK3: cond.true: 807 // CHECK3-NEXT: br label [[COND_END:%.*]] 808 // CHECK3: cond.false: 809 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 810 // CHECK3-NEXT: br label [[COND_END]] 811 // CHECK3: cond.end: 812 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 813 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 814 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 815 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 816 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 817 // CHECK3: omp.inner.for.cond: 818 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 819 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 820 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 821 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 822 // CHECK3: omp.inner.for.cond.cleanup: 823 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 824 // CHECK3: omp.inner.for.body: 825 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 826 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 827 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 828 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 829 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 830 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 831 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 832 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 833 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 834 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] 835 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 836 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 837 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6 838 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 839 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6 840 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 841 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6 842 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 843 // CHECK3: omp.body.continue: 844 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 845 // CHECK3: omp.inner.for.inc: 846 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 847 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 848 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 849 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 850 // CHECK3: omp.inner.for.end: 851 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 852 // CHECK3: omp.loop.exit: 853 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 854 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 855 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 856 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 857 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 858 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 859 // CHECK3: .omp.final.then: 860 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 861 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 862 // CHECK3: .omp.final.done: 863 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 864 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 865 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 866 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 867 // CHECK3: arraydestroy.body: 868 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 869 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 870 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 871 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 872 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 873 // CHECK3: arraydestroy.done6: 874 // CHECK3-NEXT: ret void 875 // 876 // 877 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 878 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 879 // CHECK3-NEXT: entry: 880 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 881 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 882 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 883 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 884 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 885 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 886 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 887 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 888 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 889 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 890 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 891 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 892 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 893 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 894 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 895 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 896 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 897 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 898 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 899 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 900 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 901 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 902 // CHECK3: omp_offload.failed: 903 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 904 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 905 // CHECK3: omp_offload.cont: 906 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 907 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 908 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 909 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 910 // CHECK3: arraydestroy.body: 911 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 912 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 913 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 914 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 915 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 916 // CHECK3: arraydestroy.done2: 917 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 918 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 919 // CHECK3-NEXT: ret i32 [[TMP4]] 920 // 921 // 922 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 923 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 924 // CHECK3-NEXT: entry: 925 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 926 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 927 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 928 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 929 // CHECK3-NEXT: ret void 930 // 931 // 932 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 933 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 934 // CHECK3-NEXT: entry: 935 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 936 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 937 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 938 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 939 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 940 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 941 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 942 // CHECK3-NEXT: ret void 943 // 944 // 945 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 946 // CHECK3-SAME: () #[[ATTR4]] { 947 // CHECK3-NEXT: entry: 948 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 949 // CHECK3-NEXT: ret void 950 // 951 // 952 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 953 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 954 // CHECK3-NEXT: entry: 955 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 956 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 957 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 958 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 959 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 960 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 961 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 962 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 963 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 964 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 965 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 966 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 967 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 968 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 969 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 970 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 971 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 972 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 973 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 974 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 975 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 976 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 977 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 978 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 979 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 980 // CHECK3: arrayctor.loop: 981 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 982 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 983 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 984 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 985 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 986 // CHECK3: arrayctor.cont: 987 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 988 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 989 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 990 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 991 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 992 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 993 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 994 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 995 // CHECK3: cond.true: 996 // CHECK3-NEXT: br label [[COND_END:%.*]] 997 // CHECK3: cond.false: 998 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 999 // CHECK3-NEXT: br label [[COND_END]] 1000 // CHECK3: cond.end: 1001 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1002 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1003 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1004 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1005 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1006 // CHECK3: omp.inner.for.cond: 1007 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1008 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1009 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1010 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1011 // CHECK3: omp.inner.for.cond.cleanup: 1012 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1013 // CHECK3: omp.inner.for.body: 1014 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1015 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1016 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1017 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1018 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12 1019 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1020 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1021 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 1022 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12 1023 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1024 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 1025 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1026 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1027 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12 1028 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1029 // CHECK3: omp.body.continue: 1030 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1031 // CHECK3: omp.inner.for.inc: 1032 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1033 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1034 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1035 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1036 // CHECK3: omp.inner.for.end: 1037 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1038 // CHECK3: omp.loop.exit: 1039 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1040 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1041 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1042 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1043 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 1044 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1045 // CHECK3: .omp.final.then: 1046 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1047 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1048 // CHECK3: .omp.final.done: 1049 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1050 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1051 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1052 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1053 // CHECK3: arraydestroy.body: 1054 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1055 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1056 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1057 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1058 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1059 // CHECK3: arraydestroy.done7: 1060 // CHECK3-NEXT: ret void 1061 // 1062 // 1063 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1064 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1065 // CHECK3-NEXT: entry: 1066 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1067 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1068 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1069 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1070 // CHECK3-NEXT: ret void 1071 // 1072 // 1073 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1074 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1075 // CHECK3-NEXT: entry: 1076 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1077 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1078 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1079 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1080 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1081 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1082 // CHECK3-NEXT: ret void 1083 // 1084 // 1085 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1086 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1087 // CHECK3-NEXT: entry: 1088 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1089 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1090 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1091 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1092 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1093 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1094 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1095 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1096 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1097 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1098 // CHECK3-NEXT: ret void 1099 // 1100 // 1101 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1102 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1103 // CHECK3-NEXT: entry: 1104 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1105 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1106 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1107 // CHECK3-NEXT: ret void 1108 // 1109 // 1110 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 1111 // CHECK3-SAME: () #[[ATTR0]] { 1112 // CHECK3-NEXT: entry: 1113 // CHECK3-NEXT: call void @__cxx_global_var_init() 1114 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1115 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1116 // CHECK3-NEXT: ret void 1117 // 1118 // 1119 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1120 // CHECK3-SAME: () #[[ATTR0]] { 1121 // CHECK3-NEXT: entry: 1122 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1123 // CHECK3-NEXT: ret void 1124 // 1125 // 1126 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1127 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1128 // CHECK5-NEXT: entry: 1129 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1130 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1131 // CHECK5-NEXT: ret void 1132 // 1133 // 1134 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1135 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1136 // CHECK5-NEXT: entry: 1137 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1138 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1139 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1140 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1141 // CHECK5-NEXT: ret void 1142 // 1143 // 1144 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1145 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1146 // CHECK5-NEXT: entry: 1147 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1148 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1149 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1150 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1151 // CHECK5-NEXT: ret void 1152 // 1153 // 1154 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1155 // CHECK5-SAME: () #[[ATTR0]] { 1156 // CHECK5-NEXT: entry: 1157 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1158 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1159 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1160 // CHECK5-NEXT: ret void 1161 // 1162 // 1163 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1164 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1165 // CHECK5-NEXT: entry: 1166 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1167 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1168 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1169 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1170 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1171 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1172 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1173 // CHECK5-NEXT: ret void 1174 // 1175 // 1176 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1177 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1178 // CHECK5-NEXT: entry: 1179 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1180 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1181 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1182 // CHECK5: arraydestroy.body: 1183 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1184 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1185 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1186 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1187 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1188 // CHECK5: arraydestroy.done1: 1189 // CHECK5-NEXT: ret void 1190 // 1191 // 1192 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1193 // CHECK5-SAME: () #[[ATTR0]] { 1194 // CHECK5-NEXT: entry: 1195 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1196 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1197 // CHECK5-NEXT: ret void 1198 // 1199 // 1200 // CHECK5-LABEL: define {{[^@]+}}@main 1201 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1202 // CHECK5-NEXT: entry: 1203 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1204 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1205 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1206 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1207 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1208 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1209 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1210 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1211 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1212 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1213 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1214 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1215 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1216 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1217 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1218 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1219 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1220 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1221 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1222 // CHECK5: arrayctor.loop: 1223 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1224 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1225 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 1226 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1227 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1228 // CHECK5: arrayctor.cont: 1229 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1230 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1231 // CHECK5: omp.inner.for.cond: 1232 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1233 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1234 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1235 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1236 // CHECK5: omp.inner.for.cond.cleanup: 1237 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1238 // CHECK5: omp.inner.for.body: 1239 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1240 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1241 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1242 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1243 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2 1244 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1245 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1246 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 1247 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2 1248 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1249 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1250 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 1251 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1252 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1253 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2 1254 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1255 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 1256 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1257 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2 1258 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1259 // CHECK5: omp.body.continue: 1260 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1261 // CHECK5: omp.inner.for.inc: 1262 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1263 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1264 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1265 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1266 // CHECK5: omp.inner.for.end: 1267 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1268 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1269 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1270 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 1271 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1272 // CHECK5: arraydestroy.body: 1273 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1274 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1275 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1276 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1277 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1278 // CHECK5: arraydestroy.done6: 1279 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1280 // CHECK5-NEXT: ret i32 [[CALL]] 1281 // 1282 // 1283 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1284 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 1285 // CHECK5-NEXT: entry: 1286 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1287 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1288 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1289 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1290 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1291 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1292 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1293 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 1294 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1295 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1296 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1297 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1298 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1299 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1300 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1301 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 1302 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 1303 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1304 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 1305 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1306 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1307 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1308 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 1309 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1310 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1311 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1312 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 1313 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1314 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1315 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1316 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1317 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1318 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1319 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1320 // CHECK5: arrayctor.loop: 1321 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1322 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1323 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 1324 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1325 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1326 // CHECK5: arrayctor.cont: 1327 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1328 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 1329 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1330 // CHECK5: omp.inner.for.cond: 1331 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1332 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1333 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1334 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1335 // CHECK5: omp.inner.for.cond.cleanup: 1336 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1337 // CHECK5: omp.inner.for.body: 1338 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1339 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1340 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1341 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1342 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6 1343 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1344 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 1345 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] 1346 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 1347 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6 1348 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1349 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64 1350 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]] 1351 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* 1352 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 1353 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6 1354 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1355 // CHECK5: omp.body.continue: 1356 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1357 // CHECK5: omp.inner.for.inc: 1358 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1359 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1 1360 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1361 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1362 // CHECK5: omp.inner.for.end: 1363 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1364 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1365 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1366 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 1367 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1368 // CHECK5: arraydestroy.body: 1369 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1370 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1371 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1372 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1373 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1374 // CHECK5: arraydestroy.done11: 1375 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1376 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1377 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 1378 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] 1379 // CHECK5: arraydestroy.body13: 1380 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] 1381 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 1382 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] 1383 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] 1384 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] 1385 // CHECK5: arraydestroy.done17: 1386 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1387 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 1388 // CHECK5-NEXT: ret i32 [[TMP14]] 1389 // 1390 // 1391 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1392 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1393 // CHECK5-NEXT: entry: 1394 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1395 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1396 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1397 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1398 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1399 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1400 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 1401 // CHECK5-NEXT: ret void 1402 // 1403 // 1404 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1405 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1406 // CHECK5-NEXT: entry: 1407 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1408 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1409 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1410 // CHECK5-NEXT: ret void 1411 // 1412 // 1413 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1414 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1415 // CHECK5-NEXT: entry: 1416 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1417 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1418 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1419 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1420 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1421 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1422 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1423 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1424 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1425 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1426 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 1427 // CHECK5-NEXT: ret void 1428 // 1429 // 1430 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1431 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1432 // CHECK5-NEXT: entry: 1433 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1434 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1435 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1436 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1437 // CHECK5-NEXT: ret void 1438 // 1439 // 1440 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1441 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1442 // CHECK5-NEXT: entry: 1443 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1444 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1445 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1446 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1447 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1448 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1449 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1450 // CHECK5-NEXT: ret void 1451 // 1452 // 1453 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1454 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1455 // CHECK5-NEXT: entry: 1456 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1457 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1458 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1459 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1460 // CHECK5-NEXT: ret void 1461 // 1462 // 1463 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1464 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1465 // CHECK5-NEXT: entry: 1466 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1467 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1468 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1469 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1470 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1471 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1472 // CHECK5-NEXT: ret void 1473 // 1474 // 1475 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1476 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1477 // CHECK5-NEXT: entry: 1478 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1479 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1480 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1481 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1482 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1483 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1484 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1485 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1486 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1487 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1488 // CHECK5-NEXT: ret void 1489 // 1490 // 1491 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1492 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1493 // CHECK5-NEXT: entry: 1494 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1495 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1496 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1497 // CHECK5-NEXT: ret void 1498 // 1499 // 1500 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 1501 // CHECK5-SAME: () #[[ATTR0]] { 1502 // CHECK5-NEXT: entry: 1503 // CHECK5-NEXT: call void @__cxx_global_var_init() 1504 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 1505 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 1506 // CHECK5-NEXT: ret void 1507 // 1508 // 1509 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 1510 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1511 // CHECK7-NEXT: entry: 1512 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1513 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1514 // CHECK7-NEXT: ret void 1515 // 1516 // 1517 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1518 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1519 // CHECK7-NEXT: entry: 1520 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1521 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1522 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1523 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1524 // CHECK7-NEXT: ret void 1525 // 1526 // 1527 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1528 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1529 // CHECK7-NEXT: entry: 1530 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1531 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1532 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1533 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1534 // CHECK7-NEXT: ret void 1535 // 1536 // 1537 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1538 // CHECK7-SAME: () #[[ATTR0]] { 1539 // CHECK7-NEXT: entry: 1540 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 1541 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 1542 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1543 // CHECK7-NEXT: ret void 1544 // 1545 // 1546 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1547 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1548 // CHECK7-NEXT: entry: 1549 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1550 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1551 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1552 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1553 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1554 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1555 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1556 // CHECK7-NEXT: ret void 1557 // 1558 // 1559 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1560 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1561 // CHECK7-NEXT: entry: 1562 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1563 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1564 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1565 // CHECK7: arraydestroy.body: 1566 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1567 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1568 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1569 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1570 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1571 // CHECK7: arraydestroy.done1: 1572 // CHECK7-NEXT: ret void 1573 // 1574 // 1575 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1576 // CHECK7-SAME: () #[[ATTR0]] { 1577 // CHECK7-NEXT: entry: 1578 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1579 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1580 // CHECK7-NEXT: ret void 1581 // 1582 // 1583 // CHECK7-LABEL: define {{[^@]+}}@main 1584 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 1585 // CHECK7-NEXT: entry: 1586 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1587 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1588 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1589 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1590 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1591 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1592 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1593 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1594 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1595 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1596 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1597 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 1598 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1599 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1600 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1601 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1602 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1603 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1604 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1605 // CHECK7: arrayctor.loop: 1606 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1607 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1608 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1609 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1610 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1611 // CHECK7: arrayctor.cont: 1612 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1613 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1614 // CHECK7: omp.inner.for.cond: 1615 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1616 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 1617 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1618 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1619 // CHECK7: omp.inner.for.cond.cleanup: 1620 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1621 // CHECK7: omp.inner.for.body: 1622 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1623 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1624 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1625 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 1626 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3 1627 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1628 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]] 1629 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3 1630 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1631 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]] 1632 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 1633 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1634 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3 1635 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1636 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 1637 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1638 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3 1639 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1640 // CHECK7: omp.body.continue: 1641 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1642 // CHECK7: omp.inner.for.inc: 1643 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1644 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 1645 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1646 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1647 // CHECK7: omp.inner.for.end: 1648 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1649 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1650 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1651 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 1652 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1653 // CHECK7: arraydestroy.body: 1654 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1655 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1656 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1657 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1658 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1659 // CHECK7: arraydestroy.done5: 1660 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1661 // CHECK7-NEXT: ret i32 [[CALL]] 1662 // 1663 // 1664 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1665 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 1666 // CHECK7-NEXT: entry: 1667 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1668 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1669 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1670 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1671 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1672 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1673 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1674 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1675 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1676 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1677 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1678 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1679 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1680 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1681 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1682 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 1683 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 1684 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1685 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 1686 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1687 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1688 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1689 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 1690 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1691 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1692 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1693 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1694 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1695 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1696 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1697 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1698 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1699 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1700 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1701 // CHECK7: arrayctor.loop: 1702 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1703 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1704 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1705 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1706 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1707 // CHECK7: arrayctor.cont: 1708 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1709 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 1710 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1711 // CHECK7: omp.inner.for.cond: 1712 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1713 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1714 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1715 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1716 // CHECK7: omp.inner.for.cond.cleanup: 1717 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1718 // CHECK7: omp.inner.for.body: 1719 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1720 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1721 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1722 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1723 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7 1724 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1725 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]] 1726 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 1727 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7 1728 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1729 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]] 1730 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1731 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 1732 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7 1733 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1734 // CHECK7: omp.body.continue: 1735 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1736 // CHECK7: omp.inner.for.inc: 1737 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1738 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1 1739 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1740 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1741 // CHECK7: omp.inner.for.end: 1742 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1743 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1744 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1745 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 1746 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1747 // CHECK7: arraydestroy.body: 1748 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1749 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1750 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1751 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 1752 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 1753 // CHECK7: arraydestroy.done10: 1754 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 1755 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1756 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 1757 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] 1758 // CHECK7: arraydestroy.body12: 1759 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] 1760 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 1761 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] 1762 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] 1763 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] 1764 // CHECK7: arraydestroy.done16: 1765 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1766 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 1767 // CHECK7-NEXT: ret i32 [[TMP14]] 1768 // 1769 // 1770 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1771 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1772 // CHECK7-NEXT: entry: 1773 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1774 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1775 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1776 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1777 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1778 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1779 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 1780 // CHECK7-NEXT: ret void 1781 // 1782 // 1783 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1784 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1785 // CHECK7-NEXT: entry: 1786 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1787 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1788 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1789 // CHECK7-NEXT: ret void 1790 // 1791 // 1792 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1793 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1794 // CHECK7-NEXT: entry: 1795 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1796 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1797 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1798 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1799 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1800 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1801 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1802 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1803 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1804 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1805 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 1806 // CHECK7-NEXT: ret void 1807 // 1808 // 1809 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1810 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1811 // CHECK7-NEXT: entry: 1812 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1813 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1814 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1815 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1816 // CHECK7-NEXT: ret void 1817 // 1818 // 1819 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1820 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1821 // CHECK7-NEXT: entry: 1822 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1823 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1824 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1825 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1826 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1827 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1828 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1829 // CHECK7-NEXT: ret void 1830 // 1831 // 1832 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1833 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1834 // CHECK7-NEXT: entry: 1835 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1836 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1837 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1838 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1839 // CHECK7-NEXT: ret void 1840 // 1841 // 1842 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1843 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1844 // CHECK7-NEXT: entry: 1845 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1846 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1847 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1848 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1849 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1850 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1851 // CHECK7-NEXT: ret void 1852 // 1853 // 1854 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1855 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1856 // CHECK7-NEXT: entry: 1857 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1858 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1859 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1860 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1861 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1862 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1863 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1864 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1865 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1866 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1867 // CHECK7-NEXT: ret void 1868 // 1869 // 1870 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1871 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1872 // CHECK7-NEXT: entry: 1873 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1874 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1875 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1876 // CHECK7-NEXT: ret void 1877 // 1878 // 1879 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 1880 // CHECK7-SAME: () #[[ATTR0]] { 1881 // CHECK7-NEXT: entry: 1882 // CHECK7-NEXT: call void @__cxx_global_var_init() 1883 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 1884 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 1885 // CHECK7-NEXT: ret void 1886 // 1887 // 1888 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1889 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1890 // CHECK9-NEXT: entry: 1891 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1892 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1893 // CHECK9-NEXT: ret void 1894 // 1895 // 1896 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1897 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1898 // CHECK9-NEXT: entry: 1899 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1900 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1901 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1902 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1903 // CHECK9-NEXT: ret void 1904 // 1905 // 1906 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1907 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1908 // CHECK9-NEXT: entry: 1909 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1910 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1911 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1912 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1913 // CHECK9-NEXT: ret void 1914 // 1915 // 1916 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1917 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1918 // CHECK9-NEXT: entry: 1919 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1920 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1921 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1922 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1923 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1924 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1925 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 1926 // CHECK9-NEXT: ret void 1927 // 1928 // 1929 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1930 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1931 // CHECK9-NEXT: entry: 1932 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1933 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1934 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1935 // CHECK9-NEXT: ret void 1936 // 1937 // 1938 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1939 // CHECK9-SAME: () #[[ATTR0]] { 1940 // CHECK9-NEXT: entry: 1941 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1942 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1943 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1944 // CHECK9-NEXT: ret void 1945 // 1946 // 1947 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1948 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1949 // CHECK9-NEXT: entry: 1950 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1951 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1952 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1953 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1954 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1955 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1956 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1957 // CHECK9-NEXT: ret void 1958 // 1959 // 1960 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1961 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1962 // CHECK9-NEXT: entry: 1963 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1964 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1965 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1966 // CHECK9: arraydestroy.body: 1967 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1968 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1969 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1970 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1971 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1972 // CHECK9: arraydestroy.done1: 1973 // CHECK9-NEXT: ret void 1974 // 1975 // 1976 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1977 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1978 // CHECK9-NEXT: entry: 1979 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1980 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1981 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1982 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1983 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1984 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1985 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1986 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1987 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1988 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1989 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 1990 // CHECK9-NEXT: ret void 1991 // 1992 // 1993 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1994 // CHECK9-SAME: () #[[ATTR0]] { 1995 // CHECK9-NEXT: entry: 1996 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1997 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1998 // CHECK9-NEXT: ret void 1999 // 2000 // 2001 // CHECK9-LABEL: define {{[^@]+}}@main 2002 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2003 // CHECK9-NEXT: entry: 2004 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2005 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2006 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 2007 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2008 // CHECK9-NEXT: ret i32 0 2009 // 2010 // 2011 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 2012 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 2013 // CHECK9-NEXT: entry: 2014 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2015 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2016 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 2017 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 2018 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 2019 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2020 // CHECK9-NEXT: ret void 2021 // 2022 // 2023 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2024 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 2025 // CHECK9-NEXT: entry: 2026 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2027 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2028 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2029 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2030 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 2031 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2032 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2033 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2034 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2035 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 2036 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 2037 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 2038 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2039 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2040 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2041 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2042 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2043 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 2044 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2045 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2046 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2047 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2048 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 2049 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2050 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2051 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2052 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2053 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2054 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2055 // CHECK9: cond.true: 2056 // CHECK9-NEXT: br label [[COND_END:%.*]] 2057 // CHECK9: cond.false: 2058 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2059 // CHECK9-NEXT: br label [[COND_END]] 2060 // CHECK9: cond.end: 2061 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2062 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2063 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2064 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2065 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2066 // CHECK9: omp.inner.for.cond: 2067 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2068 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 2069 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2070 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2071 // CHECK9: omp.inner.for.body: 2072 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2073 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2074 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2075 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 2076 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4 2077 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 2078 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 2079 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4 2080 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2081 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4 2082 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 2083 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 2084 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 2085 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 2086 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 2087 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 2088 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2089 // CHECK9: omp.body.continue: 2090 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2091 // CHECK9: omp.inner.for.inc: 2092 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2093 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 2094 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2095 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2096 // CHECK9: omp.inner.for.end: 2097 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2098 // CHECK9: omp.loop.exit: 2099 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2100 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2101 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2102 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2103 // CHECK9: .omp.final.then: 2104 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 2105 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2106 // CHECK9: .omp.final.done: 2107 // CHECK9-NEXT: ret void 2108 // 2109 // 2110 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 2111 // CHECK9-SAME: () #[[ATTR0]] { 2112 // CHECK9-NEXT: entry: 2113 // CHECK9-NEXT: call void @__cxx_global_var_init() 2114 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2115 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2116 // CHECK9-NEXT: ret void 2117 // 2118 // 2119 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2120 // CHECK9-SAME: () #[[ATTR0]] { 2121 // CHECK9-NEXT: entry: 2122 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2123 // CHECK9-NEXT: ret void 2124 // 2125 // 2126 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2127 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2128 // CHECK11-NEXT: entry: 2129 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2130 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2131 // CHECK11-NEXT: ret void 2132 // 2133 // 2134 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2135 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2136 // CHECK11-NEXT: entry: 2137 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2138 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2139 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2140 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2141 // CHECK11-NEXT: ret void 2142 // 2143 // 2144 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2145 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2146 // CHECK11-NEXT: entry: 2147 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2148 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2149 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2150 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2151 // CHECK11-NEXT: ret void 2152 // 2153 // 2154 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2155 // CHECK11-SAME: () #[[ATTR0]] { 2156 // CHECK11-NEXT: entry: 2157 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2158 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2159 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2160 // CHECK11-NEXT: ret void 2161 // 2162 // 2163 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2164 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2165 // CHECK11-NEXT: entry: 2166 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2167 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2168 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2169 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2170 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2171 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2172 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2173 // CHECK11-NEXT: ret void 2174 // 2175 // 2176 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2177 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2178 // CHECK11-NEXT: entry: 2179 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2180 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2181 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2182 // CHECK11: arraydestroy.body: 2183 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2184 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2185 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2186 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2187 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2188 // CHECK11: arraydestroy.done1: 2189 // CHECK11-NEXT: ret void 2190 // 2191 // 2192 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2193 // CHECK11-SAME: () #[[ATTR0]] { 2194 // CHECK11-NEXT: entry: 2195 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2196 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2197 // CHECK11-NEXT: ret void 2198 // 2199 // 2200 // CHECK11-LABEL: define {{[^@]+}}@main 2201 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2202 // CHECK11-NEXT: entry: 2203 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2204 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2205 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2206 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2207 // CHECK11-NEXT: ret i32 0 2208 // 2209 // 2210 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2211 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2212 // CHECK11-NEXT: entry: 2213 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2214 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2215 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2216 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2217 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2218 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2219 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 2220 // CHECK11-NEXT: ret void 2221 // 2222 // 2223 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2224 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2225 // CHECK11-NEXT: entry: 2226 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2227 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2228 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2229 // CHECK11-NEXT: ret void 2230 // 2231 // 2232 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2233 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2234 // CHECK11-NEXT: entry: 2235 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2236 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2237 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2238 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2239 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2240 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2241 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2242 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2243 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2244 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2245 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2246 // CHECK11-NEXT: ret void 2247 // 2248 // 2249 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 2250 // CHECK11-SAME: () #[[ATTR0]] { 2251 // CHECK11-NEXT: entry: 2252 // CHECK11-NEXT: call void @__cxx_global_var_init() 2253 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2254 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2255 // CHECK11-NEXT: ret void 2256 // 2257