1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
15
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute simd private(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute simd private(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global, bound tid and loop vars
80
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84 [&]() {
85 g = 2;
86 g1 = 2;
87 sivar = 4;
88
89 }();
90 }
91 }();
92 return 0;
93 #else
94 #pragma omp target
95 #pragma omp teams distribute simd private(t_var, vec, s_arr, var, sivar)
96 for (int i = 0; i < 2; ++i) {
97 vec[i] = t_var;
98 s_arr[i] = var;
99 sivar += i;
100 }
101 return tmain<int>();
102 #endif
103 }
104
105
106
107 // Skip global, bound tid and loop vars
108
109 // private(s_arr)
110
111 // private(var)
112
113
114
115
116
117 // Skip global, bound tid and loop vars
118
119 // private(s_arr)
120
121
122 // private(var)
123
124
125 #endif
126 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
127 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
128 // CHECK1-NEXT: entry:
129 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
130 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
131 // CHECK1-NEXT: ret void
132 //
133 //
134 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
135 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
136 // CHECK1-NEXT: entry:
137 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
138 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
139 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
140 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
141 // CHECK1-NEXT: ret void
142 //
143 //
144 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
145 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
146 // CHECK1-NEXT: entry:
147 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
148 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
149 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
150 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
151 // CHECK1-NEXT: ret void
152 //
153 //
154 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
155 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
156 // CHECK1-NEXT: entry:
157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
158 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
159 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
160 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
161 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
162 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
163 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
164 // CHECK1-NEXT: ret void
165 //
166 //
167 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
168 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
169 // CHECK1-NEXT: entry:
170 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
171 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
172 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
173 // CHECK1-NEXT: ret void
174 //
175 //
176 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
177 // CHECK1-SAME: () #[[ATTR0]] {
178 // CHECK1-NEXT: entry:
179 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
180 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
181 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
182 // CHECK1-NEXT: ret void
183 //
184 //
185 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
186 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
187 // CHECK1-NEXT: entry:
188 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
189 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
191 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
192 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
193 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
194 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
195 // CHECK1-NEXT: ret void
196 //
197 //
198 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
199 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
200 // CHECK1-NEXT: entry:
201 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
202 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
203 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
204 // CHECK1: arraydestroy.body:
205 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
206 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
207 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
208 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
209 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
210 // CHECK1: arraydestroy.done1:
211 // CHECK1-NEXT: ret void
212 //
213 //
214 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
215 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
216 // CHECK1-NEXT: entry:
217 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
218 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
219 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
220 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
221 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
222 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
223 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
224 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
225 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
226 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
227 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
228 // CHECK1-NEXT: ret void
229 //
230 //
231 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
232 // CHECK1-SAME: () #[[ATTR0]] {
233 // CHECK1-NEXT: entry:
234 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
235 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
236 // CHECK1-NEXT: ret void
237 //
238 //
239 // CHECK1-LABEL: define {{[^@]+}}@main
240 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
241 // CHECK1-NEXT: entry:
242 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
243 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
244 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
245 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
246 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
247 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
248 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
249 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
250 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
251 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
252 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
253 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
254 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
255 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
256 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
257 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
258 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
259 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
260 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
261 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
262 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
263 // CHECK1-NEXT: store i64 2, i64* [[TMP8]], align 8
264 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
265 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
266 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
267 // CHECK1: omp_offload.failed:
268 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
269 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
270 // CHECK1: omp_offload.cont:
271 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
272 // CHECK1-NEXT: ret i32 [[CALL]]
273 //
274 //
275 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
276 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
277 // CHECK1-NEXT: entry:
278 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
279 // CHECK1-NEXT: ret void
280 //
281 //
282 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
283 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
284 // CHECK1-NEXT: entry:
285 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
286 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
287 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
288 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
289 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
290 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
291 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
292 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
293 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
294 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
295 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
296 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
297 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
298 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
299 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
300 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
301 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
302 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
303 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
304 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
305 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
306 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
307 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
308 // CHECK1: arrayctor.loop:
309 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
310 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
311 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
312 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
313 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
314 // CHECK1: arrayctor.cont:
315 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
316 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
317 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
318 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
319 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
320 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
321 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
322 // CHECK1: cond.true:
323 // CHECK1-NEXT: br label [[COND_END:%.*]]
324 // CHECK1: cond.false:
325 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
326 // CHECK1-NEXT: br label [[COND_END]]
327 // CHECK1: cond.end:
328 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
329 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
330 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
331 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
332 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
333 // CHECK1: omp.inner.for.cond:
334 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
335 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
336 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
337 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
338 // CHECK1: omp.inner.for.cond.cleanup:
339 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
340 // CHECK1: omp.inner.for.body:
341 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
342 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
343 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
344 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
345 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5
346 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
347 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
348 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
349 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
350 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
351 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
352 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
353 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8*
354 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
355 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5
356 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
357 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5
358 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
359 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5
360 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
361 // CHECK1: omp.body.continue:
362 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
363 // CHECK1: omp.inner.for.inc:
364 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
365 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
366 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
367 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
368 // CHECK1: omp.inner.for.end:
369 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
370 // CHECK1: omp.loop.exit:
371 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
372 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
373 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
374 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
375 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
376 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
377 // CHECK1: .omp.final.then:
378 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
379 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
380 // CHECK1: .omp.final.done:
381 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
382 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
383 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2
384 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
385 // CHECK1: arraydestroy.body:
386 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
387 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
388 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
389 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
390 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
391 // CHECK1: arraydestroy.done7:
392 // CHECK1-NEXT: ret void
393 //
394 //
395 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
396 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
397 // CHECK1-NEXT: entry:
398 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
399 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
400 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
401 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
402 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
403 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
404 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
405 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
406 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
407 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
408 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
409 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
410 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
411 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
412 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
413 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
414 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
415 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
416 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
417 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
418 // CHECK1-NEXT: store i32 1, i32* [[TMP1]], align 4
419 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
420 // CHECK1-NEXT: store i32 0, i32* [[TMP2]], align 4
421 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
422 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
423 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
424 // CHECK1-NEXT: store i8** null, i8*** [[TMP4]], align 8
425 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
426 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
427 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
428 // CHECK1-NEXT: store i64* null, i64** [[TMP6]], align 8
429 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
430 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
431 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
432 // CHECK1-NEXT: store i8** null, i8*** [[TMP8]], align 8
433 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
434 // CHECK1-NEXT: store i64 2, i64* [[TMP9]], align 8
435 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
436 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
437 // CHECK1-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
438 // CHECK1: omp_offload.failed:
439 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
440 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
441 // CHECK1: omp_offload.cont:
442 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
443 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
444 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
445 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
446 // CHECK1: arraydestroy.body:
447 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
448 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
449 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
450 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
451 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
452 // CHECK1: arraydestroy.done2:
453 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
454 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
455 // CHECK1-NEXT: ret i32 [[TMP13]]
456 //
457 //
458 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
459 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
460 // CHECK1-NEXT: entry:
461 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
462 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
463 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
464 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
465 // CHECK1-NEXT: ret void
466 //
467 //
468 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
469 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
470 // CHECK1-NEXT: entry:
471 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
472 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
473 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
474 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
475 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
476 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
477 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
478 // CHECK1-NEXT: ret void
479 //
480 //
481 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
482 // CHECK1-SAME: () #[[ATTR4]] {
483 // CHECK1-NEXT: entry:
484 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
485 // CHECK1-NEXT: ret void
486 //
487 //
488 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
489 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
490 // CHECK1-NEXT: entry:
491 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
492 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
493 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
494 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
495 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
496 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
497 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
498 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
499 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
500 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
501 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
502 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
503 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
504 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
505 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
506 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
507 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
508 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
509 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
510 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
511 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
512 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
513 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
514 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
515 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
516 // CHECK1: arrayctor.loop:
517 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
518 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
519 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
520 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
521 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
522 // CHECK1: arrayctor.cont:
523 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
524 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
525 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
526 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
527 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
528 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
529 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
530 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
531 // CHECK1: cond.true:
532 // CHECK1-NEXT: br label [[COND_END:%.*]]
533 // CHECK1: cond.false:
534 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
535 // CHECK1-NEXT: br label [[COND_END]]
536 // CHECK1: cond.end:
537 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
538 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
539 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
540 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
541 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
542 // CHECK1: omp.inner.for.cond:
543 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
544 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
545 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
546 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
547 // CHECK1: omp.inner.for.cond.cleanup:
548 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
549 // CHECK1: omp.inner.for.body:
550 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
551 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
552 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
553 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
554 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11
555 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
556 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
557 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
558 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
559 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11
560 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
561 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
562 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
563 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8*
564 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
565 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11
566 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
567 // CHECK1: omp.body.continue:
568 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
569 // CHECK1: omp.inner.for.inc:
570 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
571 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
572 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
573 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
574 // CHECK1: omp.inner.for.end:
575 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
576 // CHECK1: omp.loop.exit:
577 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
578 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
579 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
580 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
581 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
582 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
583 // CHECK1: .omp.final.then:
584 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
585 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
586 // CHECK1: .omp.final.done:
587 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
588 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
589 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2
590 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
591 // CHECK1: arraydestroy.body:
592 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
593 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
594 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
595 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
596 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
597 // CHECK1: arraydestroy.done8:
598 // CHECK1-NEXT: ret void
599 //
600 //
601 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
602 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
603 // CHECK1-NEXT: entry:
604 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
605 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
606 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
607 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
608 // CHECK1-NEXT: ret void
609 //
610 //
611 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
612 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
613 // CHECK1-NEXT: entry:
614 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
615 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
616 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
617 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
618 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
619 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
620 // CHECK1-NEXT: ret void
621 //
622 //
623 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
624 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
625 // CHECK1-NEXT: entry:
626 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
627 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
628 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
629 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
630 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
631 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
632 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
633 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
634 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
635 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
636 // CHECK1-NEXT: ret void
637 //
638 //
639 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
640 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
641 // CHECK1-NEXT: entry:
642 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
643 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
644 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
645 // CHECK1-NEXT: ret void
646 //
647 //
648 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
649 // CHECK1-SAME: () #[[ATTR0]] {
650 // CHECK1-NEXT: entry:
651 // CHECK1-NEXT: call void @__cxx_global_var_init()
652 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
653 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
654 // CHECK1-NEXT: ret void
655 //
656 //
657 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
658 // CHECK1-SAME: () #[[ATTR0]] {
659 // CHECK1-NEXT: entry:
660 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
661 // CHECK1-NEXT: ret void
662 //
663 //
664 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
665 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
666 // CHECK3-NEXT: entry:
667 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
668 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
669 // CHECK3-NEXT: ret void
670 //
671 //
672 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
673 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
674 // CHECK3-NEXT: entry:
675 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
676 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
677 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
678 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
679 // CHECK3-NEXT: ret void
680 //
681 //
682 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
683 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
684 // CHECK3-NEXT: entry:
685 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
686 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
687 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
688 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
689 // CHECK3-NEXT: ret void
690 //
691 //
692 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
693 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
694 // CHECK3-NEXT: entry:
695 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
696 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
697 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
698 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
699 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
700 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
701 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
702 // CHECK3-NEXT: ret void
703 //
704 //
705 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
706 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
707 // CHECK3-NEXT: entry:
708 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
709 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
710 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
711 // CHECK3-NEXT: ret void
712 //
713 //
714 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
715 // CHECK3-SAME: () #[[ATTR0]] {
716 // CHECK3-NEXT: entry:
717 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
718 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
719 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
720 // CHECK3-NEXT: ret void
721 //
722 //
723 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
724 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
725 // CHECK3-NEXT: entry:
726 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
727 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
728 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
729 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
730 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
731 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
732 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
733 // CHECK3-NEXT: ret void
734 //
735 //
736 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
737 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
738 // CHECK3-NEXT: entry:
739 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
740 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
741 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
742 // CHECK3: arraydestroy.body:
743 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
744 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
745 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
746 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
747 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
748 // CHECK3: arraydestroy.done1:
749 // CHECK3-NEXT: ret void
750 //
751 //
752 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
753 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
754 // CHECK3-NEXT: entry:
755 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
756 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
757 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
758 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
759 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
760 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
761 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
762 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
763 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
764 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
765 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
766 // CHECK3-NEXT: ret void
767 //
768 //
769 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
770 // CHECK3-SAME: () #[[ATTR0]] {
771 // CHECK3-NEXT: entry:
772 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
773 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
774 // CHECK3-NEXT: ret void
775 //
776 //
777 // CHECK3-LABEL: define {{[^@]+}}@main
778 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
779 // CHECK3-NEXT: entry:
780 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
781 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
782 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
783 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
784 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
785 // CHECK3-NEXT: store i32 1, i32* [[TMP0]], align 4
786 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
787 // CHECK3-NEXT: store i32 0, i32* [[TMP1]], align 4
788 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
789 // CHECK3-NEXT: store i8** null, i8*** [[TMP2]], align 4
790 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
791 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
792 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
793 // CHECK3-NEXT: store i64* null, i64** [[TMP4]], align 4
794 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
795 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
796 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
797 // CHECK3-NEXT: store i8** null, i8*** [[TMP6]], align 4
798 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
799 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
800 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
801 // CHECK3-NEXT: store i64 2, i64* [[TMP8]], align 8
802 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
803 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
804 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
805 // CHECK3: omp_offload.failed:
806 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
807 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
808 // CHECK3: omp_offload.cont:
809 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
810 // CHECK3-NEXT: ret i32 [[CALL]]
811 //
812 //
813 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
814 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
815 // CHECK3-NEXT: entry:
816 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
817 // CHECK3-NEXT: ret void
818 //
819 //
820 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
821 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
822 // CHECK3-NEXT: entry:
823 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
824 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
825 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
826 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
827 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
828 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
829 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
830 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
831 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
832 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
833 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
834 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
835 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
836 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
837 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
838 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
839 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
840 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
841 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
842 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
843 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
844 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
845 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
846 // CHECK3: arrayctor.loop:
847 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
848 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
849 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
850 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
851 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
852 // CHECK3: arrayctor.cont:
853 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
854 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
855 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
856 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
857 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
858 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
859 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
860 // CHECK3: cond.true:
861 // CHECK3-NEXT: br label [[COND_END:%.*]]
862 // CHECK3: cond.false:
863 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
864 // CHECK3-NEXT: br label [[COND_END]]
865 // CHECK3: cond.end:
866 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
867 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
868 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
869 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
870 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
871 // CHECK3: omp.inner.for.cond:
872 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
873 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
874 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
875 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
876 // CHECK3: omp.inner.for.cond.cleanup:
877 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
878 // CHECK3: omp.inner.for.body:
879 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
880 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
881 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
882 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
883 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
884 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
885 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
886 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
887 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
888 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]]
889 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
890 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
891 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6
892 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
893 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6
894 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
895 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6
896 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
897 // CHECK3: omp.body.continue:
898 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
899 // CHECK3: omp.inner.for.inc:
900 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
901 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
902 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
903 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
904 // CHECK3: omp.inner.for.end:
905 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
906 // CHECK3: omp.loop.exit:
907 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
908 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
909 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
910 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
911 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
912 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
913 // CHECK3: .omp.final.then:
914 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
915 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
916 // CHECK3: .omp.final.done:
917 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
918 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
919 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
920 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
921 // CHECK3: arraydestroy.body:
922 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
923 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
924 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
925 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
926 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
927 // CHECK3: arraydestroy.done6:
928 // CHECK3-NEXT: ret void
929 //
930 //
931 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
932 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
933 // CHECK3-NEXT: entry:
934 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
935 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
936 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
937 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
938 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
939 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
940 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
941 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
942 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
943 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
944 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
945 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
946 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
947 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
948 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
949 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
950 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
951 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
952 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
953 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
954 // CHECK3-NEXT: store i32 1, i32* [[TMP1]], align 4
955 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
956 // CHECK3-NEXT: store i32 0, i32* [[TMP2]], align 4
957 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
958 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
959 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
960 // CHECK3-NEXT: store i8** null, i8*** [[TMP4]], align 4
961 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
962 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
963 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
964 // CHECK3-NEXT: store i64* null, i64** [[TMP6]], align 4
965 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
966 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
967 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
968 // CHECK3-NEXT: store i8** null, i8*** [[TMP8]], align 4
969 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
970 // CHECK3-NEXT: store i64 2, i64* [[TMP9]], align 8
971 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
972 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
973 // CHECK3-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
974 // CHECK3: omp_offload.failed:
975 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
976 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
977 // CHECK3: omp_offload.cont:
978 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
979 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
980 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
981 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
982 // CHECK3: arraydestroy.body:
983 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
984 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
985 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
986 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
987 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
988 // CHECK3: arraydestroy.done2:
989 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
990 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
991 // CHECK3-NEXT: ret i32 [[TMP13]]
992 //
993 //
994 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
995 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
996 // CHECK3-NEXT: entry:
997 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
998 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
999 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1000 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1001 // CHECK3-NEXT: ret void
1002 //
1003 //
1004 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1005 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1006 // CHECK3-NEXT: entry:
1007 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1008 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1009 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1010 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1011 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1012 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1013 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1014 // CHECK3-NEXT: ret void
1015 //
1016 //
1017 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1018 // CHECK3-SAME: () #[[ATTR4]] {
1019 // CHECK3-NEXT: entry:
1020 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
1021 // CHECK3-NEXT: ret void
1022 //
1023 //
1024 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1025 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1026 // CHECK3-NEXT: entry:
1027 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1028 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1029 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1030 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1031 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1032 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1033 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1034 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1035 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1036 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1037 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1038 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1039 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1040 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1041 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1042 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1043 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1044 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1045 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1046 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1047 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1048 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1049 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1050 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1051 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1052 // CHECK3: arrayctor.loop:
1053 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1054 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1055 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1056 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1057 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1058 // CHECK3: arrayctor.cont:
1059 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1060 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1061 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1062 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1063 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1064 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1065 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1066 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1067 // CHECK3: cond.true:
1068 // CHECK3-NEXT: br label [[COND_END:%.*]]
1069 // CHECK3: cond.false:
1070 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1071 // CHECK3-NEXT: br label [[COND_END]]
1072 // CHECK3: cond.end:
1073 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1074 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1075 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1076 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1077 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1078 // CHECK3: omp.inner.for.cond:
1079 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1080 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
1081 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1082 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1083 // CHECK3: omp.inner.for.cond.cleanup:
1084 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1085 // CHECK3: omp.inner.for.body:
1086 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1087 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1088 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1089 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
1090 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12
1091 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
1092 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1093 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
1094 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12
1095 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
1096 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
1097 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
1098 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
1099 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12
1100 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1101 // CHECK3: omp.body.continue:
1102 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1103 // CHECK3: omp.inner.for.inc:
1104 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1105 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1106 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1107 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1108 // CHECK3: omp.inner.for.end:
1109 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1110 // CHECK3: omp.loop.exit:
1111 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1112 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
1113 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
1114 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1115 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1116 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1117 // CHECK3: .omp.final.then:
1118 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1119 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1120 // CHECK3: .omp.final.done:
1121 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1122 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1123 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
1124 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1125 // CHECK3: arraydestroy.body:
1126 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1127 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1128 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1129 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1130 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1131 // CHECK3: arraydestroy.done7:
1132 // CHECK3-NEXT: ret void
1133 //
1134 //
1135 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1136 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1137 // CHECK3-NEXT: entry:
1138 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1139 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1140 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1141 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1142 // CHECK3-NEXT: ret void
1143 //
1144 //
1145 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1146 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1147 // CHECK3-NEXT: entry:
1148 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1149 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1150 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1151 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1152 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1153 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1154 // CHECK3-NEXT: ret void
1155 //
1156 //
1157 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1158 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1159 // CHECK3-NEXT: entry:
1160 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1161 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1162 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1163 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1164 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1165 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1166 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1167 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1168 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1169 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1170 // CHECK3-NEXT: ret void
1171 //
1172 //
1173 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1174 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1175 // CHECK3-NEXT: entry:
1176 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1177 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1178 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1179 // CHECK3-NEXT: ret void
1180 //
1181 //
1182 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1183 // CHECK3-SAME: () #[[ATTR0]] {
1184 // CHECK3-NEXT: entry:
1185 // CHECK3-NEXT: call void @__cxx_global_var_init()
1186 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
1187 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
1188 // CHECK3-NEXT: ret void
1189 //
1190 //
1191 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1192 // CHECK3-SAME: () #[[ATTR0]] {
1193 // CHECK3-NEXT: entry:
1194 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1195 // CHECK3-NEXT: ret void
1196 //
1197 //
1198 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
1199 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1200 // CHECK5-NEXT: entry:
1201 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1202 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1203 // CHECK5-NEXT: ret void
1204 //
1205 //
1206 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1207 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1208 // CHECK5-NEXT: entry:
1209 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1210 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1211 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1212 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1213 // CHECK5-NEXT: ret void
1214 //
1215 //
1216 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1217 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1218 // CHECK5-NEXT: entry:
1219 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1220 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1221 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1222 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1223 // CHECK5-NEXT: ret void
1224 //
1225 //
1226 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1227 // CHECK5-SAME: () #[[ATTR0]] {
1228 // CHECK5-NEXT: entry:
1229 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
1230 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
1231 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1232 // CHECK5-NEXT: ret void
1233 //
1234 //
1235 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1236 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1237 // CHECK5-NEXT: entry:
1238 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1239 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1240 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1241 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1242 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1243 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1244 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1245 // CHECK5-NEXT: ret void
1246 //
1247 //
1248 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1249 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1250 // CHECK5-NEXT: entry:
1251 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1252 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1253 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1254 // CHECK5: arraydestroy.body:
1255 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1256 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1257 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1258 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1259 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1260 // CHECK5: arraydestroy.done1:
1261 // CHECK5-NEXT: ret void
1262 //
1263 //
1264 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1265 // CHECK5-SAME: () #[[ATTR0]] {
1266 // CHECK5-NEXT: entry:
1267 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1268 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1269 // CHECK5-NEXT: ret void
1270 //
1271 //
1272 // CHECK5-LABEL: define {{[^@]+}}@main
1273 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1274 // CHECK5-NEXT: entry:
1275 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1276 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1277 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1278 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1279 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1280 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1281 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1282 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1283 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1284 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1285 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1286 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1287 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1288 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1289 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1290 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1291 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1292 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1293 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1294 // CHECK5: arrayctor.loop:
1295 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1296 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1297 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1298 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1299 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1300 // CHECK5: arrayctor.cont:
1301 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1302 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1303 // CHECK5: omp.inner.for.cond:
1304 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1305 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
1306 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1307 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1308 // CHECK5: omp.inner.for.cond.cleanup:
1309 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1310 // CHECK5: omp.inner.for.body:
1311 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1312 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1313 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1314 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
1315 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
1316 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1317 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1318 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1319 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
1320 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1321 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
1322 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
1323 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1324 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1325 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
1326 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1327 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
1328 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
1329 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
1330 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1331 // CHECK5: omp.body.continue:
1332 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1333 // CHECK5: omp.inner.for.inc:
1334 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1335 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
1336 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1337 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1338 // CHECK5: omp.inner.for.end:
1339 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1340 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1341 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1342 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
1343 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1344 // CHECK5: arraydestroy.body:
1345 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1346 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1347 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1348 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1349 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1350 // CHECK5: arraydestroy.done6:
1351 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1352 // CHECK5-NEXT: ret i32 [[CALL]]
1353 //
1354 //
1355 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1356 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1357 // CHECK5-NEXT: entry:
1358 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1359 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1360 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1361 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1362 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1363 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1364 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1365 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1366 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1367 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1368 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1369 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1370 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1371 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1372 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1373 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1374 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
1375 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1376 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
1377 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1378 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1379 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1380 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1381 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1382 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1383 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1384 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1385 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1386 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1387 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1388 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1389 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1390 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1391 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1392 // CHECK5: arrayctor.loop:
1393 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1394 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1395 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1396 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1397 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1398 // CHECK5: arrayctor.cont:
1399 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1400 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
1401 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1402 // CHECK5: omp.inner.for.cond:
1403 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1404 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
1405 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1406 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1407 // CHECK5: omp.inner.for.cond.cleanup:
1408 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1409 // CHECK5: omp.inner.for.body:
1410 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1411 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1412 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1413 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
1414 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
1415 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1416 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1417 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
1418 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
1419 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
1420 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1421 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
1422 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
1423 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
1424 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
1425 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
1426 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1427 // CHECK5: omp.body.continue:
1428 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1429 // CHECK5: omp.inner.for.inc:
1430 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1431 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
1432 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1433 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1434 // CHECK5: omp.inner.for.end:
1435 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1436 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1437 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1438 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
1439 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1440 // CHECK5: arraydestroy.body:
1441 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1442 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1443 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1444 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1445 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1446 // CHECK5: arraydestroy.done11:
1447 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1448 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1449 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
1450 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
1451 // CHECK5: arraydestroy.body13:
1452 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1453 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1454 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
1455 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1456 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1457 // CHECK5: arraydestroy.done17:
1458 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1459 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
1460 // CHECK5-NEXT: ret i32 [[TMP14]]
1461 //
1462 //
1463 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1464 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1465 // CHECK5-NEXT: entry:
1466 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1467 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1468 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1469 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1470 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1471 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1472 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
1473 // CHECK5-NEXT: ret void
1474 //
1475 //
1476 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1477 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1478 // CHECK5-NEXT: entry:
1479 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1480 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1481 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1482 // CHECK5-NEXT: ret void
1483 //
1484 //
1485 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1486 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1487 // CHECK5-NEXT: entry:
1488 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1489 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1490 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1491 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1492 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1493 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1494 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1495 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1496 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1497 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1498 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
1499 // CHECK5-NEXT: ret void
1500 //
1501 //
1502 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1503 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1504 // CHECK5-NEXT: entry:
1505 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1506 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1507 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1508 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1509 // CHECK5-NEXT: ret void
1510 //
1511 //
1512 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1513 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1514 // CHECK5-NEXT: entry:
1515 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1516 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1517 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1518 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1519 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1520 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1521 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1522 // CHECK5-NEXT: ret void
1523 //
1524 //
1525 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1526 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1527 // CHECK5-NEXT: entry:
1528 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1529 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1530 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1531 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1532 // CHECK5-NEXT: ret void
1533 //
1534 //
1535 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1536 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1537 // CHECK5-NEXT: entry:
1538 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1539 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1540 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1541 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1542 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1543 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1544 // CHECK5-NEXT: ret void
1545 //
1546 //
1547 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1548 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1549 // CHECK5-NEXT: entry:
1550 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1551 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1552 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1553 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1554 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1555 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1556 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1557 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1558 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1559 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1560 // CHECK5-NEXT: ret void
1561 //
1562 //
1563 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1564 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1565 // CHECK5-NEXT: entry:
1566 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1567 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1568 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1569 // CHECK5-NEXT: ret void
1570 //
1571 //
1572 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1573 // CHECK5-SAME: () #[[ATTR0]] {
1574 // CHECK5-NEXT: entry:
1575 // CHECK5-NEXT: call void @__cxx_global_var_init()
1576 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
1577 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
1578 // CHECK5-NEXT: ret void
1579 //
1580 //
1581 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
1582 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1583 // CHECK7-NEXT: entry:
1584 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1585 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1586 // CHECK7-NEXT: ret void
1587 //
1588 //
1589 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1590 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1591 // CHECK7-NEXT: entry:
1592 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1593 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1594 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1595 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1596 // CHECK7-NEXT: ret void
1597 //
1598 //
1599 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1600 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1601 // CHECK7-NEXT: entry:
1602 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1603 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1604 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1605 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1606 // CHECK7-NEXT: ret void
1607 //
1608 //
1609 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1610 // CHECK7-SAME: () #[[ATTR0]] {
1611 // CHECK7-NEXT: entry:
1612 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
1613 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
1614 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1615 // CHECK7-NEXT: ret void
1616 //
1617 //
1618 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1619 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1620 // CHECK7-NEXT: entry:
1621 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1622 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1623 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1624 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1625 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1626 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1627 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1628 // CHECK7-NEXT: ret void
1629 //
1630 //
1631 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1632 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1633 // CHECK7-NEXT: entry:
1634 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1635 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1636 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1637 // CHECK7: arraydestroy.body:
1638 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1639 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1640 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1641 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1642 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1643 // CHECK7: arraydestroy.done1:
1644 // CHECK7-NEXT: ret void
1645 //
1646 //
1647 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1648 // CHECK7-SAME: () #[[ATTR0]] {
1649 // CHECK7-NEXT: entry:
1650 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1651 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1652 // CHECK7-NEXT: ret void
1653 //
1654 //
1655 // CHECK7-LABEL: define {{[^@]+}}@main
1656 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
1657 // CHECK7-NEXT: entry:
1658 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1659 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1660 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1661 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1662 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1663 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1664 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1665 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1666 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1667 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1668 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1669 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
1670 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1671 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1672 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1673 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1674 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1675 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1676 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1677 // CHECK7: arrayctor.loop:
1678 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1679 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1680 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1681 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1682 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1683 // CHECK7: arrayctor.cont:
1684 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1685 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1686 // CHECK7: omp.inner.for.cond:
1687 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1688 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
1689 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1690 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1691 // CHECK7: omp.inner.for.cond.cleanup:
1692 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1693 // CHECK7: omp.inner.for.body:
1694 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1695 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1696 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1697 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
1698 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
1699 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1700 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
1701 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
1702 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1703 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
1704 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
1705 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1706 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
1707 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1708 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
1709 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
1710 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
1711 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1712 // CHECK7: omp.body.continue:
1713 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1714 // CHECK7: omp.inner.for.inc:
1715 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1716 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
1717 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1718 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1719 // CHECK7: omp.inner.for.end:
1720 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
1721 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1722 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1723 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
1724 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1725 // CHECK7: arraydestroy.body:
1726 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1727 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1728 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1729 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1730 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1731 // CHECK7: arraydestroy.done5:
1732 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1733 // CHECK7-NEXT: ret i32 [[CALL]]
1734 //
1735 //
1736 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1737 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
1738 // CHECK7-NEXT: entry:
1739 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1740 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1741 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1742 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1743 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1744 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1745 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1746 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1747 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1748 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1749 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1750 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1751 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1752 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1753 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1754 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1755 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
1756 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1757 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
1758 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1759 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1760 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1761 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1762 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1763 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1764 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1765 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1766 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1767 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1768 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1769 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1770 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1771 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1772 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1773 // CHECK7: arrayctor.loop:
1774 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1775 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1776 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1777 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1778 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1779 // CHECK7: arrayctor.cont:
1780 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1781 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
1782 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1783 // CHECK7: omp.inner.for.cond:
1784 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1785 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
1786 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1787 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1788 // CHECK7: omp.inner.for.cond.cleanup:
1789 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1790 // CHECK7: omp.inner.for.body:
1791 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1792 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1793 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1794 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
1795 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
1796 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
1797 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
1798 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
1799 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
1800 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
1801 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
1802 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
1803 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
1804 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
1805 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1806 // CHECK7: omp.body.continue:
1807 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1808 // CHECK7: omp.inner.for.inc:
1809 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1810 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
1811 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1812 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1813 // CHECK7: omp.inner.for.end:
1814 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
1815 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1816 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1817 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
1818 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1819 // CHECK7: arraydestroy.body:
1820 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1821 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1822 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1823 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
1824 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
1825 // CHECK7: arraydestroy.done10:
1826 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
1827 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1828 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
1829 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
1830 // CHECK7: arraydestroy.body12:
1831 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
1832 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
1833 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
1834 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
1835 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
1836 // CHECK7: arraydestroy.done16:
1837 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1838 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
1839 // CHECK7-NEXT: ret i32 [[TMP14]]
1840 //
1841 //
1842 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1843 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1844 // CHECK7-NEXT: entry:
1845 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1846 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1847 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1848 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1849 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1850 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1851 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
1852 // CHECK7-NEXT: ret void
1853 //
1854 //
1855 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1856 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1857 // CHECK7-NEXT: entry:
1858 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1859 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1860 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1861 // CHECK7-NEXT: ret void
1862 //
1863 //
1864 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1865 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1866 // CHECK7-NEXT: entry:
1867 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1868 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1869 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1870 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1871 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1872 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1873 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1874 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1875 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1876 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1877 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
1878 // CHECK7-NEXT: ret void
1879 //
1880 //
1881 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1882 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1883 // CHECK7-NEXT: entry:
1884 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1885 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1886 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1887 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1888 // CHECK7-NEXT: ret void
1889 //
1890 //
1891 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1892 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1893 // CHECK7-NEXT: entry:
1894 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1895 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1896 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1897 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1898 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1899 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1900 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1901 // CHECK7-NEXT: ret void
1902 //
1903 //
1904 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1905 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1906 // CHECK7-NEXT: entry:
1907 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1908 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1909 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1910 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1911 // CHECK7-NEXT: ret void
1912 //
1913 //
1914 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1915 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1916 // CHECK7-NEXT: entry:
1917 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1918 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1919 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1920 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1921 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1922 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1923 // CHECK7-NEXT: ret void
1924 //
1925 //
1926 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1927 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1928 // CHECK7-NEXT: entry:
1929 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1930 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1931 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1932 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1933 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1934 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1935 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1936 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1937 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1938 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1939 // CHECK7-NEXT: ret void
1940 //
1941 //
1942 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1943 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1944 // CHECK7-NEXT: entry:
1945 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1946 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1947 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1948 // CHECK7-NEXT: ret void
1949 //
1950 //
1951 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1952 // CHECK7-SAME: () #[[ATTR0]] {
1953 // CHECK7-NEXT: entry:
1954 // CHECK7-NEXT: call void @__cxx_global_var_init()
1955 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
1956 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
1957 // CHECK7-NEXT: ret void
1958 //
1959 //
1960 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
1961 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1962 // CHECK9-NEXT: entry:
1963 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1964 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1965 // CHECK9-NEXT: ret void
1966 //
1967 //
1968 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1969 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1970 // CHECK9-NEXT: entry:
1971 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1972 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1973 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1974 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1975 // CHECK9-NEXT: ret void
1976 //
1977 //
1978 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1979 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1980 // CHECK9-NEXT: entry:
1981 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1982 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1983 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1984 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1985 // CHECK9-NEXT: ret void
1986 //
1987 //
1988 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1989 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1990 // CHECK9-NEXT: entry:
1991 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1992 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1993 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1994 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1995 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1996 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1997 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
1998 // CHECK9-NEXT: ret void
1999 //
2000 //
2001 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2002 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2003 // CHECK9-NEXT: entry:
2004 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2005 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2006 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2007 // CHECK9-NEXT: ret void
2008 //
2009 //
2010 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2011 // CHECK9-SAME: () #[[ATTR0]] {
2012 // CHECK9-NEXT: entry:
2013 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2014 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2015 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2016 // CHECK9-NEXT: ret void
2017 //
2018 //
2019 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2020 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2021 // CHECK9-NEXT: entry:
2022 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2023 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2024 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2025 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2026 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2027 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2028 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2029 // CHECK9-NEXT: ret void
2030 //
2031 //
2032 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2033 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2034 // CHECK9-NEXT: entry:
2035 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2036 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2037 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2038 // CHECK9: arraydestroy.body:
2039 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2040 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2041 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2042 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2043 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2044 // CHECK9: arraydestroy.done1:
2045 // CHECK9-NEXT: ret void
2046 //
2047 //
2048 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2049 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2050 // CHECK9-NEXT: entry:
2051 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2052 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2053 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2054 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2055 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2056 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2057 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2058 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2059 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2060 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2061 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
2062 // CHECK9-NEXT: ret void
2063 //
2064 //
2065 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2066 // CHECK9-SAME: () #[[ATTR0]] {
2067 // CHECK9-NEXT: entry:
2068 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2069 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2070 // CHECK9-NEXT: ret void
2071 //
2072 //
2073 // CHECK9-LABEL: define {{[^@]+}}@main
2074 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2075 // CHECK9-NEXT: entry:
2076 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2077 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2078 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
2079 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2080 // CHECK9-NEXT: ret i32 0
2081 //
2082 //
2083 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
2084 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
2085 // CHECK9-NEXT: entry:
2086 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2087 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2088 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
2089 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2090 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
2091 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2092 // CHECK9-NEXT: ret void
2093 //
2094 //
2095 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
2096 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
2097 // CHECK9-NEXT: entry:
2098 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2099 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2100 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2101 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
2102 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
2103 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2104 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2105 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2106 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2107 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
2108 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
2109 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
2110 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2111 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2112 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2113 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2114 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2115 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
2116 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2117 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2118 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2119 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2120 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
2121 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2122 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2123 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2124 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2125 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2126 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2127 // CHECK9: cond.true:
2128 // CHECK9-NEXT: br label [[COND_END:%.*]]
2129 // CHECK9: cond.false:
2130 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2131 // CHECK9-NEXT: br label [[COND_END]]
2132 // CHECK9: cond.end:
2133 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2134 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2135 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2136 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2137 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2138 // CHECK9: omp.inner.for.cond:
2139 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2140 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
2141 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2142 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2143 // CHECK9: omp.inner.for.body:
2144 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2145 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2146 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2147 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
2148 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4
2149 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
2150 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
2151 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4
2152 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
2153 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4
2154 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
2155 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
2156 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
2157 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
2158 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4
2159 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
2160 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2161 // CHECK9: omp.body.continue:
2162 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2163 // CHECK9: omp.inner.for.inc:
2164 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2165 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
2166 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2167 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2168 // CHECK9: omp.inner.for.end:
2169 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2170 // CHECK9: omp.loop.exit:
2171 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2172 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2173 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
2174 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2175 // CHECK9: .omp.final.then:
2176 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
2177 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
2178 // CHECK9: .omp.final.done:
2179 // CHECK9-NEXT: ret void
2180 //
2181 //
2182 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
2183 // CHECK9-SAME: () #[[ATTR0]] {
2184 // CHECK9-NEXT: entry:
2185 // CHECK9-NEXT: call void @__cxx_global_var_init()
2186 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
2187 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
2188 // CHECK9-NEXT: ret void
2189 //
2190 //
2191 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2192 // CHECK9-SAME: () #[[ATTR0]] {
2193 // CHECK9-NEXT: entry:
2194 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
2195 // CHECK9-NEXT: ret void
2196 //
2197 //
2198 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
2199 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2200 // CHECK11-NEXT: entry:
2201 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2202 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2203 // CHECK11-NEXT: ret void
2204 //
2205 //
2206 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2207 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2208 // CHECK11-NEXT: entry:
2209 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2210 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2211 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2212 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2213 // CHECK11-NEXT: ret void
2214 //
2215 //
2216 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2217 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2218 // CHECK11-NEXT: entry:
2219 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2220 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2221 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2222 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2223 // CHECK11-NEXT: ret void
2224 //
2225 //
2226 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2227 // CHECK11-SAME: () #[[ATTR0]] {
2228 // CHECK11-NEXT: entry:
2229 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2230 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2231 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2232 // CHECK11-NEXT: ret void
2233 //
2234 //
2235 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2236 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2237 // CHECK11-NEXT: entry:
2238 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2239 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2240 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2241 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2242 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2243 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2244 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2245 // CHECK11-NEXT: ret void
2246 //
2247 //
2248 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2249 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2250 // CHECK11-NEXT: entry:
2251 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2252 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2253 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2254 // CHECK11: arraydestroy.body:
2255 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2256 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2257 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2258 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2259 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2260 // CHECK11: arraydestroy.done1:
2261 // CHECK11-NEXT: ret void
2262 //
2263 //
2264 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2265 // CHECK11-SAME: () #[[ATTR0]] {
2266 // CHECK11-NEXT: entry:
2267 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2268 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2269 // CHECK11-NEXT: ret void
2270 //
2271 //
2272 // CHECK11-LABEL: define {{[^@]+}}@main
2273 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
2274 // CHECK11-NEXT: entry:
2275 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2276 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2277 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
2278 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2279 // CHECK11-NEXT: ret i32 0
2280 //
2281 //
2282 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2283 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2284 // CHECK11-NEXT: entry:
2285 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2286 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2287 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2288 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2289 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2290 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2291 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
2292 // CHECK11-NEXT: ret void
2293 //
2294 //
2295 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2296 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2297 // CHECK11-NEXT: entry:
2298 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2299 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2300 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2301 // CHECK11-NEXT: ret void
2302 //
2303 //
2304 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2305 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2306 // CHECK11-NEXT: entry:
2307 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2308 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2309 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2310 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2311 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2312 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2313 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2314 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2315 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2316 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2317 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
2318 // CHECK11-NEXT: ret void
2319 //
2320 //
2321 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
2322 // CHECK11-SAME: () #[[ATTR0]] {
2323 // CHECK11-NEXT: entry:
2324 // CHECK11-NEXT: call void @__cxx_global_var_init()
2325 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
2326 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
2327 // CHECK11-NEXT: ret void
2328 //
2329