1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
15
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute parallel for simd private(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global, bound tid and loop vars
80
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84
85 // Skip global, bound tid and loop vars
86 [&]() {
87 g = 2;
88 g1 = 2;
89 sivar = 4;
90
91 }();
92 }
93 }();
94 return 0;
95
96
97 #else
98 #pragma omp target
99 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var, sivar)
100 for (int i = 0; i < 2; ++i) {
101 vec[i] = t_var;
102 s_arr[i] = var;
103 sivar += i;
104 }
105 return tmain<int>();
106 #endif
107 }
108
109
110
111 // Skip global, bound tid and loop vars
112
113 // private(s_arr)
114
115 // private(var)
116
117
118 // Skip global, bound tid and loop vars
119
120 // private(s_arr)
121
122 // private(var)
123
124
125
126
127 // Skip global, bound tid and loop vars
128
129 // private(s_arr)
130
131
132 // private(var)
133
134
135 // Skip global, bound tid and loop vars
136 // prev lb and ub
137 // iter variables
138
139 // private(s_arr)
140
141
142 // private(var)
143
144
145
146 #endif
147 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
148 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
149 // CHECK1-NEXT: entry:
150 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
151 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
152 // CHECK1-NEXT: ret void
153 //
154 //
155 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
156 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
157 // CHECK1-NEXT: entry:
158 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
159 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
160 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
161 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
162 // CHECK1-NEXT: ret void
163 //
164 //
165 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
166 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
167 // CHECK1-NEXT: entry:
168 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
169 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
170 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
171 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
172 // CHECK1-NEXT: ret void
173 //
174 //
175 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
176 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
177 // CHECK1-NEXT: entry:
178 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
179 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
180 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
181 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
182 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
183 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
184 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
185 // CHECK1-NEXT: ret void
186 //
187 //
188 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
189 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
190 // CHECK1-NEXT: entry:
191 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
192 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
193 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
194 // CHECK1-NEXT: ret void
195 //
196 //
197 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
198 // CHECK1-SAME: () #[[ATTR0]] {
199 // CHECK1-NEXT: entry:
200 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
201 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
202 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
203 // CHECK1-NEXT: ret void
204 //
205 //
206 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
207 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
208 // CHECK1-NEXT: entry:
209 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
210 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
211 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
212 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
213 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
214 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
215 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
216 // CHECK1-NEXT: ret void
217 //
218 //
219 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
220 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
221 // CHECK1-NEXT: entry:
222 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
223 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
224 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
225 // CHECK1: arraydestroy.body:
226 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
227 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
228 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
229 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
230 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
231 // CHECK1: arraydestroy.done1:
232 // CHECK1-NEXT: ret void
233 //
234 //
235 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
236 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
237 // CHECK1-NEXT: entry:
238 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
239 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
240 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
241 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
242 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
243 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
244 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
245 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
246 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
247 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
248 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
249 // CHECK1-NEXT: ret void
250 //
251 //
252 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
253 // CHECK1-SAME: () #[[ATTR0]] {
254 // CHECK1-NEXT: entry:
255 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
256 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
257 // CHECK1-NEXT: ret void
258 //
259 //
260 // CHECK1-LABEL: define {{[^@]+}}@main
261 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
262 // CHECK1-NEXT: entry:
263 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
265 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
266 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
267 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
268 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
269 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
270 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
271 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
272 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
273 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
274 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
275 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
276 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
277 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
278 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
279 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
280 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
281 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
282 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
283 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
284 // CHECK1-NEXT: store i64 2, i64* [[TMP8]], align 8
285 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
286 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
287 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
288 // CHECK1: omp_offload.failed:
289 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
290 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
291 // CHECK1: omp_offload.cont:
292 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
293 // CHECK1-NEXT: ret i32 [[CALL]]
294 //
295 //
296 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
297 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
298 // CHECK1-NEXT: entry:
299 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
300 // CHECK1-NEXT: ret void
301 //
302 //
303 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
304 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
305 // CHECK1-NEXT: entry:
306 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
307 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
308 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
309 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
310 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
311 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
312 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
313 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
314 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
315 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
316 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
317 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
318 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
319 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
320 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
321 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
322 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
323 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
324 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
325 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
326 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
327 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
328 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
329 // CHECK1: arrayctor.loop:
330 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
331 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
332 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
333 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
334 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
335 // CHECK1: arrayctor.cont:
336 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
337 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
338 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
339 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
340 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
341 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
342 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
343 // CHECK1: cond.true:
344 // CHECK1-NEXT: br label [[COND_END:%.*]]
345 // CHECK1: cond.false:
346 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
347 // CHECK1-NEXT: br label [[COND_END]]
348 // CHECK1: cond.end:
349 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
350 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
351 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
352 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
353 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
354 // CHECK1: omp.inner.for.cond:
355 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
356 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
357 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
358 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
359 // CHECK1: omp.inner.for.cond.cleanup:
360 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
361 // CHECK1: omp.inner.for.body:
362 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
363 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
364 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
365 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
366 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5
367 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
368 // CHECK1: omp.inner.for.inc:
369 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
370 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
371 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
372 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
373 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
374 // CHECK1: omp.inner.for.end:
375 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
376 // CHECK1: omp.loop.exit:
377 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
378 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
379 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
380 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
381 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
382 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
383 // CHECK1: .omp.final.then:
384 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
385 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
386 // CHECK1: .omp.final.done:
387 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
388 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
389 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2
390 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
391 // CHECK1: arraydestroy.body:
392 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
393 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
394 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
395 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
396 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
397 // CHECK1: arraydestroy.done3:
398 // CHECK1-NEXT: ret void
399 //
400 //
401 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
402 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
403 // CHECK1-NEXT: entry:
404 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
405 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
406 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
407 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
408 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
409 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
410 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
411 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
412 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
413 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
414 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
415 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
416 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
417 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
418 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
419 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
420 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
421 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
422 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
423 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
424 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
425 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
426 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
427 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
428 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
429 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
430 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
431 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
432 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
433 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
434 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
435 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
436 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
437 // CHECK1: arrayctor.loop:
438 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
439 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
440 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
441 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
442 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
443 // CHECK1: arrayctor.cont:
444 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
445 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
446 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
447 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
448 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
449 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
450 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
451 // CHECK1: cond.true:
452 // CHECK1-NEXT: br label [[COND_END:%.*]]
453 // CHECK1: cond.false:
454 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
455 // CHECK1-NEXT: br label [[COND_END]]
456 // CHECK1: cond.end:
457 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
458 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
459 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
460 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
461 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
462 // CHECK1: omp.inner.for.cond:
463 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
464 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
465 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
466 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
467 // CHECK1: omp.inner.for.cond.cleanup:
468 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
469 // CHECK1: omp.inner.for.body:
470 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
471 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
472 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
473 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
474 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !9
475 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
476 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
477 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
478 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
479 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
480 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
481 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
482 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8*
483 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
484 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !9
485 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
486 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !9
487 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
488 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !9
489 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
490 // CHECK1: omp.body.continue:
491 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
492 // CHECK1: omp.inner.for.inc:
493 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
494 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
495 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
496 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
497 // CHECK1: omp.inner.for.end:
498 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
499 // CHECK1: omp.loop.exit:
500 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
501 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
502 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
503 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
504 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
505 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
506 // CHECK1: .omp.final.then:
507 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
508 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
509 // CHECK1: .omp.final.done:
510 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
511 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
512 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2
513 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
514 // CHECK1: arraydestroy.body:
515 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
516 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
517 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
518 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
519 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
520 // CHECK1: arraydestroy.done8:
521 // CHECK1-NEXT: ret void
522 //
523 //
524 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
525 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
526 // CHECK1-NEXT: entry:
527 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
528 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
529 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
530 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
531 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
532 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
533 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
534 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
535 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
536 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
537 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
538 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
539 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
540 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
541 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
542 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
543 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
544 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
545 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
546 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
547 // CHECK1-NEXT: store i32 1, i32* [[TMP1]], align 4
548 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
549 // CHECK1-NEXT: store i32 0, i32* [[TMP2]], align 4
550 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
551 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
552 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
553 // CHECK1-NEXT: store i8** null, i8*** [[TMP4]], align 8
554 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
555 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
556 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
557 // CHECK1-NEXT: store i64* null, i64** [[TMP6]], align 8
558 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
559 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
560 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
561 // CHECK1-NEXT: store i8** null, i8*** [[TMP8]], align 8
562 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
563 // CHECK1-NEXT: store i64 2, i64* [[TMP9]], align 8
564 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
565 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
566 // CHECK1-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
567 // CHECK1: omp_offload.failed:
568 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
569 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
570 // CHECK1: omp_offload.cont:
571 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
572 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
573 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
574 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
575 // CHECK1: arraydestroy.body:
576 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
577 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
578 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
579 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
580 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
581 // CHECK1: arraydestroy.done2:
582 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
583 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
584 // CHECK1-NEXT: ret i32 [[TMP13]]
585 //
586 //
587 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
588 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
589 // CHECK1-NEXT: entry:
590 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
591 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
592 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
593 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
594 // CHECK1-NEXT: ret void
595 //
596 //
597 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
598 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
599 // CHECK1-NEXT: entry:
600 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
601 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
602 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
603 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
604 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
605 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
606 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
607 // CHECK1-NEXT: ret void
608 //
609 //
610 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
611 // CHECK1-SAME: () #[[ATTR4]] {
612 // CHECK1-NEXT: entry:
613 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
614 // CHECK1-NEXT: ret void
615 //
616 //
617 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
618 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
619 // CHECK1-NEXT: entry:
620 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
621 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
622 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
623 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
624 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
625 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
626 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
627 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
628 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
629 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
630 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
631 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
632 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
633 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
634 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
635 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
636 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
637 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
638 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
639 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
640 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
641 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
642 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
643 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
644 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
645 // CHECK1: arrayctor.loop:
646 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
647 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
648 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
649 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
650 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
651 // CHECK1: arrayctor.cont:
652 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
653 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
654 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
655 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
656 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
657 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
658 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
659 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
660 // CHECK1: cond.true:
661 // CHECK1-NEXT: br label [[COND_END:%.*]]
662 // CHECK1: cond.false:
663 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
664 // CHECK1-NEXT: br label [[COND_END]]
665 // CHECK1: cond.end:
666 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
667 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
668 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
669 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
670 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
671 // CHECK1: omp.inner.for.cond:
672 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
673 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
674 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
675 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
676 // CHECK1: omp.inner.for.cond.cleanup:
677 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
678 // CHECK1: omp.inner.for.body:
679 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
680 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
681 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
682 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
683 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14
684 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
685 // CHECK1: omp.inner.for.inc:
686 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
687 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
688 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
689 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
690 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
691 // CHECK1: omp.inner.for.end:
692 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
693 // CHECK1: omp.loop.exit:
694 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
695 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
696 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
697 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
698 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
699 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
700 // CHECK1: .omp.final.then:
701 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
702 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
703 // CHECK1: .omp.final.done:
704 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
705 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
706 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2
707 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
708 // CHECK1: arraydestroy.body:
709 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
710 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
711 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
712 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
713 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
714 // CHECK1: arraydestroy.done5:
715 // CHECK1-NEXT: ret void
716 //
717 //
718 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
719 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
720 // CHECK1-NEXT: entry:
721 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
722 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
723 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
724 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
725 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
726 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
727 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
728 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
729 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
730 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
731 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
732 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
733 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
734 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
735 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
736 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8
737 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
738 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
739 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
740 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
741 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
742 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
743 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
744 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
745 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
746 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
747 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
748 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
749 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
750 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
751 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
752 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
753 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
754 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
755 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
756 // CHECK1: arrayctor.loop:
757 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
758 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
759 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
760 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
761 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
762 // CHECK1: arrayctor.cont:
763 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
764 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8
765 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
766 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
767 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
768 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
769 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
770 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
771 // CHECK1: cond.true:
772 // CHECK1-NEXT: br label [[COND_END:%.*]]
773 // CHECK1: cond.false:
774 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
775 // CHECK1-NEXT: br label [[COND_END]]
776 // CHECK1: cond.end:
777 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
778 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
779 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
780 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
781 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
782 // CHECK1: omp.inner.for.cond:
783 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
784 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
785 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
786 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
787 // CHECK1: omp.inner.for.cond.cleanup:
788 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
789 // CHECK1: omp.inner.for.body:
790 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
791 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
792 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
793 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
794 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !17
795 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
796 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
797 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
798 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
799 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17
800 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
801 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
802 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]]
803 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8*
804 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
805 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17
806 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
807 // CHECK1: omp.body.continue:
808 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
809 // CHECK1: omp.inner.for.inc:
810 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
811 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
812 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
813 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
814 // CHECK1: omp.inner.for.end:
815 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
816 // CHECK1: omp.loop.exit:
817 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
818 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
819 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
820 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
821 // CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
822 // CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
823 // CHECK1: .omp.final.then:
824 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
825 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
826 // CHECK1: .omp.final.done:
827 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
828 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
829 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2
830 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
831 // CHECK1: arraydestroy.body:
832 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
833 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
834 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
835 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
836 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
837 // CHECK1: arraydestroy.done9:
838 // CHECK1-NEXT: ret void
839 //
840 //
841 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
842 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
843 // CHECK1-NEXT: entry:
844 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
845 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
846 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
847 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
848 // CHECK1-NEXT: ret void
849 //
850 //
851 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
852 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
853 // CHECK1-NEXT: entry:
854 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
855 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
856 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
857 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
858 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
859 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
860 // CHECK1-NEXT: ret void
861 //
862 //
863 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
864 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
865 // CHECK1-NEXT: entry:
866 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
867 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
868 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
869 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
870 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
871 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
872 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
873 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
874 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
875 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
876 // CHECK1-NEXT: ret void
877 //
878 //
879 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
880 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
881 // CHECK1-NEXT: entry:
882 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
883 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
884 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
885 // CHECK1-NEXT: ret void
886 //
887 //
888 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
889 // CHECK1-SAME: () #[[ATTR0]] {
890 // CHECK1-NEXT: entry:
891 // CHECK1-NEXT: call void @__cxx_global_var_init()
892 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
893 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
894 // CHECK1-NEXT: ret void
895 //
896 //
897 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
898 // CHECK1-SAME: () #[[ATTR0]] {
899 // CHECK1-NEXT: entry:
900 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
901 // CHECK1-NEXT: ret void
902 //
903 //
904 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
905 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
906 // CHECK3-NEXT: entry:
907 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
908 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
909 // CHECK3-NEXT: ret void
910 //
911 //
912 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
913 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
914 // CHECK3-NEXT: entry:
915 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
916 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
917 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
918 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
919 // CHECK3-NEXT: ret void
920 //
921 //
922 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
923 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
924 // CHECK3-NEXT: entry:
925 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
926 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
927 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
928 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
929 // CHECK3-NEXT: ret void
930 //
931 //
932 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
933 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
934 // CHECK3-NEXT: entry:
935 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
936 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
937 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
938 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
939 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
940 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
941 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
942 // CHECK3-NEXT: ret void
943 //
944 //
945 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
946 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
947 // CHECK3-NEXT: entry:
948 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
949 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
950 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
951 // CHECK3-NEXT: ret void
952 //
953 //
954 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
955 // CHECK3-SAME: () #[[ATTR0]] {
956 // CHECK3-NEXT: entry:
957 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
958 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
959 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
960 // CHECK3-NEXT: ret void
961 //
962 //
963 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
964 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
965 // CHECK3-NEXT: entry:
966 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
967 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
968 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
969 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
970 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
971 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
972 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
973 // CHECK3-NEXT: ret void
974 //
975 //
976 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
977 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
978 // CHECK3-NEXT: entry:
979 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
980 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
981 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
982 // CHECK3: arraydestroy.body:
983 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
984 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
985 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
986 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
987 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
988 // CHECK3: arraydestroy.done1:
989 // CHECK3-NEXT: ret void
990 //
991 //
992 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
993 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
994 // CHECK3-NEXT: entry:
995 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
996 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
997 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
998 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
999 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1000 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1001 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1002 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1003 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1004 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1005 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1006 // CHECK3-NEXT: ret void
1007 //
1008 //
1009 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1010 // CHECK3-SAME: () #[[ATTR0]] {
1011 // CHECK3-NEXT: entry:
1012 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1013 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1014 // CHECK3-NEXT: ret void
1015 //
1016 //
1017 // CHECK3-LABEL: define {{[^@]+}}@main
1018 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1019 // CHECK3-NEXT: entry:
1020 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1021 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1022 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1023 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1024 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1025 // CHECK3-NEXT: store i32 1, i32* [[TMP0]], align 4
1026 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1027 // CHECK3-NEXT: store i32 0, i32* [[TMP1]], align 4
1028 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1029 // CHECK3-NEXT: store i8** null, i8*** [[TMP2]], align 4
1030 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1031 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
1032 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1033 // CHECK3-NEXT: store i64* null, i64** [[TMP4]], align 4
1034 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1035 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
1036 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1037 // CHECK3-NEXT: store i8** null, i8*** [[TMP6]], align 4
1038 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1039 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
1040 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1041 // CHECK3-NEXT: store i64 2, i64* [[TMP8]], align 8
1042 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1043 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1044 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1045 // CHECK3: omp_offload.failed:
1046 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
1047 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1048 // CHECK3: omp_offload.cont:
1049 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1050 // CHECK3-NEXT: ret i32 [[CALL]]
1051 //
1052 //
1053 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
1054 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1055 // CHECK3-NEXT: entry:
1056 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1057 // CHECK3-NEXT: ret void
1058 //
1059 //
1060 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1061 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1062 // CHECK3-NEXT: entry:
1063 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1064 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1065 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1066 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1067 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1068 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1069 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1070 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1071 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1072 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1073 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1074 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1075 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1076 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1077 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1078 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1079 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1080 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1081 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1082 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1083 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1084 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1085 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1086 // CHECK3: arrayctor.loop:
1087 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1088 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1089 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1090 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1091 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1092 // CHECK3: arrayctor.cont:
1093 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1094 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1095 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1096 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1097 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1098 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1099 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1100 // CHECK3: cond.true:
1101 // CHECK3-NEXT: br label [[COND_END:%.*]]
1102 // CHECK3: cond.false:
1103 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1104 // CHECK3-NEXT: br label [[COND_END]]
1105 // CHECK3: cond.end:
1106 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1107 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1108 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1109 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1110 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1111 // CHECK3: omp.inner.for.cond:
1112 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1113 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
1114 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1115 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1116 // CHECK3: omp.inner.for.cond.cleanup:
1117 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1118 // CHECK3: omp.inner.for.body:
1119 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
1120 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
1121 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6
1122 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1123 // CHECK3: omp.inner.for.inc:
1124 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1125 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
1126 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1127 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1128 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1129 // CHECK3: omp.inner.for.end:
1130 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1131 // CHECK3: omp.loop.exit:
1132 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1133 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1134 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
1135 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1136 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1137 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1138 // CHECK3: .omp.final.then:
1139 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1140 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1141 // CHECK3: .omp.final.done:
1142 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1143 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1144 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2
1145 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1146 // CHECK3: arraydestroy.body:
1147 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1148 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1149 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1150 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
1151 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1152 // CHECK3: arraydestroy.done3:
1153 // CHECK3-NEXT: ret void
1154 //
1155 //
1156 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1157 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1158 // CHECK3-NEXT: entry:
1159 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1160 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1161 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1162 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1163 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1164 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1165 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1166 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1167 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1168 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1169 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1170 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1171 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1172 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1173 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1174 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1175 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1176 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1177 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1178 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1179 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1180 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1181 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1182 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1183 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
1184 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
1185 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1186 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1187 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1188 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1189 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1190 // CHECK3: arrayctor.loop:
1191 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1192 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1193 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1194 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1195 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1196 // CHECK3: arrayctor.cont:
1197 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1198 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1199 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1200 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1201 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1202 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1203 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1204 // CHECK3: cond.true:
1205 // CHECK3-NEXT: br label [[COND_END:%.*]]
1206 // CHECK3: cond.false:
1207 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1208 // CHECK3-NEXT: br label [[COND_END]]
1209 // CHECK3: cond.end:
1210 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1211 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1212 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1213 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1214 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1215 // CHECK3: omp.inner.for.cond:
1216 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1217 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
1218 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1219 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1220 // CHECK3: omp.inner.for.cond.cleanup:
1221 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1222 // CHECK3: omp.inner.for.body:
1223 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1224 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1225 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1226 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
1227 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10
1228 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
1229 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
1230 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
1231 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
1232 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]]
1233 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1234 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1235 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !10
1236 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
1237 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10
1238 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
1239 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !10
1240 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1241 // CHECK3: omp.body.continue:
1242 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1243 // CHECK3: omp.inner.for.inc:
1244 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1245 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1
1246 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
1247 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
1248 // CHECK3: omp.inner.for.end:
1249 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1250 // CHECK3: omp.loop.exit:
1251 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1252 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
1253 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
1254 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1255 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1256 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1257 // CHECK3: .omp.final.then:
1258 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1259 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1260 // CHECK3: .omp.final.done:
1261 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1262 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1263 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
1264 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1265 // CHECK3: arraydestroy.body:
1266 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1267 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1268 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1269 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1270 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1271 // CHECK3: arraydestroy.done6:
1272 // CHECK3-NEXT: ret void
1273 //
1274 //
1275 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1276 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
1277 // CHECK3-NEXT: entry:
1278 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1279 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1280 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1281 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1282 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1283 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1284 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1285 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1286 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1287 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
1288 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1289 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1290 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1291 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1292 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1293 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1294 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1295 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1296 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1297 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1298 // CHECK3-NEXT: store i32 1, i32* [[TMP1]], align 4
1299 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1300 // CHECK3-NEXT: store i32 0, i32* [[TMP2]], align 4
1301 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1302 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
1303 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1304 // CHECK3-NEXT: store i8** null, i8*** [[TMP4]], align 4
1305 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1306 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
1307 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1308 // CHECK3-NEXT: store i64* null, i64** [[TMP6]], align 4
1309 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1310 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
1311 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1312 // CHECK3-NEXT: store i8** null, i8*** [[TMP8]], align 4
1313 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1314 // CHECK3-NEXT: store i64 2, i64* [[TMP9]], align 8
1315 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1316 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
1317 // CHECK3-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1318 // CHECK3: omp_offload.failed:
1319 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1320 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1321 // CHECK3: omp_offload.cont:
1322 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1323 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1324 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1325 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1326 // CHECK3: arraydestroy.body:
1327 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1328 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1329 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1330 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1331 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1332 // CHECK3: arraydestroy.done2:
1333 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1334 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
1335 // CHECK3-NEXT: ret i32 [[TMP13]]
1336 //
1337 //
1338 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1339 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1340 // CHECK3-NEXT: entry:
1341 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1342 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1343 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1344 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1345 // CHECK3-NEXT: ret void
1346 //
1347 //
1348 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1349 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1350 // CHECK3-NEXT: entry:
1351 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1352 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1353 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1354 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1355 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1356 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1357 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1358 // CHECK3-NEXT: ret void
1359 //
1360 //
1361 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1362 // CHECK3-SAME: () #[[ATTR4]] {
1363 // CHECK3-NEXT: entry:
1364 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
1365 // CHECK3-NEXT: ret void
1366 //
1367 //
1368 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
1369 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1370 // CHECK3-NEXT: entry:
1371 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1372 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1373 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1374 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1375 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1376 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1377 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1378 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1379 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1380 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1381 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1382 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1383 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1384 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1385 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1386 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1387 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1388 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1389 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1390 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1391 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1392 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1393 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1394 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1395 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1396 // CHECK3: arrayctor.loop:
1397 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1398 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1399 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1400 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1401 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1402 // CHECK3: arrayctor.cont:
1403 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1404 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1405 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1406 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1407 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1408 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1409 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1410 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1411 // CHECK3: cond.true:
1412 // CHECK3-NEXT: br label [[COND_END:%.*]]
1413 // CHECK3: cond.false:
1414 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1415 // CHECK3-NEXT: br label [[COND_END]]
1416 // CHECK3: cond.end:
1417 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1418 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1419 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1420 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1421 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1422 // CHECK3: omp.inner.for.cond:
1423 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1424 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
1425 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1426 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1427 // CHECK3: omp.inner.for.cond.cleanup:
1428 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1429 // CHECK3: omp.inner.for.body:
1430 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
1431 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
1432 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15
1433 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1434 // CHECK3: omp.inner.for.inc:
1435 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1436 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
1437 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1438 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1439 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
1440 // CHECK3: omp.inner.for.end:
1441 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1442 // CHECK3: omp.loop.exit:
1443 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1444 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1445 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
1446 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1447 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1448 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1449 // CHECK3: .omp.final.then:
1450 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1451 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1452 // CHECK3: .omp.final.done:
1453 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1454 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1455 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2
1456 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1457 // CHECK3: arraydestroy.body:
1458 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1459 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1460 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1461 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1462 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1463 // CHECK3: arraydestroy.done5:
1464 // CHECK3-NEXT: ret void
1465 //
1466 //
1467 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
1468 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1469 // CHECK3-NEXT: entry:
1470 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1471 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1472 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1473 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1474 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1475 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1476 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1477 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1478 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1479 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1480 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1481 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1482 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1483 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1484 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1485 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1486 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1487 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1488 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1489 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1490 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1491 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1492 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1493 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1494 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1495 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1496 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
1497 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
1498 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1499 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1500 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1501 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1502 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1503 // CHECK3: arrayctor.loop:
1504 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1505 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1506 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1507 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1508 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1509 // CHECK3: arrayctor.cont:
1510 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1511 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1512 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1513 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1514 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1515 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1516 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1517 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1518 // CHECK3: cond.true:
1519 // CHECK3-NEXT: br label [[COND_END:%.*]]
1520 // CHECK3: cond.false:
1521 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1522 // CHECK3-NEXT: br label [[COND_END]]
1523 // CHECK3: cond.end:
1524 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1525 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1526 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1527 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1528 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1529 // CHECK3: omp.inner.for.cond:
1530 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1531 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
1532 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1533 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1534 // CHECK3: omp.inner.for.cond.cleanup:
1535 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1536 // CHECK3: omp.inner.for.body:
1537 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1538 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1539 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1540 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
1541 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18
1542 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
1543 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
1544 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
1545 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18
1546 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
1547 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]]
1548 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
1549 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
1550 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18
1551 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1552 // CHECK3: omp.body.continue:
1553 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1554 // CHECK3: omp.inner.for.inc:
1555 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1556 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
1557 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
1558 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
1559 // CHECK3: omp.inner.for.end:
1560 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1561 // CHECK3: omp.loop.exit:
1562 // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1563 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
1564 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
1565 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1566 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
1567 // CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1568 // CHECK3: .omp.final.then:
1569 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1570 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1571 // CHECK3: .omp.final.done:
1572 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1573 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1574 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
1575 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1576 // CHECK3: arraydestroy.body:
1577 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1578 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1579 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1580 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1581 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1582 // CHECK3: arraydestroy.done7:
1583 // CHECK3-NEXT: ret void
1584 //
1585 //
1586 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1587 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1588 // CHECK3-NEXT: entry:
1589 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1590 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1591 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1592 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1593 // CHECK3-NEXT: ret void
1594 //
1595 //
1596 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1597 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1598 // CHECK3-NEXT: entry:
1599 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1600 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1601 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1602 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1603 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1604 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1605 // CHECK3-NEXT: ret void
1606 //
1607 //
1608 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1609 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1610 // CHECK3-NEXT: entry:
1611 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1612 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1613 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1614 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1615 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1616 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1617 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1618 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1619 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1620 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1621 // CHECK3-NEXT: ret void
1622 //
1623 //
1624 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1625 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1626 // CHECK3-NEXT: entry:
1627 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1628 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1629 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1630 // CHECK3-NEXT: ret void
1631 //
1632 //
1633 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
1634 // CHECK3-SAME: () #[[ATTR0]] {
1635 // CHECK3-NEXT: entry:
1636 // CHECK3-NEXT: call void @__cxx_global_var_init()
1637 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
1638 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
1639 // CHECK3-NEXT: ret void
1640 //
1641 //
1642 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1643 // CHECK3-SAME: () #[[ATTR0]] {
1644 // CHECK3-NEXT: entry:
1645 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1646 // CHECK3-NEXT: ret void
1647 //
1648 //
1649 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
1650 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1651 // CHECK5-NEXT: entry:
1652 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1653 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1654 // CHECK5-NEXT: ret void
1655 //
1656 //
1657 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1658 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1659 // CHECK5-NEXT: entry:
1660 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1661 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1662 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1663 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1664 // CHECK5-NEXT: ret void
1665 //
1666 //
1667 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1668 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1669 // CHECK5-NEXT: entry:
1670 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1671 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1672 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1673 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1674 // CHECK5-NEXT: ret void
1675 //
1676 //
1677 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1678 // CHECK5-SAME: () #[[ATTR0]] {
1679 // CHECK5-NEXT: entry:
1680 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
1681 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
1682 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1683 // CHECK5-NEXT: ret void
1684 //
1685 //
1686 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1687 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1688 // CHECK5-NEXT: entry:
1689 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1690 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1691 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1692 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1693 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1694 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1695 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1696 // CHECK5-NEXT: ret void
1697 //
1698 //
1699 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1700 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1701 // CHECK5-NEXT: entry:
1702 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1703 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1704 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1705 // CHECK5: arraydestroy.body:
1706 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1707 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1708 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1709 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1710 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1711 // CHECK5: arraydestroy.done1:
1712 // CHECK5-NEXT: ret void
1713 //
1714 //
1715 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1716 // CHECK5-SAME: () #[[ATTR0]] {
1717 // CHECK5-NEXT: entry:
1718 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1719 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1720 // CHECK5-NEXT: ret void
1721 //
1722 //
1723 // CHECK5-LABEL: define {{[^@]+}}@main
1724 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1725 // CHECK5-NEXT: entry:
1726 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1727 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1728 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1729 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1730 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1731 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1732 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1733 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1734 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1735 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1736 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1737 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1738 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1739 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1740 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1741 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1742 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1743 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1744 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1745 // CHECK5: arrayctor.loop:
1746 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1747 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1748 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1749 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1750 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1751 // CHECK5: arrayctor.cont:
1752 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1753 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1754 // CHECK5: omp.inner.for.cond:
1755 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1756 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
1757 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1758 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1759 // CHECK5: omp.inner.for.cond.cleanup:
1760 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1761 // CHECK5: omp.inner.for.body:
1762 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1763 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1764 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1765 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
1766 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
1767 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1768 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1769 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1770 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
1771 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1772 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
1773 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
1774 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1775 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1776 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
1777 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1778 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
1779 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
1780 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
1781 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1782 // CHECK5: omp.body.continue:
1783 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1784 // CHECK5: omp.inner.for.inc:
1785 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1786 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
1787 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1788 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1789 // CHECK5: omp.inner.for.end:
1790 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1791 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1792 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1793 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
1794 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1795 // CHECK5: arraydestroy.body:
1796 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1797 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1798 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1799 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1800 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1801 // CHECK5: arraydestroy.done6:
1802 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1803 // CHECK5-NEXT: ret i32 [[CALL]]
1804 //
1805 //
1806 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1807 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1808 // CHECK5-NEXT: entry:
1809 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1810 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1811 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1812 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1813 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1814 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1815 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1816 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1817 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1818 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1819 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1820 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1821 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1822 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1823 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1824 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1825 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
1826 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1827 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
1828 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1829 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1830 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1831 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1832 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1833 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1834 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1835 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1836 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1837 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1838 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1839 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1840 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1841 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1842 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1843 // CHECK5: arrayctor.loop:
1844 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1845 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1846 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1847 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1848 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1849 // CHECK5: arrayctor.cont:
1850 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1851 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
1852 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1853 // CHECK5: omp.inner.for.cond:
1854 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1855 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
1856 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1857 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1858 // CHECK5: omp.inner.for.cond.cleanup:
1859 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1860 // CHECK5: omp.inner.for.body:
1861 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1862 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1863 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1864 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
1865 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
1866 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1867 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1868 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
1869 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
1870 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
1871 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1872 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
1873 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
1874 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
1875 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
1876 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
1877 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1878 // CHECK5: omp.body.continue:
1879 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1880 // CHECK5: omp.inner.for.inc:
1881 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1882 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
1883 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1884 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1885 // CHECK5: omp.inner.for.end:
1886 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1887 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1888 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1889 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
1890 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1891 // CHECK5: arraydestroy.body:
1892 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1893 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1894 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1895 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1896 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1897 // CHECK5: arraydestroy.done11:
1898 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1899 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1900 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
1901 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
1902 // CHECK5: arraydestroy.body13:
1903 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1904 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1905 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
1906 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1907 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1908 // CHECK5: arraydestroy.done17:
1909 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1910 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
1911 // CHECK5-NEXT: ret i32 [[TMP14]]
1912 //
1913 //
1914 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1915 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1916 // CHECK5-NEXT: entry:
1917 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1918 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1919 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1920 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1921 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1922 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1923 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
1924 // CHECK5-NEXT: ret void
1925 //
1926 //
1927 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1928 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1929 // CHECK5-NEXT: entry:
1930 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1931 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1932 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1933 // CHECK5-NEXT: ret void
1934 //
1935 //
1936 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1937 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1938 // CHECK5-NEXT: entry:
1939 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1940 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1941 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1942 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1943 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1944 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1945 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1946 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1947 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1948 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1949 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
1950 // CHECK5-NEXT: ret void
1951 //
1952 //
1953 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1954 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1955 // CHECK5-NEXT: entry:
1956 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1957 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1958 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1959 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1960 // CHECK5-NEXT: ret void
1961 //
1962 //
1963 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1964 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1965 // CHECK5-NEXT: entry:
1966 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1967 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1968 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1969 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1970 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1971 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1972 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1973 // CHECK5-NEXT: ret void
1974 //
1975 //
1976 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1977 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1978 // CHECK5-NEXT: entry:
1979 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1980 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1981 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1982 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1983 // CHECK5-NEXT: ret void
1984 //
1985 //
1986 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1987 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1988 // CHECK5-NEXT: entry:
1989 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1990 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1991 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1992 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1993 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1994 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1995 // CHECK5-NEXT: ret void
1996 //
1997 //
1998 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1999 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2000 // CHECK5-NEXT: entry:
2001 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2002 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2003 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2004 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2005 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2006 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2007 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2008 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2009 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2010 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2011 // CHECK5-NEXT: ret void
2012 //
2013 //
2014 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2015 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2016 // CHECK5-NEXT: entry:
2017 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2018 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2019 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2020 // CHECK5-NEXT: ret void
2021 //
2022 //
2023 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2024 // CHECK5-SAME: () #[[ATTR0]] {
2025 // CHECK5-NEXT: entry:
2026 // CHECK5-NEXT: call void @__cxx_global_var_init()
2027 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
2028 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
2029 // CHECK5-NEXT: ret void
2030 //
2031 //
2032 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
2033 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
2034 // CHECK7-NEXT: entry:
2035 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2036 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2037 // CHECK7-NEXT: ret void
2038 //
2039 //
2040 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2041 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2042 // CHECK7-NEXT: entry:
2043 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2044 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2045 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2046 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2047 // CHECK7-NEXT: ret void
2048 //
2049 //
2050 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2051 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2052 // CHECK7-NEXT: entry:
2053 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2054 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2055 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2056 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2057 // CHECK7-NEXT: ret void
2058 //
2059 //
2060 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2061 // CHECK7-SAME: () #[[ATTR0]] {
2062 // CHECK7-NEXT: entry:
2063 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
2064 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
2065 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2066 // CHECK7-NEXT: ret void
2067 //
2068 //
2069 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2070 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2071 // CHECK7-NEXT: entry:
2072 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2073 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2074 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2075 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2076 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2077 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2078 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2079 // CHECK7-NEXT: ret void
2080 //
2081 //
2082 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2083 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2084 // CHECK7-NEXT: entry:
2085 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2086 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2087 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2088 // CHECK7: arraydestroy.body:
2089 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2090 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2091 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2092 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2093 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2094 // CHECK7: arraydestroy.done1:
2095 // CHECK7-NEXT: ret void
2096 //
2097 //
2098 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2099 // CHECK7-SAME: () #[[ATTR0]] {
2100 // CHECK7-NEXT: entry:
2101 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2102 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2103 // CHECK7-NEXT: ret void
2104 //
2105 //
2106 // CHECK7-LABEL: define {{[^@]+}}@main
2107 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
2108 // CHECK7-NEXT: entry:
2109 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2110 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
2111 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2112 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2113 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2114 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2115 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2116 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2117 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2118 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2119 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2120 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
2121 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2122 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2123 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2124 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2125 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2126 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2127 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2128 // CHECK7: arrayctor.loop:
2129 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2130 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2131 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2132 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2133 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2134 // CHECK7: arrayctor.cont:
2135 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
2136 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2137 // CHECK7: omp.inner.for.cond:
2138 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
2139 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
2140 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2141 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2142 // CHECK7: omp.inner.for.cond.cleanup:
2143 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2144 // CHECK7: omp.inner.for.body:
2145 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
2146 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2147 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2148 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
2149 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
2150 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
2151 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
2152 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
2153 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
2154 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
2155 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
2156 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
2157 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
2158 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
2159 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
2160 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2161 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
2162 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2163 // CHECK7: omp.body.continue:
2164 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2165 // CHECK7: omp.inner.for.inc:
2166 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
2167 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
2168 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
2169 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2170 // CHECK7: omp.inner.for.end:
2171 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
2172 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2173 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2174 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
2175 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2176 // CHECK7: arraydestroy.body:
2177 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2178 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2179 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2180 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2181 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2182 // CHECK7: arraydestroy.done5:
2183 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
2184 // CHECK7-NEXT: ret i32 [[CALL]]
2185 //
2186 //
2187 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2188 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
2189 // CHECK7-NEXT: entry:
2190 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2191 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2192 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2193 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2194 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2195 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2196 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
2197 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2198 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2199 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2200 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2201 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2202 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2203 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2204 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2205 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
2206 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
2207 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
2208 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
2209 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2210 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2211 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2212 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
2213 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2214 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2215 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2216 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2217 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2218 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2219 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2220 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
2221 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2222 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2223 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2224 // CHECK7: arrayctor.loop:
2225 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2226 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2227 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2228 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2229 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2230 // CHECK7: arrayctor.cont:
2231 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2232 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
2233 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2234 // CHECK7: omp.inner.for.cond:
2235 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
2236 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
2237 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2238 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2239 // CHECK7: omp.inner.for.cond.cleanup:
2240 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2241 // CHECK7: omp.inner.for.body:
2242 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
2243 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
2244 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2245 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
2246 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
2247 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
2248 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
2249 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
2250 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
2251 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
2252 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
2253 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
2254 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
2255 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
2256 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2257 // CHECK7: omp.body.continue:
2258 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2259 // CHECK7: omp.inner.for.inc:
2260 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
2261 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
2262 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
2263 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
2264 // CHECK7: omp.inner.for.end:
2265 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
2266 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2267 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2268 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
2269 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2270 // CHECK7: arraydestroy.body:
2271 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2272 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2273 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2274 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
2275 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
2276 // CHECK7: arraydestroy.done10:
2277 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
2278 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2279 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
2280 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
2281 // CHECK7: arraydestroy.body12:
2282 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
2283 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
2284 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
2285 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
2286 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
2287 // CHECK7: arraydestroy.done16:
2288 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2289 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
2290 // CHECK7-NEXT: ret i32 [[TMP14]]
2291 //
2292 //
2293 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2294 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2295 // CHECK7-NEXT: entry:
2296 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2297 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2298 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2299 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2300 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2301 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2302 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
2303 // CHECK7-NEXT: ret void
2304 //
2305 //
2306 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2307 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2308 // CHECK7-NEXT: entry:
2309 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2310 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2311 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2312 // CHECK7-NEXT: ret void
2313 //
2314 //
2315 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2316 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2317 // CHECK7-NEXT: entry:
2318 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2319 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2320 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2321 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2322 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2323 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2324 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2325 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2326 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2327 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2328 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
2329 // CHECK7-NEXT: ret void
2330 //
2331 //
2332 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2333 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2334 // CHECK7-NEXT: entry:
2335 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2336 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2337 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2338 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2339 // CHECK7-NEXT: ret void
2340 //
2341 //
2342 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2343 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2344 // CHECK7-NEXT: entry:
2345 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2346 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2347 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2348 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2349 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2350 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2351 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2352 // CHECK7-NEXT: ret void
2353 //
2354 //
2355 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2356 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2357 // CHECK7-NEXT: entry:
2358 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2359 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2360 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2361 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2362 // CHECK7-NEXT: ret void
2363 //
2364 //
2365 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2366 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2367 // CHECK7-NEXT: entry:
2368 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2369 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2370 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2371 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2372 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2373 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2374 // CHECK7-NEXT: ret void
2375 //
2376 //
2377 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2378 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2379 // CHECK7-NEXT: entry:
2380 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2381 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2382 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2383 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2384 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2385 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2386 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2387 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2388 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2389 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2390 // CHECK7-NEXT: ret void
2391 //
2392 //
2393 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2394 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2395 // CHECK7-NEXT: entry:
2396 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2397 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2398 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2399 // CHECK7-NEXT: ret void
2400 //
2401 //
2402 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2403 // CHECK7-SAME: () #[[ATTR0]] {
2404 // CHECK7-NEXT: entry:
2405 // CHECK7-NEXT: call void @__cxx_global_var_init()
2406 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
2407 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
2408 // CHECK7-NEXT: ret void
2409 //
2410 //
2411 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
2412 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
2413 // CHECK9-NEXT: entry:
2414 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2415 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2416 // CHECK9-NEXT: ret void
2417 //
2418 //
2419 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2420 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2421 // CHECK9-NEXT: entry:
2422 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2423 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2424 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2425 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2426 // CHECK9-NEXT: ret void
2427 //
2428 //
2429 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2430 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2431 // CHECK9-NEXT: entry:
2432 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2433 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2434 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2435 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2436 // CHECK9-NEXT: ret void
2437 //
2438 //
2439 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2440 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2441 // CHECK9-NEXT: entry:
2442 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2443 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2444 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2445 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2446 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2447 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2448 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
2449 // CHECK9-NEXT: ret void
2450 //
2451 //
2452 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2453 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2454 // CHECK9-NEXT: entry:
2455 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2456 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2457 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2458 // CHECK9-NEXT: ret void
2459 //
2460 //
2461 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2462 // CHECK9-SAME: () #[[ATTR0]] {
2463 // CHECK9-NEXT: entry:
2464 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2465 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2466 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2467 // CHECK9-NEXT: ret void
2468 //
2469 //
2470 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2471 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2472 // CHECK9-NEXT: entry:
2473 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2474 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2475 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2476 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2477 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2478 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2479 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2480 // CHECK9-NEXT: ret void
2481 //
2482 //
2483 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2484 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2485 // CHECK9-NEXT: entry:
2486 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2487 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2488 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2489 // CHECK9: arraydestroy.body:
2490 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2491 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2492 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2493 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2494 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2495 // CHECK9: arraydestroy.done1:
2496 // CHECK9-NEXT: ret void
2497 //
2498 //
2499 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2500 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2501 // CHECK9-NEXT: entry:
2502 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2503 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2504 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2505 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2506 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2507 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2508 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2509 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2510 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2511 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2512 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
2513 // CHECK9-NEXT: ret void
2514 //
2515 //
2516 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2517 // CHECK9-SAME: () #[[ATTR0]] {
2518 // CHECK9-NEXT: entry:
2519 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2520 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2521 // CHECK9-NEXT: ret void
2522 //
2523 //
2524 // CHECK9-LABEL: define {{[^@]+}}@main
2525 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2526 // CHECK9-NEXT: entry:
2527 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2528 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2529 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
2530 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2531 // CHECK9-NEXT: ret i32 0
2532 //
2533 //
2534 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
2535 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
2536 // CHECK9-NEXT: entry:
2537 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2538 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2539 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
2540 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2541 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
2542 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2543 // CHECK9-NEXT: ret void
2544 //
2545 //
2546 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
2547 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
2548 // CHECK9-NEXT: entry:
2549 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2550 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2551 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2552 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
2553 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
2554 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2555 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2556 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2557 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2558 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
2559 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
2560 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
2561 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2562 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2563 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2564 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2565 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
2566 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2567 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2568 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2569 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2570 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
2571 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2572 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2573 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2574 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2575 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2576 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2577 // CHECK9: cond.true:
2578 // CHECK9-NEXT: br label [[COND_END:%.*]]
2579 // CHECK9: cond.false:
2580 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2581 // CHECK9-NEXT: br label [[COND_END]]
2582 // CHECK9: cond.end:
2583 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2584 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2585 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2586 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2587 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2588 // CHECK9: omp.inner.for.cond:
2589 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2590 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
2591 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2592 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2593 // CHECK9: omp.inner.for.body:
2594 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
2595 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2596 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
2597 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2598 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4
2599 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2600 // CHECK9: omp.inner.for.inc:
2601 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2602 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
2603 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2604 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2605 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2606 // CHECK9: omp.inner.for.end:
2607 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2608 // CHECK9: omp.loop.exit:
2609 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2610 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2611 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2612 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2613 // CHECK9: .omp.final.then:
2614 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
2615 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
2616 // CHECK9: .omp.final.done:
2617 // CHECK9-NEXT: ret void
2618 //
2619 //
2620 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
2621 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
2622 // CHECK9-NEXT: entry:
2623 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2624 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2625 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2626 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2627 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2628 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
2629 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
2630 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2631 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2632 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2633 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2634 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
2635 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
2636 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
2637 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2638 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2639 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2640 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2641 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2642 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2643 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2644 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
2645 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2646 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2647 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2648 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2649 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2650 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
2651 // CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2652 // CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
2653 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2654 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2655 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8
2656 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2657 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2658 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2659 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2660 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2661 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2662 // CHECK9: cond.true:
2663 // CHECK9-NEXT: br label [[COND_END:%.*]]
2664 // CHECK9: cond.false:
2665 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2666 // CHECK9-NEXT: br label [[COND_END]]
2667 // CHECK9: cond.end:
2668 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2669 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2670 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2671 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2672 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2673 // CHECK9: omp.inner.for.cond:
2674 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2675 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
2676 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2677 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2678 // CHECK9: omp.inner.for.body:
2679 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2680 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2681 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2682 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
2683 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !8
2684 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8
2685 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
2686 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !8
2687 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
2688 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8, !llvm.access.group !8
2689 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
2690 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8
2691 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
2692 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
2693 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8
2694 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
2695 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2696 // CHECK9: omp.body.continue:
2697 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2698 // CHECK9: omp.inner.for.inc:
2699 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2700 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
2701 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
2702 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2703 // CHECK9: omp.inner.for.end:
2704 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2705 // CHECK9: omp.loop.exit:
2706 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2707 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2708 // CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
2709 // CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2710 // CHECK9: .omp.final.then:
2711 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
2712 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
2713 // CHECK9: .omp.final.done:
2714 // CHECK9-NEXT: ret void
2715 //
2716 //
2717 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2718 // CHECK9-SAME: () #[[ATTR0]] {
2719 // CHECK9-NEXT: entry:
2720 // CHECK9-NEXT: call void @__cxx_global_var_init()
2721 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
2722 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
2723 // CHECK9-NEXT: ret void
2724 //
2725 //
2726 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2727 // CHECK9-SAME: () #[[ATTR0]] {
2728 // CHECK9-NEXT: entry:
2729 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
2730 // CHECK9-NEXT: ret void
2731 //
2732 //
2733 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
2734 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2735 // CHECK11-NEXT: entry:
2736 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2737 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2738 // CHECK11-NEXT: ret void
2739 //
2740 //
2741 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2742 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2743 // CHECK11-NEXT: entry:
2744 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2745 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2746 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2747 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2748 // CHECK11-NEXT: ret void
2749 //
2750 //
2751 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2752 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2753 // CHECK11-NEXT: entry:
2754 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2755 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2756 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2757 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2758 // CHECK11-NEXT: ret void
2759 //
2760 //
2761 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2762 // CHECK11-SAME: () #[[ATTR0]] {
2763 // CHECK11-NEXT: entry:
2764 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2765 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2766 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2767 // CHECK11-NEXT: ret void
2768 //
2769 //
2770 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2771 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2772 // CHECK11-NEXT: entry:
2773 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2774 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2775 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2776 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2777 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2778 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2779 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2780 // CHECK11-NEXT: ret void
2781 //
2782 //
2783 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2784 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2785 // CHECK11-NEXT: entry:
2786 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2787 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2788 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2789 // CHECK11: arraydestroy.body:
2790 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2791 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2792 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2793 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2794 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2795 // CHECK11: arraydestroy.done1:
2796 // CHECK11-NEXT: ret void
2797 //
2798 //
2799 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2800 // CHECK11-SAME: () #[[ATTR0]] {
2801 // CHECK11-NEXT: entry:
2802 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2803 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2804 // CHECK11-NEXT: ret void
2805 //
2806 //
2807 // CHECK11-LABEL: define {{[^@]+}}@main
2808 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
2809 // CHECK11-NEXT: entry:
2810 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2811 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2812 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
2813 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2814 // CHECK11-NEXT: ret i32 0
2815 //
2816 //
2817 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2818 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2819 // CHECK11-NEXT: entry:
2820 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2821 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2822 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2823 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2824 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2825 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2826 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
2827 // CHECK11-NEXT: ret void
2828 //
2829 //
2830 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2831 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2832 // CHECK11-NEXT: entry:
2833 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2834 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2835 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2836 // CHECK11-NEXT: ret void
2837 //
2838 //
2839 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2840 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2841 // CHECK11-NEXT: entry:
2842 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2843 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2844 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2845 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2846 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2847 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2848 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2849 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2850 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2851 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2852 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
2853 // CHECK11-NEXT: ret void
2854 //
2855 //
2856 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2857 // CHECK11-SAME: () #[[ATTR0]] {
2858 // CHECK11-NEXT: entry:
2859 // CHECK11-NEXT: call void @__cxx_global_var_init()
2860 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
2861 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
2862 // CHECK11-NEXT: ret void
2863 //
2864