1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5
6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
9
10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5
11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
13
14 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3
15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
16 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
17
18 // expected-no-diagnostics
19 #ifndef HEADER
20 #define HEADER
21
22 typedef __INTPTR_TYPE__ intptr_t;
23
24
25 void foo();
26
27 struct S {
28 intptr_t a, b, c;
SS29 S(intptr_t a) : a(a) {}
operator charS30 operator char() { return a; }
~SS31 ~S() {}
32 };
33
34 template <typename T, int C>
tmain()35 int tmain() {
36 #pragma omp target
37 #pragma omp teams distribute parallel for simd num_threads(C)
38 for (int i = 0; i < 100; i++)
39 foo();
40 #pragma omp target
41 #pragma omp teams distribute parallel for simd num_threads(T(23))
42 for (int i = 0; i < 100; i++)
43 foo();
44 return 0;
45 }
46
main()47 int main() {
48 S s(0);
49 char a = s;
50 #pragma omp target
51 #pragma omp teams distribute parallel for simd num_threads(2)
52 for (int i = 0; i < 100; i++) {
53 foo();
54 }
55 #pragma omp target
56
57 #pragma omp teams distribute parallel for simd num_threads(a)
58 for (int i = 0; i < 100; i++) {
59 foo();
60 }
61 return a + tmain<char, 5>() + tmain<S, 1>();
62 }
63
64 // tmain 5
65
66 // tmain 1
67
68
69
70
71
72
73
74
75
76
77 #endif
78 // CHECK1-LABEL: define {{[^@]+}}@main
79 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
80 // CHECK1-NEXT: entry:
81 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
82 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8
83 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1
84 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8
85 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
86 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
87 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
88 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
89 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
90 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
91 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
92 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
93 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
94 // CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0)
95 // CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]])
96 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
97 // CHECK1: invoke.cont:
98 // CHECK1-NEXT: store i8 [[CALL]], i8* [[A]], align 1
99 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
100 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
101 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
102 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
103 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
104 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
105 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
106 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
107 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
108 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
109 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
110 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
111 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
112 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
113 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
114 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
115 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
116 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
117 // CHECK1-NEXT: store i64 100, i64* [[TMP8]], align 8
118 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
119 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
120 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
121 // CHECK1: omp_offload.failed:
122 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]]
123 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
124 // CHECK1: lpad:
125 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
126 // CHECK1-NEXT: cleanup
127 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
128 // CHECK1-NEXT: store i8* [[TMP12]], i8** [[EXN_SLOT]], align 8
129 // CHECK1-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 1
130 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[EHSELECTOR_SLOT]], align 4
131 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
132 // CHECK1-NEXT: br label [[EH_RESUME:%.*]]
133 // CHECK1: omp_offload.cont:
134 // CHECK1-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1
135 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8*
136 // CHECK1-NEXT: store i8 [[TMP14]], i8* [[CONV]], align 1
137 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[A_CASTED]], align 8
138 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
139 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
140 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
141 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
142 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
143 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
144 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
145 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8
146 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
147 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
148 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[A]], align 1
149 // CHECK1-NEXT: store i8 [[TMP23]], i8* [[DOTCAPTURE_EXPR_]], align 1
150 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
151 // CHECK1-NEXT: [[TMP25:%.*]] = zext i8 [[TMP24]] to i32
152 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
153 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
154 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4
155 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
156 // CHECK1-NEXT: store i32 1, i32* [[TMP27]], align 4
157 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
158 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 8
159 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
160 // CHECK1-NEXT: store i8** [[TMP22]], i8*** [[TMP29]], align 8
161 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
162 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 8
163 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
164 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8
165 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
166 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8
167 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
168 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8
169 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
170 // CHECK1-NEXT: store i64 100, i64* [[TMP34]], align 8
171 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP25]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
172 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
173 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
174 // CHECK1: omp_offload.failed3:
175 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR6]]
176 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
177 // CHECK1: omp_offload.cont4:
178 // CHECK1-NEXT: [[TMP37:%.*]] = load i8, i8* [[A]], align 1
179 // CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP37]] to i32
180 // CHECK1-NEXT: [[CALL7:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv()
181 // CHECK1-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[LPAD]]
182 // CHECK1: invoke.cont6:
183 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV5]], [[CALL7]]
184 // CHECK1-NEXT: [[CALL9:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv()
185 // CHECK1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD]]
186 // CHECK1: invoke.cont8:
187 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD]], [[CALL9]]
188 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[RETVAL]], align 4
189 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
190 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[RETVAL]], align 4
191 // CHECK1-NEXT: ret i32 [[TMP38]]
192 // CHECK1: eh.resume:
193 // CHECK1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8
194 // CHECK1-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4
195 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0
196 // CHECK1-NEXT: [[LPAD_VAL11:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
197 // CHECK1-NEXT: resume { i8*, i32 } [[LPAD_VAL11]]
198 //
199 //
200 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El
201 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
202 // CHECK1-NEXT: entry:
203 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
204 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
205 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
206 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
207 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
208 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
209 // CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
210 // CHECK1-NEXT: ret void
211 //
212 //
213 // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv
214 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
215 // CHECK1-NEXT: entry:
216 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
217 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
218 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
219 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
220 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8
221 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
222 // CHECK1-NEXT: ret i8 [[CONV]]
223 //
224 //
225 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50
226 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
227 // CHECK1-NEXT: entry:
228 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
229 // CHECK1-NEXT: ret void
230 //
231 //
232 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
233 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
234 // CHECK1-NEXT: entry:
235 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
236 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
237 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
238 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
241 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
242 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
243 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
244 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
245 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
246 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
247 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
248 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
249 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
250 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
251 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
252 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
253 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
254 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
255 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
256 // CHECK1: cond.true:
257 // CHECK1-NEXT: br label [[COND_END:%.*]]
258 // CHECK1: cond.false:
259 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
260 // CHECK1-NEXT: br label [[COND_END]]
261 // CHECK1: cond.end:
262 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
263 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
264 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
265 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
266 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
267 // CHECK1: omp.inner.for.cond:
268 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
269 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
270 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
271 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
272 // CHECK1: omp.inner.for.body:
273 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9
274 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
275 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
276 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
277 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
278 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9
279 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
280 // CHECK1: omp.inner.for.inc:
281 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
282 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
283 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
284 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
285 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
286 // CHECK1: omp.inner.for.end:
287 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
288 // CHECK1: omp.loop.exit:
289 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
290 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
291 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
292 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
293 // CHECK1: .omp.final.then:
294 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
295 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
296 // CHECK1: .omp.final.done:
297 // CHECK1-NEXT: ret void
298 //
299 //
300 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
301 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
302 // CHECK1-NEXT: entry:
303 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
304 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
305 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
306 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
307 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
308 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
309 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
310 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
311 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
312 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
313 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
314 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
315 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
316 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
317 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
318 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
319 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
320 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
321 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
322 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
323 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
324 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
325 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
326 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
327 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
328 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
329 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
330 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
331 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
332 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
333 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
334 // CHECK1: cond.true:
335 // CHECK1-NEXT: br label [[COND_END:%.*]]
336 // CHECK1: cond.false:
337 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
338 // CHECK1-NEXT: br label [[COND_END]]
339 // CHECK1: cond.end:
340 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
341 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
342 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
343 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
344 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
345 // CHECK1: omp.inner.for.cond:
346 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
347 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
348 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
349 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
350 // CHECK1: omp.inner.for.body:
351 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
352 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
353 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
354 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
355 // CHECK1-NEXT: invoke void @_Z3foov()
356 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13
357 // CHECK1: invoke.cont:
358 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
359 // CHECK1: omp.body.continue:
360 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
361 // CHECK1: omp.inner.for.inc:
362 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
363 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
364 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
365 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
366 // CHECK1: omp.inner.for.end:
367 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
368 // CHECK1: omp.loop.exit:
369 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
370 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
371 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
372 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
373 // CHECK1: .omp.final.then:
374 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
375 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
376 // CHECK1: .omp.final.done:
377 // CHECK1-NEXT: ret void
378 // CHECK1: terminate.lpad:
379 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
380 // CHECK1-NEXT: catch i8* null
381 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
382 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group !13
383 // CHECK1-NEXT: unreachable
384 //
385 //
386 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate
387 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
388 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
389 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR9]]
390 // CHECK1-NEXT: unreachable
391 //
392 //
393 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
394 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
395 // CHECK1-NEXT: entry:
396 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
397 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
398 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
399 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
400 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
401 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
402 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
403 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
404 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
405 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
406 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
407 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
408 // CHECK1-NEXT: ret void
409 //
410 //
411 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
412 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
413 // CHECK1-NEXT: entry:
414 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
415 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
416 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
417 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
418 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
419 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
420 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
421 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
422 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
423 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
424 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
425 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
426 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
427 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
428 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
429 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
430 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
431 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
432 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
433 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
434 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
435 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
436 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
437 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
438 // CHECK1: cond.true:
439 // CHECK1-NEXT: br label [[COND_END:%.*]]
440 // CHECK1: cond.false:
441 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
442 // CHECK1-NEXT: br label [[COND_END]]
443 // CHECK1: cond.end:
444 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
445 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
446 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
447 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
448 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
449 // CHECK1: omp.inner.for.cond:
450 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
451 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
452 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
453 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
454 // CHECK1: omp.inner.for.body:
455 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
456 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
457 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
458 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
459 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
460 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
461 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
462 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
463 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
464 // CHECK1: omp.inner.for.inc:
465 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
466 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
467 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
468 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
470 // CHECK1: omp.inner.for.end:
471 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
472 // CHECK1: omp.loop.exit:
473 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
474 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
475 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
476 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
477 // CHECK1: .omp.final.then:
478 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
479 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
480 // CHECK1: .omp.final.done:
481 // CHECK1-NEXT: ret void
482 //
483 //
484 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
485 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
486 // CHECK1-NEXT: entry:
487 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
488 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
489 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
490 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
491 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
492 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
493 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
494 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
495 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
496 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
497 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
498 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
499 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
500 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
501 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
502 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
503 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
504 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
505 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
506 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
507 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
508 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
509 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
510 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
511 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
512 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
513 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
514 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
515 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
516 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
517 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
518 // CHECK1: cond.true:
519 // CHECK1-NEXT: br label [[COND_END:%.*]]
520 // CHECK1: cond.false:
521 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
522 // CHECK1-NEXT: br label [[COND_END]]
523 // CHECK1: cond.end:
524 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
525 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
526 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
527 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
528 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
529 // CHECK1: omp.inner.for.cond:
530 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
531 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
532 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
533 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
534 // CHECK1: omp.inner.for.body:
535 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
536 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
537 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
538 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
539 // CHECK1-NEXT: invoke void @_Z3foov()
540 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21
541 // CHECK1: invoke.cont:
542 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
543 // CHECK1: omp.body.continue:
544 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
545 // CHECK1: omp.inner.for.inc:
546 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
547 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
548 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
549 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
550 // CHECK1: omp.inner.for.end:
551 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
552 // CHECK1: omp.loop.exit:
553 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
554 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
555 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
556 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
557 // CHECK1: .omp.final.then:
558 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
559 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
560 // CHECK1: .omp.final.done:
561 // CHECK1-NEXT: ret void
562 // CHECK1: terminate.lpad:
563 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
564 // CHECK1-NEXT: catch i8* null
565 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
566 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !21
567 // CHECK1-NEXT: unreachable
568 //
569 //
570 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
571 // CHECK1-SAME: () #[[ATTR2]] comdat {
572 // CHECK1-NEXT: entry:
573 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
574 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
575 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
576 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
577 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
578 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
579 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
580 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
581 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
582 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
583 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
584 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
585 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
586 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
587 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
588 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
589 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
590 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
591 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
592 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
593 // CHECK1-NEXT: store i64 100, i64* [[TMP8]], align 8
594 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 5, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
595 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
596 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
597 // CHECK1: omp_offload.failed:
598 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]]
599 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
600 // CHECK1: omp_offload.cont:
601 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
602 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
603 // CHECK1-NEXT: store i32 1, i32* [[TMP11]], align 4
604 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
605 // CHECK1-NEXT: store i32 0, i32* [[TMP12]], align 4
606 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
607 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8
608 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
609 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8
610 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
611 // CHECK1-NEXT: store i64* null, i64** [[TMP15]], align 8
612 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
613 // CHECK1-NEXT: store i64* null, i64** [[TMP16]], align 8
614 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
615 // CHECK1-NEXT: store i8** null, i8*** [[TMP17]], align 8
616 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
617 // CHECK1-NEXT: store i8** null, i8*** [[TMP18]], align 8
618 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
619 // CHECK1-NEXT: store i64 100, i64* [[TMP19]], align 8
620 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 23, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
621 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
622 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
623 // CHECK1: omp_offload.failed3:
624 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]]
625 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
626 // CHECK1: omp_offload.cont4:
627 // CHECK1-NEXT: ret i32 0
628 //
629 //
630 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv
631 // CHECK1-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
632 // CHECK1-NEXT: entry:
633 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
634 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
635 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
636 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
637 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
638 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
639 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
640 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
641 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
642 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
643 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
644 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
645 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
646 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
647 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
648 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
649 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
650 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
651 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
652 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
653 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
654 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
655 // CHECK1-NEXT: store i64 100, i64* [[TMP8]], align 8
656 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
657 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
658 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
659 // CHECK1: omp_offload.failed:
660 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]]
661 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
662 // CHECK1: omp_offload.cont:
663 // CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
664 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
665 // CHECK1: invoke.cont:
666 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
667 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
668 // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
669 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
670 // CHECK1-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32
671 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
672 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
673 // CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4
674 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
675 // CHECK1-NEXT: store i32 0, i32* [[TMP14]], align 4
676 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
677 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8
678 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
679 // CHECK1-NEXT: store i8** null, i8*** [[TMP16]], align 8
680 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
681 // CHECK1-NEXT: store i64* null, i64** [[TMP17]], align 8
682 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
683 // CHECK1-NEXT: store i64* null, i64** [[TMP18]], align 8
684 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
685 // CHECK1-NEXT: store i8** null, i8*** [[TMP19]], align 8
686 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
687 // CHECK1-NEXT: store i8** null, i8*** [[TMP20]], align 8
688 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
689 // CHECK1-NEXT: store i64 100, i64* [[TMP21]], align 8
690 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
691 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
692 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
693 // CHECK1: omp_offload.failed3:
694 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]]
695 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
696 // CHECK1: omp_offload.cont4:
697 // CHECK1-NEXT: ret i32 0
698 // CHECK1: terminate.lpad:
699 // CHECK1-NEXT: [[TMP24:%.*]] = landingpad { i8*, i32 }
700 // CHECK1-NEXT: catch i8* null
701 // CHECK1-NEXT: [[TMP25:%.*]] = extractvalue { i8*, i32 } [[TMP24]], 0
702 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP25]]) #[[ATTR9]]
703 // CHECK1-NEXT: unreachable
704 //
705 //
706 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev
707 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 {
708 // CHECK1-NEXT: entry:
709 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
710 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
711 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
712 // CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
713 // CHECK1-NEXT: ret void
714 //
715 //
716 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El
717 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
718 // CHECK1-NEXT: entry:
719 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
720 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
721 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
722 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
723 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
724 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
725 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
726 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8
727 // CHECK1-NEXT: ret void
728 //
729 //
730 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev
731 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
732 // CHECK1-NEXT: entry:
733 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
734 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
735 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
736 // CHECK1-NEXT: ret void
737 //
738 //
739 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36
740 // CHECK1-SAME: () #[[ATTR3]] {
741 // CHECK1-NEXT: entry:
742 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
743 // CHECK1-NEXT: ret void
744 //
745 //
746 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
747 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
748 // CHECK1-NEXT: entry:
749 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
750 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
751 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
752 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
753 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
754 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
755 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
756 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
757 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
758 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
759 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
760 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
761 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
762 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
763 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
764 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
765 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
766 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
767 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
768 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
769 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
770 // CHECK1: cond.true:
771 // CHECK1-NEXT: br label [[COND_END:%.*]]
772 // CHECK1: cond.false:
773 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
774 // CHECK1-NEXT: br label [[COND_END]]
775 // CHECK1: cond.end:
776 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
777 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
778 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
779 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
780 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
781 // CHECK1: omp.inner.for.cond:
782 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
783 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
784 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
785 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
786 // CHECK1: omp.inner.for.body:
787 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24
788 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
789 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
790 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
791 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
792 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
793 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
794 // CHECK1: omp.inner.for.inc:
795 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
796 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
797 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
798 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
799 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
800 // CHECK1: omp.inner.for.end:
801 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
802 // CHECK1: omp.loop.exit:
803 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
804 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
805 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
806 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
807 // CHECK1: .omp.final.then:
808 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
809 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
810 // CHECK1: .omp.final.done:
811 // CHECK1-NEXT: ret void
812 //
813 //
814 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
815 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
816 // CHECK1-NEXT: entry:
817 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
818 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
819 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
820 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
821 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
822 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
823 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
824 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
825 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
826 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
827 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
828 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
829 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
830 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
831 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
832 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
833 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
834 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
835 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
836 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
837 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
838 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
839 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
840 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
841 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
842 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
843 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
844 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
845 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
846 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
847 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
848 // CHECK1: cond.true:
849 // CHECK1-NEXT: br label [[COND_END:%.*]]
850 // CHECK1: cond.false:
851 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
852 // CHECK1-NEXT: br label [[COND_END]]
853 // CHECK1: cond.end:
854 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
855 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
856 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
857 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
858 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
859 // CHECK1: omp.inner.for.cond:
860 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
861 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
862 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
863 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
864 // CHECK1: omp.inner.for.body:
865 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
866 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
867 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
868 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
869 // CHECK1-NEXT: invoke void @_Z3foov()
870 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27
871 // CHECK1: invoke.cont:
872 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
873 // CHECK1: omp.body.continue:
874 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
875 // CHECK1: omp.inner.for.inc:
876 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
877 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
878 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
879 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
880 // CHECK1: omp.inner.for.end:
881 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
882 // CHECK1: omp.loop.exit:
883 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
884 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
885 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
886 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
887 // CHECK1: .omp.final.then:
888 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
889 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
890 // CHECK1: .omp.final.done:
891 // CHECK1-NEXT: ret void
892 // CHECK1: terminate.lpad:
893 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
894 // CHECK1-NEXT: catch i8* null
895 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
896 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !27
897 // CHECK1-NEXT: unreachable
898 //
899 //
900 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40
901 // CHECK1-SAME: () #[[ATTR3]] {
902 // CHECK1-NEXT: entry:
903 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*))
904 // CHECK1-NEXT: ret void
905 //
906 //
907 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
908 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
909 // CHECK1-NEXT: entry:
910 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
911 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
912 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
913 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
914 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
915 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
916 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
917 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
918 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
919 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
920 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
921 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
922 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
923 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
924 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
925 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
926 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
927 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
928 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
929 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
930 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
931 // CHECK1: cond.true:
932 // CHECK1-NEXT: br label [[COND_END:%.*]]
933 // CHECK1: cond.false:
934 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
935 // CHECK1-NEXT: br label [[COND_END]]
936 // CHECK1: cond.end:
937 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
938 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
939 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
940 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
941 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
942 // CHECK1: omp.inner.for.cond:
943 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
944 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
945 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
946 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
947 // CHECK1: omp.inner.for.body:
948 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30
949 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
950 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
951 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
952 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
953 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30
954 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
955 // CHECK1: omp.inner.for.inc:
956 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
957 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
958 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
959 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
960 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
961 // CHECK1: omp.inner.for.end:
962 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
963 // CHECK1: omp.loop.exit:
964 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
965 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
966 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
967 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
968 // CHECK1: .omp.final.then:
969 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
970 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
971 // CHECK1: .omp.final.done:
972 // CHECK1-NEXT: ret void
973 //
974 //
975 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
976 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
977 // CHECK1-NEXT: entry:
978 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
979 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
980 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
981 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
982 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
983 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
984 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
985 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
986 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
987 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
988 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
989 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
990 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
991 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
992 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
993 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
994 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
995 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
996 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
997 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
998 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
999 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1000 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1001 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1002 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1003 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1004 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1005 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1006 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1007 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1008 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1009 // CHECK1: cond.true:
1010 // CHECK1-NEXT: br label [[COND_END:%.*]]
1011 // CHECK1: cond.false:
1012 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1013 // CHECK1-NEXT: br label [[COND_END]]
1014 // CHECK1: cond.end:
1015 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1016 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1017 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1018 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1019 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1020 // CHECK1: omp.inner.for.cond:
1021 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
1022 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
1023 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1024 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1025 // CHECK1: omp.inner.for.body:
1026 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
1027 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1028 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1029 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
1030 // CHECK1-NEXT: invoke void @_Z3foov()
1031 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33
1032 // CHECK1: invoke.cont:
1033 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1034 // CHECK1: omp.body.continue:
1035 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1036 // CHECK1: omp.inner.for.inc:
1037 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
1038 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1039 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
1040 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
1041 // CHECK1: omp.inner.for.end:
1042 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1043 // CHECK1: omp.loop.exit:
1044 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1045 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1046 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1047 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1048 // CHECK1: .omp.final.then:
1049 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
1050 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1051 // CHECK1: .omp.final.done:
1052 // CHECK1-NEXT: ret void
1053 // CHECK1: terminate.lpad:
1054 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
1055 // CHECK1-NEXT: catch i8* null
1056 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
1057 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !33
1058 // CHECK1-NEXT: unreachable
1059 //
1060 //
1061 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36
1062 // CHECK1-SAME: () #[[ATTR3]] {
1063 // CHECK1-NEXT: entry:
1064 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*))
1065 // CHECK1-NEXT: ret void
1066 //
1067 //
1068 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8
1069 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
1070 // CHECK1-NEXT: entry:
1071 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1072 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1073 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1074 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1075 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1076 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1077 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1078 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1079 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1080 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1081 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1082 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1083 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1084 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1085 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1086 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1087 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1088 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1089 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1090 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1091 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1092 // CHECK1: cond.true:
1093 // CHECK1-NEXT: br label [[COND_END:%.*]]
1094 // CHECK1: cond.false:
1095 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1096 // CHECK1-NEXT: br label [[COND_END]]
1097 // CHECK1: cond.end:
1098 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1099 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1100 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1101 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1102 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1103 // CHECK1: omp.inner.for.cond:
1104 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
1105 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
1106 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1107 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1108 // CHECK1: omp.inner.for.body:
1109 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36
1110 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
1111 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1112 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
1113 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1114 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
1115 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1116 // CHECK1: omp.inner.for.inc:
1117 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
1118 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
1119 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1120 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
1121 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
1122 // CHECK1: omp.inner.for.end:
1123 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1124 // CHECK1: omp.loop.exit:
1125 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1126 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1127 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1128 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1129 // CHECK1: .omp.final.then:
1130 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
1131 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1132 // CHECK1: .omp.final.done:
1133 // CHECK1-NEXT: ret void
1134 //
1135 //
1136 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1137 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1138 // CHECK1-NEXT: entry:
1139 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1140 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1141 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1142 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1143 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1144 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1145 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1146 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1147 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1148 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1149 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1150 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1151 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1152 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1153 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1154 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1155 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1156 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1157 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1158 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1159 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1160 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1161 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1162 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1163 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1164 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1165 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1166 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1167 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1168 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1169 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1170 // CHECK1: cond.true:
1171 // CHECK1-NEXT: br label [[COND_END:%.*]]
1172 // CHECK1: cond.false:
1173 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1174 // CHECK1-NEXT: br label [[COND_END]]
1175 // CHECK1: cond.end:
1176 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1177 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1178 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1179 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1180 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1181 // CHECK1: omp.inner.for.cond:
1182 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
1183 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
1184 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1185 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1186 // CHECK1: omp.inner.for.body:
1187 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
1188 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1189 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1190 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
1191 // CHECK1-NEXT: invoke void @_Z3foov()
1192 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39
1193 // CHECK1: invoke.cont:
1194 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1195 // CHECK1: omp.body.continue:
1196 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1197 // CHECK1: omp.inner.for.inc:
1198 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
1199 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1200 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
1201 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
1202 // CHECK1: omp.inner.for.end:
1203 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1204 // CHECK1: omp.loop.exit:
1205 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1206 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1207 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1208 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1209 // CHECK1: .omp.final.then:
1210 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
1211 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1212 // CHECK1: .omp.final.done:
1213 // CHECK1-NEXT: ret void
1214 // CHECK1: terminate.lpad:
1215 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
1216 // CHECK1-NEXT: catch i8* null
1217 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
1218 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !39
1219 // CHECK1-NEXT: unreachable
1220 //
1221 //
1222 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40
1223 // CHECK1-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1224 // CHECK1-NEXT: entry:
1225 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1226 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1227 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1228 // CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
1229 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1230 // CHECK1: invoke.cont:
1231 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
1232 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
1233 // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1234 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1235 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
1236 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
1237 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1238 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]])
1239 // CHECK1-NEXT: ret void
1240 // CHECK1: terminate.lpad:
1241 // CHECK1-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 }
1242 // CHECK1-NEXT: catch i8* null
1243 // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0
1244 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP3]]) #[[ATTR9]]
1245 // CHECK1-NEXT: unreachable
1246 //
1247 //
1248 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
1249 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
1250 // CHECK1-NEXT: entry:
1251 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1252 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1253 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1254 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1255 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1256 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1257 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1258 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1259 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1260 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1261 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1262 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1263 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1264 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1265 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1266 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1267 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1268 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1269 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1270 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1271 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1272 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1273 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1274 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1275 // CHECK1: cond.true:
1276 // CHECK1-NEXT: br label [[COND_END:%.*]]
1277 // CHECK1: cond.false:
1278 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1279 // CHECK1-NEXT: br label [[COND_END]]
1280 // CHECK1: cond.end:
1281 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1282 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1283 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1284 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1285 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1286 // CHECK1: omp.inner.for.cond:
1287 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
1288 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
1289 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1290 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1291 // CHECK1: omp.inner.for.body:
1292 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
1293 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
1294 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
1295 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
1296 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1297 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
1298 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1299 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
1300 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1301 // CHECK1: omp.inner.for.inc:
1302 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
1303 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
1304 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
1305 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
1306 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
1307 // CHECK1: omp.inner.for.end:
1308 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1309 // CHECK1: omp.loop.exit:
1310 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1311 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1312 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
1313 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1314 // CHECK1: .omp.final.then:
1315 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
1316 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1317 // CHECK1: .omp.final.done:
1318 // CHECK1-NEXT: ret void
1319 //
1320 //
1321 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
1322 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1323 // CHECK1-NEXT: entry:
1324 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1325 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1326 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1327 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1328 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1329 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1330 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1331 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1332 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1333 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1334 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1335 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1336 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1337 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1338 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1339 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1340 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1341 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1342 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1343 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1344 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1345 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1346 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1347 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1348 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1349 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1350 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1351 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1352 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1353 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1354 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1355 // CHECK1: cond.true:
1356 // CHECK1-NEXT: br label [[COND_END:%.*]]
1357 // CHECK1: cond.false:
1358 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1359 // CHECK1-NEXT: br label [[COND_END]]
1360 // CHECK1: cond.end:
1361 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1362 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1363 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1364 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1365 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1366 // CHECK1: omp.inner.for.cond:
1367 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
1368 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
1369 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1370 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1371 // CHECK1: omp.inner.for.body:
1372 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
1373 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1374 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1375 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
1376 // CHECK1-NEXT: invoke void @_Z3foov()
1377 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45
1378 // CHECK1: invoke.cont:
1379 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1380 // CHECK1: omp.body.continue:
1381 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1382 // CHECK1: omp.inner.for.inc:
1383 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
1384 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1385 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
1386 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
1387 // CHECK1: omp.inner.for.end:
1388 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1389 // CHECK1: omp.loop.exit:
1390 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1391 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1392 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1393 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1394 // CHECK1: .omp.final.then:
1395 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
1396 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1397 // CHECK1: .omp.final.done:
1398 // CHECK1-NEXT: ret void
1399 // CHECK1: terminate.lpad:
1400 // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
1401 // CHECK1-NEXT: catch i8* null
1402 // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
1403 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !45
1404 // CHECK1-NEXT: unreachable
1405 //
1406 //
1407 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1408 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" {
1409 // CHECK1-NEXT: entry:
1410 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1411 // CHECK1-NEXT: ret void
1412 //
1413 //
1414 // CHECK3-LABEL: define {{[^@]+}}@main
1415 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1416 // CHECK3-NEXT: entry:
1417 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1418 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1419 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1
1420 // CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8
1421 // CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1422 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1423 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1424 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1425 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1426 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1427 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1428 // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
1429 // CHECK3-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
1430 // CHECK3-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
1431 // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
1432 // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4
1433 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1434 // CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0)
1435 // CHECK3-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]])
1436 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1437 // CHECK3: invoke.cont:
1438 // CHECK3-NEXT: store i8 [[CALL]], i8* [[A]], align 1
1439 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1440 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1441 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1442 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1443 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1444 // CHECK3: omp.inner.for.cond:
1445 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1446 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
1447 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1448 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1449 // CHECK3: omp.inner.for.body:
1450 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1451 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1452 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1453 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
1454 // CHECK3-NEXT: invoke void @_Z3foov()
1455 // CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !2
1456 // CHECK3: invoke.cont1:
1457 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1458 // CHECK3: omp.body.continue:
1459 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1460 // CHECK3: omp.inner.for.inc:
1461 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1462 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
1463 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1464 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1465 // CHECK3: lpad:
1466 // CHECK3-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 }
1467 // CHECK3-NEXT: cleanup
1468 // CHECK3-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0
1469 // CHECK3-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8
1470 // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1
1471 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4
1472 // CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]]
1473 // CHECK3-NEXT: br label [[EH_RESUME:%.*]]
1474 // CHECK3: omp.inner.for.end:
1475 // CHECK3-NEXT: store i32 100, i32* [[I]], align 4
1476 // CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1
1477 // CHECK3-NEXT: store i8 [[TMP8]], i8* [[DOTCAPTURE_EXPR_]], align 1
1478 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
1479 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB5]], align 4
1480 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
1481 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
1482 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
1483 // CHECK3: omp.inner.for.cond8:
1484 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
1485 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
1486 // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
1487 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END17:%.*]]
1488 // CHECK3: omp.inner.for.body10:
1489 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
1490 // CHECK3-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP12]], 1
1491 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]
1492 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[I7]], align 4, !llvm.access.group !6
1493 // CHECK3-NEXT: invoke void @_Z3foov()
1494 // CHECK3-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group !6
1495 // CHECK3: invoke.cont13:
1496 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]
1497 // CHECK3: omp.body.continue14:
1498 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]
1499 // CHECK3: omp.inner.for.inc15:
1500 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
1501 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP13]], 1
1502 // CHECK3-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
1503 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP7:![0-9]+]]
1504 // CHECK3: omp.inner.for.end17:
1505 // CHECK3-NEXT: store i32 100, i32* [[I7]], align 4
1506 // CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1
1507 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32
1508 // CHECK3-NEXT: [[CALL19:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv()
1509 // CHECK3-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]]
1510 // CHECK3: invoke.cont18:
1511 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]]
1512 // CHECK3-NEXT: [[CALL22:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv()
1513 // CHECK3-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]]
1514 // CHECK3: invoke.cont21:
1515 // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]]
1516 // CHECK3-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4
1517 // CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
1518 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4
1519 // CHECK3-NEXT: ret i32 [[TMP15]]
1520 // CHECK3: eh.resume:
1521 // CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8
1522 // CHECK3-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4
1523 // CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0
1524 // CHECK3-NEXT: [[LPAD_VAL24:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1525 // CHECK3-NEXT: resume { i8*, i32 } [[LPAD_VAL24]]
1526 // CHECK3: terminate.lpad:
1527 // CHECK3-NEXT: [[TMP16:%.*]] = landingpad { i8*, i32 }
1528 // CHECK3-NEXT: catch i8* null
1529 // CHECK3-NEXT: [[TMP17:%.*]] = extractvalue { i8*, i32 } [[TMP16]], 0
1530 // CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP17]]) #[[ATTR7:[0-9]+]], !llvm.access.group !2
1531 // CHECK3-NEXT: unreachable
1532 //
1533 //
1534 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El
1535 // CHECK3-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1536 // CHECK3-NEXT: entry:
1537 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1538 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1539 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1540 // CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1541 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1542 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
1543 // CHECK3-NEXT: call void @_ZN1SC2El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
1544 // CHECK3-NEXT: ret void
1545 //
1546 //
1547 // CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv
1548 // CHECK3-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
1549 // CHECK3-NEXT: entry:
1550 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1551 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1552 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1553 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1554 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8
1555 // CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
1556 // CHECK3-NEXT: ret i8 [[CONV]]
1557 //
1558 //
1559 // CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate
1560 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat {
1561 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
1562 // CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]
1563 // CHECK3-NEXT: unreachable
1564 //
1565 //
1566 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
1567 // CHECK3-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1568 // CHECK3-NEXT: entry:
1569 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1570 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1571 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1572 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1573 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1574 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1575 // CHECK3-NEXT: [[DOTOMP_LB3:%.*]] = alloca i32, align 4
1576 // CHECK3-NEXT: [[DOTOMP_UB4:%.*]] = alloca i32, align 4
1577 // CHECK3-NEXT: [[DOTOMP_IV5:%.*]] = alloca i32, align 4
1578 // CHECK3-NEXT: [[I6:%.*]] = alloca i32, align 4
1579 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1580 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1581 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1582 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1583 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1584 // CHECK3: omp.inner.for.cond:
1585 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1586 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
1587 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1588 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1589 // CHECK3: omp.inner.for.body:
1590 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1591 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1592 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1593 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
1594 // CHECK3-NEXT: invoke void @_Z3foov()
1595 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !9
1596 // CHECK3: invoke.cont:
1597 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1598 // CHECK3: omp.body.continue:
1599 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1600 // CHECK3: omp.inner.for.inc:
1601 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1602 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
1603 // CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1604 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1605 // CHECK3: omp.inner.for.end:
1606 // CHECK3-NEXT: store i32 100, i32* [[I]], align 4
1607 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB3]], align 4
1608 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB4]], align 4
1609 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB3]], align 4
1610 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4
1611 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]
1612 // CHECK3: omp.inner.for.cond7:
1613 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12
1614 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !12
1615 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1616 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END16:%.*]]
1617 // CHECK3: omp.inner.for.body9:
1618 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12
1619 // CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1
1620 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
1621 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !12
1622 // CHECK3-NEXT: invoke void @_Z3foov()
1623 // CHECK3-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group !12
1624 // CHECK3: invoke.cont12:
1625 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]]
1626 // CHECK3: omp.body.continue13:
1627 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC14:%.*]]
1628 // CHECK3: omp.inner.for.inc14:
1629 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12
1630 // CHECK3-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP9]], 1
1631 // CHECK3-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12
1632 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]]
1633 // CHECK3: omp.inner.for.end16:
1634 // CHECK3-NEXT: store i32 100, i32* [[I6]], align 4
1635 // CHECK3-NEXT: ret i32 0
1636 // CHECK3: terminate.lpad:
1637 // CHECK3-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 }
1638 // CHECK3-NEXT: catch i8* null
1639 // CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0
1640 // CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7]], !llvm.access.group !9
1641 // CHECK3-NEXT: unreachable
1642 //
1643 //
1644 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv
1645 // CHECK3-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1646 // CHECK3-NEXT: entry:
1647 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1648 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1649 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1650 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1651 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1652 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1653 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1654 // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
1655 // CHECK3-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
1656 // CHECK3-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
1657 // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
1658 // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4
1659 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1660 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1661 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1662 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1663 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1664 // CHECK3: omp.inner.for.cond:
1665 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1666 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15
1667 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1668 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1669 // CHECK3: omp.inner.for.body:
1670 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1671 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1672 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1673 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
1674 // CHECK3-NEXT: invoke void @_Z3foov()
1675 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !15
1676 // CHECK3: invoke.cont:
1677 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1678 // CHECK3: omp.body.continue:
1679 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1680 // CHECK3: omp.inner.for.inc:
1681 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1682 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
1683 // CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
1684 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
1685 // CHECK3: omp.inner.for.end:
1686 // CHECK3-NEXT: store i32 100, i32* [[I]], align 4
1687 // CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
1688 // CHECK3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]]
1689 // CHECK3: invoke.cont2:
1690 // CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
1691 // CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
1692 // CHECK3-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1693 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
1694 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB5]], align 4
1695 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
1696 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV6]], align 4
1697 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
1698 // CHECK3: omp.inner.for.cond8:
1699 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !18
1700 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !18
1701 // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1702 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END17:%.*]]
1703 // CHECK3: omp.inner.for.body10:
1704 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !18
1705 // CHECK3-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP8]], 1
1706 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]
1707 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[I7]], align 4, !llvm.access.group !18
1708 // CHECK3-NEXT: invoke void @_Z3foov()
1709 // CHECK3-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group !18
1710 // CHECK3: invoke.cont13:
1711 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]
1712 // CHECK3: omp.body.continue14:
1713 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]
1714 // CHECK3: omp.inner.for.inc15:
1715 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !18
1716 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP9]], 1
1717 // CHECK3-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !18
1718 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP19:![0-9]+]]
1719 // CHECK3: omp.inner.for.end17:
1720 // CHECK3-NEXT: store i32 100, i32* [[I7]], align 4
1721 // CHECK3-NEXT: ret i32 0
1722 // CHECK3: terminate.lpad:
1723 // CHECK3-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 }
1724 // CHECK3-NEXT: catch i8* null
1725 // CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0
1726 // CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7]], !llvm.access.group !15
1727 // CHECK3-NEXT: unreachable
1728 //
1729 //
1730 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev
1731 // CHECK3-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 {
1732 // CHECK3-NEXT: entry:
1733 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1734 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1735 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1736 // CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
1737 // CHECK3-NEXT: ret void
1738 //
1739 //
1740 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El
1741 // CHECK3-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 {
1742 // CHECK3-NEXT: entry:
1743 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1744 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1745 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1746 // CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1747 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1748 // CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1749 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
1750 // CHECK3-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8
1751 // CHECK3-NEXT: ret void
1752 //
1753 //
1754 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev
1755 // CHECK3-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 {
1756 // CHECK3-NEXT: entry:
1757 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1758 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1759 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1760 // CHECK3-NEXT: ret void
1761 //
1762 //
1763 // CHECK5-LABEL: define {{[^@]+}}@main
1764 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1765 // CHECK5-NEXT: entry:
1766 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1767 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1768 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1
1769 // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8
1770 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1771 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1772 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1773 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
1774 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
1775 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
1776 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1777 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1778 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1779 // CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0)
1780 // CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]])
1781 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1782 // CHECK5: invoke.cont:
1783 // CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1
1784 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1785 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1786 // CHECK5-NEXT: store i32 1, i32* [[TMP0]], align 4
1787 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1788 // CHECK5-NEXT: store i32 0, i32* [[TMP1]], align 4
1789 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1790 // CHECK5-NEXT: store i8** null, i8*** [[TMP2]], align 8
1791 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1792 // CHECK5-NEXT: store i8** null, i8*** [[TMP3]], align 8
1793 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1794 // CHECK5-NEXT: store i64* null, i64** [[TMP4]], align 8
1795 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1796 // CHECK5-NEXT: store i64* null, i64** [[TMP5]], align 8
1797 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1798 // CHECK5-NEXT: store i8** null, i8*** [[TMP6]], align 8
1799 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1800 // CHECK5-NEXT: store i8** null, i8*** [[TMP7]], align 8
1801 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1802 // CHECK5-NEXT: store i64 100, i64* [[TMP8]], align 8
1803 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1804 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1805 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1806 // CHECK5: omp_offload.failed:
1807 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]]
1808 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1809 // CHECK5: lpad:
1810 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
1811 // CHECK5-NEXT: cleanup
1812 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
1813 // CHECK5-NEXT: store i8* [[TMP12]], i8** [[EXN_SLOT]], align 8
1814 // CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 1
1815 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[EHSELECTOR_SLOT]], align 4
1816 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
1817 // CHECK5-NEXT: br label [[EH_RESUME:%.*]]
1818 // CHECK5: omp_offload.cont:
1819 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1
1820 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8*
1821 // CHECK5-NEXT: store i8 [[TMP14]], i8* [[CONV]], align 1
1822 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[A_CASTED]], align 8
1823 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1824 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1825 // CHECK5-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
1826 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1827 // CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1828 // CHECK5-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
1829 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1830 // CHECK5-NEXT: store i8* null, i8** [[TMP20]], align 8
1831 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1832 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1833 // CHECK5-NEXT: [[TMP23:%.*]] = load i8, i8* [[A]], align 1
1834 // CHECK5-NEXT: store i8 [[TMP23]], i8* [[DOTCAPTURE_EXPR_]], align 1
1835 // CHECK5-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1836 // CHECK5-NEXT: [[TMP25:%.*]] = zext i8 [[TMP24]] to i32
1837 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1838 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
1839 // CHECK5-NEXT: store i32 1, i32* [[TMP26]], align 4
1840 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
1841 // CHECK5-NEXT: store i32 1, i32* [[TMP27]], align 4
1842 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
1843 // CHECK5-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 8
1844 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
1845 // CHECK5-NEXT: store i8** [[TMP22]], i8*** [[TMP29]], align 8
1846 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
1847 // CHECK5-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 8
1848 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
1849 // CHECK5-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8
1850 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
1851 // CHECK5-NEXT: store i8** null, i8*** [[TMP32]], align 8
1852 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
1853 // CHECK5-NEXT: store i8** null, i8*** [[TMP33]], align 8
1854 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
1855 // CHECK5-NEXT: store i64 100, i64* [[TMP34]], align 8
1856 // CHECK5-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP25]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
1857 // CHECK5-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
1858 // CHECK5-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
1859 // CHECK5: omp_offload.failed3:
1860 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR6]]
1861 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]]
1862 // CHECK5: omp_offload.cont4:
1863 // CHECK5-NEXT: [[TMP37:%.*]] = load i8, i8* [[A]], align 1
1864 // CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP37]] to i32
1865 // CHECK5-NEXT: [[CALL7:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv()
1866 // CHECK5-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[LPAD]]
1867 // CHECK5: invoke.cont6:
1868 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV5]], [[CALL7]]
1869 // CHECK5-NEXT: [[CALL9:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv()
1870 // CHECK5-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD]]
1871 // CHECK5: invoke.cont8:
1872 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD]], [[CALL9]]
1873 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[RETVAL]], align 4
1874 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
1875 // CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[RETVAL]], align 4
1876 // CHECK5-NEXT: ret i32 [[TMP38]]
1877 // CHECK5: eh.resume:
1878 // CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8
1879 // CHECK5-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4
1880 // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0
1881 // CHECK5-NEXT: [[LPAD_VAL11:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1882 // CHECK5-NEXT: resume { i8*, i32 } [[LPAD_VAL11]]
1883 //
1884 //
1885 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El
1886 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1887 // CHECK5-NEXT: entry:
1888 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1889 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1890 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1891 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1892 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1893 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
1894 // CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
1895 // CHECK5-NEXT: ret void
1896 //
1897 //
1898 // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv
1899 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
1900 // CHECK5-NEXT: entry:
1901 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1902 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1903 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1904 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1905 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8
1906 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
1907 // CHECK5-NEXT: ret i8 [[CONV]]
1908 //
1909 //
1910 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50
1911 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1912 // CHECK5-NEXT: entry:
1913 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1914 // CHECK5-NEXT: ret void
1915 //
1916 //
1917 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
1918 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
1919 // CHECK5-NEXT: entry:
1920 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1921 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1922 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1923 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1924 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1925 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1926 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1927 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1928 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1929 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1930 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1931 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1932 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1933 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1934 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1935 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1936 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1937 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1938 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1939 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1940 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1941 // CHECK5: cond.true:
1942 // CHECK5-NEXT: br label [[COND_END:%.*]]
1943 // CHECK5: cond.false:
1944 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1945 // CHECK5-NEXT: br label [[COND_END]]
1946 // CHECK5: cond.end:
1947 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1948 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1949 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1950 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1951 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1952 // CHECK5: omp.inner.for.cond:
1953 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1954 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
1955 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1956 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1957 // CHECK5: omp.inner.for.body:
1958 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9
1959 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
1960 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1961 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
1962 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1963 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9
1964 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1965 // CHECK5: omp.inner.for.inc:
1966 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1967 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
1968 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1969 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
1970 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1971 // CHECK5: omp.inner.for.end:
1972 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1973 // CHECK5: omp.loop.exit:
1974 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1975 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1976 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1977 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1978 // CHECK5: .omp.final.then:
1979 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
1980 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
1981 // CHECK5: .omp.final.done:
1982 // CHECK5-NEXT: ret void
1983 //
1984 //
1985 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
1986 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1987 // CHECK5-NEXT: entry:
1988 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1989 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1990 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1991 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1992 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1993 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1994 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1995 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1996 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1997 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1998 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1999 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2000 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2001 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2002 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2003 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2004 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2005 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2006 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2007 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2008 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2009 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2010 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2011 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2012 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2013 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2014 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2015 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2016 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2017 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2018 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2019 // CHECK5: cond.true:
2020 // CHECK5-NEXT: br label [[COND_END:%.*]]
2021 // CHECK5: cond.false:
2022 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2023 // CHECK5-NEXT: br label [[COND_END]]
2024 // CHECK5: cond.end:
2025 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2026 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2027 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2028 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2029 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2030 // CHECK5: omp.inner.for.cond:
2031 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
2032 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
2033 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2034 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2035 // CHECK5: omp.inner.for.body:
2036 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
2037 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2038 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2039 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
2040 // CHECK5-NEXT: invoke void @_Z3foov()
2041 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13
2042 // CHECK5: invoke.cont:
2043 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2044 // CHECK5: omp.body.continue:
2045 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2046 // CHECK5: omp.inner.for.inc:
2047 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
2048 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2049 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
2050 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
2051 // CHECK5: omp.inner.for.end:
2052 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2053 // CHECK5: omp.loop.exit:
2054 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2055 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2056 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2057 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2058 // CHECK5: .omp.final.then:
2059 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2060 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2061 // CHECK5: .omp.final.done:
2062 // CHECK5-NEXT: ret void
2063 // CHECK5: terminate.lpad:
2064 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
2065 // CHECK5-NEXT: catch i8* null
2066 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
2067 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group !13
2068 // CHECK5-NEXT: unreachable
2069 //
2070 //
2071 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate
2072 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
2073 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
2074 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR9]]
2075 // CHECK5-NEXT: unreachable
2076 //
2077 //
2078 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
2079 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
2080 // CHECK5-NEXT: entry:
2081 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2082 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2083 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2084 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2085 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
2086 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
2087 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
2088 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2089 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
2090 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
2091 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2092 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
2093 // CHECK5-NEXT: ret void
2094 //
2095 //
2096 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
2097 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
2098 // CHECK5-NEXT: entry:
2099 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2100 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2101 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2102 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2103 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2104 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2105 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2106 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2107 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2108 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2109 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2110 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2111 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2112 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2113 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2114 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2115 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2116 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2117 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2118 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2119 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2120 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2121 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2122 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2123 // CHECK5: cond.true:
2124 // CHECK5-NEXT: br label [[COND_END:%.*]]
2125 // CHECK5: cond.false:
2126 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2127 // CHECK5-NEXT: br label [[COND_END]]
2128 // CHECK5: cond.end:
2129 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2130 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2131 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2132 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2133 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2134 // CHECK5: omp.inner.for.cond:
2135 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2136 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
2137 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2138 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2139 // CHECK5: omp.inner.for.body:
2140 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
2141 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
2142 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
2143 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
2144 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2145 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
2146 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
2147 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
2148 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2149 // CHECK5: omp.inner.for.inc:
2150 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2151 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
2152 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
2153 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2154 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
2155 // CHECK5: omp.inner.for.end:
2156 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2157 // CHECK5: omp.loop.exit:
2158 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2159 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2160 // CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
2161 // CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2162 // CHECK5: .omp.final.then:
2163 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2164 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2165 // CHECK5: .omp.final.done:
2166 // CHECK5-NEXT: ret void
2167 //
2168 //
2169 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
2170 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2171 // CHECK5-NEXT: entry:
2172 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2173 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2174 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2175 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2176 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2177 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2178 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2179 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2180 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2181 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2182 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2183 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2184 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2185 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2186 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2187 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2188 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2189 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2190 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2191 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2192 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2193 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2194 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2195 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2196 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2197 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2198 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2199 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2200 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2201 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2202 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2203 // CHECK5: cond.true:
2204 // CHECK5-NEXT: br label [[COND_END:%.*]]
2205 // CHECK5: cond.false:
2206 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2207 // CHECK5-NEXT: br label [[COND_END]]
2208 // CHECK5: cond.end:
2209 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2210 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2211 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2212 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2213 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2214 // CHECK5: omp.inner.for.cond:
2215 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2216 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
2217 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2218 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2219 // CHECK5: omp.inner.for.body:
2220 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2221 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2222 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2223 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
2224 // CHECK5-NEXT: invoke void @_Z3foov()
2225 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21
2226 // CHECK5: invoke.cont:
2227 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2228 // CHECK5: omp.body.continue:
2229 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2230 // CHECK5: omp.inner.for.inc:
2231 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2232 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2233 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2234 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
2235 // CHECK5: omp.inner.for.end:
2236 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2237 // CHECK5: omp.loop.exit:
2238 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2239 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2240 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2241 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2242 // CHECK5: .omp.final.then:
2243 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2244 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2245 // CHECK5: .omp.final.done:
2246 // CHECK5-NEXT: ret void
2247 // CHECK5: terminate.lpad:
2248 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
2249 // CHECK5-NEXT: catch i8* null
2250 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
2251 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !21
2252 // CHECK5-NEXT: unreachable
2253 //
2254 //
2255 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
2256 // CHECK5-SAME: () #[[ATTR2]] comdat {
2257 // CHECK5-NEXT: entry:
2258 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2259 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2260 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2261 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2262 // CHECK5-NEXT: store i32 1, i32* [[TMP0]], align 4
2263 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2264 // CHECK5-NEXT: store i32 0, i32* [[TMP1]], align 4
2265 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2266 // CHECK5-NEXT: store i8** null, i8*** [[TMP2]], align 8
2267 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2268 // CHECK5-NEXT: store i8** null, i8*** [[TMP3]], align 8
2269 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2270 // CHECK5-NEXT: store i64* null, i64** [[TMP4]], align 8
2271 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2272 // CHECK5-NEXT: store i64* null, i64** [[TMP5]], align 8
2273 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2274 // CHECK5-NEXT: store i8** null, i8*** [[TMP6]], align 8
2275 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2276 // CHECK5-NEXT: store i8** null, i8*** [[TMP7]], align 8
2277 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2278 // CHECK5-NEXT: store i64 100, i64* [[TMP8]], align 8
2279 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 5, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2280 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2281 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2282 // CHECK5: omp_offload.failed:
2283 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]]
2284 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
2285 // CHECK5: omp_offload.cont:
2286 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2287 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
2288 // CHECK5-NEXT: store i32 1, i32* [[TMP11]], align 4
2289 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
2290 // CHECK5-NEXT: store i32 0, i32* [[TMP12]], align 4
2291 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
2292 // CHECK5-NEXT: store i8** null, i8*** [[TMP13]], align 8
2293 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
2294 // CHECK5-NEXT: store i8** null, i8*** [[TMP14]], align 8
2295 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
2296 // CHECK5-NEXT: store i64* null, i64** [[TMP15]], align 8
2297 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
2298 // CHECK5-NEXT: store i64* null, i64** [[TMP16]], align 8
2299 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
2300 // CHECK5-NEXT: store i8** null, i8*** [[TMP17]], align 8
2301 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
2302 // CHECK5-NEXT: store i8** null, i8*** [[TMP18]], align 8
2303 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
2304 // CHECK5-NEXT: store i64 100, i64* [[TMP19]], align 8
2305 // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 23, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
2306 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2307 // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
2308 // CHECK5: omp_offload.failed3:
2309 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]]
2310 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]]
2311 // CHECK5: omp_offload.cont4:
2312 // CHECK5-NEXT: ret i32 0
2313 //
2314 //
2315 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv
2316 // CHECK5-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2317 // CHECK5-NEXT: entry:
2318 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2319 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2320 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
2321 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2322 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2323 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2324 // CHECK5-NEXT: store i32 1, i32* [[TMP0]], align 4
2325 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2326 // CHECK5-NEXT: store i32 0, i32* [[TMP1]], align 4
2327 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2328 // CHECK5-NEXT: store i8** null, i8*** [[TMP2]], align 8
2329 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2330 // CHECK5-NEXT: store i8** null, i8*** [[TMP3]], align 8
2331 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2332 // CHECK5-NEXT: store i64* null, i64** [[TMP4]], align 8
2333 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2334 // CHECK5-NEXT: store i64* null, i64** [[TMP5]], align 8
2335 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2336 // CHECK5-NEXT: store i8** null, i8*** [[TMP6]], align 8
2337 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2338 // CHECK5-NEXT: store i8** null, i8*** [[TMP7]], align 8
2339 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2340 // CHECK5-NEXT: store i64 100, i64* [[TMP8]], align 8
2341 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2342 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2343 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2344 // CHECK5: omp_offload.failed:
2345 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]]
2346 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
2347 // CHECK5: omp_offload.cont:
2348 // CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
2349 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2350 // CHECK5: invoke.cont:
2351 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
2352 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
2353 // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2354 // CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2355 // CHECK5-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32
2356 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2357 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
2358 // CHECK5-NEXT: store i32 1, i32* [[TMP13]], align 4
2359 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
2360 // CHECK5-NEXT: store i32 0, i32* [[TMP14]], align 4
2361 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
2362 // CHECK5-NEXT: store i8** null, i8*** [[TMP15]], align 8
2363 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
2364 // CHECK5-NEXT: store i8** null, i8*** [[TMP16]], align 8
2365 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
2366 // CHECK5-NEXT: store i64* null, i64** [[TMP17]], align 8
2367 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
2368 // CHECK5-NEXT: store i64* null, i64** [[TMP18]], align 8
2369 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
2370 // CHECK5-NEXT: store i8** null, i8*** [[TMP19]], align 8
2371 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
2372 // CHECK5-NEXT: store i8** null, i8*** [[TMP20]], align 8
2373 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
2374 // CHECK5-NEXT: store i64 100, i64* [[TMP21]], align 8
2375 // CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
2376 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2377 // CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
2378 // CHECK5: omp_offload.failed3:
2379 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]]
2380 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]]
2381 // CHECK5: omp_offload.cont4:
2382 // CHECK5-NEXT: ret i32 0
2383 // CHECK5: terminate.lpad:
2384 // CHECK5-NEXT: [[TMP24:%.*]] = landingpad { i8*, i32 }
2385 // CHECK5-NEXT: catch i8* null
2386 // CHECK5-NEXT: [[TMP25:%.*]] = extractvalue { i8*, i32 } [[TMP24]], 0
2387 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP25]]) #[[ATTR9]]
2388 // CHECK5-NEXT: unreachable
2389 //
2390 //
2391 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev
2392 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 {
2393 // CHECK5-NEXT: entry:
2394 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2395 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2396 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2397 // CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
2398 // CHECK5-NEXT: ret void
2399 //
2400 //
2401 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El
2402 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
2403 // CHECK5-NEXT: entry:
2404 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2405 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2406 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2407 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2408 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2409 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2410 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
2411 // CHECK5-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8
2412 // CHECK5-NEXT: ret void
2413 //
2414 //
2415 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36
2416 // CHECK5-SAME: () #[[ATTR3]] {
2417 // CHECK5-NEXT: entry:
2418 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
2419 // CHECK5-NEXT: ret void
2420 //
2421 //
2422 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
2423 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
2424 // CHECK5-NEXT: entry:
2425 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2426 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2427 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2428 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2429 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2430 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2431 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2432 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2433 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2434 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2435 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2436 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2437 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2438 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2439 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2440 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2441 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2442 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2443 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2444 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2445 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2446 // CHECK5: cond.true:
2447 // CHECK5-NEXT: br label [[COND_END:%.*]]
2448 // CHECK5: cond.false:
2449 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2450 // CHECK5-NEXT: br label [[COND_END]]
2451 // CHECK5: cond.end:
2452 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2453 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2454 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2455 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2456 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2457 // CHECK5: omp.inner.for.cond:
2458 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2459 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
2460 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2461 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2462 // CHECK5: omp.inner.for.body:
2463 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24
2464 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
2465 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2466 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
2467 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2468 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
2469 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2470 // CHECK5: omp.inner.for.inc:
2471 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2472 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
2473 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2474 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2475 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
2476 // CHECK5: omp.inner.for.end:
2477 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2478 // CHECK5: omp.loop.exit:
2479 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2480 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2481 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2482 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2483 // CHECK5: .omp.final.then:
2484 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2485 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2486 // CHECK5: .omp.final.done:
2487 // CHECK5-NEXT: ret void
2488 //
2489 //
2490 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5
2491 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2492 // CHECK5-NEXT: entry:
2493 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2494 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2495 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2496 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2497 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2498 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2499 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2500 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2501 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2502 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2503 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2504 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2505 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2506 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2507 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2508 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2509 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2510 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2511 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2512 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2513 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2514 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2515 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2516 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2517 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2518 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2519 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2520 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2521 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2522 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2523 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2524 // CHECK5: cond.true:
2525 // CHECK5-NEXT: br label [[COND_END:%.*]]
2526 // CHECK5: cond.false:
2527 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2528 // CHECK5-NEXT: br label [[COND_END]]
2529 // CHECK5: cond.end:
2530 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2531 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2532 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2533 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2534 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2535 // CHECK5: omp.inner.for.cond:
2536 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
2537 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
2538 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2539 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2540 // CHECK5: omp.inner.for.body:
2541 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
2542 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2543 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2544 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
2545 // CHECK5-NEXT: invoke void @_Z3foov()
2546 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27
2547 // CHECK5: invoke.cont:
2548 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2549 // CHECK5: omp.body.continue:
2550 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2551 // CHECK5: omp.inner.for.inc:
2552 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
2553 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2554 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
2555 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
2556 // CHECK5: omp.inner.for.end:
2557 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2558 // CHECK5: omp.loop.exit:
2559 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2560 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2561 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2562 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2563 // CHECK5: .omp.final.then:
2564 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2565 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2566 // CHECK5: .omp.final.done:
2567 // CHECK5-NEXT: ret void
2568 // CHECK5: terminate.lpad:
2569 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
2570 // CHECK5-NEXT: catch i8* null
2571 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
2572 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !27
2573 // CHECK5-NEXT: unreachable
2574 //
2575 //
2576 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40
2577 // CHECK5-SAME: () #[[ATTR3]] {
2578 // CHECK5-NEXT: entry:
2579 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*))
2580 // CHECK5-NEXT: ret void
2581 //
2582 //
2583 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6
2584 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
2585 // CHECK5-NEXT: entry:
2586 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2587 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2588 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2589 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2590 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2591 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2592 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2593 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2594 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2595 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2596 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2597 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2598 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2599 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2600 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2601 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2602 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2603 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2604 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2605 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2606 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2607 // CHECK5: cond.true:
2608 // CHECK5-NEXT: br label [[COND_END:%.*]]
2609 // CHECK5: cond.false:
2610 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2611 // CHECK5-NEXT: br label [[COND_END]]
2612 // CHECK5: cond.end:
2613 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2614 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2615 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2616 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2617 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2618 // CHECK5: omp.inner.for.cond:
2619 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
2620 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
2621 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2622 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2623 // CHECK5: omp.inner.for.body:
2624 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30
2625 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
2626 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2627 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
2628 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2629 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30
2630 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2631 // CHECK5: omp.inner.for.inc:
2632 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
2633 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
2634 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2635 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
2636 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
2637 // CHECK5: omp.inner.for.end:
2638 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2639 // CHECK5: omp.loop.exit:
2640 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2641 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2642 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2643 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2644 // CHECK5: .omp.final.then:
2645 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2646 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2647 // CHECK5: .omp.final.done:
2648 // CHECK5-NEXT: ret void
2649 //
2650 //
2651 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
2652 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2653 // CHECK5-NEXT: entry:
2654 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2655 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2656 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2657 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2658 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2659 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2660 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2661 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2662 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2663 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2664 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2665 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2666 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2667 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2668 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2669 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2670 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2671 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2672 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2673 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2674 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2675 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2676 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2677 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2678 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2679 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2680 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2681 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2682 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2683 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2684 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2685 // CHECK5: cond.true:
2686 // CHECK5-NEXT: br label [[COND_END:%.*]]
2687 // CHECK5: cond.false:
2688 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2689 // CHECK5-NEXT: br label [[COND_END]]
2690 // CHECK5: cond.end:
2691 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2692 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2693 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2694 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2695 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2696 // CHECK5: omp.inner.for.cond:
2697 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2698 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
2699 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2700 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2701 // CHECK5: omp.inner.for.body:
2702 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2703 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2704 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2705 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
2706 // CHECK5-NEXT: invoke void @_Z3foov()
2707 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33
2708 // CHECK5: invoke.cont:
2709 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2710 // CHECK5: omp.body.continue:
2711 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2712 // CHECK5: omp.inner.for.inc:
2713 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2714 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2715 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2716 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
2717 // CHECK5: omp.inner.for.end:
2718 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2719 // CHECK5: omp.loop.exit:
2720 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2721 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2722 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2723 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2724 // CHECK5: .omp.final.then:
2725 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2726 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2727 // CHECK5: .omp.final.done:
2728 // CHECK5-NEXT: ret void
2729 // CHECK5: terminate.lpad:
2730 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
2731 // CHECK5-NEXT: catch i8* null
2732 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
2733 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !33
2734 // CHECK5-NEXT: unreachable
2735 //
2736 //
2737 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36
2738 // CHECK5-SAME: () #[[ATTR3]] {
2739 // CHECK5-NEXT: entry:
2740 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*))
2741 // CHECK5-NEXT: ret void
2742 //
2743 //
2744 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8
2745 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
2746 // CHECK5-NEXT: entry:
2747 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2748 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2749 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2750 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2751 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2752 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2753 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2754 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2755 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2756 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2757 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2758 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2759 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2760 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2761 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2762 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2763 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2764 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2765 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2766 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2767 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2768 // CHECK5: cond.true:
2769 // CHECK5-NEXT: br label [[COND_END:%.*]]
2770 // CHECK5: cond.false:
2771 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2772 // CHECK5-NEXT: br label [[COND_END]]
2773 // CHECK5: cond.end:
2774 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2775 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2776 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2777 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2778 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2779 // CHECK5: omp.inner.for.cond:
2780 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
2781 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
2782 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2783 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2784 // CHECK5: omp.inner.for.body:
2785 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36
2786 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
2787 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2788 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
2789 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2790 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
2791 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2792 // CHECK5: omp.inner.for.inc:
2793 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
2794 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
2795 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2796 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
2797 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
2798 // CHECK5: omp.inner.for.end:
2799 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2800 // CHECK5: omp.loop.exit:
2801 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2802 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2803 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2804 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2805 // CHECK5: .omp.final.then:
2806 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2807 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2808 // CHECK5: .omp.final.done:
2809 // CHECK5-NEXT: ret void
2810 //
2811 //
2812 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9
2813 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2814 // CHECK5-NEXT: entry:
2815 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2816 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2817 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2818 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2819 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2820 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2821 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2822 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2823 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2824 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2825 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2826 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2827 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2828 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2829 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2830 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2831 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2832 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2833 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2834 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2835 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2836 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2837 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2838 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2839 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2840 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2841 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2842 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2843 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2844 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2845 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2846 // CHECK5: cond.true:
2847 // CHECK5-NEXT: br label [[COND_END:%.*]]
2848 // CHECK5: cond.false:
2849 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2850 // CHECK5-NEXT: br label [[COND_END]]
2851 // CHECK5: cond.end:
2852 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2853 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2854 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2855 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2856 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2857 // CHECK5: omp.inner.for.cond:
2858 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
2859 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
2860 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2861 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2862 // CHECK5: omp.inner.for.body:
2863 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
2864 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2865 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2866 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
2867 // CHECK5-NEXT: invoke void @_Z3foov()
2868 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39
2869 // CHECK5: invoke.cont:
2870 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2871 // CHECK5: omp.body.continue:
2872 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2873 // CHECK5: omp.inner.for.inc:
2874 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
2875 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2876 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
2877 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
2878 // CHECK5: omp.inner.for.end:
2879 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2880 // CHECK5: omp.loop.exit:
2881 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2882 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2883 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2884 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2885 // CHECK5: .omp.final.then:
2886 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2887 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2888 // CHECK5: .omp.final.done:
2889 // CHECK5-NEXT: ret void
2890 // CHECK5: terminate.lpad:
2891 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
2892 // CHECK5-NEXT: catch i8* null
2893 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
2894 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !39
2895 // CHECK5-NEXT: unreachable
2896 //
2897 //
2898 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40
2899 // CHECK5-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2900 // CHECK5-NEXT: entry:
2901 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2902 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
2903 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2904 // CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
2905 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2906 // CHECK5: invoke.cont:
2907 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
2908 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
2909 // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2910 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2911 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
2912 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
2913 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2914 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2915 // CHECK5-NEXT: ret void
2916 // CHECK5: terminate.lpad:
2917 // CHECK5-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 }
2918 // CHECK5-NEXT: catch i8* null
2919 // CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0
2920 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP3]]) #[[ATTR9]]
2921 // CHECK5-NEXT: unreachable
2922 //
2923 //
2924 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10
2925 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
2926 // CHECK5-NEXT: entry:
2927 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2928 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2929 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2930 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2931 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2932 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2933 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2934 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2935 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2936 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2937 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2938 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2939 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2940 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2941 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2942 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2943 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2944 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2945 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2946 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2947 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2948 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2949 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2950 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2951 // CHECK5: cond.true:
2952 // CHECK5-NEXT: br label [[COND_END:%.*]]
2953 // CHECK5: cond.false:
2954 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2955 // CHECK5-NEXT: br label [[COND_END]]
2956 // CHECK5: cond.end:
2957 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2958 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2959 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2960 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2961 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2962 // CHECK5: omp.inner.for.cond:
2963 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
2964 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
2965 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2966 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2967 // CHECK5: omp.inner.for.body:
2968 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
2969 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
2970 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
2971 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
2972 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2973 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
2974 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
2975 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
2976 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2977 // CHECK5: omp.inner.for.inc:
2978 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
2979 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
2980 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
2981 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
2982 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
2983 // CHECK5: omp.inner.for.end:
2984 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2985 // CHECK5: omp.loop.exit:
2986 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2987 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2988 // CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
2989 // CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2990 // CHECK5: .omp.final.then:
2991 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
2992 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
2993 // CHECK5: .omp.final.done:
2994 // CHECK5-NEXT: ret void
2995 //
2996 //
2997 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11
2998 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2999 // CHECK5-NEXT: entry:
3000 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3001 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3002 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3003 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3004 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3005 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3006 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3007 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3008 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3009 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3010 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3011 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3012 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3013 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3014 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3015 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3016 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
3017 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3018 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
3019 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3020 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
3021 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
3022 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
3023 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3024 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3025 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3026 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
3027 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3028 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3029 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
3030 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3031 // CHECK5: cond.true:
3032 // CHECK5-NEXT: br label [[COND_END:%.*]]
3033 // CHECK5: cond.false:
3034 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3035 // CHECK5-NEXT: br label [[COND_END]]
3036 // CHECK5: cond.end:
3037 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3038 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3039 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3040 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
3041 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3042 // CHECK5: omp.inner.for.cond:
3043 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3044 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
3045 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3046 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3047 // CHECK5: omp.inner.for.body:
3048 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3049 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
3050 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3051 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
3052 // CHECK5-NEXT: invoke void @_Z3foov()
3053 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45
3054 // CHECK5: invoke.cont:
3055 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3056 // CHECK5: omp.body.continue:
3057 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3058 // CHECK5: omp.inner.for.inc:
3059 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3060 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
3061 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3062 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
3063 // CHECK5: omp.inner.for.end:
3064 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3065 // CHECK5: omp.loop.exit:
3066 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
3067 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3068 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
3069 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3070 // CHECK5: .omp.final.then:
3071 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
3072 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
3073 // CHECK5: .omp.final.done:
3074 // CHECK5-NEXT: ret void
3075 // CHECK5: terminate.lpad:
3076 // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 }
3077 // CHECK5-NEXT: catch i8* null
3078 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0
3079 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !45
3080 // CHECK5-NEXT: unreachable
3081 //
3082 //
3083 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev
3084 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
3085 // CHECK5-NEXT: entry:
3086 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3087 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3088 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3089 // CHECK5-NEXT: ret void
3090 //
3091 //
3092 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3093 // CHECK5-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" {
3094 // CHECK5-NEXT: entry:
3095 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
3096 // CHECK5-NEXT: ret void
3097 //
3098