1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5
6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
9
10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5
11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
13
14 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s
16 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17
18 // expected-no-diagnostics
19 #ifndef HEADER
20 #define HEADER
21
22 typedef __INTPTR_TYPE__ intptr_t;
23
24
25 void foo();
26
27 struct S {
28 intptr_t a, b, c;
SS29 S(intptr_t a) : a(a) {}
operator charS30 operator char() { return a; }
~SS31 ~S() {}
32 };
33
34 template <typename T, int C>
tmain()35 int tmain() {
36 #pragma omp target
37 #pragma omp teams distribute parallel for num_threads(C)
38 for (int i = 0; i < 100; i++)
39 foo();
40 #pragma omp target
41 #pragma omp teams distribute parallel for num_threads(T(23))
42 for (int i = 0; i < 100; i++)
43 foo();
44 return 0;
45 }
46
main()47 int main() {
48 S s(0);
49 char a = s;
50 #pragma omp target
51 #pragma omp teams distribute parallel for num_threads(2)
52 for (int i = 0; i < 100; i++) {
53 foo();
54 }
55 #pragma omp target
56
57 #pragma omp teams distribute parallel for num_threads(a)
58 for (int i = 0; i < 100; i++) {
59 foo();
60 }
61 return a + tmain<char, 5>() + tmain<S, 1>();
62 }
63
64 // tmain 5
65
66 // tmain 1
67
68
69
70
71
72
73
74
75 #endif
76 // CHECK1-LABEL: define {{[^@]+}}@main
77 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
78 // CHECK1-NEXT: entry:
79 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
80 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8
81 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1
82 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8
83 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
84 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
85 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
86 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
87 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
88 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
89 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
90 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
91 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
92 // CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0)
93 // CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]])
94 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
95 // CHECK1: invoke.cont:
96 // CHECK1-NEXT: store i8 [[CALL]], i8* [[A]], align 1
97 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
98 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
99 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
100 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
101 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
102 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
103 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
104 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
105 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
106 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
107 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
108 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
109 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
110 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
111 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
112 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
113 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
114 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
115 // CHECK1-NEXT: store i64 100, i64* [[TMP8]], align 8
116 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
117 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
118 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
119 // CHECK1: omp_offload.failed:
120 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]]
121 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
122 // CHECK1: lpad:
123 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
124 // CHECK1-NEXT: cleanup
125 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
126 // CHECK1-NEXT: store i8* [[TMP12]], i8** [[EXN_SLOT]], align 8
127 // CHECK1-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 1
128 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[EHSELECTOR_SLOT]], align 4
129 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
130 // CHECK1-NEXT: br label [[EH_RESUME:%.*]]
131 // CHECK1: omp_offload.cont:
132 // CHECK1-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1
133 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8*
134 // CHECK1-NEXT: store i8 [[TMP14]], i8* [[CONV]], align 1
135 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[A_CASTED]], align 8
136 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
137 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
138 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
139 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
140 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
141 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
142 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
143 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8
144 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
145 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
146 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[A]], align 1
147 // CHECK1-NEXT: store i8 [[TMP23]], i8* [[DOTCAPTURE_EXPR_]], align 1
148 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
149 // CHECK1-NEXT: [[TMP25:%.*]] = zext i8 [[TMP24]] to i32
150 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
151 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
152 // CHECK1-NEXT: store i32 1, i32* [[TMP26]], align 4
153 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
154 // CHECK1-NEXT: store i32 1, i32* [[TMP27]], align 4
155 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
156 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 8
157 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
158 // CHECK1-NEXT: store i8** [[TMP22]], i8*** [[TMP29]], align 8
159 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
160 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 8
161 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
162 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8
163 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
164 // CHECK1-NEXT: store i8** null, i8*** [[TMP32]], align 8
165 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
166 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8
167 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
168 // CHECK1-NEXT: store i64 100, i64* [[TMP34]], align 8
169 // CHECK1-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP25]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
170 // CHECK1-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
171 // CHECK1-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
172 // CHECK1: omp_offload.failed3:
173 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR6]]
174 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
175 // CHECK1: omp_offload.cont4:
176 // CHECK1-NEXT: [[TMP37:%.*]] = load i8, i8* [[A]], align 1
177 // CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP37]] to i32
178 // CHECK1-NEXT: [[CALL7:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv()
179 // CHECK1-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[LPAD]]
180 // CHECK1: invoke.cont6:
181 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV5]], [[CALL7]]
182 // CHECK1-NEXT: [[CALL9:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv()
183 // CHECK1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD]]
184 // CHECK1: invoke.cont8:
185 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD]], [[CALL9]]
186 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[RETVAL]], align 4
187 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
188 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[RETVAL]], align 4
189 // CHECK1-NEXT: ret i32 [[TMP38]]
190 // CHECK1: eh.resume:
191 // CHECK1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8
192 // CHECK1-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4
193 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0
194 // CHECK1-NEXT: [[LPAD_VAL11:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
195 // CHECK1-NEXT: resume { i8*, i32 } [[LPAD_VAL11]]
196 //
197 //
198 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El
199 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
200 // CHECK1-NEXT: entry:
201 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
202 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
203 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
204 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
205 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
206 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
207 // CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
208 // CHECK1-NEXT: ret void
209 //
210 //
211 // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv
212 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
213 // CHECK1-NEXT: entry:
214 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
216 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
217 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
218 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8
219 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
220 // CHECK1-NEXT: ret i8 [[CONV]]
221 //
222 //
223 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50
224 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
225 // CHECK1-NEXT: entry:
226 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
227 // CHECK1-NEXT: ret void
228 //
229 //
230 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
231 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
232 // CHECK1-NEXT: entry:
233 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
234 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
235 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
236 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
237 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
238 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
241 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
242 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
243 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
244 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
245 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
246 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
247 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
248 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
249 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
250 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
251 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
252 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
253 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
254 // CHECK1: cond.true:
255 // CHECK1-NEXT: br label [[COND_END:%.*]]
256 // CHECK1: cond.false:
257 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
258 // CHECK1-NEXT: br label [[COND_END]]
259 // CHECK1: cond.end:
260 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
261 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
262 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
263 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
264 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
265 // CHECK1: omp.inner.for.cond:
266 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
267 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
268 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
269 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
270 // CHECK1: omp.inner.for.body:
271 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)
272 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
273 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
274 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
275 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
276 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
277 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
278 // CHECK1: omp.inner.for.inc:
279 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
280 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
281 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
282 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
283 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
284 // CHECK1: omp.inner.for.end:
285 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
286 // CHECK1: omp.loop.exit:
287 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
288 // CHECK1-NEXT: ret void
289 //
290 //
291 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
292 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
293 // CHECK1-NEXT: entry:
294 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
295 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
296 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
297 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
298 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
299 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
300 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
303 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
304 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
305 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
306 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
307 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
308 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
309 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
310 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
311 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
312 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
313 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
314 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
315 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
316 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
317 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
318 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
319 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
320 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
321 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
322 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
323 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
324 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
325 // CHECK1: cond.true:
326 // CHECK1-NEXT: br label [[COND_END:%.*]]
327 // CHECK1: cond.false:
328 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
329 // CHECK1-NEXT: br label [[COND_END]]
330 // CHECK1: cond.end:
331 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
332 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
333 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
334 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
335 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
336 // CHECK1: omp.inner.for.cond:
337 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
338 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
339 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
340 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
341 // CHECK1: omp.inner.for.body:
342 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
343 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
344 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
345 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
346 // CHECK1-NEXT: invoke void @_Z3foov()
347 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
348 // CHECK1: invoke.cont:
349 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
350 // CHECK1: omp.body.continue:
351 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
352 // CHECK1: omp.inner.for.inc:
353 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
354 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
355 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
356 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
357 // CHECK1: omp.inner.for.end:
358 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
359 // CHECK1: omp.loop.exit:
360 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
361 // CHECK1-NEXT: ret void
362 // CHECK1: terminate.lpad:
363 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
364 // CHECK1-NEXT: catch i8* null
365 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
366 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9:[0-9]+]]
367 // CHECK1-NEXT: unreachable
368 //
369 //
370 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate
371 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
372 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
373 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR9]]
374 // CHECK1-NEXT: unreachable
375 //
376 //
377 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
378 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
379 // CHECK1-NEXT: entry:
380 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
381 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
382 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
383 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
384 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
385 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
386 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
387 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
388 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
389 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
390 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
391 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
392 // CHECK1-NEXT: ret void
393 //
394 //
395 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
396 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
397 // CHECK1-NEXT: entry:
398 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
399 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
400 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
401 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
402 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
403 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
404 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
405 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
406 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
407 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
408 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
409 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
410 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
411 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
412 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
413 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
414 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
415 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
416 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
417 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
418 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
419 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
420 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
421 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
422 // CHECK1: cond.true:
423 // CHECK1-NEXT: br label [[COND_END:%.*]]
424 // CHECK1: cond.false:
425 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
426 // CHECK1-NEXT: br label [[COND_END]]
427 // CHECK1: cond.end:
428 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
429 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
430 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
431 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
432 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
433 // CHECK1: omp.inner.for.cond:
434 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
435 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
436 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
437 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
438 // CHECK1: omp.inner.for.body:
439 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
440 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
441 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
442 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
443 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
444 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
445 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
446 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
447 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
448 // CHECK1: omp.inner.for.inc:
449 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
450 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
451 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
452 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
453 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
454 // CHECK1: omp.inner.for.end:
455 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
456 // CHECK1: omp.loop.exit:
457 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
458 // CHECK1-NEXT: ret void
459 //
460 //
461 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
462 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
463 // CHECK1-NEXT: entry:
464 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
465 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
466 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
467 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
468 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
469 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
470 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
471 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
472 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
473 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
474 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
475 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
476 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
477 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
478 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
479 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
480 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
481 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
482 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
483 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
484 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
485 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
486 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
487 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
488 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
489 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
490 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
491 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
492 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
493 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
494 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
495 // CHECK1: cond.true:
496 // CHECK1-NEXT: br label [[COND_END:%.*]]
497 // CHECK1: cond.false:
498 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
499 // CHECK1-NEXT: br label [[COND_END]]
500 // CHECK1: cond.end:
501 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
502 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
503 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
504 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
505 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
506 // CHECK1: omp.inner.for.cond:
507 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
508 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
509 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
510 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
511 // CHECK1: omp.inner.for.body:
512 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
513 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
514 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
515 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
516 // CHECK1-NEXT: invoke void @_Z3foov()
517 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
518 // CHECK1: invoke.cont:
519 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
520 // CHECK1: omp.body.continue:
521 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
522 // CHECK1: omp.inner.for.inc:
523 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
524 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
525 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
526 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
527 // CHECK1: omp.inner.for.end:
528 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
529 // CHECK1: omp.loop.exit:
530 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
531 // CHECK1-NEXT: ret void
532 // CHECK1: terminate.lpad:
533 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
534 // CHECK1-NEXT: catch i8* null
535 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
536 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
537 // CHECK1-NEXT: unreachable
538 //
539 //
540 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
541 // CHECK1-SAME: () #[[ATTR2]] comdat {
542 // CHECK1-NEXT: entry:
543 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
544 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
545 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
546 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
547 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
548 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
549 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
550 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
551 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
552 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
553 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
554 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
555 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
556 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
557 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
558 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
559 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
560 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
561 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
562 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
563 // CHECK1-NEXT: store i64 100, i64* [[TMP8]], align 8
564 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 5, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
565 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
566 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
567 // CHECK1: omp_offload.failed:
568 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]]
569 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
570 // CHECK1: omp_offload.cont:
571 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
572 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
573 // CHECK1-NEXT: store i32 1, i32* [[TMP11]], align 4
574 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
575 // CHECK1-NEXT: store i32 0, i32* [[TMP12]], align 4
576 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
577 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8
578 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
579 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8
580 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
581 // CHECK1-NEXT: store i64* null, i64** [[TMP15]], align 8
582 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
583 // CHECK1-NEXT: store i64* null, i64** [[TMP16]], align 8
584 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
585 // CHECK1-NEXT: store i8** null, i8*** [[TMP17]], align 8
586 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
587 // CHECK1-NEXT: store i8** null, i8*** [[TMP18]], align 8
588 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
589 // CHECK1-NEXT: store i64 100, i64* [[TMP19]], align 8
590 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 23, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
591 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
592 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
593 // CHECK1: omp_offload.failed3:
594 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]]
595 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
596 // CHECK1: omp_offload.cont4:
597 // CHECK1-NEXT: ret i32 0
598 //
599 //
600 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv
601 // CHECK1-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
602 // CHECK1-NEXT: entry:
603 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
604 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
605 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
606 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
607 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
608 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
609 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
610 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
611 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
612 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
613 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
614 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
615 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
616 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
617 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
618 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
619 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
620 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
621 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
622 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
623 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
624 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
625 // CHECK1-NEXT: store i64 100, i64* [[TMP8]], align 8
626 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
627 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
628 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
629 // CHECK1: omp_offload.failed:
630 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]]
631 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
632 // CHECK1: omp_offload.cont:
633 // CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
634 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
635 // CHECK1: invoke.cont:
636 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
637 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
638 // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
639 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
640 // CHECK1-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32
641 // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
642 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
643 // CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4
644 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
645 // CHECK1-NEXT: store i32 0, i32* [[TMP14]], align 4
646 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
647 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8
648 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
649 // CHECK1-NEXT: store i8** null, i8*** [[TMP16]], align 8
650 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
651 // CHECK1-NEXT: store i64* null, i64** [[TMP17]], align 8
652 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
653 // CHECK1-NEXT: store i64* null, i64** [[TMP18]], align 8
654 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
655 // CHECK1-NEXT: store i8** null, i8*** [[TMP19]], align 8
656 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
657 // CHECK1-NEXT: store i8** null, i8*** [[TMP20]], align 8
658 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
659 // CHECK1-NEXT: store i64 100, i64* [[TMP21]], align 8
660 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
661 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
662 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
663 // CHECK1: omp_offload.failed3:
664 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]]
665 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
666 // CHECK1: omp_offload.cont4:
667 // CHECK1-NEXT: ret i32 0
668 // CHECK1: terminate.lpad:
669 // CHECK1-NEXT: [[TMP24:%.*]] = landingpad { i8*, i32 }
670 // CHECK1-NEXT: catch i8* null
671 // CHECK1-NEXT: [[TMP25:%.*]] = extractvalue { i8*, i32 } [[TMP24]], 0
672 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP25]]) #[[ATTR9]]
673 // CHECK1-NEXT: unreachable
674 //
675 //
676 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev
677 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 {
678 // CHECK1-NEXT: entry:
679 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
680 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
681 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
682 // CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
683 // CHECK1-NEXT: ret void
684 //
685 //
686 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El
687 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
688 // CHECK1-NEXT: entry:
689 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
690 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
691 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
692 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
693 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
694 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
695 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
696 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8
697 // CHECK1-NEXT: ret void
698 //
699 //
700 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev
701 // CHECK1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
702 // CHECK1-NEXT: entry:
703 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
704 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
705 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
706 // CHECK1-NEXT: ret void
707 //
708 //
709 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36
710 // CHECK1-SAME: () #[[ATTR3]] {
711 // CHECK1-NEXT: entry:
712 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
713 // CHECK1-NEXT: ret void
714 //
715 //
716 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
717 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
718 // CHECK1-NEXT: entry:
719 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
720 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
721 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
722 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
723 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
724 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
725 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
726 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
727 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
728 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
729 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
730 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
731 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
732 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
733 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
734 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
735 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
736 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
737 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
738 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
739 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
740 // CHECK1: cond.true:
741 // CHECK1-NEXT: br label [[COND_END:%.*]]
742 // CHECK1: cond.false:
743 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
744 // CHECK1-NEXT: br label [[COND_END]]
745 // CHECK1: cond.end:
746 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
747 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
748 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
749 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
750 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
751 // CHECK1: omp.inner.for.cond:
752 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
753 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
754 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
755 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
756 // CHECK1: omp.inner.for.body:
757 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)
758 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
759 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
760 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
761 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
762 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
763 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
764 // CHECK1: omp.inner.for.inc:
765 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
766 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
767 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
768 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
769 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
770 // CHECK1: omp.inner.for.end:
771 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
772 // CHECK1: omp.loop.exit:
773 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
774 // CHECK1-NEXT: ret void
775 //
776 //
777 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
778 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
779 // CHECK1-NEXT: entry:
780 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
781 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
782 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
783 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
784 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
785 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
786 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
787 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
788 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
789 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
790 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
791 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
792 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
793 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
794 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
795 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
796 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
797 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
798 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
799 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
800 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
801 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
802 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
803 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
804 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
805 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
806 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
807 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
808 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
809 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
810 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
811 // CHECK1: cond.true:
812 // CHECK1-NEXT: br label [[COND_END:%.*]]
813 // CHECK1: cond.false:
814 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
815 // CHECK1-NEXT: br label [[COND_END]]
816 // CHECK1: cond.end:
817 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
818 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
819 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
820 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
821 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
822 // CHECK1: omp.inner.for.cond:
823 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
824 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
825 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
826 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
827 // CHECK1: omp.inner.for.body:
828 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
829 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
830 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
831 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
832 // CHECK1-NEXT: invoke void @_Z3foov()
833 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
834 // CHECK1: invoke.cont:
835 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
836 // CHECK1: omp.body.continue:
837 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
838 // CHECK1: omp.inner.for.inc:
839 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
840 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
841 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
842 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
843 // CHECK1: omp.inner.for.end:
844 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
845 // CHECK1: omp.loop.exit:
846 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
847 // CHECK1-NEXT: ret void
848 // CHECK1: terminate.lpad:
849 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
850 // CHECK1-NEXT: catch i8* null
851 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
852 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
853 // CHECK1-NEXT: unreachable
854 //
855 //
856 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40
857 // CHECK1-SAME: () #[[ATTR3]] {
858 // CHECK1-NEXT: entry:
859 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*))
860 // CHECK1-NEXT: ret void
861 //
862 //
863 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
864 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
865 // CHECK1-NEXT: entry:
866 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
867 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
868 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
869 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
870 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
871 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
872 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
873 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
874 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
875 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
876 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
877 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
878 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
879 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
880 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
881 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
882 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
883 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
884 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
885 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
886 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
887 // CHECK1: cond.true:
888 // CHECK1-NEXT: br label [[COND_END:%.*]]
889 // CHECK1: cond.false:
890 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
891 // CHECK1-NEXT: br label [[COND_END]]
892 // CHECK1: cond.end:
893 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
894 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
895 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
896 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
897 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
898 // CHECK1: omp.inner.for.cond:
899 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
900 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
901 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
902 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
903 // CHECK1: omp.inner.for.body:
904 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)
905 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
906 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
907 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
908 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
909 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
910 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
911 // CHECK1: omp.inner.for.inc:
912 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
913 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
914 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
915 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
916 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
917 // CHECK1: omp.inner.for.end:
918 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
919 // CHECK1: omp.loop.exit:
920 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
921 // CHECK1-NEXT: ret void
922 //
923 //
924 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
925 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
926 // CHECK1-NEXT: entry:
927 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
928 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
929 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
930 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
931 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
932 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
933 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
934 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
935 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
936 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
937 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
938 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
939 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
940 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
941 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
942 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
943 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
944 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
945 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
946 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
947 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
948 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
949 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
950 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
951 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
952 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
953 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
954 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
955 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
956 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
957 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
958 // CHECK1: cond.true:
959 // CHECK1-NEXT: br label [[COND_END:%.*]]
960 // CHECK1: cond.false:
961 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
962 // CHECK1-NEXT: br label [[COND_END]]
963 // CHECK1: cond.end:
964 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
965 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
966 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
967 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
968 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
969 // CHECK1: omp.inner.for.cond:
970 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
971 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
972 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
973 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
974 // CHECK1: omp.inner.for.body:
975 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
976 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
977 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
978 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
979 // CHECK1-NEXT: invoke void @_Z3foov()
980 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
981 // CHECK1: invoke.cont:
982 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
983 // CHECK1: omp.body.continue:
984 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
985 // CHECK1: omp.inner.for.inc:
986 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
987 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
988 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
989 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
990 // CHECK1: omp.inner.for.end:
991 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
992 // CHECK1: omp.loop.exit:
993 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
994 // CHECK1-NEXT: ret void
995 // CHECK1: terminate.lpad:
996 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
997 // CHECK1-NEXT: catch i8* null
998 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
999 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
1000 // CHECK1-NEXT: unreachable
1001 //
1002 //
1003 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36
1004 // CHECK1-SAME: () #[[ATTR3]] {
1005 // CHECK1-NEXT: entry:
1006 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*))
1007 // CHECK1-NEXT: ret void
1008 //
1009 //
1010 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8
1011 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
1012 // CHECK1-NEXT: entry:
1013 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1014 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1015 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1016 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1017 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1018 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1019 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1020 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1021 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1022 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1023 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1024 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1025 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1026 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1027 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1028 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1029 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1030 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1031 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1032 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1033 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1034 // CHECK1: cond.true:
1035 // CHECK1-NEXT: br label [[COND_END:%.*]]
1036 // CHECK1: cond.false:
1037 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1038 // CHECK1-NEXT: br label [[COND_END]]
1039 // CHECK1: cond.end:
1040 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1041 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1042 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1043 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1044 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1045 // CHECK1: omp.inner.for.cond:
1046 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1047 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1048 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1049 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1050 // CHECK1: omp.inner.for.body:
1051 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)
1052 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1053 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1054 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1055 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1056 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
1057 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1058 // CHECK1: omp.inner.for.inc:
1059 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1060 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1061 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1062 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1063 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1064 // CHECK1: omp.inner.for.end:
1065 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1066 // CHECK1: omp.loop.exit:
1067 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1068 // CHECK1-NEXT: ret void
1069 //
1070 //
1071 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1072 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1073 // CHECK1-NEXT: entry:
1074 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1075 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1076 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1077 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1078 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1079 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1080 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1081 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1082 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1083 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1084 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1085 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1086 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1087 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1088 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1089 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1090 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1091 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1092 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1093 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1094 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1095 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1096 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1097 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1098 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1099 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1100 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1101 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1102 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1103 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1104 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1105 // CHECK1: cond.true:
1106 // CHECK1-NEXT: br label [[COND_END:%.*]]
1107 // CHECK1: cond.false:
1108 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1109 // CHECK1-NEXT: br label [[COND_END]]
1110 // CHECK1: cond.end:
1111 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1112 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1113 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1114 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1115 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1116 // CHECK1: omp.inner.for.cond:
1117 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1118 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1119 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1120 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1121 // CHECK1: omp.inner.for.body:
1122 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1123 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1124 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1125 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1126 // CHECK1-NEXT: invoke void @_Z3foov()
1127 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1128 // CHECK1: invoke.cont:
1129 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1130 // CHECK1: omp.body.continue:
1131 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1132 // CHECK1: omp.inner.for.inc:
1133 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1134 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1135 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
1136 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1137 // CHECK1: omp.inner.for.end:
1138 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1139 // CHECK1: omp.loop.exit:
1140 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1141 // CHECK1-NEXT: ret void
1142 // CHECK1: terminate.lpad:
1143 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
1144 // CHECK1-NEXT: catch i8* null
1145 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
1146 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
1147 // CHECK1-NEXT: unreachable
1148 //
1149 //
1150 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40
1151 // CHECK1-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1152 // CHECK1-NEXT: entry:
1153 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1154 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1155 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1156 // CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
1157 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1158 // CHECK1: invoke.cont:
1159 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
1160 // CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
1161 // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1162 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1163 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
1164 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
1165 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1166 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]])
1167 // CHECK1-NEXT: ret void
1168 // CHECK1: terminate.lpad:
1169 // CHECK1-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 }
1170 // CHECK1-NEXT: catch i8* null
1171 // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0
1172 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP3]]) #[[ATTR9]]
1173 // CHECK1-NEXT: unreachable
1174 //
1175 //
1176 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
1177 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
1178 // CHECK1-NEXT: entry:
1179 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1180 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1181 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1182 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1183 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1184 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1185 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1186 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1187 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1188 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1189 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1190 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1191 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1192 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1193 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1194 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1195 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1196 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1197 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1198 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1199 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1200 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1201 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1202 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1203 // CHECK1: cond.true:
1204 // CHECK1-NEXT: br label [[COND_END:%.*]]
1205 // CHECK1: cond.false:
1206 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1207 // CHECK1-NEXT: br label [[COND_END]]
1208 // CHECK1: cond.end:
1209 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1210 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1211 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1212 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1213 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1214 // CHECK1: omp.inner.for.cond:
1215 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1216 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1217 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1218 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1219 // CHECK1: omp.inner.for.body:
1220 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
1221 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
1222 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
1223 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1224 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1225 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1226 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1227 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
1228 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1229 // CHECK1: omp.inner.for.inc:
1230 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1231 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1232 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
1233 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1234 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1235 // CHECK1: omp.inner.for.end:
1236 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1237 // CHECK1: omp.loop.exit:
1238 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1239 // CHECK1-NEXT: ret void
1240 //
1241 //
1242 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
1243 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1244 // CHECK1-NEXT: entry:
1245 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1246 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1247 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1248 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1249 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1250 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1251 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1252 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1253 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1254 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1255 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1256 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1257 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1258 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1259 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1260 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1261 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1262 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1263 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1264 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1265 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1266 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1267 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1268 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1269 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1270 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1271 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1272 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1273 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1274 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1275 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1276 // CHECK1: cond.true:
1277 // CHECK1-NEXT: br label [[COND_END:%.*]]
1278 // CHECK1: cond.false:
1279 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1280 // CHECK1-NEXT: br label [[COND_END]]
1281 // CHECK1: cond.end:
1282 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1283 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1284 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1285 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1286 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1287 // CHECK1: omp.inner.for.cond:
1288 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1289 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1290 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1291 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1292 // CHECK1: omp.inner.for.body:
1293 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1294 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1295 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1296 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1297 // CHECK1-NEXT: invoke void @_Z3foov()
1298 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1299 // CHECK1: invoke.cont:
1300 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1301 // CHECK1: omp.body.continue:
1302 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1303 // CHECK1: omp.inner.for.inc:
1304 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1305 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1306 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
1307 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1308 // CHECK1: omp.inner.for.end:
1309 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1310 // CHECK1: omp.loop.exit:
1311 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1312 // CHECK1-NEXT: ret void
1313 // CHECK1: terminate.lpad:
1314 // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
1315 // CHECK1-NEXT: catch i8* null
1316 // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
1317 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
1318 // CHECK1-NEXT: unreachable
1319 //
1320 //
1321 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1322 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" {
1323 // CHECK1-NEXT: entry:
1324 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1325 // CHECK1-NEXT: ret void
1326 //
1327 //
1328 // CHECK5-LABEL: define {{[^@]+}}@main
1329 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1330 // CHECK5-NEXT: entry:
1331 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1332 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1333 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1
1334 // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8
1335 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1336 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1337 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1338 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
1339 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
1340 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
1341 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1342 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1343 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1344 // CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0)
1345 // CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]])
1346 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1347 // CHECK5: invoke.cont:
1348 // CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1
1349 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1350 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1351 // CHECK5-NEXT: store i32 1, i32* [[TMP0]], align 4
1352 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1353 // CHECK5-NEXT: store i32 0, i32* [[TMP1]], align 4
1354 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1355 // CHECK5-NEXT: store i8** null, i8*** [[TMP2]], align 8
1356 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1357 // CHECK5-NEXT: store i8** null, i8*** [[TMP3]], align 8
1358 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1359 // CHECK5-NEXT: store i64* null, i64** [[TMP4]], align 8
1360 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1361 // CHECK5-NEXT: store i64* null, i64** [[TMP5]], align 8
1362 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1363 // CHECK5-NEXT: store i8** null, i8*** [[TMP6]], align 8
1364 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1365 // CHECK5-NEXT: store i8** null, i8*** [[TMP7]], align 8
1366 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1367 // CHECK5-NEXT: store i64 100, i64* [[TMP8]], align 8
1368 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1369 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1370 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1371 // CHECK5: omp_offload.failed:
1372 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]]
1373 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1374 // CHECK5: lpad:
1375 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
1376 // CHECK5-NEXT: cleanup
1377 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
1378 // CHECK5-NEXT: store i8* [[TMP12]], i8** [[EXN_SLOT]], align 8
1379 // CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 1
1380 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[EHSELECTOR_SLOT]], align 4
1381 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
1382 // CHECK5-NEXT: br label [[EH_RESUME:%.*]]
1383 // CHECK5: omp_offload.cont:
1384 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1
1385 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i8*
1386 // CHECK5-NEXT: store i8 [[TMP14]], i8* [[CONV]], align 1
1387 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[A_CASTED]], align 8
1388 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1389 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1390 // CHECK5-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
1391 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1392 // CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1393 // CHECK5-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
1394 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1395 // CHECK5-NEXT: store i8* null, i8** [[TMP20]], align 8
1396 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1397 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1398 // CHECK5-NEXT: [[TMP23:%.*]] = load i8, i8* [[A]], align 1
1399 // CHECK5-NEXT: store i8 [[TMP23]], i8* [[DOTCAPTURE_EXPR_]], align 1
1400 // CHECK5-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1401 // CHECK5-NEXT: [[TMP25:%.*]] = zext i8 [[TMP24]] to i32
1402 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1403 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
1404 // CHECK5-NEXT: store i32 1, i32* [[TMP26]], align 4
1405 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
1406 // CHECK5-NEXT: store i32 1, i32* [[TMP27]], align 4
1407 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
1408 // CHECK5-NEXT: store i8** [[TMP21]], i8*** [[TMP28]], align 8
1409 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
1410 // CHECK5-NEXT: store i8** [[TMP22]], i8*** [[TMP29]], align 8
1411 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
1412 // CHECK5-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP30]], align 8
1413 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
1414 // CHECK5-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8
1415 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
1416 // CHECK5-NEXT: store i8** null, i8*** [[TMP32]], align 8
1417 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
1418 // CHECK5-NEXT: store i8** null, i8*** [[TMP33]], align 8
1419 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
1420 // CHECK5-NEXT: store i64 100, i64* [[TMP34]], align 8
1421 // CHECK5-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP25]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
1422 // CHECK5-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
1423 // CHECK5-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
1424 // CHECK5: omp_offload.failed3:
1425 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR6]]
1426 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]]
1427 // CHECK5: omp_offload.cont4:
1428 // CHECK5-NEXT: [[TMP37:%.*]] = load i8, i8* [[A]], align 1
1429 // CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP37]] to i32
1430 // CHECK5-NEXT: [[CALL7:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv()
1431 // CHECK5-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[LPAD]]
1432 // CHECK5: invoke.cont6:
1433 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV5]], [[CALL7]]
1434 // CHECK5-NEXT: [[CALL9:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv()
1435 // CHECK5-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD]]
1436 // CHECK5: invoke.cont8:
1437 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD]], [[CALL9]]
1438 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[RETVAL]], align 4
1439 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]]
1440 // CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[RETVAL]], align 4
1441 // CHECK5-NEXT: ret i32 [[TMP38]]
1442 // CHECK5: eh.resume:
1443 // CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8
1444 // CHECK5-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4
1445 // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0
1446 // CHECK5-NEXT: [[LPAD_VAL11:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1447 // CHECK5-NEXT: resume { i8*, i32 } [[LPAD_VAL11]]
1448 //
1449 //
1450 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El
1451 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1452 // CHECK5-NEXT: entry:
1453 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1454 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1455 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1456 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1457 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1458 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
1459 // CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
1460 // CHECK5-NEXT: ret void
1461 //
1462 //
1463 // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv
1464 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
1465 // CHECK5-NEXT: entry:
1466 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1467 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1468 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1469 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1470 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8
1471 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
1472 // CHECK5-NEXT: ret i8 [[CONV]]
1473 //
1474 //
1475 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50
1476 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1477 // CHECK5-NEXT: entry:
1478 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1479 // CHECK5-NEXT: ret void
1480 //
1481 //
1482 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
1483 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
1484 // CHECK5-NEXT: entry:
1485 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1486 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1487 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1488 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1489 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1490 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1491 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1492 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1493 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1494 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1495 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1496 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1497 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1498 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1499 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1500 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1501 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1502 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1503 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1504 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1505 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1506 // CHECK5: cond.true:
1507 // CHECK5-NEXT: br label [[COND_END:%.*]]
1508 // CHECK5: cond.false:
1509 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1510 // CHECK5-NEXT: br label [[COND_END]]
1511 // CHECK5: cond.end:
1512 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1513 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1514 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1515 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1516 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1517 // CHECK5: omp.inner.for.cond:
1518 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1519 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1520 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1521 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1522 // CHECK5: omp.inner.for.body:
1523 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)
1524 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1525 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1526 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1527 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1528 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
1529 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1530 // CHECK5: omp.inner.for.inc:
1531 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1532 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1533 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1534 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1535 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1536 // CHECK5: omp.inner.for.end:
1537 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1538 // CHECK5: omp.loop.exit:
1539 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1540 // CHECK5-NEXT: ret void
1541 //
1542 //
1543 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
1544 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1545 // CHECK5-NEXT: entry:
1546 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1547 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1548 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1549 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1550 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1551 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1552 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1553 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1554 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1555 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1556 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1557 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1558 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1559 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1560 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1561 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1562 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1563 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1564 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1565 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1566 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1567 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1568 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1569 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1570 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1571 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1572 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1573 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1574 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1575 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1576 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1577 // CHECK5: cond.true:
1578 // CHECK5-NEXT: br label [[COND_END:%.*]]
1579 // CHECK5: cond.false:
1580 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1581 // CHECK5-NEXT: br label [[COND_END]]
1582 // CHECK5: cond.end:
1583 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1584 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1585 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1586 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1587 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1588 // CHECK5: omp.inner.for.cond:
1589 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1590 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1591 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1592 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1593 // CHECK5: omp.inner.for.body:
1594 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1595 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1596 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1597 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1598 // CHECK5-NEXT: invoke void @_Z3foov()
1599 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1600 // CHECK5: invoke.cont:
1601 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1602 // CHECK5: omp.body.continue:
1603 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1604 // CHECK5: omp.inner.for.inc:
1605 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1606 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1607 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
1608 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1609 // CHECK5: omp.inner.for.end:
1610 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1611 // CHECK5: omp.loop.exit:
1612 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1613 // CHECK5-NEXT: ret void
1614 // CHECK5: terminate.lpad:
1615 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
1616 // CHECK5-NEXT: catch i8* null
1617 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
1618 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9:[0-9]+]]
1619 // CHECK5-NEXT: unreachable
1620 //
1621 //
1622 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate
1623 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
1624 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
1625 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR9]]
1626 // CHECK5-NEXT: unreachable
1627 //
1628 //
1629 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
1630 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
1631 // CHECK5-NEXT: entry:
1632 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1633 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1634 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1635 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1636 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
1637 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
1638 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
1639 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1640 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
1641 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
1642 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1643 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
1644 // CHECK5-NEXT: ret void
1645 //
1646 //
1647 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
1648 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
1649 // CHECK5-NEXT: entry:
1650 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1651 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1652 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1653 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1654 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1655 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1656 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1657 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1658 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1659 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1660 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1661 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1662 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1663 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1664 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1665 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1666 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1667 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1668 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1669 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1670 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1671 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1672 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1673 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1674 // CHECK5: cond.true:
1675 // CHECK5-NEXT: br label [[COND_END:%.*]]
1676 // CHECK5: cond.false:
1677 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1678 // CHECK5-NEXT: br label [[COND_END]]
1679 // CHECK5: cond.end:
1680 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1681 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1682 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1683 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1684 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1685 // CHECK5: omp.inner.for.cond:
1686 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1687 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1688 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1689 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1690 // CHECK5: omp.inner.for.body:
1691 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
1692 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
1693 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
1694 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1695 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1696 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1697 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1698 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
1699 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1700 // CHECK5: omp.inner.for.inc:
1701 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1702 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1703 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
1704 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1705 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1706 // CHECK5: omp.inner.for.end:
1707 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1708 // CHECK5: omp.loop.exit:
1709 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1710 // CHECK5-NEXT: ret void
1711 //
1712 //
1713 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
1714 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1715 // CHECK5-NEXT: entry:
1716 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1717 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1718 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1719 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1720 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1721 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1722 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1723 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1724 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1725 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1726 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1727 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1728 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1729 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1730 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1731 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1732 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1733 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1734 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1735 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1736 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1737 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1738 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1739 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1740 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1741 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1742 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1743 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1744 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1745 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1746 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1747 // CHECK5: cond.true:
1748 // CHECK5-NEXT: br label [[COND_END:%.*]]
1749 // CHECK5: cond.false:
1750 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1751 // CHECK5-NEXT: br label [[COND_END]]
1752 // CHECK5: cond.end:
1753 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1754 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1755 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1756 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1757 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1758 // CHECK5: omp.inner.for.cond:
1759 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1760 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1761 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1762 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1763 // CHECK5: omp.inner.for.body:
1764 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1765 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1766 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1767 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1768 // CHECK5-NEXT: invoke void @_Z3foov()
1769 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1770 // CHECK5: invoke.cont:
1771 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1772 // CHECK5: omp.body.continue:
1773 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1774 // CHECK5: omp.inner.for.inc:
1775 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1776 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1777 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
1778 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1779 // CHECK5: omp.inner.for.end:
1780 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1781 // CHECK5: omp.loop.exit:
1782 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1783 // CHECK5-NEXT: ret void
1784 // CHECK5: terminate.lpad:
1785 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
1786 // CHECK5-NEXT: catch i8* null
1787 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
1788 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
1789 // CHECK5-NEXT: unreachable
1790 //
1791 //
1792 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
1793 // CHECK5-SAME: () #[[ATTR2]] comdat {
1794 // CHECK5-NEXT: entry:
1795 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1796 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1797 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1798 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1799 // CHECK5-NEXT: store i32 1, i32* [[TMP0]], align 4
1800 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1801 // CHECK5-NEXT: store i32 0, i32* [[TMP1]], align 4
1802 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1803 // CHECK5-NEXT: store i8** null, i8*** [[TMP2]], align 8
1804 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1805 // CHECK5-NEXT: store i8** null, i8*** [[TMP3]], align 8
1806 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1807 // CHECK5-NEXT: store i64* null, i64** [[TMP4]], align 8
1808 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1809 // CHECK5-NEXT: store i64* null, i64** [[TMP5]], align 8
1810 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1811 // CHECK5-NEXT: store i8** null, i8*** [[TMP6]], align 8
1812 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1813 // CHECK5-NEXT: store i8** null, i8*** [[TMP7]], align 8
1814 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1815 // CHECK5-NEXT: store i64 100, i64* [[TMP8]], align 8
1816 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 5, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1817 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1818 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1819 // CHECK5: omp_offload.failed:
1820 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]]
1821 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1822 // CHECK5: omp_offload.cont:
1823 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1824 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
1825 // CHECK5-NEXT: store i32 1, i32* [[TMP11]], align 4
1826 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
1827 // CHECK5-NEXT: store i32 0, i32* [[TMP12]], align 4
1828 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
1829 // CHECK5-NEXT: store i8** null, i8*** [[TMP13]], align 8
1830 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
1831 // CHECK5-NEXT: store i8** null, i8*** [[TMP14]], align 8
1832 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
1833 // CHECK5-NEXT: store i64* null, i64** [[TMP15]], align 8
1834 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
1835 // CHECK5-NEXT: store i64* null, i64** [[TMP16]], align 8
1836 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
1837 // CHECK5-NEXT: store i8** null, i8*** [[TMP17]], align 8
1838 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
1839 // CHECK5-NEXT: store i8** null, i8*** [[TMP18]], align 8
1840 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
1841 // CHECK5-NEXT: store i64 100, i64* [[TMP19]], align 8
1842 // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 23, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
1843 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1844 // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
1845 // CHECK5: omp_offload.failed3:
1846 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]]
1847 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]]
1848 // CHECK5: omp_offload.cont4:
1849 // CHECK5-NEXT: ret i32 0
1850 //
1851 //
1852 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv
1853 // CHECK5-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
1854 // CHECK5-NEXT: entry:
1855 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1856 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1857 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1858 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1859 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1860 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1861 // CHECK5-NEXT: store i32 1, i32* [[TMP0]], align 4
1862 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1863 // CHECK5-NEXT: store i32 0, i32* [[TMP1]], align 4
1864 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1865 // CHECK5-NEXT: store i8** null, i8*** [[TMP2]], align 8
1866 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1867 // CHECK5-NEXT: store i8** null, i8*** [[TMP3]], align 8
1868 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1869 // CHECK5-NEXT: store i64* null, i64** [[TMP4]], align 8
1870 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1871 // CHECK5-NEXT: store i64* null, i64** [[TMP5]], align 8
1872 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1873 // CHECK5-NEXT: store i8** null, i8*** [[TMP6]], align 8
1874 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1875 // CHECK5-NEXT: store i8** null, i8*** [[TMP7]], align 8
1876 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1877 // CHECK5-NEXT: store i64 100, i64* [[TMP8]], align 8
1878 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1879 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1880 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1881 // CHECK5: omp_offload.failed:
1882 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]]
1883 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1884 // CHECK5: omp_offload.cont:
1885 // CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
1886 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1887 // CHECK5: invoke.cont:
1888 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
1889 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
1890 // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1891 // CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1892 // CHECK5-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32
1893 // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1894 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 0
1895 // CHECK5-NEXT: store i32 1, i32* [[TMP13]], align 4
1896 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 1
1897 // CHECK5-NEXT: store i32 0, i32* [[TMP14]], align 4
1898 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 2
1899 // CHECK5-NEXT: store i8** null, i8*** [[TMP15]], align 8
1900 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 3
1901 // CHECK5-NEXT: store i8** null, i8*** [[TMP16]], align 8
1902 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 4
1903 // CHECK5-NEXT: store i64* null, i64** [[TMP17]], align 8
1904 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 5
1905 // CHECK5-NEXT: store i64* null, i64** [[TMP18]], align 8
1906 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 6
1907 // CHECK5-NEXT: store i8** null, i8*** [[TMP19]], align 8
1908 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 7
1909 // CHECK5-NEXT: store i8** null, i8*** [[TMP20]], align 8
1910 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]], i32 0, i32 8
1911 // CHECK5-NEXT: store i64 100, i64* [[TMP21]], align 8
1912 // CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS2]])
1913 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1914 // CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
1915 // CHECK5: omp_offload.failed3:
1916 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]]
1917 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]]
1918 // CHECK5: omp_offload.cont4:
1919 // CHECK5-NEXT: ret i32 0
1920 // CHECK5: terminate.lpad:
1921 // CHECK5-NEXT: [[TMP24:%.*]] = landingpad { i8*, i32 }
1922 // CHECK5-NEXT: catch i8* null
1923 // CHECK5-NEXT: [[TMP25:%.*]] = extractvalue { i8*, i32 } [[TMP24]], 0
1924 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP25]]) #[[ATTR9]]
1925 // CHECK5-NEXT: unreachable
1926 //
1927 //
1928 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev
1929 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 {
1930 // CHECK5-NEXT: entry:
1931 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1932 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1933 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1934 // CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
1935 // CHECK5-NEXT: ret void
1936 //
1937 //
1938 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El
1939 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
1940 // CHECK5-NEXT: entry:
1941 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1942 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1943 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1944 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1945 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1946 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1947 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
1948 // CHECK5-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8
1949 // CHECK5-NEXT: ret void
1950 //
1951 //
1952 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36
1953 // CHECK5-SAME: () #[[ATTR3]] {
1954 // CHECK5-NEXT: entry:
1955 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
1956 // CHECK5-NEXT: ret void
1957 //
1958 //
1959 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
1960 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
1961 // CHECK5-NEXT: entry:
1962 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1963 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1964 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1965 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1966 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1967 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1968 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1969 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1970 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1971 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1972 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1973 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1974 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
1975 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1976 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1977 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1978 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1979 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1980 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1981 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
1982 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1983 // CHECK5: cond.true:
1984 // CHECK5-NEXT: br label [[COND_END:%.*]]
1985 // CHECK5: cond.false:
1986 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1987 // CHECK5-NEXT: br label [[COND_END]]
1988 // CHECK5: cond.end:
1989 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1990 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1991 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1992 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1993 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1994 // CHECK5: omp.inner.for.cond:
1995 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1996 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1997 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1998 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1999 // CHECK5: omp.inner.for.body:
2000 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)
2001 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2002 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2003 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2004 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2005 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
2006 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2007 // CHECK5: omp.inner.for.inc:
2008 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2009 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2010 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2011 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2012 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2013 // CHECK5: omp.inner.for.end:
2014 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2015 // CHECK5: omp.loop.exit:
2016 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2017 // CHECK5-NEXT: ret void
2018 //
2019 //
2020 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5
2021 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2022 // CHECK5-NEXT: entry:
2023 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2024 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2025 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2026 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2027 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2028 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2029 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2030 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2031 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2032 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2033 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2034 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2035 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2036 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2037 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2038 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2039 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2040 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2041 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2042 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2043 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2044 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2045 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2046 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2047 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2048 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2049 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2050 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2051 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2052 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2053 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2054 // CHECK5: cond.true:
2055 // CHECK5-NEXT: br label [[COND_END:%.*]]
2056 // CHECK5: cond.false:
2057 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2058 // CHECK5-NEXT: br label [[COND_END]]
2059 // CHECK5: cond.end:
2060 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2061 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2062 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2063 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2064 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2065 // CHECK5: omp.inner.for.cond:
2066 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2067 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2068 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2069 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2070 // CHECK5: omp.inner.for.body:
2071 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2072 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2073 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2074 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2075 // CHECK5-NEXT: invoke void @_Z3foov()
2076 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2077 // CHECK5: invoke.cont:
2078 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2079 // CHECK5: omp.body.continue:
2080 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2081 // CHECK5: omp.inner.for.inc:
2082 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2083 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2084 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
2085 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2086 // CHECK5: omp.inner.for.end:
2087 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2088 // CHECK5: omp.loop.exit:
2089 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2090 // CHECK5-NEXT: ret void
2091 // CHECK5: terminate.lpad:
2092 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
2093 // CHECK5-NEXT: catch i8* null
2094 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
2095 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
2096 // CHECK5-NEXT: unreachable
2097 //
2098 //
2099 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40
2100 // CHECK5-SAME: () #[[ATTR3]] {
2101 // CHECK5-NEXT: entry:
2102 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..6 to void (i32*, i32*, ...)*))
2103 // CHECK5-NEXT: ret void
2104 //
2105 //
2106 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6
2107 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
2108 // CHECK5-NEXT: entry:
2109 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2110 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2111 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2112 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2113 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2114 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2115 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2116 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2117 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2118 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2119 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2120 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2121 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2122 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2123 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2124 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2125 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2126 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2127 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2128 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2129 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2130 // CHECK5: cond.true:
2131 // CHECK5-NEXT: br label [[COND_END:%.*]]
2132 // CHECK5: cond.false:
2133 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2134 // CHECK5-NEXT: br label [[COND_END]]
2135 // CHECK5: cond.end:
2136 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2137 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2138 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2139 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2140 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2141 // CHECK5: omp.inner.for.cond:
2142 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2143 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2144 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2145 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2146 // CHECK5: omp.inner.for.body:
2147 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)
2148 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2149 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2150 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2151 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2152 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
2153 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2154 // CHECK5: omp.inner.for.inc:
2155 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2156 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2157 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2158 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2159 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2160 // CHECK5: omp.inner.for.end:
2161 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2162 // CHECK5: omp.loop.exit:
2163 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2164 // CHECK5-NEXT: ret void
2165 //
2166 //
2167 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
2168 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2169 // CHECK5-NEXT: entry:
2170 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2171 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2172 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2173 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2174 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2175 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2176 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2177 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2178 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2179 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2180 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2181 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2182 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2183 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2184 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2185 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2186 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2187 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2188 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2189 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2190 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2191 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2192 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2193 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2194 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2195 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2196 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2197 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2198 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2199 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2200 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2201 // CHECK5: cond.true:
2202 // CHECK5-NEXT: br label [[COND_END:%.*]]
2203 // CHECK5: cond.false:
2204 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2205 // CHECK5-NEXT: br label [[COND_END]]
2206 // CHECK5: cond.end:
2207 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2208 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2209 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2210 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2211 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2212 // CHECK5: omp.inner.for.cond:
2213 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2214 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2215 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2216 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2217 // CHECK5: omp.inner.for.body:
2218 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2219 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2220 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2221 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2222 // CHECK5-NEXT: invoke void @_Z3foov()
2223 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2224 // CHECK5: invoke.cont:
2225 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2226 // CHECK5: omp.body.continue:
2227 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2228 // CHECK5: omp.inner.for.inc:
2229 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2230 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2231 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
2232 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2233 // CHECK5: omp.inner.for.end:
2234 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2235 // CHECK5: omp.loop.exit:
2236 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2237 // CHECK5-NEXT: ret void
2238 // CHECK5: terminate.lpad:
2239 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
2240 // CHECK5-NEXT: catch i8* null
2241 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
2242 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
2243 // CHECK5-NEXT: unreachable
2244 //
2245 //
2246 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36
2247 // CHECK5-SAME: () #[[ATTR3]] {
2248 // CHECK5-NEXT: entry:
2249 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*))
2250 // CHECK5-NEXT: ret void
2251 //
2252 //
2253 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8
2254 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
2255 // CHECK5-NEXT: entry:
2256 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2257 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2258 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2259 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2260 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2261 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2262 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2263 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2264 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2265 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2266 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2267 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2268 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2269 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2270 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2271 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2272 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2273 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2274 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2275 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2276 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2277 // CHECK5: cond.true:
2278 // CHECK5-NEXT: br label [[COND_END:%.*]]
2279 // CHECK5: cond.false:
2280 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2281 // CHECK5-NEXT: br label [[COND_END]]
2282 // CHECK5: cond.end:
2283 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2284 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2285 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2286 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2287 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2288 // CHECK5: omp.inner.for.cond:
2289 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2290 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2291 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2292 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2293 // CHECK5: omp.inner.for.body:
2294 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)
2295 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2296 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2297 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2298 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2299 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
2300 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2301 // CHECK5: omp.inner.for.inc:
2302 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2303 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2304 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2305 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2306 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2307 // CHECK5: omp.inner.for.end:
2308 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2309 // CHECK5: omp.loop.exit:
2310 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2311 // CHECK5-NEXT: ret void
2312 //
2313 //
2314 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9
2315 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2316 // CHECK5-NEXT: entry:
2317 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2318 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2319 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2320 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2321 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2322 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2323 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2324 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2325 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2326 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2327 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2328 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2329 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2330 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2331 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2332 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2333 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2334 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2335 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2336 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2337 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2338 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2339 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2340 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2341 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2342 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2343 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2344 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2345 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2346 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2347 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2348 // CHECK5: cond.true:
2349 // CHECK5-NEXT: br label [[COND_END:%.*]]
2350 // CHECK5: cond.false:
2351 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2352 // CHECK5-NEXT: br label [[COND_END]]
2353 // CHECK5: cond.end:
2354 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2355 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2356 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2357 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2358 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2359 // CHECK5: omp.inner.for.cond:
2360 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2361 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2362 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2363 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2364 // CHECK5: omp.inner.for.body:
2365 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2366 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2367 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2368 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2369 // CHECK5-NEXT: invoke void @_Z3foov()
2370 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2371 // CHECK5: invoke.cont:
2372 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2373 // CHECK5: omp.body.continue:
2374 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2375 // CHECK5: omp.inner.for.inc:
2376 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2377 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2378 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
2379 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2380 // CHECK5: omp.inner.for.end:
2381 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2382 // CHECK5: omp.loop.exit:
2383 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2384 // CHECK5-NEXT: ret void
2385 // CHECK5: terminate.lpad:
2386 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
2387 // CHECK5-NEXT: catch i8* null
2388 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
2389 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
2390 // CHECK5-NEXT: unreachable
2391 //
2392 //
2393 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40
2394 // CHECK5-SAME: () #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2395 // CHECK5-NEXT: entry:
2396 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2397 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8
2398 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2399 // CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23)
2400 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2401 // CHECK5: invoke.cont:
2402 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
2403 // CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]
2404 // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2405 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2406 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
2407 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
2408 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2409 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2410 // CHECK5-NEXT: ret void
2411 // CHECK5: terminate.lpad:
2412 // CHECK5-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 }
2413 // CHECK5-NEXT: catch i8* null
2414 // CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0
2415 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP3]]) #[[ATTR9]]
2416 // CHECK5-NEXT: unreachable
2417 //
2418 //
2419 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10
2420 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
2421 // CHECK5-NEXT: entry:
2422 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2423 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2424 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2425 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2426 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2427 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2428 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2429 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2430 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2431 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2432 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2433 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2434 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2435 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2436 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2437 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_COMB_UB]], align 4
2438 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2439 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2440 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2441 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2442 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2443 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2444 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99
2445 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2446 // CHECK5: cond.true:
2447 // CHECK5-NEXT: br label [[COND_END:%.*]]
2448 // CHECK5: cond.false:
2449 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2450 // CHECK5-NEXT: br label [[COND_END]]
2451 // CHECK5: cond.end:
2452 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2453 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2454 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2455 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2456 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2457 // CHECK5: omp.inner.for.cond:
2458 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2459 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2460 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2461 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2462 // CHECK5: omp.inner.for.body:
2463 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
2464 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
2465 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
2466 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2467 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2468 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2469 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
2470 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
2471 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2472 // CHECK5: omp.inner.for.inc:
2473 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2474 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2475 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
2476 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2477 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2478 // CHECK5: omp.inner.for.end:
2479 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2480 // CHECK5: omp.loop.exit:
2481 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2482 // CHECK5-NEXT: ret void
2483 //
2484 //
2485 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11
2486 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
2487 // CHECK5-NEXT: entry:
2488 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2489 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2490 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2491 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2492 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2493 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2494 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2495 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2496 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2497 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2498 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2499 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2500 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2501 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2502 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2503 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2504 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2505 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2506 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2507 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2508 // CHECK5-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2509 // CHECK5-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2510 // CHECK5-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
2511 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2512 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2513 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2514 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2515 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2516 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2517 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2518 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2519 // CHECK5: cond.true:
2520 // CHECK5-NEXT: br label [[COND_END:%.*]]
2521 // CHECK5: cond.false:
2522 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2523 // CHECK5-NEXT: br label [[COND_END]]
2524 // CHECK5: cond.end:
2525 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2526 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2527 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2528 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2529 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2530 // CHECK5: omp.inner.for.cond:
2531 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2532 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2533 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2534 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2535 // CHECK5: omp.inner.for.body:
2536 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2537 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2538 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2539 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2540 // CHECK5-NEXT: invoke void @_Z3foov()
2541 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2542 // CHECK5: invoke.cont:
2543 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2544 // CHECK5: omp.body.continue:
2545 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2546 // CHECK5: omp.inner.for.inc:
2547 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2548 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2549 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
2550 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2551 // CHECK5: omp.inner.for.end:
2552 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2553 // CHECK5: omp.loop.exit:
2554 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2555 // CHECK5-NEXT: ret void
2556 // CHECK5: terminate.lpad:
2557 // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { i8*, i32 }
2558 // CHECK5-NEXT: catch i8* null
2559 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { i8*, i32 } [[TMP11]], 0
2560 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP12]]) #[[ATTR9]]
2561 // CHECK5-NEXT: unreachable
2562 //
2563 //
2564 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev
2565 // CHECK5-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 {
2566 // CHECK5-NEXT: entry:
2567 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2568 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2569 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2570 // CHECK5-NEXT: ret void
2571 //
2572 //
2573 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2574 // CHECK5-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" {
2575 // CHECK5-NEXT: entry:
2576 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
2577 // CHECK5-NEXT: ret void
2578 //
2579