1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute parallel for firstprivate(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global and bound tid vars 80 // skip loop vars 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 85 // Skip global and bound tid vars, and prev lb and ub vars 86 // skip loop vars 87 88 // use of private vars 89 [&]() { 90 g = 2; 91 g1 = 2; 92 sivar = 4; 93 94 }(); 95 } 96 }(); 97 return 0; 98 #else 99 #pragma omp target 100 #pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var, sivar) 101 for (int i = 0; i < 2; ++i) { 102 vec[i] = t_var; 103 s_arr[i] = var; 104 sivar += i; 105 } 106 return tmain<int>(); 107 #endif 108 } 109 110 111 112 113 114 // Skip global and bound tid vars 115 // Skip temp vars for loop 116 117 // param copy 118 119 // T_VAR and SIVAR 120 121 // preparation vars 122 123 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 124 125 // firstprivate(s_arr) 126 127 // firstprivate(var) 128 129 130 // Skip global and bound tid vars, and prev lb ub vars 131 // Skip temp vars for loop 132 133 // param copy 134 135 // T_VAR and SIVAR 136 137 // preparation vars 138 139 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 140 141 // firstprivate(s_arr) 142 143 // firstprivate(var) 144 145 146 147 148 149 150 // Skip global and bound tid vars 151 // Skip temp vars for loop 152 153 // param copy 154 155 // T_VAR and preparation variables 156 157 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 158 159 // firstprivate(s_arr) 160 161 // firstprivate(var) 162 163 164 // Skip global and bound tid vars 165 // Skip temp vars for loop 166 167 // param copy 168 169 // T_VAR and preparation variables 170 171 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 172 173 // firstprivate(s_arr) 174 175 // firstprivate(var) 176 177 178 #endif 179 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 180 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 181 // CHECK1-NEXT: entry: 182 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 183 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 184 // CHECK1-NEXT: ret void 185 // 186 // 187 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 188 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 189 // CHECK1-NEXT: entry: 190 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 191 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 193 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 194 // CHECK1-NEXT: ret void 195 // 196 // 197 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 198 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 199 // CHECK1-NEXT: entry: 200 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 201 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 202 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 203 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 204 // CHECK1-NEXT: ret void 205 // 206 // 207 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 208 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 209 // CHECK1-NEXT: entry: 210 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 211 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 213 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 214 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 215 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 216 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 217 // CHECK1-NEXT: ret void 218 // 219 // 220 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 221 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 222 // CHECK1-NEXT: entry: 223 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 224 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 225 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 226 // CHECK1-NEXT: ret void 227 // 228 // 229 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 230 // CHECK1-SAME: () #[[ATTR0]] { 231 // CHECK1-NEXT: entry: 232 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 233 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 234 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 235 // CHECK1-NEXT: ret void 236 // 237 // 238 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 239 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 240 // CHECK1-NEXT: entry: 241 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 242 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 243 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 244 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 245 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 246 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 247 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 248 // CHECK1-NEXT: ret void 249 // 250 // 251 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 252 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 253 // CHECK1-NEXT: entry: 254 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 255 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 256 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 257 // CHECK1: arraydestroy.body: 258 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 259 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 260 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 261 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 262 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 263 // CHECK1: arraydestroy.done1: 264 // CHECK1-NEXT: ret void 265 // 266 // 267 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 268 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 269 // CHECK1-NEXT: entry: 270 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 271 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 272 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 273 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 274 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 275 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 276 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 277 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 278 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 279 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 280 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 281 // CHECK1-NEXT: ret void 282 // 283 // 284 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 285 // CHECK1-SAME: () #[[ATTR0]] { 286 // CHECK1-NEXT: entry: 287 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 288 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 289 // CHECK1-NEXT: ret void 290 // 291 // 292 // CHECK1-LABEL: define {{[^@]+}}@main 293 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 294 // CHECK1-NEXT: entry: 295 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 297 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 298 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 299 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 300 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 301 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 303 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 304 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 305 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 306 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 307 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 308 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 309 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 310 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 311 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 312 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 313 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 314 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 315 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* 316 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 317 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 318 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 319 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 320 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 321 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8 322 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 323 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 324 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8 325 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 326 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 327 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 328 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 329 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 330 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 331 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 332 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 333 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 334 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 335 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 336 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 337 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 338 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 339 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 340 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 341 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 342 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 343 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 344 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 345 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 346 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 347 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 348 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 349 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 350 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 351 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 352 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 353 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 354 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 355 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 356 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 357 // CHECK1: omp_offload.failed: 358 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 359 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 360 // CHECK1: omp_offload.cont: 361 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 362 // CHECK1-NEXT: ret i32 [[CALL]] 363 // 364 // 365 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 366 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 367 // CHECK1-NEXT: entry: 368 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 369 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 370 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 371 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 372 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 373 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 374 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 375 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 376 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 377 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 378 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 379 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 380 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 381 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 382 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 383 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 384 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 385 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 386 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 387 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 388 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 389 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 390 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 391 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 392 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 393 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 394 // CHECK1-NEXT: ret void 395 // 396 // 397 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 398 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 399 // CHECK1-NEXT: entry: 400 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 401 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 402 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 403 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 404 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 405 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 406 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 407 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 408 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 409 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 410 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 411 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 412 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 413 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 414 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 415 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 416 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 417 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 418 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 419 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 420 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 421 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 422 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 423 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 424 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 425 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 426 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 427 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 428 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 429 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 430 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 431 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 432 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 433 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 434 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 435 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 436 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 437 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 438 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 439 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 440 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 441 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 442 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 443 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 444 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 445 // CHECK1: omp.arraycpy.body: 446 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 447 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 448 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 449 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 450 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 451 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 452 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 453 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 454 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 455 // CHECK1: omp.arraycpy.done4: 456 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 457 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 458 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 459 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 460 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 461 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 462 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 463 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 464 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 465 // CHECK1: cond.true: 466 // CHECK1-NEXT: br label [[COND_END:%.*]] 467 // CHECK1: cond.false: 468 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 469 // CHECK1-NEXT: br label [[COND_END]] 470 // CHECK1: cond.end: 471 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 472 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 473 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 474 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 475 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 476 // CHECK1: omp.inner.for.cond: 477 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 478 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 479 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 480 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 481 // CHECK1: omp.inner.for.cond.cleanup: 482 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 483 // CHECK1: omp.inner.for.body: 484 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 485 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 486 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 487 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 488 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 489 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 490 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 491 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 492 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 493 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 494 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 495 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 496 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) 497 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 498 // CHECK1: omp.inner.for.inc: 499 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 500 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 501 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] 502 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 503 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 504 // CHECK1: omp.inner.for.end: 505 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 506 // CHECK1: omp.loop.exit: 507 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 508 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 509 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) 510 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 511 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 512 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 513 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 514 // CHECK1: arraydestroy.body: 515 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 516 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 517 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 518 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 519 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 520 // CHECK1: arraydestroy.done11: 521 // CHECK1-NEXT: ret void 522 // 523 // 524 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 525 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 526 // CHECK1-NEXT: entry: 527 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 528 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 529 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 530 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 531 // CHECK1-NEXT: ret void 532 // 533 // 534 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 535 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 536 // CHECK1-NEXT: entry: 537 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 538 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 539 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 540 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 541 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 542 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 543 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 544 // CHECK1-NEXT: ret void 545 // 546 // 547 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 548 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 549 // CHECK1-NEXT: entry: 550 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 551 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 552 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 553 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 554 // CHECK1-NEXT: ret void 555 // 556 // 557 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 558 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 559 // CHECK1-NEXT: entry: 560 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 561 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 562 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 563 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 564 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 565 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 566 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 567 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 568 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 569 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 570 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 571 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 572 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 573 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 574 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 575 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 576 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 577 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 578 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 579 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 580 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 581 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 582 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 583 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 584 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 585 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 586 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 587 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 588 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 589 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 590 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 591 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 592 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 593 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 594 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 595 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 596 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 597 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 598 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 599 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 600 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 601 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 602 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 603 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 604 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 605 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* 606 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 607 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) 608 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 609 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 610 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 611 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] 612 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 613 // CHECK1: omp.arraycpy.body: 614 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 615 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 616 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 617 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 618 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 619 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 620 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 621 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 622 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 623 // CHECK1: omp.arraycpy.done6: 624 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) 625 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) 626 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] 627 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 628 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 629 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 630 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 631 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 632 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 633 // CHECK1: cond.true: 634 // CHECK1-NEXT: br label [[COND_END:%.*]] 635 // CHECK1: cond.false: 636 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 637 // CHECK1-NEXT: br label [[COND_END]] 638 // CHECK1: cond.end: 639 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 640 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 641 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 642 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 643 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 644 // CHECK1: omp.inner.for.cond: 645 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 646 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 647 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 648 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 649 // CHECK1: omp.inner.for.cond.cleanup: 650 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 651 // CHECK1: omp.inner.for.body: 652 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 653 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 654 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 655 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 656 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 657 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 658 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 659 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] 660 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 661 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 662 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 663 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] 664 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* 665 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* 666 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) 667 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 668 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 669 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] 670 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 671 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 672 // CHECK1: omp.body.continue: 673 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 674 // CHECK1: omp.inner.for.inc: 675 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 676 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 677 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 678 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 679 // CHECK1: omp.inner.for.end: 680 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 681 // CHECK1: omp.loop.exit: 682 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 683 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 684 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 685 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] 686 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 687 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 688 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 689 // CHECK1: arraydestroy.body: 690 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 691 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 692 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 693 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] 694 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] 695 // CHECK1: arraydestroy.done15: 696 // CHECK1-NEXT: ret void 697 // 698 // 699 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 700 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 701 // CHECK1-NEXT: entry: 702 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 703 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 704 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 705 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 706 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 707 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 708 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 709 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 710 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 711 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 712 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 713 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 714 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 715 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 716 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 717 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 718 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 719 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 720 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 721 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 722 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 723 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 724 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 725 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 726 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 727 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 728 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 729 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 730 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 731 // CHECK1-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 732 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 733 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 734 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 735 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 736 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 737 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 738 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 739 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 740 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 741 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 742 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 743 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 744 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 745 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 746 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 747 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 748 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 749 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 750 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 751 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 752 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 753 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 754 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 755 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 756 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 757 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 758 // CHECK1-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 759 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 760 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 761 // CHECK1-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 762 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 763 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 764 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 765 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 766 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 767 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 768 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 769 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 770 // CHECK1: omp_offload.failed: 771 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 772 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 773 // CHECK1: omp_offload.cont: 774 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 775 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 776 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 777 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 778 // CHECK1: arraydestroy.body: 779 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 780 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 781 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 782 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 783 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 784 // CHECK1: arraydestroy.done2: 785 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 786 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 787 // CHECK1-NEXT: ret i32 [[TMP32]] 788 // 789 // 790 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 791 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 792 // CHECK1-NEXT: entry: 793 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 794 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 795 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 796 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 797 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 798 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 799 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 800 // CHECK1-NEXT: ret void 801 // 802 // 803 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 804 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 805 // CHECK1-NEXT: entry: 806 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 807 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 808 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 809 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 810 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 811 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 812 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 813 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 814 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 815 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 816 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 817 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 818 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 819 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 820 // CHECK1-NEXT: ret void 821 // 822 // 823 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 824 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 825 // CHECK1-NEXT: entry: 826 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 827 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 828 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 829 // CHECK1-NEXT: ret void 830 // 831 // 832 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 833 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 834 // CHECK1-NEXT: entry: 835 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 836 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 837 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 838 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 839 // CHECK1-NEXT: ret void 840 // 841 // 842 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 843 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 844 // CHECK1-NEXT: entry: 845 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 846 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 847 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 848 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 849 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 850 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 851 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 852 // CHECK1-NEXT: ret void 853 // 854 // 855 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 856 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 857 // CHECK1-NEXT: entry: 858 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 859 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 860 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 861 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 862 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 863 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 864 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 865 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 866 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 867 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 868 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 869 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 870 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 871 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 872 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 873 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 874 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 875 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 876 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 877 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 878 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 879 // CHECK1-NEXT: ret void 880 // 881 // 882 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 883 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 884 // CHECK1-NEXT: entry: 885 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 886 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 887 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 888 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 889 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 890 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 891 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 892 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 893 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 894 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 895 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 896 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 897 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 898 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 899 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 900 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 901 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 902 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 903 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 904 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 905 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 906 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 907 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 908 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 909 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 910 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 911 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 912 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 913 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 914 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 915 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 916 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 917 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 918 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 919 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 920 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 921 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 922 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 923 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 924 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 925 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 926 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 927 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 928 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 929 // CHECK1: omp.arraycpy.body: 930 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 931 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 932 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 933 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 934 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 935 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 936 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 937 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 938 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 939 // CHECK1: omp.arraycpy.done4: 940 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 941 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 942 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 943 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 944 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 945 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 946 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 947 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 948 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 949 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 950 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 951 // CHECK1: cond.true: 952 // CHECK1-NEXT: br label [[COND_END:%.*]] 953 // CHECK1: cond.false: 954 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 955 // CHECK1-NEXT: br label [[COND_END]] 956 // CHECK1: cond.end: 957 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 958 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 959 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 960 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 961 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 962 // CHECK1: omp.inner.for.cond: 963 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 964 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 965 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 966 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 967 // CHECK1: omp.inner.for.cond.cleanup: 968 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 969 // CHECK1: omp.inner.for.body: 970 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 971 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 972 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 973 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 974 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 975 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 976 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 977 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 978 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 979 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) 980 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 981 // CHECK1: omp.inner.for.inc: 982 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 983 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 984 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] 985 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 986 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 987 // CHECK1: omp.inner.for.end: 988 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 989 // CHECK1: omp.loop.exit: 990 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 991 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 992 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) 993 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 994 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 995 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 996 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 997 // CHECK1: arraydestroy.body: 998 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 999 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1000 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1001 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1002 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1003 // CHECK1: arraydestroy.done11: 1004 // CHECK1-NEXT: ret void 1005 // 1006 // 1007 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1008 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1009 // CHECK1-NEXT: entry: 1010 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1011 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1012 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1013 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1014 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1015 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1016 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1017 // CHECK1-NEXT: ret void 1018 // 1019 // 1020 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 1021 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1022 // CHECK1-NEXT: entry: 1023 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1024 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1025 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1026 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1027 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1028 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1029 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1030 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1031 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1032 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1033 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1034 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1035 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1036 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1037 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1038 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 1039 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 1040 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1041 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1042 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 1043 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 1044 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1045 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1046 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1047 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1048 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1049 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1050 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1051 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1052 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1053 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1054 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1055 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1056 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1057 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1058 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1059 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1060 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1061 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 1062 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1063 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 1064 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 1065 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 1066 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1067 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1068 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* 1069 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1070 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) 1071 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 1072 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 1073 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1074 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 1075 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1076 // CHECK1: omp.arraycpy.body: 1077 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1078 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1079 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1080 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1081 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1082 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1083 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1084 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1085 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 1086 // CHECK1: omp.arraycpy.done6: 1087 // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1088 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) 1089 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) 1090 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] 1091 // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 1092 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1093 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 1094 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1095 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1096 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 1097 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1098 // CHECK1: cond.true: 1099 // CHECK1-NEXT: br label [[COND_END:%.*]] 1100 // CHECK1: cond.false: 1101 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1102 // CHECK1-NEXT: br label [[COND_END]] 1103 // CHECK1: cond.end: 1104 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 1105 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1106 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1107 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 1108 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1109 // CHECK1: omp.inner.for.cond: 1110 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1111 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1112 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 1113 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1114 // CHECK1: omp.inner.for.cond.cleanup: 1115 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1116 // CHECK1: omp.inner.for.body: 1117 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1118 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 1119 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1120 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1121 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 1122 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1123 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 1124 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] 1125 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 1126 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 1127 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 1128 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 1129 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] 1130 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* 1131 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* 1132 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) 1133 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1134 // CHECK1: omp.body.continue: 1135 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1136 // CHECK1: omp.inner.for.inc: 1137 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1138 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 1139 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 1140 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1141 // CHECK1: omp.inner.for.end: 1142 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1143 // CHECK1: omp.loop.exit: 1144 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1145 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 1146 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 1147 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] 1148 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 1149 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 1150 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1151 // CHECK1: arraydestroy.body: 1152 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1153 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1154 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1155 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] 1156 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] 1157 // CHECK1: arraydestroy.done15: 1158 // CHECK1-NEXT: ret void 1159 // 1160 // 1161 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1162 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1163 // CHECK1-NEXT: entry: 1164 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1165 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1166 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1167 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1168 // CHECK1-NEXT: ret void 1169 // 1170 // 1171 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1172 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1173 // CHECK1-NEXT: entry: 1174 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1175 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1176 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1177 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1178 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1179 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1180 // CHECK1-NEXT: ret void 1181 // 1182 // 1183 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1184 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1185 // CHECK1-NEXT: entry: 1186 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1187 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1188 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1189 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1190 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1191 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1192 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1193 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1194 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1195 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1196 // CHECK1-NEXT: ret void 1197 // 1198 // 1199 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1200 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1201 // CHECK1-NEXT: entry: 1202 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1203 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1204 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1205 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1206 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1207 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1208 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1209 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1210 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1211 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1212 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1213 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1214 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1215 // CHECK1-NEXT: ret void 1216 // 1217 // 1218 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1219 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1220 // CHECK1-NEXT: entry: 1221 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1222 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1223 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1224 // CHECK1-NEXT: ret void 1225 // 1226 // 1227 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 1228 // CHECK1-SAME: () #[[ATTR0]] { 1229 // CHECK1-NEXT: entry: 1230 // CHECK1-NEXT: call void @__cxx_global_var_init() 1231 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 1232 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 1233 // CHECK1-NEXT: ret void 1234 // 1235 // 1236 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1237 // CHECK1-SAME: () #[[ATTR0]] { 1238 // CHECK1-NEXT: entry: 1239 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1240 // CHECK1-NEXT: ret void 1241 // 1242 // 1243 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 1244 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 1245 // CHECK2-NEXT: entry: 1246 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1247 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1248 // CHECK2-NEXT: ret void 1249 // 1250 // 1251 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1252 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1253 // CHECK2-NEXT: entry: 1254 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1255 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1256 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1257 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1258 // CHECK2-NEXT: ret void 1259 // 1260 // 1261 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1262 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1263 // CHECK2-NEXT: entry: 1264 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1265 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1266 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1267 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1268 // CHECK2-NEXT: ret void 1269 // 1270 // 1271 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1272 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1273 // CHECK2-NEXT: entry: 1274 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1275 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1276 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1277 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1278 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1279 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1280 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 1281 // CHECK2-NEXT: ret void 1282 // 1283 // 1284 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1285 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1286 // CHECK2-NEXT: entry: 1287 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1288 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1289 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1290 // CHECK2-NEXT: ret void 1291 // 1292 // 1293 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1294 // CHECK2-SAME: () #[[ATTR0]] { 1295 // CHECK2-NEXT: entry: 1296 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 1297 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 1298 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1299 // CHECK2-NEXT: ret void 1300 // 1301 // 1302 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1303 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1304 // CHECK2-NEXT: entry: 1305 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1306 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1307 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1308 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1309 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1310 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1311 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1312 // CHECK2-NEXT: ret void 1313 // 1314 // 1315 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1316 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1317 // CHECK2-NEXT: entry: 1318 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1319 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1320 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1321 // CHECK2: arraydestroy.body: 1322 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1323 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1324 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1325 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1326 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1327 // CHECK2: arraydestroy.done1: 1328 // CHECK2-NEXT: ret void 1329 // 1330 // 1331 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1332 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1333 // CHECK2-NEXT: entry: 1334 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1335 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1336 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1337 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1338 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1339 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1340 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1341 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1342 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1343 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1344 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1345 // CHECK2-NEXT: ret void 1346 // 1347 // 1348 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1349 // CHECK2-SAME: () #[[ATTR0]] { 1350 // CHECK2-NEXT: entry: 1351 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1352 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1353 // CHECK2-NEXT: ret void 1354 // 1355 // 1356 // CHECK2-LABEL: define {{[^@]+}}@main 1357 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1358 // CHECK2-NEXT: entry: 1359 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1360 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1361 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1362 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1363 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1364 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1365 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1366 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1367 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1368 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1369 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1370 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1371 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1372 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1373 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 1374 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1375 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1376 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1377 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1378 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1379 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* 1380 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 1381 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1382 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 1383 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1384 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 1385 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8 1386 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1387 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 1388 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8 1389 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1390 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 1391 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1392 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1393 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 1394 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1395 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1396 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 1397 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1398 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 1399 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1400 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1401 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 1402 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1403 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1404 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 1405 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1406 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 1407 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1408 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1409 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 1410 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1411 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1412 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 1413 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1414 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8 1415 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1416 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1417 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 1418 // CHECK2-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1419 // CHECK2-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1420 // CHECK2-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1421 // CHECK2: omp_offload.failed: 1422 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 1423 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1424 // CHECK2: omp_offload.cont: 1425 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 1426 // CHECK2-NEXT: ret i32 [[CALL]] 1427 // 1428 // 1429 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 1430 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1431 // CHECK2-NEXT: entry: 1432 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1433 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1434 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1435 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1436 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1437 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1438 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1439 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1440 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1441 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1442 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1443 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1444 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1445 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1446 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1447 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1448 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1449 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1450 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1451 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 1452 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1453 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 1454 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1455 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 1456 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1457 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 1458 // CHECK2-NEXT: ret void 1459 // 1460 // 1461 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1462 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 1463 // CHECK2-NEXT: entry: 1464 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1465 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1466 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1467 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1468 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1469 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1470 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1471 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1472 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1473 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1474 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1475 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1476 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1477 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1478 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 1479 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1480 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1481 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1482 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1483 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1484 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1485 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1486 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1487 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1488 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1489 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1490 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1491 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1492 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1493 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1494 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1495 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1496 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1497 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 1498 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 1499 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1500 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1501 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1502 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1503 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1504 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1505 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1506 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1507 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1508 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1509 // CHECK2: omp.arraycpy.body: 1510 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1511 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1512 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1513 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1514 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1515 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1516 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1517 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1518 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1519 // CHECK2: omp.arraycpy.done4: 1520 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1521 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 1522 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1523 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1524 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1525 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1526 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1527 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1528 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1529 // CHECK2: cond.true: 1530 // CHECK2-NEXT: br label [[COND_END:%.*]] 1531 // CHECK2: cond.false: 1532 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1533 // CHECK2-NEXT: br label [[COND_END]] 1534 // CHECK2: cond.end: 1535 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1536 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1537 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1538 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 1539 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1540 // CHECK2: omp.inner.for.cond: 1541 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1542 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1543 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1544 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1545 // CHECK2: omp.inner.for.cond.cleanup: 1546 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1547 // CHECK2: omp.inner.for.body: 1548 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1549 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 1550 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1551 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 1552 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 1553 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1554 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 1555 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1556 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 1557 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1558 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 1559 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1560 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) 1561 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1562 // CHECK2: omp.inner.for.inc: 1563 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1564 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1565 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] 1566 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1567 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1568 // CHECK2: omp.inner.for.end: 1569 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1570 // CHECK2: omp.loop.exit: 1571 // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1572 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 1573 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) 1574 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1575 // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1576 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 1577 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1578 // CHECK2: arraydestroy.body: 1579 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1580 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1581 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1582 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1583 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1584 // CHECK2: arraydestroy.done11: 1585 // CHECK2-NEXT: ret void 1586 // 1587 // 1588 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1589 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1590 // CHECK2-NEXT: entry: 1591 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1592 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1593 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1594 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 1595 // CHECK2-NEXT: ret void 1596 // 1597 // 1598 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1599 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1600 // CHECK2-NEXT: entry: 1601 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1602 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1603 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1604 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1605 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1606 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1607 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1608 // CHECK2-NEXT: ret void 1609 // 1610 // 1611 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1612 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1613 // CHECK2-NEXT: entry: 1614 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1615 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1616 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1617 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1618 // CHECK2-NEXT: ret void 1619 // 1620 // 1621 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1622 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 1623 // CHECK2-NEXT: entry: 1624 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1625 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1626 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1627 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1628 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1629 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1630 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1631 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1632 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1633 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1634 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1635 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1636 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1637 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1638 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1639 // CHECK2-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 1640 // CHECK2-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 1641 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1642 // CHECK2-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1643 // CHECK2-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 1644 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1645 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1646 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1647 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1648 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1649 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1650 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1651 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1652 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1653 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1654 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1655 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1656 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1657 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1658 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1659 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1660 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1661 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1662 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 1663 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1664 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 1665 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 1666 // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 1667 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1668 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1669 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* 1670 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1671 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) 1672 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 1673 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1674 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1675 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] 1676 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1677 // CHECK2: omp.arraycpy.body: 1678 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1679 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1680 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1681 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1682 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1683 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1684 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1685 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1686 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 1687 // CHECK2: omp.arraycpy.done6: 1688 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) 1689 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) 1690 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] 1691 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1692 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1693 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1694 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1695 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 1696 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1697 // CHECK2: cond.true: 1698 // CHECK2-NEXT: br label [[COND_END:%.*]] 1699 // CHECK2: cond.false: 1700 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1701 // CHECK2-NEXT: br label [[COND_END]] 1702 // CHECK2: cond.end: 1703 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1704 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1705 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1706 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1707 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1708 // CHECK2: omp.inner.for.cond: 1709 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1710 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1711 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1712 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1713 // CHECK2: omp.inner.for.cond.cleanup: 1714 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1715 // CHECK2: omp.inner.for.body: 1716 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1717 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 1718 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1719 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1720 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 1721 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 1722 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 1723 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] 1724 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 1725 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1726 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 1727 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] 1728 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* 1729 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* 1730 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) 1731 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1732 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 1733 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] 1734 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 1735 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1736 // CHECK2: omp.body.continue: 1737 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1738 // CHECK2: omp.inner.for.inc: 1739 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1740 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 1741 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 1742 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1743 // CHECK2: omp.inner.for.end: 1744 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1745 // CHECK2: omp.loop.exit: 1746 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1747 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 1748 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 1749 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] 1750 // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 1751 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 1752 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1753 // CHECK2: arraydestroy.body: 1754 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1755 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1756 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1757 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] 1758 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] 1759 // CHECK2: arraydestroy.done15: 1760 // CHECK2-NEXT: ret void 1761 // 1762 // 1763 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1764 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat { 1765 // CHECK2-NEXT: entry: 1766 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1767 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1768 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1769 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1770 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1771 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1772 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1773 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1774 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1775 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1776 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1777 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1778 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1779 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 1780 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1781 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1782 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1783 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 1784 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1785 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 1786 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1787 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1788 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 1789 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 1790 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1791 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 1792 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1793 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1794 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1795 // CHECK2-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1796 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1797 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1798 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 1799 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1800 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1801 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 1802 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1803 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 1804 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1805 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1806 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 1807 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1808 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 1809 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 1810 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1811 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 1812 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1813 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 1814 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 1815 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1816 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 1817 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 1818 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1819 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 1820 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1821 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 1822 // CHECK2-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 1823 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1824 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 1825 // CHECK2-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 1826 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1827 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 1828 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1829 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1830 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 1831 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1832 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1833 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1834 // CHECK2: omp_offload.failed: 1835 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 1836 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1837 // CHECK2: omp_offload.cont: 1838 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1839 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1840 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1841 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1842 // CHECK2: arraydestroy.body: 1843 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1844 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1845 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1846 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1847 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1848 // CHECK2: arraydestroy.done2: 1849 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1850 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 1851 // CHECK2-NEXT: ret i32 [[TMP32]] 1852 // 1853 // 1854 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1855 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1856 // CHECK2-NEXT: entry: 1857 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1858 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1859 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1860 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1861 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1862 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1863 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4 1864 // CHECK2-NEXT: ret void 1865 // 1866 // 1867 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1868 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1869 // CHECK2-NEXT: entry: 1870 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1871 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1872 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1873 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1874 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1875 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1876 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1877 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1878 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1879 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1880 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1881 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1882 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1883 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1884 // CHECK2-NEXT: ret void 1885 // 1886 // 1887 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1888 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1889 // CHECK2-NEXT: entry: 1890 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1891 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1892 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1893 // CHECK2-NEXT: ret void 1894 // 1895 // 1896 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1897 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1898 // CHECK2-NEXT: entry: 1899 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1900 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1901 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1902 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1903 // CHECK2-NEXT: ret void 1904 // 1905 // 1906 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1907 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1908 // CHECK2-NEXT: entry: 1909 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1910 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1911 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1912 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1913 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1914 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1915 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 1916 // CHECK2-NEXT: ret void 1917 // 1918 // 1919 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1920 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1921 // CHECK2-NEXT: entry: 1922 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1923 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1924 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1925 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1926 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1927 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1928 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1929 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1930 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1931 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1932 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1933 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1934 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1935 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1936 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1937 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1938 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1939 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 1940 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1941 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1942 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 1943 // CHECK2-NEXT: ret void 1944 // 1945 // 1946 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1947 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1948 // CHECK2-NEXT: entry: 1949 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1950 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1951 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1952 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1953 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1954 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1955 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1956 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1957 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1958 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1959 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1960 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1961 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1962 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1963 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1964 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1965 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1966 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1967 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 1968 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1969 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1970 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1971 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1972 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1973 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1974 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1975 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1976 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1977 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1978 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1979 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1980 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1981 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 1982 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 1983 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1984 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1985 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1986 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1987 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1988 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1989 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 1990 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1991 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 1992 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1993 // CHECK2: omp.arraycpy.body: 1994 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1995 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1996 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1997 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1998 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1999 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2000 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2001 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2002 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2003 // CHECK2: omp.arraycpy.done4: 2004 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 2005 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2006 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 2007 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 2008 // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 2009 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2010 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2011 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2012 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2013 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 2014 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2015 // CHECK2: cond.true: 2016 // CHECK2-NEXT: br label [[COND_END:%.*]] 2017 // CHECK2: cond.false: 2018 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2019 // CHECK2-NEXT: br label [[COND_END]] 2020 // CHECK2: cond.end: 2021 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2022 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 2023 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2024 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2025 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2026 // CHECK2: omp.inner.for.cond: 2027 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2028 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2029 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2030 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2031 // CHECK2: omp.inner.for.cond.cleanup: 2032 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2033 // CHECK2: omp.inner.for.body: 2034 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2035 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 2036 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2037 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 2038 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 2039 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 2040 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 2041 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 2042 // CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 2043 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) 2044 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2045 // CHECK2: omp.inner.for.inc: 2046 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2047 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2048 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] 2049 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2050 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2051 // CHECK2: omp.inner.for.end: 2052 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2053 // CHECK2: omp.loop.exit: 2054 // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2055 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 2056 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) 2057 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2058 // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2059 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 2060 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2061 // CHECK2: arraydestroy.body: 2062 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2063 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2064 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2065 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2066 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2067 // CHECK2: arraydestroy.done11: 2068 // CHECK2-NEXT: ret void 2069 // 2070 // 2071 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2072 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2073 // CHECK2-NEXT: entry: 2074 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2075 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 2076 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2077 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 2078 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2079 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 2080 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2081 // CHECK2-NEXT: ret void 2082 // 2083 // 2084 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 2085 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2086 // CHECK2-NEXT: entry: 2087 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2088 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2089 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 2090 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 2091 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 2092 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2093 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 2094 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 2095 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 2096 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2097 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2098 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2099 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2100 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2101 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2102 // CHECK2-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 2103 // CHECK2-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 2104 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2105 // CHECK2-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2106 // CHECK2-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 2107 // CHECK2-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8 2108 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2109 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2110 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2111 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 2112 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 2113 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 2114 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 2115 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 2116 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 2117 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 2118 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 2119 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 2120 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 2121 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 2122 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2123 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2124 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 2125 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 2126 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 2127 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32 2128 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4 2129 // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4 2130 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2131 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2132 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* 2133 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2134 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) 2135 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 2136 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 2137 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2138 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 2139 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2140 // CHECK2: omp.arraycpy.body: 2141 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2142 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2143 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2144 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2145 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2146 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2147 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2148 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 2149 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] 2150 // CHECK2: omp.arraycpy.done6: 2151 // CHECK2-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 2152 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) 2153 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) 2154 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] 2155 // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 2156 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2157 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 2158 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2159 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2160 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 2161 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2162 // CHECK2: cond.true: 2163 // CHECK2-NEXT: br label [[COND_END:%.*]] 2164 // CHECK2: cond.false: 2165 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2166 // CHECK2-NEXT: br label [[COND_END]] 2167 // CHECK2: cond.end: 2168 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 2169 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2170 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2171 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 2172 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2173 // CHECK2: omp.inner.for.cond: 2174 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2175 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2176 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 2177 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2178 // CHECK2: omp.inner.for.cond.cleanup: 2179 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2180 // CHECK2: omp.inner.for.body: 2181 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2182 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 2183 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2184 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2185 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 2186 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2187 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 2188 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] 2189 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 2190 // CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 2191 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 2192 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 2193 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] 2194 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* 2195 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* 2196 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) 2197 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2198 // CHECK2: omp.body.continue: 2199 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2200 // CHECK2: omp.inner.for.inc: 2201 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2202 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 2203 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 2204 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2205 // CHECK2: omp.inner.for.end: 2206 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2207 // CHECK2: omp.loop.exit: 2208 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2209 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 2210 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 2211 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] 2212 // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 2213 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 2214 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2215 // CHECK2: arraydestroy.body: 2216 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2217 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2218 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2219 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] 2220 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] 2221 // CHECK2: arraydestroy.done15: 2222 // CHECK2-NEXT: ret void 2223 // 2224 // 2225 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2226 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2227 // CHECK2-NEXT: entry: 2228 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2229 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2230 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2231 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2232 // CHECK2-NEXT: ret void 2233 // 2234 // 2235 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2236 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2237 // CHECK2-NEXT: entry: 2238 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2239 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2240 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2241 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2242 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2243 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2244 // CHECK2-NEXT: ret void 2245 // 2246 // 2247 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2248 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2249 // CHECK2-NEXT: entry: 2250 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2251 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2252 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2253 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2254 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2255 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2256 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2257 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2258 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2259 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2260 // CHECK2-NEXT: ret void 2261 // 2262 // 2263 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2264 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2265 // CHECK2-NEXT: entry: 2266 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2267 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 2268 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2269 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 2270 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2271 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2272 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 2273 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 2274 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 2275 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2276 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2277 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2278 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2279 // CHECK2-NEXT: ret void 2280 // 2281 // 2282 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2283 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2284 // CHECK2-NEXT: entry: 2285 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2286 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2287 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2288 // CHECK2-NEXT: ret void 2289 // 2290 // 2291 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 2292 // CHECK2-SAME: () #[[ATTR0]] { 2293 // CHECK2-NEXT: entry: 2294 // CHECK2-NEXT: call void @__cxx_global_var_init() 2295 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 2296 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 2297 // CHECK2-NEXT: ret void 2298 // 2299 // 2300 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2301 // CHECK2-SAME: () #[[ATTR0]] { 2302 // CHECK2-NEXT: entry: 2303 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 2304 // CHECK2-NEXT: ret void 2305 // 2306 // 2307 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 2308 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 2309 // CHECK3-NEXT: entry: 2310 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2311 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2312 // CHECK3-NEXT: ret void 2313 // 2314 // 2315 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2316 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2317 // CHECK3-NEXT: entry: 2318 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2319 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2320 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2321 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2322 // CHECK3-NEXT: ret void 2323 // 2324 // 2325 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2326 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2327 // CHECK3-NEXT: entry: 2328 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2329 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2330 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2331 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2332 // CHECK3-NEXT: ret void 2333 // 2334 // 2335 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2336 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2337 // CHECK3-NEXT: entry: 2338 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2339 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2340 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2341 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2342 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2343 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2344 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 2345 // CHECK3-NEXT: ret void 2346 // 2347 // 2348 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2349 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2350 // CHECK3-NEXT: entry: 2351 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2352 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2353 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2354 // CHECK3-NEXT: ret void 2355 // 2356 // 2357 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2358 // CHECK3-SAME: () #[[ATTR0]] { 2359 // CHECK3-NEXT: entry: 2360 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 2361 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 2362 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2363 // CHECK3-NEXT: ret void 2364 // 2365 // 2366 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2367 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2368 // CHECK3-NEXT: entry: 2369 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2370 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2371 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2372 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2373 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2374 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2375 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2376 // CHECK3-NEXT: ret void 2377 // 2378 // 2379 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2380 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2381 // CHECK3-NEXT: entry: 2382 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2383 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2384 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2385 // CHECK3: arraydestroy.body: 2386 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2387 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2388 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2389 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2390 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2391 // CHECK3: arraydestroy.done1: 2392 // CHECK3-NEXT: ret void 2393 // 2394 // 2395 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2396 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2397 // CHECK3-NEXT: entry: 2398 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2399 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2400 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2401 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2402 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2403 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2404 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2405 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2406 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2407 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2408 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 2409 // CHECK3-NEXT: ret void 2410 // 2411 // 2412 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2413 // CHECK3-SAME: () #[[ATTR0]] { 2414 // CHECK3-NEXT: entry: 2415 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2416 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2417 // CHECK3-NEXT: ret void 2418 // 2419 // 2420 // CHECK3-LABEL: define {{[^@]+}}@main 2421 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 2422 // CHECK3-NEXT: entry: 2423 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2424 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2425 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2426 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2427 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2428 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2429 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2430 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 2431 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 2432 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2433 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2434 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2435 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 2436 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2437 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2438 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 2439 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 2440 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2441 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* 2442 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 2443 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2444 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 2445 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2446 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 2447 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4 2448 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2449 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 2450 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4 2451 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2452 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 2453 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2454 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 2455 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 2456 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2457 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 2458 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 2459 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2460 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 2461 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2462 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 2463 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 2464 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2465 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 2466 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 2467 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2468 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 2469 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2470 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2471 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 2472 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2473 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2474 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 2475 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2476 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 2477 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2478 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2479 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 2480 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2481 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2482 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2483 // CHECK3: omp_offload.failed: 2484 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 2485 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2486 // CHECK3: omp_offload.cont: 2487 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2488 // CHECK3-NEXT: ret i32 [[CALL]] 2489 // 2490 // 2491 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 2492 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 2493 // CHECK3-NEXT: entry: 2494 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2495 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2496 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2497 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2498 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2499 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2500 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2501 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2502 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2503 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2504 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2505 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2506 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2507 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2508 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2509 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2510 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2511 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2512 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2513 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2514 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2515 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2516 // CHECK3-NEXT: ret void 2517 // 2518 // 2519 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2520 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 2521 // CHECK3-NEXT: entry: 2522 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2523 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2524 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2525 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2526 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2527 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2528 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2529 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2530 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2531 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2532 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2533 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2534 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2535 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2536 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2537 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2538 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2539 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2540 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2541 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2542 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2543 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2544 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2545 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2546 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2547 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2548 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2549 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2550 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2551 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2552 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2553 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 2554 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 2555 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2556 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2557 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2558 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2559 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2560 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2561 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2562 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2563 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2564 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2565 // CHECK3: omp.arraycpy.body: 2566 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2567 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2568 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2569 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2570 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2571 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2572 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2573 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2574 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2575 // CHECK3: omp.arraycpy.done3: 2576 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2577 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2578 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 2579 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2580 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2581 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2582 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2583 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2584 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2585 // CHECK3: cond.true: 2586 // CHECK3-NEXT: br label [[COND_END:%.*]] 2587 // CHECK3: cond.false: 2588 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2589 // CHECK3-NEXT: br label [[COND_END]] 2590 // CHECK3: cond.end: 2591 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2592 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 2593 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2594 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 2595 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2596 // CHECK3: omp.inner.for.cond: 2597 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2598 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2599 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2600 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2601 // CHECK3: omp.inner.for.cond.cleanup: 2602 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2603 // CHECK3: omp.inner.for.body: 2604 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2605 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2606 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2607 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 2608 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2609 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2610 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 2611 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2612 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) 2613 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2614 // CHECK3: omp.inner.for.inc: 2615 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2616 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2617 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] 2618 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2619 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2620 // CHECK3: omp.inner.for.end: 2621 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2622 // CHECK3: omp.loop.exit: 2623 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2624 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 2625 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 2626 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2627 // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2628 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 2629 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2630 // CHECK3: arraydestroy.body: 2631 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2632 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2633 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2634 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2635 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2636 // CHECK3: arraydestroy.done8: 2637 // CHECK3-NEXT: ret void 2638 // 2639 // 2640 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2641 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2642 // CHECK3-NEXT: entry: 2643 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2644 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2645 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2646 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2647 // CHECK3-NEXT: ret void 2648 // 2649 // 2650 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2651 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2652 // CHECK3-NEXT: entry: 2653 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2654 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2655 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2656 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2657 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2658 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2659 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2660 // CHECK3-NEXT: ret void 2661 // 2662 // 2663 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2664 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2665 // CHECK3-NEXT: entry: 2666 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2667 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2668 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2669 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 2670 // CHECK3-NEXT: ret void 2671 // 2672 // 2673 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2674 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 2675 // CHECK3-NEXT: entry: 2676 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2677 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2678 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2679 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2680 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2681 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2682 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2683 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2684 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2685 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2686 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2687 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2688 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2689 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2690 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2691 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2692 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2693 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2694 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2695 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2696 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2697 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2698 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2699 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2700 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2701 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2702 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2703 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2704 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2705 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2706 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2707 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2708 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2709 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2710 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2711 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2712 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2713 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 2714 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 2715 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2716 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2717 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2718 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2719 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) 2720 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2721 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2722 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2723 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] 2724 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2725 // CHECK3: omp.arraycpy.body: 2726 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2727 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2728 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2729 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2730 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2731 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2732 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2733 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 2734 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2735 // CHECK3: omp.arraycpy.done3: 2736 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2737 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2738 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 2739 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2740 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2741 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2742 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2743 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 2744 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2745 // CHECK3: cond.true: 2746 // CHECK3-NEXT: br label [[COND_END:%.*]] 2747 // CHECK3: cond.false: 2748 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2749 // CHECK3-NEXT: br label [[COND_END]] 2750 // CHECK3: cond.end: 2751 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2752 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2753 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2754 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2755 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2756 // CHECK3: omp.inner.for.cond: 2757 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2758 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2759 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2760 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2761 // CHECK3: omp.inner.for.cond.cleanup: 2762 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2763 // CHECK3: omp.inner.for.body: 2764 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2765 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 2766 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2767 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2768 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2769 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 2770 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] 2771 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 2772 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2773 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] 2774 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2775 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2776 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) 2777 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2778 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2779 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] 2780 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 2781 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2782 // CHECK3: omp.body.continue: 2783 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2784 // CHECK3: omp.inner.for.inc: 2785 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2786 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 2787 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 2788 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2789 // CHECK3: omp.inner.for.end: 2790 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2791 // CHECK3: omp.loop.exit: 2792 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2793 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 2794 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 2795 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2796 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2797 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 2798 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2799 // CHECK3: arraydestroy.body: 2800 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2801 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2802 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2803 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2804 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2805 // CHECK3: arraydestroy.done11: 2806 // CHECK3-NEXT: ret void 2807 // 2808 // 2809 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2810 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 2811 // CHECK3-NEXT: entry: 2812 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2813 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2814 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2815 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2816 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2817 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2818 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2819 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2820 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2821 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2822 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2823 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2824 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2825 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 2826 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2827 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2828 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2829 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2830 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2831 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2832 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2833 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2834 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2835 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 2836 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 2837 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2838 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2839 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2840 // CHECK3-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2841 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2842 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2843 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 2844 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2845 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2846 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 2847 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2848 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 2849 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2850 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 2851 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 2852 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2853 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 2854 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 2855 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2856 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 2857 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2858 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 2859 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 2860 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2861 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 2862 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 2863 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2864 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2865 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2866 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 2867 // CHECK3-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 2868 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2869 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 2870 // CHECK3-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 2871 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2872 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 2873 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2874 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2875 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 2876 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2877 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2878 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2879 // CHECK3: omp_offload.failed: 2880 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 2881 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2882 // CHECK3: omp_offload.cont: 2883 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 2884 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2885 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2886 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2887 // CHECK3: arraydestroy.body: 2888 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2889 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2890 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2891 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2892 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2893 // CHECK3: arraydestroy.done2: 2894 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2895 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 2896 // CHECK3-NEXT: ret i32 [[TMP32]] 2897 // 2898 // 2899 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2900 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2901 // CHECK3-NEXT: entry: 2902 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2903 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2904 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2905 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2906 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2907 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2908 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4 2909 // CHECK3-NEXT: ret void 2910 // 2911 // 2912 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2913 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2914 // CHECK3-NEXT: entry: 2915 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2916 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2917 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2918 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2919 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2920 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2921 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2922 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2923 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2924 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2925 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2926 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2927 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2928 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 2929 // CHECK3-NEXT: ret void 2930 // 2931 // 2932 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2933 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2934 // CHECK3-NEXT: entry: 2935 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2936 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2937 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2938 // CHECK3-NEXT: ret void 2939 // 2940 // 2941 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2942 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2943 // CHECK3-NEXT: entry: 2944 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2945 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2946 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2947 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2948 // CHECK3-NEXT: ret void 2949 // 2950 // 2951 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2952 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2953 // CHECK3-NEXT: entry: 2954 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2955 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2956 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2957 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2958 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2959 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2960 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2961 // CHECK3-NEXT: ret void 2962 // 2963 // 2964 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 2965 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2966 // CHECK3-NEXT: entry: 2967 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2968 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2969 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2970 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2971 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2972 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2973 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2974 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2975 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2976 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2977 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2978 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2979 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2980 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 2981 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2982 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2983 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2984 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2985 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 2986 // CHECK3-NEXT: ret void 2987 // 2988 // 2989 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2990 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2991 // CHECK3-NEXT: entry: 2992 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2993 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2994 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2995 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2996 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2997 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2998 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2999 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3000 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3001 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3002 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3003 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3004 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3005 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3006 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3007 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3008 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3009 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3010 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 3011 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3012 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3013 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3014 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3015 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3016 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3017 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3018 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3019 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3020 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3021 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3022 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3023 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 3024 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 3025 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3026 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3027 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3028 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3029 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 3030 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3031 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 3032 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3033 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 3034 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3035 // CHECK3: omp.arraycpy.body: 3036 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3037 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3038 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3039 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3040 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 3041 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3042 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3043 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 3044 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3045 // CHECK3: omp.arraycpy.done4: 3046 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3047 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3048 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 3049 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 3050 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 3051 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3052 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 3053 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3054 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3055 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 3056 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3057 // CHECK3: cond.true: 3058 // CHECK3-NEXT: br label [[COND_END:%.*]] 3059 // CHECK3: cond.false: 3060 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3061 // CHECK3-NEXT: br label [[COND_END]] 3062 // CHECK3: cond.end: 3063 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 3064 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 3065 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 3066 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 3067 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3068 // CHECK3: omp.inner.for.cond: 3069 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3070 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3071 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 3072 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3073 // CHECK3: omp.inner.for.cond.cleanup: 3074 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3075 // CHECK3: omp.inner.for.body: 3076 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 3077 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3078 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3079 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 3080 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3081 // CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 3082 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) 3083 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3084 // CHECK3: omp.inner.for.inc: 3085 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3086 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3087 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] 3088 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3089 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3090 // CHECK3: omp.inner.for.end: 3091 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3092 // CHECK3: omp.loop.exit: 3093 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3094 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 3095 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 3096 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 3097 // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3098 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 3099 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3100 // CHECK3: arraydestroy.body: 3101 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3102 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3103 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3104 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 3105 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 3106 // CHECK3: arraydestroy.done10: 3107 // CHECK3-NEXT: ret void 3108 // 3109 // 3110 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3111 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3112 // CHECK3-NEXT: entry: 3113 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3114 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3115 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3116 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3117 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3118 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3119 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3120 // CHECK3-NEXT: ret void 3121 // 3122 // 3123 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 3124 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 3125 // CHECK3-NEXT: entry: 3126 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3127 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3128 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 3129 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 3130 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3131 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3132 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3133 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3134 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3135 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3136 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3137 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3138 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3139 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3140 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3141 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3142 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3143 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3144 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3145 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3146 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 3147 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3148 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3149 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3150 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 3151 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 3152 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3153 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3154 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3155 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3156 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3157 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3158 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3159 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3160 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3161 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3162 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 3163 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 3164 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 3165 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 3166 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3167 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3168 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3169 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3170 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) 3171 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3172 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 3173 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3174 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 3175 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3176 // CHECK3: omp.arraycpy.body: 3177 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3178 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3179 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3180 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3181 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 3182 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3183 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3184 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 3185 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3186 // CHECK3: omp.arraycpy.done4: 3187 // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3188 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3189 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) 3190 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 3191 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 3192 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3193 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 3194 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3195 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3196 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 3197 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3198 // CHECK3: cond.true: 3199 // CHECK3-NEXT: br label [[COND_END:%.*]] 3200 // CHECK3: cond.false: 3201 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3202 // CHECK3-NEXT: br label [[COND_END]] 3203 // CHECK3: cond.end: 3204 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 3205 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3206 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3207 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 3208 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3209 // CHECK3: omp.inner.for.cond: 3210 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3211 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3212 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 3213 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3214 // CHECK3: omp.inner.for.cond.cleanup: 3215 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3216 // CHECK3: omp.inner.for.body: 3217 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3218 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 3219 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3220 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3221 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3222 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3223 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] 3224 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 3225 // CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 3226 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 3227 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] 3228 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 3229 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* 3230 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) 3231 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3232 // CHECK3: omp.body.continue: 3233 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3234 // CHECK3: omp.inner.for.inc: 3235 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3236 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 3237 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 3238 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3239 // CHECK3: omp.inner.for.end: 3240 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3241 // CHECK3: omp.loop.exit: 3242 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3243 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 3244 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 3245 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 3246 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3247 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 3248 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3249 // CHECK3: arraydestroy.body: 3250 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3251 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3252 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3253 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 3254 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 3255 // CHECK3: arraydestroy.done12: 3256 // CHECK3-NEXT: ret void 3257 // 3258 // 3259 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3260 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3261 // CHECK3-NEXT: entry: 3262 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3263 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3264 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3265 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3266 // CHECK3-NEXT: ret void 3267 // 3268 // 3269 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3270 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3271 // CHECK3-NEXT: entry: 3272 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3273 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3274 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3275 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3276 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3277 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3278 // CHECK3-NEXT: ret void 3279 // 3280 // 3281 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3282 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3283 // CHECK3-NEXT: entry: 3284 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3285 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3286 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3287 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3288 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3289 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3290 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3291 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3292 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3293 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3294 // CHECK3-NEXT: ret void 3295 // 3296 // 3297 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3298 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3299 // CHECK3-NEXT: entry: 3300 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3301 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3302 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3303 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3304 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3305 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3306 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3307 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 3308 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 3309 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3310 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3311 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3312 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3313 // CHECK3-NEXT: ret void 3314 // 3315 // 3316 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3317 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3318 // CHECK3-NEXT: entry: 3319 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3320 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3321 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3322 // CHECK3-NEXT: ret void 3323 // 3324 // 3325 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 3326 // CHECK3-SAME: () #[[ATTR0]] { 3327 // CHECK3-NEXT: entry: 3328 // CHECK3-NEXT: call void @__cxx_global_var_init() 3329 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 3330 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 3331 // CHECK3-NEXT: ret void 3332 // 3333 // 3334 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3335 // CHECK3-SAME: () #[[ATTR0]] { 3336 // CHECK3-NEXT: entry: 3337 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3338 // CHECK3-NEXT: ret void 3339 // 3340 // 3341 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 3342 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 3343 // CHECK4-NEXT: entry: 3344 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3345 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3346 // CHECK4-NEXT: ret void 3347 // 3348 // 3349 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3350 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3351 // CHECK4-NEXT: entry: 3352 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3353 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3354 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3355 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3356 // CHECK4-NEXT: ret void 3357 // 3358 // 3359 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3360 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3361 // CHECK4-NEXT: entry: 3362 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3363 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3364 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3365 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3366 // CHECK4-NEXT: ret void 3367 // 3368 // 3369 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3370 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3371 // CHECK4-NEXT: entry: 3372 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3373 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3374 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3375 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3376 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3377 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3378 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 3379 // CHECK4-NEXT: ret void 3380 // 3381 // 3382 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3383 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3384 // CHECK4-NEXT: entry: 3385 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3386 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3387 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3388 // CHECK4-NEXT: ret void 3389 // 3390 // 3391 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3392 // CHECK4-SAME: () #[[ATTR0]] { 3393 // CHECK4-NEXT: entry: 3394 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 3395 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 3396 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3397 // CHECK4-NEXT: ret void 3398 // 3399 // 3400 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3401 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3402 // CHECK4-NEXT: entry: 3403 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3404 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3405 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3406 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3407 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3408 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3409 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3410 // CHECK4-NEXT: ret void 3411 // 3412 // 3413 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3414 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3415 // CHECK4-NEXT: entry: 3416 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 3417 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 3418 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3419 // CHECK4: arraydestroy.body: 3420 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3421 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3422 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3423 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3424 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3425 // CHECK4: arraydestroy.done1: 3426 // CHECK4-NEXT: ret void 3427 // 3428 // 3429 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3430 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3431 // CHECK4-NEXT: entry: 3432 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3433 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3434 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3435 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3436 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3437 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3438 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3439 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3440 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3441 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3442 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 3443 // CHECK4-NEXT: ret void 3444 // 3445 // 3446 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3447 // CHECK4-SAME: () #[[ATTR0]] { 3448 // CHECK4-NEXT: entry: 3449 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3450 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3451 // CHECK4-NEXT: ret void 3452 // 3453 // 3454 // CHECK4-LABEL: define {{[^@]+}}@main 3455 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 3456 // CHECK4-NEXT: entry: 3457 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3458 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3459 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 3460 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3461 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3462 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3463 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3464 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 3465 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 3466 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 3467 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3468 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3469 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 3470 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 3471 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3472 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 3473 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 3474 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3475 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* 3476 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 3477 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3478 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 3479 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3480 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 3481 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4 3482 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3483 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 3484 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4 3485 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3486 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 3487 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3488 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 3489 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 3490 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3491 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 3492 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 3493 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3494 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 3495 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3496 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 3497 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 3498 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3499 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 3500 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 3501 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3502 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 3503 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3504 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 3505 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 3506 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3507 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3508 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 3509 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3510 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4 3511 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3512 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3513 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 3514 // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3515 // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 3516 // CHECK4-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3517 // CHECK4: omp_offload.failed: 3518 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 3519 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 3520 // CHECK4: omp_offload.cont: 3521 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 3522 // CHECK4-NEXT: ret i32 [[CALL]] 3523 // 3524 // 3525 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 3526 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 3527 // CHECK4-NEXT: entry: 3528 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3529 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3530 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 3531 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 3532 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 3533 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3534 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 3535 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3536 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3537 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 3538 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 3539 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 3540 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3541 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 3542 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 3543 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3544 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 3545 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3546 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 3547 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 3548 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 3549 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 3550 // CHECK4-NEXT: ret void 3551 // 3552 // 3553 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 3554 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 3555 // CHECK4-NEXT: entry: 3556 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3557 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3558 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3559 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3560 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 3561 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 3562 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 3563 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3564 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3565 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 3566 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 3567 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3568 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3569 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 3570 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 3571 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3572 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3573 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 3574 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3575 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3576 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 3577 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3578 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3579 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3580 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3581 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 3582 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 3583 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 3584 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3585 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 3586 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 3587 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 3588 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 3589 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3590 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3591 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 3592 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3593 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 3594 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 3595 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 3596 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 3597 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 3598 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3599 // CHECK4: omp.arraycpy.body: 3600 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3601 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3602 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3603 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3604 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 3605 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3606 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3607 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 3608 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 3609 // CHECK4: omp.arraycpy.done3: 3610 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 3611 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 3612 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 3613 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3614 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 3615 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3616 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3617 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 3618 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3619 // CHECK4: cond.true: 3620 // CHECK4-NEXT: br label [[COND_END:%.*]] 3621 // CHECK4: cond.false: 3622 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3623 // CHECK4-NEXT: br label [[COND_END]] 3624 // CHECK4: cond.end: 3625 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 3626 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 3627 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 3628 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 3629 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3630 // CHECK4: omp.inner.for.cond: 3631 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3632 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3633 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 3634 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3635 // CHECK4: omp.inner.for.cond.cleanup: 3636 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3637 // CHECK4: omp.inner.for.body: 3638 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 3639 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 3640 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3641 // CHECK4-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 3642 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3643 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 3644 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 3645 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 3646 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) 3647 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3648 // CHECK4: omp.inner.for.inc: 3649 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3650 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3651 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] 3652 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3653 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3654 // CHECK4: omp.inner.for.end: 3655 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3656 // CHECK4: omp.loop.exit: 3657 // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3658 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 3659 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 3660 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 3661 // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 3662 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 3663 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3664 // CHECK4: arraydestroy.body: 3665 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3666 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3667 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3668 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 3669 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 3670 // CHECK4: arraydestroy.done8: 3671 // CHECK4-NEXT: ret void 3672 // 3673 // 3674 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev 3675 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3676 // CHECK4-NEXT: entry: 3677 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3678 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3679 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3680 // CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 3681 // CHECK4-NEXT: ret void 3682 // 3683 // 3684 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 3685 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3686 // CHECK4-NEXT: entry: 3687 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3688 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 3689 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3690 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 3691 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3692 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 3693 // CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3694 // CHECK4-NEXT: ret void 3695 // 3696 // 3697 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev 3698 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3699 // CHECK4-NEXT: entry: 3700 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3701 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3702 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3703 // CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 3704 // CHECK4-NEXT: ret void 3705 // 3706 // 3707 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 3708 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 3709 // CHECK4-NEXT: entry: 3710 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3711 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3712 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 3713 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 3714 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3715 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3716 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 3717 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 3718 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 3719 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3720 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3721 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3722 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3723 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3724 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3725 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 3726 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 3727 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3728 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3729 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 3730 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3731 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3732 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3733 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 3734 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 3735 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3736 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3737 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 3738 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 3739 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 3740 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3741 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 3742 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 3743 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3744 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3745 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 3746 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 3747 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 3748 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 3749 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3750 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3751 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 3752 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3753 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) 3754 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 3755 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 3756 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 3757 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]] 3758 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3759 // CHECK4: omp.arraycpy.body: 3760 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3761 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3762 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3763 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3764 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 3765 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3766 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3767 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 3768 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 3769 // CHECK4: omp.arraycpy.done3: 3770 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 3771 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 3772 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 3773 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3774 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3775 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3776 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3777 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 3778 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3779 // CHECK4: cond.true: 3780 // CHECK4-NEXT: br label [[COND_END:%.*]] 3781 // CHECK4: cond.false: 3782 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3783 // CHECK4-NEXT: br label [[COND_END]] 3784 // CHECK4: cond.end: 3785 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 3786 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3787 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3788 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 3789 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3790 // CHECK4: omp.inner.for.cond: 3791 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3792 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3793 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 3794 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3795 // CHECK4: omp.inner.for.cond.cleanup: 3796 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3797 // CHECK4: omp.inner.for.body: 3798 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3799 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 3800 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3801 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3802 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3803 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 3804 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] 3805 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 3806 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3807 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] 3808 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 3809 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 3810 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) 3811 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3812 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 3813 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] 3814 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 3815 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3816 // CHECK4: omp.body.continue: 3817 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3818 // CHECK4: omp.inner.for.inc: 3819 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3820 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 3821 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 3822 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3823 // CHECK4: omp.inner.for.end: 3824 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3825 // CHECK4: omp.loop.exit: 3826 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3827 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 3828 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 3829 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 3830 // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 3831 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 3832 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3833 // CHECK4: arraydestroy.body: 3834 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3835 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3836 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3837 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 3838 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 3839 // CHECK4: arraydestroy.done11: 3840 // CHECK4-NEXT: ret void 3841 // 3842 // 3843 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3844 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat { 3845 // CHECK4-NEXT: entry: 3846 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3847 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3848 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3849 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3850 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3851 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 3852 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3853 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3854 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3855 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3856 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3857 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3858 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3859 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 3860 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3861 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 3862 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3863 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 3864 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 3865 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 3866 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 3867 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 3868 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 3869 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 3870 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 3871 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3872 // CHECK4-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3873 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3874 // CHECK4-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3875 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3876 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3877 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 3878 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3879 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3880 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 3881 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3882 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 3883 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3884 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 3885 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 3886 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3887 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 3888 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 3889 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3890 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 3891 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3892 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 3893 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 3894 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3895 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 3896 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 3897 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3898 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 3899 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3900 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 3901 // CHECK4-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 3902 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3903 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 3904 // CHECK4-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 3905 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3906 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 3907 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3908 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3909 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 3910 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3911 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3912 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3913 // CHECK4: omp_offload.failed: 3914 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 3915 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 3916 // CHECK4: omp_offload.cont: 3917 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 3918 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3919 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3920 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3921 // CHECK4: arraydestroy.body: 3922 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3923 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3924 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3925 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3926 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3927 // CHECK4: arraydestroy.done2: 3928 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3929 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 3930 // CHECK4-NEXT: ret i32 [[TMP32]] 3931 // 3932 // 3933 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev 3934 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3935 // CHECK4-NEXT: entry: 3936 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3937 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3938 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3939 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 3940 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 3941 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 3942 // CHECK4-NEXT: store i32 0, i32* [[B]], align 4 3943 // CHECK4-NEXT: ret void 3944 // 3945 // 3946 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 3947 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3948 // CHECK4-NEXT: entry: 3949 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3950 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 3951 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3952 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 3953 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3954 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3955 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 3956 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 3957 // CHECK4-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 3958 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3959 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3960 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 3961 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 3962 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 3963 // CHECK4-NEXT: ret void 3964 // 3965 // 3966 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev 3967 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3968 // CHECK4-NEXT: entry: 3969 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3970 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3971 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3972 // CHECK4-NEXT: ret void 3973 // 3974 // 3975 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3976 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3977 // CHECK4-NEXT: entry: 3978 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3979 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3980 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3981 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3982 // CHECK4-NEXT: ret void 3983 // 3984 // 3985 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3986 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3987 // CHECK4-NEXT: entry: 3988 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3989 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3990 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3991 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3992 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3993 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3994 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3995 // CHECK4-NEXT: ret void 3996 // 3997 // 3998 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 3999 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 4000 // CHECK4-NEXT: entry: 4001 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4002 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 4003 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 4004 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 4005 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4006 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 4007 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 4008 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 4009 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 4010 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 4011 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 4012 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 4013 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 4014 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 4015 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 4016 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 4017 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 4018 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4019 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 4020 // CHECK4-NEXT: ret void 4021 // 4022 // 4023 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 4024 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 4025 // CHECK4-NEXT: entry: 4026 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4027 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4028 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 4029 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4030 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 4031 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 4032 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4033 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4034 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4035 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 4036 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 4037 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4038 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4039 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 4040 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 4041 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 4042 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4043 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 4044 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 4045 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 4046 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 4047 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4048 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4049 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 4050 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 4051 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 4052 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 4053 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 4054 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 4055 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 4056 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 4057 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 4058 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 4059 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4060 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4061 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 4062 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 4063 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 4064 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 4065 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 4066 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4067 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 4068 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 4069 // CHECK4: omp.arraycpy.body: 4070 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4071 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4072 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 4073 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 4074 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 4075 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 4076 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 4077 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 4078 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 4079 // CHECK4: omp.arraycpy.done4: 4080 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4081 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 4082 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 4083 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 4084 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 4085 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4086 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 4087 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4088 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4089 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 4090 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4091 // CHECK4: cond.true: 4092 // CHECK4-NEXT: br label [[COND_END:%.*]] 4093 // CHECK4: cond.false: 4094 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4095 // CHECK4-NEXT: br label [[COND_END]] 4096 // CHECK4: cond.end: 4097 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 4098 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 4099 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 4100 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 4101 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4102 // CHECK4: omp.inner.for.cond: 4103 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4104 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4105 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 4106 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4107 // CHECK4: omp.inner.for.cond.cleanup: 4108 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4109 // CHECK4: omp.inner.for.body: 4110 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 4111 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4112 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 4113 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 4114 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 4115 // CHECK4-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 4116 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) 4117 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4118 // CHECK4: omp.inner.for.inc: 4119 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4120 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4121 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] 4122 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4123 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4124 // CHECK4: omp.inner.for.end: 4125 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4126 // CHECK4: omp.loop.exit: 4127 // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4128 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 4129 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 4130 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 4131 // CHECK4-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 4132 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 4133 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4134 // CHECK4: arraydestroy.body: 4135 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4136 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4137 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4138 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 4139 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 4140 // CHECK4: arraydestroy.done10: 4141 // CHECK4-NEXT: ret void 4142 // 4143 // 4144 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 4145 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4146 // CHECK4-NEXT: entry: 4147 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4148 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 4149 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4150 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 4151 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4152 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 4153 // CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 4154 // CHECK4-NEXT: ret void 4155 // 4156 // 4157 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 4158 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 4159 // CHECK4-NEXT: entry: 4160 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4161 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4162 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 4163 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 4164 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 4165 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 4166 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 4167 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 4168 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4169 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4170 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4171 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4172 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4173 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4174 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4175 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 4176 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 4177 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 4178 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4179 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 4180 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 4181 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 4182 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4183 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4184 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 4185 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 4186 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 4187 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 4188 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 4189 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 4190 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 4191 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 4192 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 4193 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 4194 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4195 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4196 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 4197 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 4198 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4 4199 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 4200 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4201 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4202 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 4203 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 4204 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false) 4205 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 4206 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 4207 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4208 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 4209 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 4210 // CHECK4: omp.arraycpy.body: 4211 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4212 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 4213 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 4214 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 4215 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 4216 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 4217 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 4218 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 4219 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 4220 // CHECK4: omp.arraycpy.done4: 4221 // CHECK4-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4222 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 4223 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) 4224 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 4225 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 4226 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4227 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 4228 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4229 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4230 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 4231 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4232 // CHECK4: cond.true: 4233 // CHECK4-NEXT: br label [[COND_END:%.*]] 4234 // CHECK4: cond.false: 4235 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4236 // CHECK4-NEXT: br label [[COND_END]] 4237 // CHECK4: cond.end: 4238 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 4239 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4240 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4241 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 4242 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4243 // CHECK4: omp.inner.for.cond: 4244 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4245 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4246 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 4247 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4248 // CHECK4: omp.inner.for.cond.cleanup: 4249 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4250 // CHECK4: omp.inner.for.body: 4251 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4252 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 4253 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4254 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4255 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 4256 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 4257 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] 4258 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 4259 // CHECK4-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 4260 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 4261 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] 4262 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 4263 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* 4264 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) 4265 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4266 // CHECK4: omp.body.continue: 4267 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4268 // CHECK4: omp.inner.for.inc: 4269 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4270 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 4271 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 4272 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4273 // CHECK4: omp.inner.for.end: 4274 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4275 // CHECK4: omp.loop.exit: 4276 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4277 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 4278 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 4279 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 4280 // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 4281 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 4282 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4283 // CHECK4: arraydestroy.body: 4284 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4285 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4286 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4287 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 4288 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 4289 // CHECK4: arraydestroy.done12: 4290 // CHECK4-NEXT: ret void 4291 // 4292 // 4293 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4294 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4295 // CHECK4-NEXT: entry: 4296 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4297 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4298 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4299 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4300 // CHECK4-NEXT: ret void 4301 // 4302 // 4303 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4304 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4305 // CHECK4-NEXT: entry: 4306 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4307 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4308 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4309 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4310 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4311 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4312 // CHECK4-NEXT: ret void 4313 // 4314 // 4315 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4316 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4317 // CHECK4-NEXT: entry: 4318 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4319 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4320 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4321 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4322 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4323 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4324 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4325 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4326 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4327 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4328 // CHECK4-NEXT: ret void 4329 // 4330 // 4331 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 4332 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4333 // CHECK4-NEXT: entry: 4334 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4335 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 4336 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4337 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 4338 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4339 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4340 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 4341 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 4342 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 4343 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 4344 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 4345 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 4346 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4347 // CHECK4-NEXT: ret void 4348 // 4349 // 4350 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4351 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4352 // CHECK4-NEXT: entry: 4353 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4354 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4355 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4356 // CHECK4-NEXT: ret void 4357 // 4358 // 4359 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 4360 // CHECK4-SAME: () #[[ATTR0]] { 4361 // CHECK4-NEXT: entry: 4362 // CHECK4-NEXT: call void @__cxx_global_var_init() 4363 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 4364 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 4365 // CHECK4-NEXT: ret void 4366 // 4367 // 4368 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4369 // CHECK4-SAME: () #[[ATTR0]] { 4370 // CHECK4-NEXT: entry: 4371 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 4372 // CHECK4-NEXT: ret void 4373 // 4374 // 4375 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 4376 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 4377 // CHECK5-NEXT: entry: 4378 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4379 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4380 // CHECK5-NEXT: ret void 4381 // 4382 // 4383 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4384 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4385 // CHECK5-NEXT: entry: 4386 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4387 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4388 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4389 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4390 // CHECK5-NEXT: ret void 4391 // 4392 // 4393 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4394 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4395 // CHECK5-NEXT: entry: 4396 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4397 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4398 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4399 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4400 // CHECK5-NEXT: ret void 4401 // 4402 // 4403 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4404 // CHECK5-SAME: () #[[ATTR0]] { 4405 // CHECK5-NEXT: entry: 4406 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4407 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4408 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4409 // CHECK5-NEXT: ret void 4410 // 4411 // 4412 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4413 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4414 // CHECK5-NEXT: entry: 4415 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4416 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4417 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4418 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4419 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4420 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4421 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4422 // CHECK5-NEXT: ret void 4423 // 4424 // 4425 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4426 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4427 // CHECK5-NEXT: entry: 4428 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4429 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4430 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4431 // CHECK5: arraydestroy.body: 4432 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4433 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4434 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4435 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4436 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4437 // CHECK5: arraydestroy.done1: 4438 // CHECK5-NEXT: ret void 4439 // 4440 // 4441 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4442 // CHECK5-SAME: () #[[ATTR0]] { 4443 // CHECK5-NEXT: entry: 4444 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4445 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4446 // CHECK5-NEXT: ret void 4447 // 4448 // 4449 // CHECK5-LABEL: define {{[^@]+}}@main 4450 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 4451 // CHECK5-NEXT: entry: 4452 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4453 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4454 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 4455 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 4456 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 4457 // CHECK5: for.cond: 4458 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 4459 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 4460 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4461 // CHECK5: for.body: 4462 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 4463 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 4464 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 4465 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 4466 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4467 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 4468 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 4469 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 4470 // CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 4471 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 4472 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4473 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 4474 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 4475 // CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 4476 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 4477 // CHECK5: for.inc: 4478 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 4479 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 4480 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 4481 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 4482 // CHECK5: for.end: 4483 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 4484 // CHECK5-NEXT: ret i32 [[CALL]] 4485 // 4486 // 4487 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4488 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 4489 // CHECK5-NEXT: entry: 4490 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4491 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4492 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4493 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4494 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4495 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 4496 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 4497 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 4498 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4499 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4500 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 4501 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4502 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 4503 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 4504 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 4505 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 4506 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 4507 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 4508 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 4509 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 4510 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 4511 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 4512 // CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 4513 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 4514 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 4515 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 4516 // CHECK5: for.cond: 4517 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4518 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 4519 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4520 // CHECK5: for.body: 4521 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 4522 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 4523 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 4524 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 4525 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 4526 // CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 4527 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 4528 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 4529 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 4530 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 4531 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* 4532 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) 4533 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 4534 // CHECK5: for.inc: 4535 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 4536 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 4537 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 4538 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4539 // CHECK5: for.end: 4540 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 4541 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4542 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 4543 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4544 // CHECK5: arraydestroy.body: 4545 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4546 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4547 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4548 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4549 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 4550 // CHECK5: arraydestroy.done4: 4551 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 4552 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 4553 // CHECK5-NEXT: ret i32 [[TMP14]] 4554 // 4555 // 4556 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4557 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4558 // CHECK5-NEXT: entry: 4559 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4560 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4561 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4562 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4563 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4564 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4565 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 4566 // CHECK5-NEXT: ret void 4567 // 4568 // 4569 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4570 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4571 // CHECK5-NEXT: entry: 4572 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4573 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4574 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4575 // CHECK5-NEXT: ret void 4576 // 4577 // 4578 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4579 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4580 // CHECK5-NEXT: entry: 4581 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4582 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4583 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4584 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4585 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4586 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4587 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4588 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4589 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4590 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4591 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 4592 // CHECK5-NEXT: ret void 4593 // 4594 // 4595 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4596 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4597 // CHECK5-NEXT: entry: 4598 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4599 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4600 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4601 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4602 // CHECK5-NEXT: ret void 4603 // 4604 // 4605 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4606 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4607 // CHECK5-NEXT: entry: 4608 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4609 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4610 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4611 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4612 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4613 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4614 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 4615 // CHECK5-NEXT: ret void 4616 // 4617 // 4618 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4619 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4620 // CHECK5-NEXT: entry: 4621 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4622 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4623 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4624 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4625 // CHECK5-NEXT: ret void 4626 // 4627 // 4628 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4629 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4630 // CHECK5-NEXT: entry: 4631 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4632 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4633 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4634 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4635 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4636 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4637 // CHECK5-NEXT: ret void 4638 // 4639 // 4640 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4641 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4642 // CHECK5-NEXT: entry: 4643 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4644 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4645 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4646 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4647 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4648 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4649 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4650 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4651 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4652 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4653 // CHECK5-NEXT: ret void 4654 // 4655 // 4656 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4657 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4658 // CHECK5-NEXT: entry: 4659 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4660 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4661 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4662 // CHECK5-NEXT: ret void 4663 // 4664 // 4665 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 4666 // CHECK5-SAME: () #[[ATTR0]] { 4667 // CHECK5-NEXT: entry: 4668 // CHECK5-NEXT: call void @__cxx_global_var_init() 4669 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 4670 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 4671 // CHECK5-NEXT: ret void 4672 // 4673 // 4674 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init 4675 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 4676 // CHECK6-NEXT: entry: 4677 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4678 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4679 // CHECK6-NEXT: ret void 4680 // 4681 // 4682 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4683 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4684 // CHECK6-NEXT: entry: 4685 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4686 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4687 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4688 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4689 // CHECK6-NEXT: ret void 4690 // 4691 // 4692 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4693 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4694 // CHECK6-NEXT: entry: 4695 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4696 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4697 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4698 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4699 // CHECK6-NEXT: ret void 4700 // 4701 // 4702 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4703 // CHECK6-SAME: () #[[ATTR0]] { 4704 // CHECK6-NEXT: entry: 4705 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4706 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4707 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4708 // CHECK6-NEXT: ret void 4709 // 4710 // 4711 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4712 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4713 // CHECK6-NEXT: entry: 4714 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4715 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4716 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4717 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4718 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4719 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4720 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4721 // CHECK6-NEXT: ret void 4722 // 4723 // 4724 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4725 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4726 // CHECK6-NEXT: entry: 4727 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4728 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4729 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4730 // CHECK6: arraydestroy.body: 4731 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4732 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4733 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4734 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4735 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4736 // CHECK6: arraydestroy.done1: 4737 // CHECK6-NEXT: ret void 4738 // 4739 // 4740 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4741 // CHECK6-SAME: () #[[ATTR0]] { 4742 // CHECK6-NEXT: entry: 4743 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4744 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4745 // CHECK6-NEXT: ret void 4746 // 4747 // 4748 // CHECK6-LABEL: define {{[^@]+}}@main 4749 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 4750 // CHECK6-NEXT: entry: 4751 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4752 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 4753 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 4754 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 4755 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 4756 // CHECK6: for.cond: 4757 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 4758 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 4759 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4760 // CHECK6: for.body: 4761 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 4762 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 4763 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 4764 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 4765 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4766 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 4767 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 4768 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 4769 // CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 4770 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 4771 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4772 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 4773 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 4774 // CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 4775 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 4776 // CHECK6: for.inc: 4777 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 4778 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 4779 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 4780 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 4781 // CHECK6: for.end: 4782 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 4783 // CHECK6-NEXT: ret i32 [[CALL]] 4784 // 4785 // 4786 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4787 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { 4788 // CHECK6-NEXT: entry: 4789 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4790 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4791 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4792 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4793 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4794 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 4795 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 4796 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 4797 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 4798 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4799 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 4800 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4801 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 4802 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 4803 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 4804 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 4805 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 4806 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 4807 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 4808 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 4809 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 4810 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 4811 // CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 4812 // CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 4813 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 4814 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 4815 // CHECK6: for.cond: 4816 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4817 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 4818 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4819 // CHECK6: for.body: 4820 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 4821 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 4822 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 4823 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 4824 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 4825 // CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 4826 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 4827 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 4828 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 4829 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 4830 // CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* 4831 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) 4832 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 4833 // CHECK6: for.inc: 4834 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 4835 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 4836 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 4837 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4838 // CHECK6: for.end: 4839 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 4840 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4841 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 4842 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4843 // CHECK6: arraydestroy.body: 4844 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4845 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4846 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4847 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4848 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 4849 // CHECK6: arraydestroy.done4: 4850 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 4851 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 4852 // CHECK6-NEXT: ret i32 [[TMP14]] 4853 // 4854 // 4855 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4856 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4857 // CHECK6-NEXT: entry: 4858 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4859 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4860 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4861 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4862 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4863 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4864 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 4865 // CHECK6-NEXT: ret void 4866 // 4867 // 4868 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4869 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4870 // CHECK6-NEXT: entry: 4871 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4872 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4873 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4874 // CHECK6-NEXT: ret void 4875 // 4876 // 4877 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4878 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4879 // CHECK6-NEXT: entry: 4880 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4881 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4882 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4883 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4884 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4885 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4886 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4887 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4888 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4889 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4890 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 4891 // CHECK6-NEXT: ret void 4892 // 4893 // 4894 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4895 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4896 // CHECK6-NEXT: entry: 4897 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4898 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4899 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4900 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4901 // CHECK6-NEXT: ret void 4902 // 4903 // 4904 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4905 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4906 // CHECK6-NEXT: entry: 4907 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4908 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4909 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4910 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4911 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4912 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4913 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 4914 // CHECK6-NEXT: ret void 4915 // 4916 // 4917 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4918 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4919 // CHECK6-NEXT: entry: 4920 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4921 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4922 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4923 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4924 // CHECK6-NEXT: ret void 4925 // 4926 // 4927 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4928 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4929 // CHECK6-NEXT: entry: 4930 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4931 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4932 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4933 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4934 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4935 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4936 // CHECK6-NEXT: ret void 4937 // 4938 // 4939 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4940 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4941 // CHECK6-NEXT: entry: 4942 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4943 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4944 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4945 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4946 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4947 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4948 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4949 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4950 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4951 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4952 // CHECK6-NEXT: ret void 4953 // 4954 // 4955 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4956 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4957 // CHECK6-NEXT: entry: 4958 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 4959 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 4960 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 4961 // CHECK6-NEXT: ret void 4962 // 4963 // 4964 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 4965 // CHECK6-SAME: () #[[ATTR0]] { 4966 // CHECK6-NEXT: entry: 4967 // CHECK6-NEXT: call void @__cxx_global_var_init() 4968 // CHECK6-NEXT: call void @__cxx_global_var_init.1() 4969 // CHECK6-NEXT: call void @__cxx_global_var_init.2() 4970 // CHECK6-NEXT: ret void 4971 // 4972 // 4973 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 4974 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 4975 // CHECK7-NEXT: entry: 4976 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4977 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4978 // CHECK7-NEXT: ret void 4979 // 4980 // 4981 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4982 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4983 // CHECK7-NEXT: entry: 4984 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4985 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4986 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4987 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4988 // CHECK7-NEXT: ret void 4989 // 4990 // 4991 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4992 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4993 // CHECK7-NEXT: entry: 4994 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4995 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4996 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4997 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4998 // CHECK7-NEXT: ret void 4999 // 5000 // 5001 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5002 // CHECK7-SAME: () #[[ATTR0]] { 5003 // CHECK7-NEXT: entry: 5004 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 5005 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 5006 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5007 // CHECK7-NEXT: ret void 5008 // 5009 // 5010 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5011 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5012 // CHECK7-NEXT: entry: 5013 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5014 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5015 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5016 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5017 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5018 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5019 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5020 // CHECK7-NEXT: ret void 5021 // 5022 // 5023 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5024 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5025 // CHECK7-NEXT: entry: 5026 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 5027 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 5028 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5029 // CHECK7: arraydestroy.body: 5030 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5031 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 5032 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5033 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5034 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5035 // CHECK7: arraydestroy.done1: 5036 // CHECK7-NEXT: ret void 5037 // 5038 // 5039 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5040 // CHECK7-SAME: () #[[ATTR0]] { 5041 // CHECK7-NEXT: entry: 5042 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5043 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5044 // CHECK7-NEXT: ret void 5045 // 5046 // 5047 // CHECK7-LABEL: define {{[^@]+}}@main 5048 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 5049 // CHECK7-NEXT: entry: 5050 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5051 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5052 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 5053 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 5054 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 5055 // CHECK7: for.cond: 5056 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 5057 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 5058 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5059 // CHECK7: for.body: 5060 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 5061 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 5062 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] 5063 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 5064 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 5065 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] 5066 // CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 5067 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) 5068 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 5069 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 5070 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 5071 // CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 5072 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 5073 // CHECK7: for.inc: 5074 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 5075 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 5076 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 5077 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 5078 // CHECK7: for.end: 5079 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 5080 // CHECK7-NEXT: ret i32 [[CALL]] 5081 // 5082 // 5083 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 5084 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 5085 // CHECK7-NEXT: entry: 5086 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5087 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 5088 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 5089 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 5090 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 5091 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 5092 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 5093 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 5094 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5095 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 5096 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 5097 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 5098 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 5099 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 5100 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 5101 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 5102 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 5103 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 5104 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 5105 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 5106 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 5107 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 5108 // CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 5109 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 5110 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 5111 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 5112 // CHECK7: for.cond: 5113 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 5114 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 5115 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5116 // CHECK7: for.body: 5117 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 5118 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 5119 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] 5120 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 5121 // CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 5122 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 5123 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] 5124 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 5125 // CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* 5126 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) 5127 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 5128 // CHECK7: for.inc: 5129 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 5130 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 5131 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 5132 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 5133 // CHECK7: for.end: 5134 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 5135 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 5136 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 5137 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5138 // CHECK7: arraydestroy.body: 5139 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5140 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 5141 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5142 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 5143 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 5144 // CHECK7: arraydestroy.done3: 5145 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 5146 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 5147 // CHECK7-NEXT: ret i32 [[TMP14]] 5148 // 5149 // 5150 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5151 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5152 // CHECK7-NEXT: entry: 5153 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5154 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5155 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5156 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5157 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5158 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5159 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 5160 // CHECK7-NEXT: ret void 5161 // 5162 // 5163 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5164 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5165 // CHECK7-NEXT: entry: 5166 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5167 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5168 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5169 // CHECK7-NEXT: ret void 5170 // 5171 // 5172 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5173 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5174 // CHECK7-NEXT: entry: 5175 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5176 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5177 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5178 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5179 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5180 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5181 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5182 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5183 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5184 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5185 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 5186 // CHECK7-NEXT: ret void 5187 // 5188 // 5189 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 5190 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5191 // CHECK7-NEXT: entry: 5192 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5193 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5194 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5195 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 5196 // CHECK7-NEXT: ret void 5197 // 5198 // 5199 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 5200 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5201 // CHECK7-NEXT: entry: 5202 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5203 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5204 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5205 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5206 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5207 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5208 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 5209 // CHECK7-NEXT: ret void 5210 // 5211 // 5212 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 5213 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5214 // CHECK7-NEXT: entry: 5215 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5216 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5217 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5218 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5219 // CHECK7-NEXT: ret void 5220 // 5221 // 5222 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 5223 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5224 // CHECK7-NEXT: entry: 5225 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5226 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5227 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5228 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 5229 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5230 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 5231 // CHECK7-NEXT: ret void 5232 // 5233 // 5234 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 5235 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5236 // CHECK7-NEXT: entry: 5237 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5238 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5239 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5240 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5241 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5242 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 5243 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5244 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5245 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 5246 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 5247 // CHECK7-NEXT: ret void 5248 // 5249 // 5250 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 5251 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5252 // CHECK7-NEXT: entry: 5253 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5254 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5255 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5256 // CHECK7-NEXT: ret void 5257 // 5258 // 5259 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 5260 // CHECK7-SAME: () #[[ATTR0]] { 5261 // CHECK7-NEXT: entry: 5262 // CHECK7-NEXT: call void @__cxx_global_var_init() 5263 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 5264 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 5265 // CHECK7-NEXT: ret void 5266 // 5267 // 5268 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init 5269 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 5270 // CHECK8-NEXT: entry: 5271 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 5272 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5273 // CHECK8-NEXT: ret void 5274 // 5275 // 5276 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5277 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5278 // CHECK8-NEXT: entry: 5279 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5280 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5281 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5282 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 5283 // CHECK8-NEXT: ret void 5284 // 5285 // 5286 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5287 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5288 // CHECK8-NEXT: entry: 5289 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5290 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5291 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5292 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5293 // CHECK8-NEXT: ret void 5294 // 5295 // 5296 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5297 // CHECK8-SAME: () #[[ATTR0]] { 5298 // CHECK8-NEXT: entry: 5299 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 5300 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 5301 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5302 // CHECK8-NEXT: ret void 5303 // 5304 // 5305 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5306 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5307 // CHECK8-NEXT: entry: 5308 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5309 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5310 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5311 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5312 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5313 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5314 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5315 // CHECK8-NEXT: ret void 5316 // 5317 // 5318 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5319 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5320 // CHECK8-NEXT: entry: 5321 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 5322 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 5323 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5324 // CHECK8: arraydestroy.body: 5325 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5326 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 5327 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5328 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5329 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5330 // CHECK8: arraydestroy.done1: 5331 // CHECK8-NEXT: ret void 5332 // 5333 // 5334 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5335 // CHECK8-SAME: () #[[ATTR0]] { 5336 // CHECK8-NEXT: entry: 5337 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5338 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5339 // CHECK8-NEXT: ret void 5340 // 5341 // 5342 // CHECK8-LABEL: define {{[^@]+}}@main 5343 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 5344 // CHECK8-NEXT: entry: 5345 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5346 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 5347 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 5348 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 5349 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 5350 // CHECK8: for.cond: 5351 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 5352 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 5353 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5354 // CHECK8: for.body: 5355 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 5356 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 5357 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] 5358 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 5359 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 5360 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] 5361 // CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 5362 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) 5363 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 5364 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 5365 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 5366 // CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 5367 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 5368 // CHECK8: for.inc: 5369 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 5370 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 5371 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 5372 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 5373 // CHECK8: for.end: 5374 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 5375 // CHECK8-NEXT: ret i32 [[CALL]] 5376 // 5377 // 5378 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 5379 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { 5380 // CHECK8-NEXT: entry: 5381 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5382 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 5383 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 5384 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 5385 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 5386 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 5387 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 5388 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 5389 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 5390 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 5391 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 5392 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 5393 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 5394 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 5395 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 5396 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 5397 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 5398 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 5399 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 5400 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 5401 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 5402 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 5403 // CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 5404 // CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 5405 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 5406 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 5407 // CHECK8: for.cond: 5408 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 5409 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 5410 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 5411 // CHECK8: for.body: 5412 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 5413 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 5414 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] 5415 // CHECK8-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 5416 // CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 5417 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 5418 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] 5419 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 5420 // CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* 5421 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) 5422 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 5423 // CHECK8: for.inc: 5424 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 5425 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 5426 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 5427 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 5428 // CHECK8: for.end: 5429 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 5430 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 5431 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 5432 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5433 // CHECK8: arraydestroy.body: 5434 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5435 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 5436 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5437 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 5438 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 5439 // CHECK8: arraydestroy.done3: 5440 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 5441 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 5442 // CHECK8-NEXT: ret i32 [[TMP14]] 5443 // 5444 // 5445 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5446 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5447 // CHECK8-NEXT: entry: 5448 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5449 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5450 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5451 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5452 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5453 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5454 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 5455 // CHECK8-NEXT: ret void 5456 // 5457 // 5458 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5459 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5460 // CHECK8-NEXT: entry: 5461 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5462 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5463 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5464 // CHECK8-NEXT: ret void 5465 // 5466 // 5467 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5468 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5469 // CHECK8-NEXT: entry: 5470 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 5471 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5472 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 5473 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5474 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 5475 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5476 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5477 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5478 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5479 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5480 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 5481 // CHECK8-NEXT: ret void 5482 // 5483 // 5484 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 5485 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5486 // CHECK8-NEXT: entry: 5487 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5488 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5489 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5490 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 5491 // CHECK8-NEXT: ret void 5492 // 5493 // 5494 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 5495 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5496 // CHECK8-NEXT: entry: 5497 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5498 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5499 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5500 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5501 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5502 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5503 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 5504 // CHECK8-NEXT: ret void 5505 // 5506 // 5507 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 5508 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5509 // CHECK8-NEXT: entry: 5510 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5511 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5512 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5513 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5514 // CHECK8-NEXT: ret void 5515 // 5516 // 5517 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 5518 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5519 // CHECK8-NEXT: entry: 5520 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5521 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5522 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5523 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 5524 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5525 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 5526 // CHECK8-NEXT: ret void 5527 // 5528 // 5529 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 5530 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5531 // CHECK8-NEXT: entry: 5532 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5533 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5534 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5535 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5536 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5537 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 5538 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5539 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5540 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 5541 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 5542 // CHECK8-NEXT: ret void 5543 // 5544 // 5545 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 5546 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5547 // CHECK8-NEXT: entry: 5548 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 5549 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 5550 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 5551 // CHECK8-NEXT: ret void 5552 // 5553 // 5554 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 5555 // CHECK8-SAME: () #[[ATTR0]] { 5556 // CHECK8-NEXT: entry: 5557 // CHECK8-NEXT: call void @__cxx_global_var_init() 5558 // CHECK8-NEXT: call void @__cxx_global_var_init.1() 5559 // CHECK8-NEXT: call void @__cxx_global_var_init.2() 5560 // CHECK8-NEXT: ret void 5561 // 5562 // 5563 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 5564 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 5565 // CHECK9-NEXT: entry: 5566 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 5567 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5568 // CHECK9-NEXT: ret void 5569 // 5570 // 5571 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5572 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5573 // CHECK9-NEXT: entry: 5574 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5575 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5576 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5577 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 5578 // CHECK9-NEXT: ret void 5579 // 5580 // 5581 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5582 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5583 // CHECK9-NEXT: entry: 5584 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5585 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5586 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5587 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5588 // CHECK9-NEXT: ret void 5589 // 5590 // 5591 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5592 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5593 // CHECK9-NEXT: entry: 5594 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5595 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5596 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5597 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5598 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5599 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5600 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 5601 // CHECK9-NEXT: ret void 5602 // 5603 // 5604 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5605 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5606 // CHECK9-NEXT: entry: 5607 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5608 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5609 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5610 // CHECK9-NEXT: ret void 5611 // 5612 // 5613 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5614 // CHECK9-SAME: () #[[ATTR0]] { 5615 // CHECK9-NEXT: entry: 5616 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 5617 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 5618 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5619 // CHECK9-NEXT: ret void 5620 // 5621 // 5622 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5623 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5624 // CHECK9-NEXT: entry: 5625 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5626 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5627 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5628 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5629 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5630 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5631 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5632 // CHECK9-NEXT: ret void 5633 // 5634 // 5635 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5636 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5637 // CHECK9-NEXT: entry: 5638 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5639 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5640 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5641 // CHECK9: arraydestroy.body: 5642 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5643 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5644 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5645 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5646 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5647 // CHECK9: arraydestroy.done1: 5648 // CHECK9-NEXT: ret void 5649 // 5650 // 5651 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5652 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5653 // CHECK9-NEXT: entry: 5654 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5655 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5656 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5657 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5658 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5659 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5660 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5661 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5662 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5663 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5664 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 5665 // CHECK9-NEXT: ret void 5666 // 5667 // 5668 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5669 // CHECK9-SAME: () #[[ATTR0]] { 5670 // CHECK9-NEXT: entry: 5671 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5672 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5673 // CHECK9-NEXT: ret void 5674 // 5675 // 5676 // CHECK9-LABEL: define {{[^@]+}}@main 5677 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 5678 // CHECK9-NEXT: entry: 5679 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5680 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5681 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 5682 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 5683 // CHECK9-NEXT: ret i32 0 5684 // 5685 // 5686 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 5687 // CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 5688 // CHECK9-NEXT: entry: 5689 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 5690 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 5691 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 5692 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5693 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 5694 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 5695 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 5696 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 5697 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 5698 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 5699 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 5700 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 5701 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 5702 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 5703 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 5704 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 5705 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 5706 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 5707 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 5708 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 5709 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 5710 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 5711 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 5712 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 5713 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 5714 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 5715 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 5716 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 5717 // CHECK9-NEXT: ret void 5718 // 5719 // 5720 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 5721 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 5722 // CHECK9-NEXT: entry: 5723 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5724 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5725 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 5726 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 5727 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 5728 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5729 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5730 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 5731 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 5732 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 5733 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5734 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5735 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 5736 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 5737 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 5738 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 5739 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5740 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5741 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 5742 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 5743 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 5744 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 5745 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 5746 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 5747 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 5748 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 5749 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 5750 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5751 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5752 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5753 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5754 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5755 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 5756 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 5757 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5758 // CHECK9: cond.true: 5759 // CHECK9-NEXT: br label [[COND_END:%.*]] 5760 // CHECK9: cond.false: 5761 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 5762 // CHECK9-NEXT: br label [[COND_END]] 5763 // CHECK9: cond.end: 5764 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5765 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 5766 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 5767 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5768 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5769 // CHECK9: omp.inner.for.cond: 5770 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5771 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 5772 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5773 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5774 // CHECK9: omp.inner.for.body: 5775 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 5776 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 5777 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 5778 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 5779 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 5780 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* 5781 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 5782 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 5783 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 5784 // CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 5785 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 5786 // CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 5787 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 5788 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 5789 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 5790 // CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 5791 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 5792 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) 5793 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5794 // CHECK9: omp.inner.for.inc: 5795 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5796 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5797 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 5798 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 5799 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 5800 // CHECK9: omp.inner.for.end: 5801 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5802 // CHECK9: omp.loop.exit: 5803 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5804 // CHECK9-NEXT: ret void 5805 // 5806 // 5807 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 5808 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 5809 // CHECK9-NEXT: entry: 5810 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5811 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5812 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 5813 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 5814 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 5815 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 5816 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 5817 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5818 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5819 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 5820 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5821 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5822 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5823 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5824 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 5825 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 5826 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5827 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5828 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 5829 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 5830 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 5831 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 5832 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 5833 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 5834 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 5835 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 5836 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 5837 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5838 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 5839 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 5840 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 5841 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 5842 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 5843 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 5844 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 5845 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5846 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5847 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5848 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5849 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5850 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5851 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 5852 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5853 // CHECK9: cond.true: 5854 // CHECK9-NEXT: br label [[COND_END:%.*]] 5855 // CHECK9: cond.false: 5856 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5857 // CHECK9-NEXT: br label [[COND_END]] 5858 // CHECK9: cond.end: 5859 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5860 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5861 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5862 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 5863 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5864 // CHECK9: omp.inner.for.cond: 5865 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5866 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5867 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 5868 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5869 // CHECK9: omp.inner.for.body: 5870 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5871 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 5872 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5873 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5874 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 5875 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 5876 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 5877 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 5878 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 5879 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 5880 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 5881 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 5882 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 5883 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 5884 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 5885 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 5886 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5887 // CHECK9: omp.body.continue: 5888 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5889 // CHECK9: omp.inner.for.inc: 5890 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5891 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 5892 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 5893 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 5894 // CHECK9: omp.inner.for.end: 5895 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5896 // CHECK9: omp.loop.exit: 5897 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5898 // CHECK9-NEXT: ret void 5899 // 5900 // 5901 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 5902 // CHECK9-SAME: () #[[ATTR0]] { 5903 // CHECK9-NEXT: entry: 5904 // CHECK9-NEXT: call void @__cxx_global_var_init() 5905 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 5906 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 5907 // CHECK9-NEXT: ret void 5908 // 5909 // 5910 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5911 // CHECK9-SAME: () #[[ATTR0]] { 5912 // CHECK9-NEXT: entry: 5913 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 5914 // CHECK9-NEXT: ret void 5915 // 5916 // 5917 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init 5918 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 5919 // CHECK10-NEXT: entry: 5920 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 5921 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5922 // CHECK10-NEXT: ret void 5923 // 5924 // 5925 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5926 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5927 // CHECK10-NEXT: entry: 5928 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5929 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5930 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5931 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 5932 // CHECK10-NEXT: ret void 5933 // 5934 // 5935 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5936 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5937 // CHECK10-NEXT: entry: 5938 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5939 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5940 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5941 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5942 // CHECK10-NEXT: ret void 5943 // 5944 // 5945 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5946 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5947 // CHECK10-NEXT: entry: 5948 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5949 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5950 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5951 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5952 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5953 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5954 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 5955 // CHECK10-NEXT: ret void 5956 // 5957 // 5958 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5959 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5960 // CHECK10-NEXT: entry: 5961 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5962 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5963 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5964 // CHECK10-NEXT: ret void 5965 // 5966 // 5967 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5968 // CHECK10-SAME: () #[[ATTR0]] { 5969 // CHECK10-NEXT: entry: 5970 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 5971 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 5972 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5973 // CHECK10-NEXT: ret void 5974 // 5975 // 5976 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5977 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5978 // CHECK10-NEXT: entry: 5979 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5980 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5981 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5982 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5983 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5984 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5985 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5986 // CHECK10-NEXT: ret void 5987 // 5988 // 5989 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5990 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5991 // CHECK10-NEXT: entry: 5992 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5993 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5994 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5995 // CHECK10: arraydestroy.body: 5996 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5997 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5998 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5999 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 6000 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 6001 // CHECK10: arraydestroy.done1: 6002 // CHECK10-NEXT: ret void 6003 // 6004 // 6005 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 6006 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6007 // CHECK10-NEXT: entry: 6008 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6009 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 6010 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6011 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 6012 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6013 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 6014 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 6015 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 6016 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 6017 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 6018 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 6019 // CHECK10-NEXT: ret void 6020 // 6021 // 6022 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 6023 // CHECK10-SAME: () #[[ATTR0]] { 6024 // CHECK10-NEXT: entry: 6025 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 6026 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 6027 // CHECK10-NEXT: ret void 6028 // 6029 // 6030 // CHECK10-LABEL: define {{[^@]+}}@main 6031 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 6032 // CHECK10-NEXT: entry: 6033 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 6034 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 6035 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 6036 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 6037 // CHECK10-NEXT: ret i32 0 6038 // 6039 // 6040 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 6041 // CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 6042 // CHECK10-NEXT: entry: 6043 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 6044 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 6045 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 6046 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 6047 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 6048 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 6049 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 6050 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 6051 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 6052 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 6053 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 6054 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 6055 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 6056 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 6057 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 6058 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 6059 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 6060 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 6061 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 6062 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 6063 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 6064 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 6065 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 6066 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 6067 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 6068 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 6069 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 6070 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 6071 // CHECK10-NEXT: ret void 6072 // 6073 // 6074 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 6075 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 6076 // CHECK10-NEXT: entry: 6077 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6078 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6079 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 6080 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 6081 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 6082 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 6083 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6084 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 6085 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 6086 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 6087 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6088 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6089 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 6090 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 6091 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 6092 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 6093 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6094 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6095 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 6096 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 6097 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 6098 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 6099 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 6100 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 6101 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 6102 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 6103 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 6104 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6105 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6106 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6107 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6108 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6109 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 6110 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 6111 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6112 // CHECK10: cond.true: 6113 // CHECK10-NEXT: br label [[COND_END:%.*]] 6114 // CHECK10: cond.false: 6115 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 6116 // CHECK10-NEXT: br label [[COND_END]] 6117 // CHECK10: cond.end: 6118 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6119 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 6120 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 6121 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6122 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6123 // CHECK10: omp.inner.for.cond: 6124 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6125 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 6126 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6127 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6128 // CHECK10: omp.inner.for.body: 6129 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 6130 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 6131 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 6132 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 6133 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 6134 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* 6135 // CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 6136 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 6137 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 6138 // CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 6139 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 6140 // CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 6141 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 6142 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 6143 // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 6144 // CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 6145 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 6146 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) 6147 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6148 // CHECK10: omp.inner.for.inc: 6149 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6150 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6151 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 6152 // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 6153 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 6154 // CHECK10: omp.inner.for.end: 6155 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6156 // CHECK10: omp.loop.exit: 6157 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6158 // CHECK10-NEXT: ret void 6159 // 6160 // 6161 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 6162 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 6163 // CHECK10-NEXT: entry: 6164 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6165 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6166 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 6167 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 6168 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 6169 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 6170 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 6171 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 6172 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6173 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 6174 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6175 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6176 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6177 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6178 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 6179 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 6180 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6181 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6182 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 6183 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 6184 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 6185 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 6186 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 6187 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 6188 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 6189 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 6190 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 6191 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6192 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 6193 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 6194 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32 6195 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 6196 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32 6197 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 6198 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 6199 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6200 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6201 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6202 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 6203 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6204 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6205 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 6206 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6207 // CHECK10: cond.true: 6208 // CHECK10-NEXT: br label [[COND_END:%.*]] 6209 // CHECK10: cond.false: 6210 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6211 // CHECK10-NEXT: br label [[COND_END]] 6212 // CHECK10: cond.end: 6213 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6214 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6215 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6216 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 6217 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6218 // CHECK10: omp.inner.for.cond: 6219 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6220 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6221 // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6222 // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6223 // CHECK10: omp.inner.for.body: 6224 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6225 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 6226 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6227 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6228 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 6229 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 6230 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 6231 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 6232 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 6233 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 6234 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 6235 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 6236 // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 6237 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 6238 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 6239 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 6240 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6241 // CHECK10: omp.body.continue: 6242 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6243 // CHECK10: omp.inner.for.inc: 6244 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6245 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 6246 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 6247 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 6248 // CHECK10: omp.inner.for.end: 6249 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6250 // CHECK10: omp.loop.exit: 6251 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 6252 // CHECK10-NEXT: ret void 6253 // 6254 // 6255 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 6256 // CHECK10-SAME: () #[[ATTR0]] { 6257 // CHECK10-NEXT: entry: 6258 // CHECK10-NEXT: call void @__cxx_global_var_init() 6259 // CHECK10-NEXT: call void @__cxx_global_var_init.1() 6260 // CHECK10-NEXT: call void @__cxx_global_var_init.2() 6261 // CHECK10-NEXT: ret void 6262 // 6263 // 6264 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6265 // CHECK10-SAME: () #[[ATTR0]] { 6266 // CHECK10-NEXT: entry: 6267 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 6268 // CHECK10-NEXT: ret void 6269 // 6270 // 6271 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 6272 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 6273 // CHECK11-NEXT: entry: 6274 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 6275 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 6276 // CHECK11-NEXT: ret void 6277 // 6278 // 6279 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 6280 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 6281 // CHECK11-NEXT: entry: 6282 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6283 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6284 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6285 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 6286 // CHECK11-NEXT: ret void 6287 // 6288 // 6289 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 6290 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6291 // CHECK11-NEXT: entry: 6292 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6293 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6294 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6295 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 6296 // CHECK11-NEXT: ret void 6297 // 6298 // 6299 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 6300 // CHECK11-SAME: () #[[ATTR0]] { 6301 // CHECK11-NEXT: entry: 6302 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 6303 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 6304 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 6305 // CHECK11-NEXT: ret void 6306 // 6307 // 6308 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 6309 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6310 // CHECK11-NEXT: entry: 6311 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6312 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 6313 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6314 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 6315 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6316 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 6317 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 6318 // CHECK11-NEXT: ret void 6319 // 6320 // 6321 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 6322 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 6323 // CHECK11-NEXT: entry: 6324 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 6325 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 6326 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 6327 // CHECK11: arraydestroy.body: 6328 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 6329 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 6330 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 6331 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 6332 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 6333 // CHECK11: arraydestroy.done1: 6334 // CHECK11-NEXT: ret void 6335 // 6336 // 6337 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 6338 // CHECK11-SAME: () #[[ATTR0]] { 6339 // CHECK11-NEXT: entry: 6340 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 6341 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 6342 // CHECK11-NEXT: ret void 6343 // 6344 // 6345 // CHECK11-LABEL: define {{[^@]+}}@main 6346 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 6347 // CHECK11-NEXT: entry: 6348 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 6349 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 6350 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 6351 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 6352 // CHECK11-NEXT: ret i32 0 6353 // 6354 // 6355 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 6356 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6357 // CHECK11-NEXT: entry: 6358 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6359 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6360 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6361 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 6362 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 6363 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 6364 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 6365 // CHECK11-NEXT: ret void 6366 // 6367 // 6368 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 6369 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6370 // CHECK11-NEXT: entry: 6371 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6372 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6373 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6374 // CHECK11-NEXT: ret void 6375 // 6376 // 6377 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 6378 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6379 // CHECK11-NEXT: entry: 6380 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6381 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 6382 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6383 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 6384 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6385 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 6386 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 6387 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 6388 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 6389 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 6390 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 6391 // CHECK11-NEXT: ret void 6392 // 6393 // 6394 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 6395 // CHECK11-SAME: () #[[ATTR0]] { 6396 // CHECK11-NEXT: entry: 6397 // CHECK11-NEXT: call void @__cxx_global_var_init() 6398 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 6399 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 6400 // CHECK11-NEXT: ret void 6401 // 6402 // 6403 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init 6404 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 6405 // CHECK12-NEXT: entry: 6406 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 6407 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 6408 // CHECK12-NEXT: ret void 6409 // 6410 // 6411 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 6412 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 6413 // CHECK12-NEXT: entry: 6414 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6415 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6416 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6417 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 6418 // CHECK12-NEXT: ret void 6419 // 6420 // 6421 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 6422 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6423 // CHECK12-NEXT: entry: 6424 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6425 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6426 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6427 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 6428 // CHECK12-NEXT: ret void 6429 // 6430 // 6431 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 6432 // CHECK12-SAME: () #[[ATTR0]] { 6433 // CHECK12-NEXT: entry: 6434 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 6435 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 6436 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 6437 // CHECK12-NEXT: ret void 6438 // 6439 // 6440 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 6441 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6442 // CHECK12-NEXT: entry: 6443 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6444 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 6445 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6446 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 6447 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6448 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 6449 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 6450 // CHECK12-NEXT: ret void 6451 // 6452 // 6453 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 6454 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 6455 // CHECK12-NEXT: entry: 6456 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 6457 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 6458 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 6459 // CHECK12: arraydestroy.body: 6460 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 6461 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 6462 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 6463 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 6464 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 6465 // CHECK12: arraydestroy.done1: 6466 // CHECK12-NEXT: ret void 6467 // 6468 // 6469 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 6470 // CHECK12-SAME: () #[[ATTR0]] { 6471 // CHECK12-NEXT: entry: 6472 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 6473 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 6474 // CHECK12-NEXT: ret void 6475 // 6476 // 6477 // CHECK12-LABEL: define {{[^@]+}}@main 6478 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 6479 // CHECK12-NEXT: entry: 6480 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 6481 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 6482 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 6483 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 6484 // CHECK12-NEXT: ret i32 0 6485 // 6486 // 6487 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 6488 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6489 // CHECK12-NEXT: entry: 6490 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6491 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6492 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6493 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 6494 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 6495 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 6496 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 6497 // CHECK12-NEXT: ret void 6498 // 6499 // 6500 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 6501 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6502 // CHECK12-NEXT: entry: 6503 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6504 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6505 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6506 // CHECK12-NEXT: ret void 6507 // 6508 // 6509 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 6510 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 6511 // CHECK12-NEXT: entry: 6512 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 6513 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 6514 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 6515 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 6516 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 6517 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 6518 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 6519 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 6520 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 6521 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 6522 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 6523 // CHECK12-NEXT: ret void 6524 // 6525 // 6526 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp 6527 // CHECK12-SAME: () #[[ATTR0]] { 6528 // CHECK12-NEXT: entry: 6529 // CHECK12-NEXT: call void @__cxx_global_var_init() 6530 // CHECK12-NEXT: call void @__cxx_global_var_init.1() 6531 // CHECK12-NEXT: call void @__cxx_global_var_init.2() 6532 // CHECK12-NEXT: ret void 6533 // 6534