1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute parallel for firstprivate(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global and bound tid vars
80 // skip loop vars
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84
85 // Skip global and bound tid vars, and prev lb and ub vars
86 // skip loop vars
87
88 // use of private vars
89 [&]() {
90 g = 2;
91 g1 = 2;
92 sivar = 4;
93
94 }();
95 }
96 }();
97 return 0;
98 #else
99 #pragma omp target
100 #pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var, sivar)
101 for (int i = 0; i < 2; ++i) {
102 vec[i] = t_var;
103 s_arr[i] = var;
104 sivar += i;
105 }
106 return tmain<int>();
107 #endif
108 }
109
110
111
112
113
114 // Skip global and bound tid vars
115 // Skip temp vars for loop
116
117 // param copy
118
119 // T_VAR and SIVAR
120
121 // preparation vars
122
123 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
124
125 // firstprivate(s_arr)
126
127 // firstprivate(var)
128
129
130 // Skip global and bound tid vars, and prev lb ub vars
131 // Skip temp vars for loop
132
133 // param copy
134
135 // T_VAR and SIVAR
136
137 // preparation vars
138
139 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
140
141 // firstprivate(s_arr)
142
143 // firstprivate(var)
144
145
146
147
148
149
150 // Skip global and bound tid vars
151 // Skip temp vars for loop
152
153 // param copy
154
155 // T_VAR and preparation variables
156
157 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
158
159 // firstprivate(s_arr)
160
161 // firstprivate(var)
162
163
164 // Skip global and bound tid vars
165 // Skip temp vars for loop
166
167 // param copy
168
169 // T_VAR and preparation variables
170
171 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
172
173 // firstprivate(s_arr)
174
175 // firstprivate(var)
176
177
178 #endif
179 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
180 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
181 // CHECK1-NEXT: entry:
182 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
183 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
184 // CHECK1-NEXT: ret void
185 //
186 //
187 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
188 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
189 // CHECK1-NEXT: entry:
190 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
191 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
192 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
193 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
194 // CHECK1-NEXT: ret void
195 //
196 //
197 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
198 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
199 // CHECK1-NEXT: entry:
200 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
201 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
202 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
203 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
204 // CHECK1-NEXT: ret void
205 //
206 //
207 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
208 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
209 // CHECK1-NEXT: entry:
210 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
211 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
212 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
213 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
214 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
215 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
216 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
217 // CHECK1-NEXT: ret void
218 //
219 //
220 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
221 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
222 // CHECK1-NEXT: entry:
223 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
224 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
225 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
226 // CHECK1-NEXT: ret void
227 //
228 //
229 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
230 // CHECK1-SAME: () #[[ATTR0]] {
231 // CHECK1-NEXT: entry:
232 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
233 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
234 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
235 // CHECK1-NEXT: ret void
236 //
237 //
238 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
239 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
240 // CHECK1-NEXT: entry:
241 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
242 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
243 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
244 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
245 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
246 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
247 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
248 // CHECK1-NEXT: ret void
249 //
250 //
251 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
252 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
253 // CHECK1-NEXT: entry:
254 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
255 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
256 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
257 // CHECK1: arraydestroy.body:
258 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
259 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
260 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
261 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
262 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
263 // CHECK1: arraydestroy.done1:
264 // CHECK1-NEXT: ret void
265 //
266 //
267 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
268 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
269 // CHECK1-NEXT: entry:
270 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
271 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
272 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
273 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
274 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
275 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
276 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
277 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
278 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
279 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
280 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
281 // CHECK1-NEXT: ret void
282 //
283 //
284 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
285 // CHECK1-SAME: () #[[ATTR0]] {
286 // CHECK1-NEXT: entry:
287 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
288 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
289 // CHECK1-NEXT: ret void
290 //
291 //
292 // CHECK1-LABEL: define {{[^@]+}}@main
293 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
294 // CHECK1-NEXT: entry:
295 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
296 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
297 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
298 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
299 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
300 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
301 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
303 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
304 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
305 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
306 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
307 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
308 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
309 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
310 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
311 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
312 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
313 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
314 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
315 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
316 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
317 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
318 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
319 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
320 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
321 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8
322 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
323 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
324 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8
325 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
326 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
327 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
328 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
329 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
330 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
331 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
332 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
333 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
334 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
335 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
336 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
337 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8
338 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
339 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
340 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8
341 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
342 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
343 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
344 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
345 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8
346 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
347 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
348 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
349 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
350 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8
351 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
352 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
353 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
354 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
355 // CHECK1-NEXT: store i32 1, i32* [[TMP31]], align 4
356 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
357 // CHECK1-NEXT: store i32 5, i32* [[TMP32]], align 4
358 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
359 // CHECK1-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8
360 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
361 // CHECK1-NEXT: store i8** [[TMP30]], i8*** [[TMP34]], align 8
362 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
363 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP35]], align 8
364 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
365 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP36]], align 8
366 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
367 // CHECK1-NEXT: store i8** null, i8*** [[TMP37]], align 8
368 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
369 // CHECK1-NEXT: store i8** null, i8*** [[TMP38]], align 8
370 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
371 // CHECK1-NEXT: store i64 2, i64* [[TMP39]], align 8
372 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
373 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
374 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
375 // CHECK1: omp_offload.failed:
376 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
377 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
378 // CHECK1: omp_offload.cont:
379 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
380 // CHECK1-NEXT: ret i32 [[CALL]]
381 //
382 //
383 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
384 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
385 // CHECK1-NEXT: entry:
386 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
387 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
388 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
389 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
390 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
391 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
392 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
393 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
394 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
395 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
396 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
397 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
398 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
399 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
400 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
401 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
402 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
403 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
404 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
405 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
406 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
407 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
408 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
409 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
410 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
411 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
412 // CHECK1-NEXT: ret void
413 //
414 //
415 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
416 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
417 // CHECK1-NEXT: entry:
418 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
419 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
420 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
421 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
422 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
423 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
424 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
425 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
426 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
427 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
428 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
429 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
430 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
431 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
432 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
433 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
434 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
435 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
436 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
437 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
438 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
439 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
440 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
441 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
442 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
443 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
444 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
445 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
446 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
447 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
448 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
449 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
450 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
451 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
452 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
453 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
454 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
455 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
456 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
457 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
458 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
459 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
460 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
461 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
462 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
463 // CHECK1: omp.arraycpy.body:
464 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
465 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
466 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
467 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
468 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
469 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
470 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
471 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
472 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
473 // CHECK1: omp.arraycpy.done4:
474 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
475 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]])
476 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
477 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
478 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
479 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
480 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
481 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
482 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
483 // CHECK1: cond.true:
484 // CHECK1-NEXT: br label [[COND_END:%.*]]
485 // CHECK1: cond.false:
486 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
487 // CHECK1-NEXT: br label [[COND_END]]
488 // CHECK1: cond.end:
489 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
490 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
491 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
492 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
493 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
494 // CHECK1: omp.inner.for.cond:
495 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
496 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
497 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
498 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
499 // CHECK1: omp.inner.for.cond.cleanup:
500 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
501 // CHECK1: omp.inner.for.body:
502 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
503 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
504 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
505 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
506 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
507 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
508 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
509 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
510 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
511 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
512 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
513 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
514 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
515 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
516 // CHECK1: omp.inner.for.inc:
517 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
518 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
519 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
520 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
521 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
522 // CHECK1: omp.inner.for.end:
523 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
524 // CHECK1: omp.loop.exit:
525 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
526 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
527 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
528 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
529 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
530 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
531 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
532 // CHECK1: arraydestroy.body:
533 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
534 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
535 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
536 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
537 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
538 // CHECK1: arraydestroy.done11:
539 // CHECK1-NEXT: ret void
540 //
541 //
542 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
543 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
544 // CHECK1-NEXT: entry:
545 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
546 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
547 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
548 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]])
549 // CHECK1-NEXT: ret void
550 //
551 //
552 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
553 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
554 // CHECK1-NEXT: entry:
555 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
556 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
557 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
558 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
559 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
560 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
561 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
562 // CHECK1-NEXT: ret void
563 //
564 //
565 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
566 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
567 // CHECK1-NEXT: entry:
568 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
569 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
570 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
571 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
572 // CHECK1-NEXT: ret void
573 //
574 //
575 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
576 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
577 // CHECK1-NEXT: entry:
578 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
579 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
580 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
581 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
582 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
583 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
584 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
585 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
586 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
587 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
588 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
589 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
590 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
591 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
592 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
593 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
594 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
595 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
596 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
597 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
598 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
599 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
600 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
601 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
602 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
603 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
604 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
605 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
606 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
607 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
608 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
609 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
610 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
611 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
612 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
613 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
614 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
615 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
616 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
617 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
618 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
619 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
620 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
621 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
622 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
623 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
624 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
625 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
626 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
627 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
628 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
629 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
630 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
631 // CHECK1: omp.arraycpy.body:
632 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
633 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
634 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
635 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
636 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
637 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
638 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
639 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
640 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
641 // CHECK1: omp.arraycpy.done6:
642 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
643 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]])
644 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
645 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
646 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
647 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
648 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
649 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
650 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
651 // CHECK1: cond.true:
652 // CHECK1-NEXT: br label [[COND_END:%.*]]
653 // CHECK1: cond.false:
654 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
655 // CHECK1-NEXT: br label [[COND_END]]
656 // CHECK1: cond.end:
657 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
658 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
659 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
660 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
661 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
662 // CHECK1: omp.inner.for.cond:
663 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
664 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
665 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
666 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
667 // CHECK1: omp.inner.for.cond.cleanup:
668 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
669 // CHECK1: omp.inner.for.body:
670 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
671 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
672 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
673 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
674 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
675 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
676 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
677 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
678 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
679 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
680 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
681 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
682 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
683 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
684 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
685 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
686 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
687 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
688 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
689 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
690 // CHECK1: omp.body.continue:
691 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
692 // CHECK1: omp.inner.for.inc:
693 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
694 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
695 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
696 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
697 // CHECK1: omp.inner.for.end:
698 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
699 // CHECK1: omp.loop.exit:
700 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
701 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
702 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
703 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
704 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
705 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
706 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
707 // CHECK1: arraydestroy.body:
708 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
709 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
710 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
711 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
712 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
713 // CHECK1: arraydestroy.done15:
714 // CHECK1-NEXT: ret void
715 //
716 //
717 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
718 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
719 // CHECK1-NEXT: entry:
720 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
721 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
722 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
723 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
724 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
725 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
726 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
727 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
728 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
729 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
730 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
731 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
732 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
733 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
734 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
735 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
736 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
737 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
738 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
739 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
740 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
741 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
742 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
743 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
744 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
745 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
746 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
747 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
748 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
749 // CHECK1-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
750 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
751 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
752 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8
753 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
754 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
755 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
756 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
757 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
758 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
759 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
760 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8
761 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
762 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
763 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8
764 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
765 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8
766 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
767 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
768 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
769 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
770 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
771 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8
772 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
773 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
774 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
775 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
776 // CHECK1-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8
777 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
778 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
779 // CHECK1-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8
780 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
781 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8
782 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
783 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
784 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
785 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
786 // CHECK1-NEXT: store i32 1, i32* [[TMP29]], align 4
787 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
788 // CHECK1-NEXT: store i32 4, i32* [[TMP30]], align 4
789 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
790 // CHECK1-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8
791 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
792 // CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
793 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
794 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64** [[TMP33]], align 8
795 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
796 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i64** [[TMP34]], align 8
797 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
798 // CHECK1-NEXT: store i8** null, i8*** [[TMP35]], align 8
799 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
800 // CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8
801 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
802 // CHECK1-NEXT: store i64 2, i64* [[TMP37]], align 8
803 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
804 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
805 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
806 // CHECK1: omp_offload.failed:
807 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
808 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
809 // CHECK1: omp_offload.cont:
810 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
811 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
812 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
813 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
814 // CHECK1: arraydestroy.body:
815 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
816 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
817 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
818 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
819 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
820 // CHECK1: arraydestroy.done2:
821 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
822 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[RETVAL]], align 4
823 // CHECK1-NEXT: ret i32 [[TMP41]]
824 //
825 //
826 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
827 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
828 // CHECK1-NEXT: entry:
829 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
830 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
831 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
832 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
833 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
834 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
835 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4
836 // CHECK1-NEXT: ret void
837 //
838 //
839 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
840 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
841 // CHECK1-NEXT: entry:
842 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
843 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
844 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
845 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
846 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
847 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
848 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
849 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
850 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
851 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
852 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
853 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
854 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
855 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
856 // CHECK1-NEXT: ret void
857 //
858 //
859 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
860 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
861 // CHECK1-NEXT: entry:
862 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
863 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
864 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
865 // CHECK1-NEXT: ret void
866 //
867 //
868 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
869 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
870 // CHECK1-NEXT: entry:
871 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
872 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
873 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
874 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
875 // CHECK1-NEXT: ret void
876 //
877 //
878 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
879 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
880 // CHECK1-NEXT: entry:
881 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
882 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
883 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
884 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
885 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
886 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
887 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
888 // CHECK1-NEXT: ret void
889 //
890 //
891 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
892 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
893 // CHECK1-NEXT: entry:
894 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
895 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
896 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
897 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
898 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
899 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
900 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
901 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
902 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
903 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
904 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
905 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
906 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
907 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
908 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
909 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
910 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
911 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
912 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
913 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
914 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
915 // CHECK1-NEXT: ret void
916 //
917 //
918 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
919 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
920 // CHECK1-NEXT: entry:
921 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
922 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
923 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
924 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
925 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
926 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
927 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
928 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
929 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
930 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
931 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
932 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
933 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
934 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
935 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
936 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
937 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
938 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
939 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
940 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
941 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
942 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
943 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
944 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
945 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
946 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
947 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
948 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
949 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
950 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
951 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
952 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
953 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
954 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
955 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
956 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
957 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
958 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
959 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
960 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
961 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
962 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
963 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
964 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
965 // CHECK1: omp.arraycpy.body:
966 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
967 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
968 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
969 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
970 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
971 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
972 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
973 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
974 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
975 // CHECK1: omp.arraycpy.done4:
976 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
977 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
978 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]])
979 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
980 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
981 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
982 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
983 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
984 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
985 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
986 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
987 // CHECK1: cond.true:
988 // CHECK1-NEXT: br label [[COND_END:%.*]]
989 // CHECK1: cond.false:
990 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
991 // CHECK1-NEXT: br label [[COND_END]]
992 // CHECK1: cond.end:
993 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
994 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
995 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
996 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
997 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
998 // CHECK1: omp.inner.for.cond:
999 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1000 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1001 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1002 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1003 // CHECK1: omp.inner.for.cond.cleanup:
1004 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1005 // CHECK1: omp.inner.for.body:
1006 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1007 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
1008 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1009 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
1010 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
1011 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1012 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
1013 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1014 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
1015 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
1016 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1017 // CHECK1: omp.inner.for.inc:
1018 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1019 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1020 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1021 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1022 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1023 // CHECK1: omp.inner.for.end:
1024 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1025 // CHECK1: omp.loop.exit:
1026 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1027 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
1028 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
1029 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1030 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
1031 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
1032 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1033 // CHECK1: arraydestroy.body:
1034 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1035 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1036 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1037 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1038 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1039 // CHECK1: arraydestroy.done11:
1040 // CHECK1-NEXT: ret void
1041 //
1042 //
1043 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1044 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1045 // CHECK1-NEXT: entry:
1046 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1047 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1048 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1049 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1050 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1051 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1052 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
1053 // CHECK1-NEXT: ret void
1054 //
1055 //
1056 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
1057 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1058 // CHECK1-NEXT: entry:
1059 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1060 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1061 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1062 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1063 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1064 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1065 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1066 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1067 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1068 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1069 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1070 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1071 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1072 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1073 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1074 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1075 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1076 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1077 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1078 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
1079 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
1080 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1081 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1082 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1083 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1084 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1085 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1086 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1087 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1088 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1089 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1090 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1091 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1092 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1093 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1094 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1095 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1096 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1097 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
1098 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1099 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
1100 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
1101 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
1102 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1103 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1104 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1105 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1106 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
1107 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1108 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
1109 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1110 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
1111 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1112 // CHECK1: omp.arraycpy.body:
1113 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1114 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1115 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1116 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
1117 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1118 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1119 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1120 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1121 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1122 // CHECK1: omp.arraycpy.done6:
1123 // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1124 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
1125 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]])
1126 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
1127 // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
1128 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1129 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
1130 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1131 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1132 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
1133 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1134 // CHECK1: cond.true:
1135 // CHECK1-NEXT: br label [[COND_END:%.*]]
1136 // CHECK1: cond.false:
1137 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1138 // CHECK1-NEXT: br label [[COND_END]]
1139 // CHECK1: cond.end:
1140 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1141 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1142 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1143 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
1144 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1145 // CHECK1: omp.inner.for.cond:
1146 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1147 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1148 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1149 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1150 // CHECK1: omp.inner.for.cond.cleanup:
1151 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1152 // CHECK1: omp.inner.for.body:
1153 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1154 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1155 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1156 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1157 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
1158 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1159 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
1160 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
1161 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
1162 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
1163 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
1164 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
1165 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
1166 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
1167 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
1168 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false)
1169 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1170 // CHECK1: omp.body.continue:
1171 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1172 // CHECK1: omp.inner.for.inc:
1173 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1174 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
1175 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
1176 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1177 // CHECK1: omp.inner.for.end:
1178 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1179 // CHECK1: omp.loop.exit:
1180 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1181 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1182 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1183 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
1184 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1185 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
1186 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1187 // CHECK1: arraydestroy.body:
1188 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1189 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1190 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1191 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1192 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1193 // CHECK1: arraydestroy.done15:
1194 // CHECK1-NEXT: ret void
1195 //
1196 //
1197 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1198 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1199 // CHECK1-NEXT: entry:
1200 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1201 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1202 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1203 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1204 // CHECK1-NEXT: ret void
1205 //
1206 //
1207 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1208 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1209 // CHECK1-NEXT: entry:
1210 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1211 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1212 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1213 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1214 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1215 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1216 // CHECK1-NEXT: ret void
1217 //
1218 //
1219 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1220 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1221 // CHECK1-NEXT: entry:
1222 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1223 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1224 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1225 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1226 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1227 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1228 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1229 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1230 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1231 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1232 // CHECK1-NEXT: ret void
1233 //
1234 //
1235 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
1236 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1237 // CHECK1-NEXT: entry:
1238 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1239 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1240 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1241 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1242 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1243 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1244 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1245 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
1246 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
1247 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1248 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1249 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1250 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1251 // CHECK1-NEXT: ret void
1252 //
1253 //
1254 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1255 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1256 // CHECK1-NEXT: entry:
1257 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1258 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1259 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1260 // CHECK1-NEXT: ret void
1261 //
1262 //
1263 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp
1264 // CHECK1-SAME: () #[[ATTR0]] {
1265 // CHECK1-NEXT: entry:
1266 // CHECK1-NEXT: call void @__cxx_global_var_init()
1267 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
1268 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
1269 // CHECK1-NEXT: ret void
1270 //
1271 //
1272 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1273 // CHECK1-SAME: () #[[ATTR0]] {
1274 // CHECK1-NEXT: entry:
1275 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1276 // CHECK1-NEXT: ret void
1277 //
1278 //
1279 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1280 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1281 // CHECK3-NEXT: entry:
1282 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1283 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1284 // CHECK3-NEXT: ret void
1285 //
1286 //
1287 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1288 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1289 // CHECK3-NEXT: entry:
1290 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1291 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1292 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1293 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1294 // CHECK3-NEXT: ret void
1295 //
1296 //
1297 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1298 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1299 // CHECK3-NEXT: entry:
1300 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1301 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1302 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1303 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1304 // CHECK3-NEXT: ret void
1305 //
1306 //
1307 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1308 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1309 // CHECK3-NEXT: entry:
1310 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1311 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1312 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1313 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1314 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1315 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1316 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
1317 // CHECK3-NEXT: ret void
1318 //
1319 //
1320 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1321 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1322 // CHECK3-NEXT: entry:
1323 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1324 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1325 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1326 // CHECK3-NEXT: ret void
1327 //
1328 //
1329 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1330 // CHECK3-SAME: () #[[ATTR0]] {
1331 // CHECK3-NEXT: entry:
1332 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
1333 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
1334 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1335 // CHECK3-NEXT: ret void
1336 //
1337 //
1338 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1339 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1340 // CHECK3-NEXT: entry:
1341 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1342 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1343 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1344 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1345 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1346 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1347 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1348 // CHECK3-NEXT: ret void
1349 //
1350 //
1351 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1352 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1353 // CHECK3-NEXT: entry:
1354 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1355 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1356 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1357 // CHECK3: arraydestroy.body:
1358 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1359 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1360 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1361 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1362 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1363 // CHECK3: arraydestroy.done1:
1364 // CHECK3-NEXT: ret void
1365 //
1366 //
1367 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1368 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1369 // CHECK3-NEXT: entry:
1370 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1371 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1372 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1373 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1374 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1375 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1376 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1377 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1378 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1379 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1380 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1381 // CHECK3-NEXT: ret void
1382 //
1383 //
1384 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1385 // CHECK3-SAME: () #[[ATTR0]] {
1386 // CHECK3-NEXT: entry:
1387 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1388 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1389 // CHECK3-NEXT: ret void
1390 //
1391 //
1392 // CHECK3-LABEL: define {{[^@]+}}@main
1393 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1394 // CHECK3-NEXT: entry:
1395 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1396 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1397 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1398 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
1399 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
1400 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
1401 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1402 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1403 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
1404 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
1405 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1406 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1407 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
1408 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1409 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1410 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
1411 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
1412 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1413 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
1414 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
1415 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1416 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
1417 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1418 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
1419 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4
1420 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1421 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
1422 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4
1423 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1424 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
1425 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1426 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
1427 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
1428 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1429 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
1430 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
1431 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1432 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
1433 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1434 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
1435 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4
1436 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1437 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
1438 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4
1439 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1440 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1441 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1442 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
1443 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4
1444 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1445 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
1446 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4
1447 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1448 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
1449 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1450 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1451 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1452 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1453 // CHECK3-NEXT: store i32 1, i32* [[TMP31]], align 4
1454 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1455 // CHECK3-NEXT: store i32 5, i32* [[TMP32]], align 4
1456 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1457 // CHECK3-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 4
1458 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1459 // CHECK3-NEXT: store i8** [[TMP30]], i8*** [[TMP34]], align 4
1460 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1461 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP35]], align 4
1462 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1463 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP36]], align 4
1464 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1465 // CHECK3-NEXT: store i8** null, i8*** [[TMP37]], align 4
1466 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1467 // CHECK3-NEXT: store i8** null, i8*** [[TMP38]], align 4
1468 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1469 // CHECK3-NEXT: store i64 2, i64* [[TMP39]], align 8
1470 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1471 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
1472 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1473 // CHECK3: omp_offload.failed:
1474 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
1475 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1476 // CHECK3: omp_offload.cont:
1477 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1478 // CHECK3-NEXT: ret i32 [[CALL]]
1479 //
1480 //
1481 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
1482 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1483 // CHECK3-NEXT: entry:
1484 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1485 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1486 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1487 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1488 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1489 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1490 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1491 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1492 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1493 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1494 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1495 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1496 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1497 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1498 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1499 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
1500 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
1501 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1502 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
1503 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
1504 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1505 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
1506 // CHECK3-NEXT: ret void
1507 //
1508 //
1509 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1510 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
1511 // CHECK3-NEXT: entry:
1512 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1513 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1514 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1515 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1516 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1517 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1518 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1519 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1520 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1521 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1522 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1523 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1524 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1525 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
1526 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1527 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1528 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1529 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1530 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1531 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1532 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1533 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1534 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1535 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1536 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1537 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1538 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1539 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1540 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1541 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1542 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1543 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1544 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1545 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1546 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1547 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
1548 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1549 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
1550 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1551 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1552 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1553 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
1554 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1555 // CHECK3: omp.arraycpy.body:
1556 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1557 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1558 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1559 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
1560 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1561 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1562 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1563 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1564 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1565 // CHECK3: omp.arraycpy.done3:
1566 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1567 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]])
1568 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1569 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1570 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1571 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1572 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1573 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1574 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1575 // CHECK3: cond.true:
1576 // CHECK3-NEXT: br label [[COND_END:%.*]]
1577 // CHECK3: cond.false:
1578 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1579 // CHECK3-NEXT: br label [[COND_END]]
1580 // CHECK3: cond.end:
1581 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1582 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1583 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1584 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1585 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1586 // CHECK3: omp.inner.for.cond:
1587 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1588 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1589 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1590 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1591 // CHECK3: omp.inner.for.cond.cleanup:
1592 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1593 // CHECK3: omp.inner.for.body:
1594 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1595 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1596 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
1597 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4
1598 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1599 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
1600 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4
1601 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1602 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]])
1603 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1604 // CHECK3: omp.inner.for.inc:
1605 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1606 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1607 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1608 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1609 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1610 // CHECK3: omp.inner.for.end:
1611 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1612 // CHECK3: omp.loop.exit:
1613 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1614 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
1615 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
1616 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1617 // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1618 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
1619 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1620 // CHECK3: arraydestroy.body:
1621 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1622 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1623 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1624 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1625 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1626 // CHECK3: arraydestroy.done8:
1627 // CHECK3-NEXT: ret void
1628 //
1629 //
1630 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1631 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1632 // CHECK3-NEXT: entry:
1633 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
1634 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
1635 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
1636 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]])
1637 // CHECK3-NEXT: ret void
1638 //
1639 //
1640 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1641 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1642 // CHECK3-NEXT: entry:
1643 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1644 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
1645 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1646 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
1647 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1648 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
1649 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
1650 // CHECK3-NEXT: ret void
1651 //
1652 //
1653 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1654 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1655 // CHECK3-NEXT: entry:
1656 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
1657 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
1658 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
1659 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
1660 // CHECK3-NEXT: ret void
1661 //
1662 //
1663 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1664 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
1665 // CHECK3-NEXT: entry:
1666 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1667 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1668 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1669 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1670 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1671 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1672 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1673 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1674 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1675 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1676 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1677 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1678 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1679 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1680 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1681 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
1682 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1683 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1684 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1685 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1686 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1687 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1688 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1689 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1690 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1691 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1692 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1693 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1694 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1695 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1696 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1697 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1698 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1699 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1700 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1701 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1702 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1703 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
1704 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
1705 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1706 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1707 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
1708 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1709 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
1710 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1711 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1712 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1713 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
1714 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1715 // CHECK3: omp.arraycpy.body:
1716 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1717 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1718 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1719 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
1720 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1721 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1722 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1723 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1724 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1725 // CHECK3: omp.arraycpy.done3:
1726 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1727 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]])
1728 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1729 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1730 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1731 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1732 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1733 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
1734 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1735 // CHECK3: cond.true:
1736 // CHECK3-NEXT: br label [[COND_END:%.*]]
1737 // CHECK3: cond.false:
1738 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1739 // CHECK3-NEXT: br label [[COND_END]]
1740 // CHECK3: cond.end:
1741 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1742 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1743 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1744 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1745 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1746 // CHECK3: omp.inner.for.cond:
1747 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1748 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1749 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1750 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1751 // CHECK3: omp.inner.for.cond.cleanup:
1752 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1753 // CHECK3: omp.inner.for.body:
1754 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1755 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
1756 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1757 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1758 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
1759 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
1760 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
1761 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
1762 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1763 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
1764 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
1765 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
1766 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
1767 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
1768 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
1769 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
1770 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
1771 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1772 // CHECK3: omp.body.continue:
1773 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1774 // CHECK3: omp.inner.for.inc:
1775 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1776 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
1777 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
1778 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1779 // CHECK3: omp.inner.for.end:
1780 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1781 // CHECK3: omp.loop.exit:
1782 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1783 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1784 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1785 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1786 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
1787 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
1788 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1789 // CHECK3: arraydestroy.body:
1790 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1791 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1792 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1793 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1794 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1795 // CHECK3: arraydestroy.done11:
1796 // CHECK3-NEXT: ret void
1797 //
1798 //
1799 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1800 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
1801 // CHECK3-NEXT: entry:
1802 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1803 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1804 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1805 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1806 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1807 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1808 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
1809 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1810 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
1811 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
1812 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
1813 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1814 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1815 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
1816 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1817 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1818 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1819 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1820 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1821 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1822 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1823 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
1824 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
1825 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1826 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
1827 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1828 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
1829 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
1830 // CHECK3-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
1831 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1832 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
1833 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4
1834 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1835 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
1836 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
1837 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1838 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
1839 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1840 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
1841 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4
1842 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1843 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
1844 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4
1845 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1846 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4
1847 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1848 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
1849 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
1850 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1851 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
1852 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4
1853 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1854 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
1855 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1856 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
1857 // CHECK3-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4
1858 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1859 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
1860 // CHECK3-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4
1861 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1862 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
1863 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1864 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1865 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1866 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1867 // CHECK3-NEXT: store i32 1, i32* [[TMP29]], align 4
1868 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1869 // CHECK3-NEXT: store i32 4, i32* [[TMP30]], align 4
1870 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1871 // CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
1872 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1873 // CHECK3-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4
1874 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1875 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64** [[TMP33]], align 4
1876 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1877 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i64** [[TMP34]], align 4
1878 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1879 // CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4
1880 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1881 // CHECK3-NEXT: store i8** null, i8*** [[TMP36]], align 4
1882 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1883 // CHECK3-NEXT: store i64 2, i64* [[TMP37]], align 8
1884 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB3]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1885 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
1886 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1887 // CHECK3: omp_offload.failed:
1888 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
1889 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1890 // CHECK3: omp_offload.cont:
1891 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1892 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1893 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1894 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1895 // CHECK3: arraydestroy.body:
1896 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1897 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1898 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1899 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1900 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1901 // CHECK3: arraydestroy.done2:
1902 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1903 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[RETVAL]], align 4
1904 // CHECK3-NEXT: ret i32 [[TMP41]]
1905 //
1906 //
1907 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1908 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1909 // CHECK3-NEXT: entry:
1910 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
1911 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
1912 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
1913 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
1914 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
1915 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
1916 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4
1917 // CHECK3-NEXT: ret void
1918 //
1919 //
1920 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1921 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1922 // CHECK3-NEXT: entry:
1923 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1924 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
1925 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1926 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
1927 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1928 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1929 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
1930 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
1931 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
1932 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1933 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1934 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1935 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1936 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1937 // CHECK3-NEXT: ret void
1938 //
1939 //
1940 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1941 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1942 // CHECK3-NEXT: entry:
1943 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
1944 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
1945 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
1946 // CHECK3-NEXT: ret void
1947 //
1948 //
1949 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1950 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1951 // CHECK3-NEXT: entry:
1952 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1953 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1954 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1955 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1956 // CHECK3-NEXT: ret void
1957 //
1958 //
1959 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1960 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1961 // CHECK3-NEXT: entry:
1962 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1963 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1964 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1965 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1966 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1967 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1968 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1969 // CHECK3-NEXT: ret void
1970 //
1971 //
1972 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1973 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1974 // CHECK3-NEXT: entry:
1975 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1976 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1977 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
1978 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
1979 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
1980 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1981 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1982 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1983 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
1984 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
1985 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1986 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
1987 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
1988 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
1989 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
1990 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
1991 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1992 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
1993 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
1994 // CHECK3-NEXT: ret void
1995 //
1996 //
1997 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
1998 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1999 // CHECK3-NEXT: entry:
2000 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2001 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2002 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2003 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2004 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2005 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2006 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2007 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2008 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2009 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2010 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2011 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2012 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2013 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
2014 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2015 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2016 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2017 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2018 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
2019 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2020 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2021 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2022 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2023 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2024 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2025 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2026 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2027 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2028 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2029 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2030 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2031 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2032 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2033 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2034 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2035 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
2036 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2037 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
2038 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2039 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2040 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2041 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
2042 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2043 // CHECK3: omp.arraycpy.body:
2044 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2045 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2046 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2047 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
2048 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2049 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2050 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2051 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2052 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2053 // CHECK3: omp.arraycpy.done4:
2054 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2055 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2056 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]])
2057 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2058 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
2059 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2060 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
2061 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2062 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2063 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
2064 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2065 // CHECK3: cond.true:
2066 // CHECK3-NEXT: br label [[COND_END:%.*]]
2067 // CHECK3: cond.false:
2068 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2069 // CHECK3-NEXT: br label [[COND_END]]
2070 // CHECK3: cond.end:
2071 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2072 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2073 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2074 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
2075 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2076 // CHECK3: omp.inner.for.cond:
2077 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2078 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2079 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2080 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2081 // CHECK3: omp.inner.for.cond.cleanup:
2082 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2083 // CHECK3: omp.inner.for.body:
2084 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2085 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2086 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2087 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4
2088 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2089 // CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
2090 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]])
2091 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2092 // CHECK3: omp.inner.for.inc:
2093 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2094 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2095 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2096 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2097 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2098 // CHECK3: omp.inner.for.end:
2099 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2100 // CHECK3: omp.loop.exit:
2101 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2102 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
2103 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
2104 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2105 // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2106 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
2107 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2108 // CHECK3: arraydestroy.body:
2109 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2110 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2111 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2112 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
2113 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
2114 // CHECK3: arraydestroy.done10:
2115 // CHECK3-NEXT: ret void
2116 //
2117 //
2118 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2119 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2120 // CHECK3-NEXT: entry:
2121 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2122 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
2123 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2124 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
2125 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2126 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
2127 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]])
2128 // CHECK3-NEXT: ret void
2129 //
2130 //
2131 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
2132 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2133 // CHECK3-NEXT: entry:
2134 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2135 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2136 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2137 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2138 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2139 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2140 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2141 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2142 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2143 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2144 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2145 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2146 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2147 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2148 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2149 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
2150 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2151 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2152 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2153 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2154 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
2155 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2156 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2157 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2158 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2159 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2160 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2161 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2162 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2163 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2164 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2165 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2166 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2167 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2168 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2169 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2170 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2171 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2172 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
2173 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
2174 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2175 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2176 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
2177 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2178 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
2179 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2180 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2181 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2182 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
2183 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2184 // CHECK3: omp.arraycpy.body:
2185 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2186 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2187 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2188 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]])
2189 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2190 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2191 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2192 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
2193 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2194 // CHECK3: omp.arraycpy.done4:
2195 // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2196 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2197 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]])
2198 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2199 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
2200 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2201 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
2202 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2203 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2204 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
2205 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2206 // CHECK3: cond.true:
2207 // CHECK3-NEXT: br label [[COND_END:%.*]]
2208 // CHECK3: cond.false:
2209 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2210 // CHECK3-NEXT: br label [[COND_END]]
2211 // CHECK3: cond.end:
2212 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
2213 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2214 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2215 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
2216 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2217 // CHECK3: omp.inner.for.cond:
2218 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2219 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2220 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
2221 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2222 // CHECK3: omp.inner.for.cond.cleanup:
2223 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2224 // CHECK3: omp.inner.for.body:
2225 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2226 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
2227 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2228 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2229 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2230 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2231 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
2232 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
2233 // CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
2234 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
2235 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
2236 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
2237 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
2238 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false)
2239 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2240 // CHECK3: omp.body.continue:
2241 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2242 // CHECK3: omp.inner.for.inc:
2243 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2244 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
2245 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
2246 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2247 // CHECK3: omp.inner.for.end:
2248 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2249 // CHECK3: omp.loop.exit:
2250 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2251 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2252 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2253 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2254 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2255 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
2256 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2257 // CHECK3: arraydestroy.body:
2258 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2259 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2260 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2261 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2262 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2263 // CHECK3: arraydestroy.done12:
2264 // CHECK3-NEXT: ret void
2265 //
2266 //
2267 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2268 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2269 // CHECK3-NEXT: entry:
2270 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2271 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2272 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2273 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2274 // CHECK3-NEXT: ret void
2275 //
2276 //
2277 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2278 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2279 // CHECK3-NEXT: entry:
2280 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2281 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2282 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2283 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2284 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2285 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2286 // CHECK3-NEXT: ret void
2287 //
2288 //
2289 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2290 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2291 // CHECK3-NEXT: entry:
2292 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2293 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2294 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2295 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2296 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2297 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2298 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2299 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2300 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2301 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2302 // CHECK3-NEXT: ret void
2303 //
2304 //
2305 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2306 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2307 // CHECK3-NEXT: entry:
2308 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2309 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
2310 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2311 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
2312 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2313 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2314 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
2315 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
2316 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
2317 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2318 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2319 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2320 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2321 // CHECK3-NEXT: ret void
2322 //
2323 //
2324 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2325 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2326 // CHECK3-NEXT: entry:
2327 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2328 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2329 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2330 // CHECK3-NEXT: ret void
2331 //
2332 //
2333 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp
2334 // CHECK3-SAME: () #[[ATTR0]] {
2335 // CHECK3-NEXT: entry:
2336 // CHECK3-NEXT: call void @__cxx_global_var_init()
2337 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
2338 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
2339 // CHECK3-NEXT: ret void
2340 //
2341 //
2342 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2343 // CHECK3-SAME: () #[[ATTR0]] {
2344 // CHECK3-NEXT: entry:
2345 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2346 // CHECK3-NEXT: ret void
2347 //
2348 //
2349 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
2350 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
2351 // CHECK9-NEXT: entry:
2352 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2353 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2354 // CHECK9-NEXT: ret void
2355 //
2356 //
2357 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2358 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2359 // CHECK9-NEXT: entry:
2360 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2361 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2362 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2363 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2364 // CHECK9-NEXT: ret void
2365 //
2366 //
2367 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2368 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2369 // CHECK9-NEXT: entry:
2370 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2371 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2372 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2373 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2374 // CHECK9-NEXT: ret void
2375 //
2376 //
2377 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2378 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2379 // CHECK9-NEXT: entry:
2380 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2381 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2382 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2383 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2384 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2385 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2386 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
2387 // CHECK9-NEXT: ret void
2388 //
2389 //
2390 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2391 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2392 // CHECK9-NEXT: entry:
2393 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2394 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2395 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2396 // CHECK9-NEXT: ret void
2397 //
2398 //
2399 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2400 // CHECK9-SAME: () #[[ATTR0]] {
2401 // CHECK9-NEXT: entry:
2402 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2403 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2404 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2405 // CHECK9-NEXT: ret void
2406 //
2407 //
2408 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2409 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2410 // CHECK9-NEXT: entry:
2411 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2412 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2413 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2414 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2415 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2416 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2417 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2418 // CHECK9-NEXT: ret void
2419 //
2420 //
2421 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2422 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2423 // CHECK9-NEXT: entry:
2424 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2425 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2426 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2427 // CHECK9: arraydestroy.body:
2428 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2429 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2430 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2431 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2432 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2433 // CHECK9: arraydestroy.done1:
2434 // CHECK9-NEXT: ret void
2435 //
2436 //
2437 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2438 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2439 // CHECK9-NEXT: entry:
2440 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2441 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2442 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2443 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2444 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2445 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2446 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2447 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2448 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2449 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2450 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
2451 // CHECK9-NEXT: ret void
2452 //
2453 //
2454 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2455 // CHECK9-SAME: () #[[ATTR0]] {
2456 // CHECK9-NEXT: entry:
2457 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2458 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2459 // CHECK9-NEXT: ret void
2460 //
2461 //
2462 // CHECK9-LABEL: define {{[^@]+}}@main
2463 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2464 // CHECK9-NEXT: entry:
2465 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2466 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2467 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
2468 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2469 // CHECK9-NEXT: ret i32 0
2470 //
2471 //
2472 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
2473 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
2474 // CHECK9-NEXT: entry:
2475 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
2476 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2477 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2478 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2479 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
2480 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
2481 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2482 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
2483 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2484 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
2485 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
2486 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2487 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2488 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
2489 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
2490 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
2491 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
2492 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
2493 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
2494 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
2495 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
2496 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
2497 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
2498 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
2499 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
2500 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
2501 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
2502 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
2503 // CHECK9-NEXT: ret void
2504 //
2505 //
2506 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
2507 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] {
2508 // CHECK9-NEXT: entry:
2509 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2510 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2511 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
2512 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2513 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2514 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2515 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2516 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
2517 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2518 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2519 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2520 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2521 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2522 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
2523 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
2524 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2525 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2526 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2527 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
2528 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
2529 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2530 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
2531 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2532 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2533 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
2534 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2535 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2536 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2537 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2538 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2539 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2540 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2541 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2542 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2543 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2544 // CHECK9: cond.true:
2545 // CHECK9-NEXT: br label [[COND_END:%.*]]
2546 // CHECK9: cond.false:
2547 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2548 // CHECK9-NEXT: br label [[COND_END]]
2549 // CHECK9: cond.end:
2550 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2551 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2552 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2553 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2554 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2555 // CHECK9: omp.inner.for.cond:
2556 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2557 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2558 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2559 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2560 // CHECK9: omp.inner.for.body:
2561 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2562 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2563 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2564 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2565 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
2566 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
2567 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
2568 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
2569 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
2570 // CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
2571 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
2572 // CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
2573 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
2574 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
2575 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
2576 // CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
2577 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
2578 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
2579 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2580 // CHECK9: omp.inner.for.inc:
2581 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2582 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2583 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2584 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2585 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
2586 // CHECK9: omp.inner.for.end:
2587 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2588 // CHECK9: omp.loop.exit:
2589 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2590 // CHECK9-NEXT: ret void
2591 //
2592 //
2593 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
2594 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] {
2595 // CHECK9-NEXT: entry:
2596 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2597 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2598 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2599 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2600 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
2601 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2602 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2603 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
2604 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2605 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
2606 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2607 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2608 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2609 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2610 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2611 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2612 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2613 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2614 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2615 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2616 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
2617 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
2618 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
2619 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
2620 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
2621 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
2622 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
2623 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2624 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2625 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2626 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
2627 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2628 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
2629 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
2630 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
2631 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2632 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2633 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2634 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2635 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2636 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2637 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2638 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2639 // CHECK9: cond.true:
2640 // CHECK9-NEXT: br label [[COND_END:%.*]]
2641 // CHECK9: cond.false:
2642 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2643 // CHECK9-NEXT: br label [[COND_END]]
2644 // CHECK9: cond.end:
2645 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2646 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2647 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2648 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2649 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2650 // CHECK9: omp.inner.for.cond:
2651 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2652 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2653 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2654 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2655 // CHECK9: omp.inner.for.body:
2656 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2657 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2658 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2659 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2660 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4
2661 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
2662 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
2663 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4
2664 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
2665 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
2666 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
2667 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
2668 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
2669 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
2670 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
2671 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
2672 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2673 // CHECK9: omp.body.continue:
2674 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2675 // CHECK9: omp.inner.for.inc:
2676 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2677 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
2678 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
2679 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
2680 // CHECK9: omp.inner.for.end:
2681 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2682 // CHECK9: omp.loop.exit:
2683 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2684 // CHECK9-NEXT: ret void
2685 //
2686 //
2687 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp
2688 // CHECK9-SAME: () #[[ATTR0]] {
2689 // CHECK9-NEXT: entry:
2690 // CHECK9-NEXT: call void @__cxx_global_var_init()
2691 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
2692 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
2693 // CHECK9-NEXT: ret void
2694 //
2695 //
2696 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2697 // CHECK9-SAME: () #[[ATTR0]] {
2698 // CHECK9-NEXT: entry:
2699 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
2700 // CHECK9-NEXT: ret void
2701 //
2702