1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 6 // Test host codegen. 7 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 9 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 10 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 13 14 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 17 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 20 #ifdef CK1 21 22 template <typename T, int X, long long Y> 23 struct SS{ 24 T a[X][Y]; 25 26 int foo(void) { 27 28 #pragma omp target 29 #pragma omp teams distribute collapse(2) 30 for(int i = 0; i < X; i++) { 31 for(int j = 0; j < Y; j++) { 32 a[i][j] = (T)0; 33 } 34 } 35 36 // discard loop variables not needed here 37 38 return a[0][0]; 39 } 40 }; 41 42 int teams_template_struct(void) { 43 SS<int, 123, 456> V; 44 return V.foo(); 45 46 } 47 #endif // CK1 48 49 // Test host codegen. 50 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 52 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 53 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 54 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 55 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 56 57 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 58 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 59 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 60 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 62 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 63 #ifdef CK2 64 65 template <typename T, int n, int m> 66 int tmain(T argc) { 67 T a[n][m]; 68 #pragma omp target 69 #pragma omp teams distribute collapse(2) 70 for(int i = 0; i < n; i++) { 71 for(int j = 0; j < m; j++) { 72 a[i][j] = (T)0; 73 } 74 } 75 return 0; 76 } 77 78 int main (int argc, char **argv) { 79 int n = 100; 80 int m = 2; 81 int a[n][m]; 82 #pragma omp target 83 #pragma omp teams distribute collapse(2) 84 for(int i = 0; i < n; i++) { 85 for(int j = 0; j < m; j++) { 86 a[i][j] = 0; 87 } 88 } 89 return tmain<int, 10, 2>(argc); 90 } 91 92 93 94 95 96 // discard loop variables not needed here 97 98 #endif // CK2 99 #endif // #ifndef HEADER 100 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv 101 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 102 // CHECK1-NEXT: entry: 103 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 104 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 105 // CHECK1-NEXT: ret i32 [[CALL]] 106 // 107 // 108 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 109 // CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 110 // CHECK1-NEXT: entry: 111 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 112 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 113 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 114 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 115 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 116 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 117 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 118 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 119 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 120 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 121 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 122 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 123 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 124 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 125 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 126 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 127 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 128 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 129 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 130 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 131 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 132 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 133 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 134 // CHECK1: omp_offload.failed: 135 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 136 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 137 // CHECK1: omp_offload.cont: 138 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 139 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 140 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 141 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 142 // CHECK1-NEXT: ret i32 [[TMP9]] 143 // 144 // 145 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 146 // CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 149 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 150 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 151 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 152 // CHECK1-NEXT: ret void 153 // 154 // 155 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 156 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { 157 // CHECK1-NEXT: entry: 158 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 159 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 160 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 161 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 162 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 163 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 165 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 166 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 167 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 168 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 169 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 170 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 171 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 172 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 173 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 174 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 175 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 176 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 177 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 178 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 179 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 180 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 181 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 182 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 183 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 184 // CHECK1: cond.true: 185 // CHECK1-NEXT: br label [[COND_END:%.*]] 186 // CHECK1: cond.false: 187 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 188 // CHECK1-NEXT: br label [[COND_END]] 189 // CHECK1: cond.end: 190 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 191 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 192 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 193 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 194 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 195 // CHECK1: omp.inner.for.cond: 196 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 197 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 198 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 199 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 200 // CHECK1: omp.inner.for.body: 201 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 202 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 203 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 204 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 205 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 206 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 207 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 208 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 209 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 210 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 211 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 212 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 213 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 214 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 215 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 216 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 217 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 218 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 219 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 220 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 221 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 222 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 223 // CHECK1: omp.body.continue: 224 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 225 // CHECK1: omp.inner.for.inc: 226 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 227 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 228 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 229 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 230 // CHECK1: omp.inner.for.end: 231 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 232 // CHECK1: omp.loop.exit: 233 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 234 // CHECK1-NEXT: ret void 235 // 236 // 237 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 238 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 239 // CHECK1-NEXT: entry: 240 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 241 // CHECK1-NEXT: ret void 242 // 243 // 244 // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_template_structv 245 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 246 // CHECK2-NEXT: entry: 247 // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 248 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 249 // CHECK2-NEXT: ret i32 [[CALL]] 250 // 251 // 252 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 253 // CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 254 // CHECK2-NEXT: entry: 255 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 256 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 257 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 258 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 259 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 260 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 261 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 262 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 263 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 264 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 265 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 266 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 267 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 268 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 269 // CHECK2-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 270 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 271 // CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8 272 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 273 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 274 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 275 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 276 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 277 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 278 // CHECK2: omp_offload.failed: 279 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 280 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 281 // CHECK2: omp_offload.cont: 282 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 283 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 284 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 285 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 286 // CHECK2-NEXT: ret i32 [[TMP9]] 287 // 288 // 289 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 290 // CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 291 // CHECK2-NEXT: entry: 292 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 293 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 294 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 295 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 296 // CHECK2-NEXT: ret void 297 // 298 // 299 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 300 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { 301 // CHECK2-NEXT: entry: 302 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 303 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 304 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 305 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 306 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 307 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 308 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 309 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 310 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 311 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 312 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 313 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 314 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 315 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 316 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 317 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 318 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 319 // CHECK2-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 320 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 321 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 322 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 323 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 324 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 325 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 326 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 327 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 328 // CHECK2: cond.true: 329 // CHECK2-NEXT: br label [[COND_END:%.*]] 330 // CHECK2: cond.false: 331 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 332 // CHECK2-NEXT: br label [[COND_END]] 333 // CHECK2: cond.end: 334 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 335 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 336 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 337 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 338 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 339 // CHECK2: omp.inner.for.cond: 340 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 341 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 342 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 343 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 344 // CHECK2: omp.inner.for.body: 345 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 346 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 347 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 348 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 349 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 350 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 351 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 352 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 353 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 354 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 355 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 356 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 357 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 358 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 359 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 360 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 361 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 362 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 363 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 364 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 365 // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 366 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 367 // CHECK2: omp.body.continue: 368 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 369 // CHECK2: omp.inner.for.inc: 370 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 371 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 372 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 373 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 374 // CHECK2: omp.inner.for.end: 375 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 376 // CHECK2: omp.loop.exit: 377 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 378 // CHECK2-NEXT: ret void 379 // 380 // 381 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 382 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 383 // CHECK2-NEXT: entry: 384 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 385 // CHECK2-NEXT: ret void 386 // 387 // 388 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv 389 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 390 // CHECK3-NEXT: entry: 391 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 392 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 393 // CHECK3-NEXT: ret i32 [[CALL]] 394 // 395 // 396 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 397 // CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 398 // CHECK3-NEXT: entry: 399 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 400 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 401 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 402 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 403 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 404 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 405 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 406 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 407 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 408 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 409 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 410 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 411 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 412 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 413 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 414 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 415 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 416 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 417 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 418 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 419 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 420 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 421 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 422 // CHECK3: omp_offload.failed: 423 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 424 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 425 // CHECK3: omp_offload.cont: 426 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 427 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 428 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 429 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 430 // CHECK3-NEXT: ret i32 [[TMP9]] 431 // 432 // 433 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 434 // CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 435 // CHECK3-NEXT: entry: 436 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 437 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 438 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 439 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 440 // CHECK3-NEXT: ret void 441 // 442 // 443 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 444 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { 445 // CHECK3-NEXT: entry: 446 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 447 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 448 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 449 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 450 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 451 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 452 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 453 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 454 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 455 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 456 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 457 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 458 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 459 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 460 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 461 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 462 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 463 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 464 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 465 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 466 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 467 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 468 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 469 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 470 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 471 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 472 // CHECK3: cond.true: 473 // CHECK3-NEXT: br label [[COND_END:%.*]] 474 // CHECK3: cond.false: 475 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 476 // CHECK3-NEXT: br label [[COND_END]] 477 // CHECK3: cond.end: 478 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 479 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 480 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 481 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 482 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 483 // CHECK3: omp.inner.for.cond: 484 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 485 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 486 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 487 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 488 // CHECK3: omp.inner.for.body: 489 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 490 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 491 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 492 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 493 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 494 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 495 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 496 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 497 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 498 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 499 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 500 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 501 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 502 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 503 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 504 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 505 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 506 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 507 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 508 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 509 // CHECK3: omp.body.continue: 510 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 511 // CHECK3: omp.inner.for.inc: 512 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 513 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 514 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 515 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 516 // CHECK3: omp.inner.for.end: 517 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 518 // CHECK3: omp.loop.exit: 519 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 520 // CHECK3-NEXT: ret void 521 // 522 // 523 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 524 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 525 // CHECK3-NEXT: entry: 526 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 527 // CHECK3-NEXT: ret void 528 // 529 // 530 // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_template_structv 531 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 532 // CHECK4-NEXT: entry: 533 // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 534 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 535 // CHECK4-NEXT: ret i32 [[CALL]] 536 // 537 // 538 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 539 // CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 540 // CHECK4-NEXT: entry: 541 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 542 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 543 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 544 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 545 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 546 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 547 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 548 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 549 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 550 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 551 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 552 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 553 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 554 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 555 // CHECK4-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 556 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 557 // CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4 558 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 559 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 560 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 561 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 562 // CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 563 // CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 564 // CHECK4: omp_offload.failed: 565 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 566 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 567 // CHECK4: omp_offload.cont: 568 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 569 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 570 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 571 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 572 // CHECK4-NEXT: ret i32 [[TMP9]] 573 // 574 // 575 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 576 // CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 577 // CHECK4-NEXT: entry: 578 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 579 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 580 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 581 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 582 // CHECK4-NEXT: ret void 583 // 584 // 585 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 586 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { 587 // CHECK4-NEXT: entry: 588 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 589 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 590 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 591 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 592 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 593 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 594 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 595 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 596 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 597 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 598 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 599 // CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 600 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 601 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 602 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 603 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 604 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 605 // CHECK4-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 606 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 607 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 608 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 609 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 610 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 611 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 612 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 613 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 614 // CHECK4: cond.true: 615 // CHECK4-NEXT: br label [[COND_END:%.*]] 616 // CHECK4: cond.false: 617 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 618 // CHECK4-NEXT: br label [[COND_END]] 619 // CHECK4: cond.end: 620 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 621 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 622 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 623 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 624 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 625 // CHECK4: omp.inner.for.cond: 626 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 627 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 628 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 629 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 630 // CHECK4: omp.inner.for.body: 631 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 632 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 633 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 634 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 635 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 636 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 637 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 638 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 639 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 640 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 641 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 642 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 643 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 644 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 645 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 646 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 647 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 648 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 649 // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 650 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 651 // CHECK4: omp.body.continue: 652 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 653 // CHECK4: omp.inner.for.inc: 654 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 655 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 656 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 657 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 658 // CHECK4: omp.inner.for.end: 659 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 660 // CHECK4: omp.loop.exit: 661 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 662 // CHECK4-NEXT: ret void 663 // 664 // 665 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 666 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 667 // CHECK4-NEXT: entry: 668 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 669 // CHECK4-NEXT: ret void 670 // 671 // 672 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv 673 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 674 // CHECK5-NEXT: entry: 675 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 676 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 677 // CHECK5-NEXT: ret i32 [[CALL]] 678 // 679 // 680 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 681 // CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 682 // CHECK5-NEXT: entry: 683 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 684 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 685 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 686 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 687 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 688 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 689 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 690 // CHECK5: for.cond: 691 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 692 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 693 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] 694 // CHECK5: for.body: 695 // CHECK5-NEXT: store i32 0, i32* [[J]], align 4 696 // CHECK5-NEXT: br label [[FOR_COND2:%.*]] 697 // CHECK5: for.cond2: 698 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 699 // CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 700 // CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 701 // CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 702 // CHECK5: for.body4: 703 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 704 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 705 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 706 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 707 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 708 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 709 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] 710 // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 711 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 712 // CHECK5: for.inc: 713 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 714 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 715 // CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 716 // CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] 717 // CHECK5: for.end: 718 // CHECK5-NEXT: br label [[FOR_INC7:%.*]] 719 // CHECK5: for.inc7: 720 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 721 // CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 722 // CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 723 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 724 // CHECK5: for.end9: 725 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 726 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 727 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 728 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 729 // CHECK5-NEXT: ret i32 [[TMP6]] 730 // 731 // 732 // CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv 733 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 734 // CHECK6-NEXT: entry: 735 // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 736 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 737 // CHECK6-NEXT: ret i32 [[CALL]] 738 // 739 // 740 // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 741 // CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 742 // CHECK6-NEXT: entry: 743 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 744 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 745 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 746 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 747 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 748 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 749 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 750 // CHECK6: for.cond: 751 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 752 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 753 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] 754 // CHECK6: for.body: 755 // CHECK6-NEXT: store i32 0, i32* [[J]], align 4 756 // CHECK6-NEXT: br label [[FOR_COND2:%.*]] 757 // CHECK6: for.cond2: 758 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 759 // CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 760 // CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 761 // CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 762 // CHECK6: for.body4: 763 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 764 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 765 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 766 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 767 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 768 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 769 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] 770 // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 771 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 772 // CHECK6: for.inc: 773 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 774 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 775 // CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 776 // CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] 777 // CHECK6: for.end: 778 // CHECK6-NEXT: br label [[FOR_INC7:%.*]] 779 // CHECK6: for.inc7: 780 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 781 // CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 782 // CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 783 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 784 // CHECK6: for.end9: 785 // CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 786 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 787 // CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 788 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 789 // CHECK6-NEXT: ret i32 [[TMP6]] 790 // 791 // 792 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv 793 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 794 // CHECK7-NEXT: entry: 795 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 796 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 797 // CHECK7-NEXT: ret i32 [[CALL]] 798 // 799 // 800 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 801 // CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 802 // CHECK7-NEXT: entry: 803 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 804 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 805 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 806 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 807 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 808 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 809 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 810 // CHECK7: for.cond: 811 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 812 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 813 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] 814 // CHECK7: for.body: 815 // CHECK7-NEXT: store i32 0, i32* [[J]], align 4 816 // CHECK7-NEXT: br label [[FOR_COND2:%.*]] 817 // CHECK7: for.cond2: 818 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 819 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 820 // CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 821 // CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 822 // CHECK7: for.body4: 823 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 824 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 825 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] 826 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 827 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] 828 // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 829 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 830 // CHECK7: for.inc: 831 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 832 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 833 // CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 834 // CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] 835 // CHECK7: for.end: 836 // CHECK7-NEXT: br label [[FOR_INC6:%.*]] 837 // CHECK7: for.inc6: 838 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 839 // CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 840 // CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 841 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 842 // CHECK7: for.end8: 843 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 844 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 845 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 846 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 847 // CHECK7-NEXT: ret i32 [[TMP6]] 848 // 849 // 850 // CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv 851 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 852 // CHECK8-NEXT: entry: 853 // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 854 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) 855 // CHECK8-NEXT: ret i32 [[CALL]] 856 // 857 // 858 // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 859 // CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 860 // CHECK8-NEXT: entry: 861 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 862 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 863 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 864 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 865 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 866 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 867 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 868 // CHECK8: for.cond: 869 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 870 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 871 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] 872 // CHECK8: for.body: 873 // CHECK8-NEXT: store i32 0, i32* [[J]], align 4 874 // CHECK8-NEXT: br label [[FOR_COND2:%.*]] 875 // CHECK8: for.cond2: 876 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 877 // CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 878 // CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 879 // CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 880 // CHECK8: for.body4: 881 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 882 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 883 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] 884 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 885 // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] 886 // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 887 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 888 // CHECK8: for.inc: 889 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 890 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 891 // CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 892 // CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] 893 // CHECK8: for.end: 894 // CHECK8-NEXT: br label [[FOR_INC6:%.*]] 895 // CHECK8: for.inc6: 896 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 897 // CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 898 // CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 899 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 900 // CHECK8: for.end8: 901 // CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 902 // CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 903 // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 904 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 905 // CHECK8-NEXT: ret i32 [[TMP6]] 906 // 907 // 908 // CHECK9-LABEL: define {{[^@]+}}@main 909 // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 910 // CHECK9-NEXT: entry: 911 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 912 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 913 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 914 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 915 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 916 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 917 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 918 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 919 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 920 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 921 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 922 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 923 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 924 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 925 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 926 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 927 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 928 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 929 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 930 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 931 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 932 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 933 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4 934 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4 935 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 936 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 937 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 938 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 939 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 940 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 941 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 942 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 943 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 944 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 945 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 946 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 947 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 948 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 949 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 950 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 951 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 952 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 953 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 954 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 955 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 956 // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 957 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 958 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 959 // CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 960 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 961 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 962 // CHECK9-NEXT: store i64 4, i64* [[TMP16]], align 8 963 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 964 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 965 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 966 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 967 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 968 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 969 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 970 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 971 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 972 // CHECK9-NEXT: store i64 4, i64* [[TMP22]], align 8 973 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 974 // CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 975 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 976 // CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 977 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 978 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 979 // CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 980 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 981 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 982 // CHECK9-NEXT: store i64 8, i64* [[TMP28]], align 8 983 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 984 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 985 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 986 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 987 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 988 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 989 // CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* 990 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 991 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 992 // CHECK9-NEXT: store i64 8, i64* [[TMP34]], align 8 993 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 994 // CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8 995 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 996 // CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** 997 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 998 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 999 // CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** 1000 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 1001 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1002 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 1003 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1004 // CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8 1005 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1006 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1007 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1008 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 1009 // CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 1010 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 1011 // CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 1012 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1013 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 1014 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1015 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 1016 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 1017 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 1018 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1019 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1020 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 1021 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1022 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 1023 // CHECK9-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 1024 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 1025 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1026 // CHECK9-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1027 // CHECK9-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 1028 // CHECK9-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1029 // CHECK9: omp_offload.failed: 1030 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 1031 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1032 // CHECK9: omp_offload.cont: 1033 // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1034 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) 1035 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1036 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1037 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) 1038 // CHECK9-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 1039 // CHECK9-NEXT: ret i32 [[TMP54]] 1040 // 1041 // 1042 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 1043 // CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1044 // CHECK9-NEXT: entry: 1045 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1046 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1047 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1048 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1049 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1050 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1051 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1052 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1053 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1054 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1055 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1056 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1057 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1058 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1059 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1060 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 1061 // CHECK9-NEXT: ret void 1062 // 1063 // 1064 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 1065 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1066 // CHECK9-NEXT: entry: 1067 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1068 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1069 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 1070 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 1071 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1072 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1073 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1074 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1075 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1076 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1077 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1078 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1079 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1080 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1081 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1082 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1083 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1084 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1085 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1086 // CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 1087 // CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 1088 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1089 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1090 // CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 1091 // CHECK9-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 1092 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1093 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1094 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1095 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 1096 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 1097 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1098 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1099 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1100 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 1101 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 1102 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 1103 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1104 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1105 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1106 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1107 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1108 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1109 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1110 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1111 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1112 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1113 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1114 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1115 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 1116 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4 1117 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1118 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1119 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1120 // CHECK9: land.lhs.true: 1121 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1122 // CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1123 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1124 // CHECK9: omp.precond.then: 1125 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1126 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1127 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 1128 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1129 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1130 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1131 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 1132 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1133 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1134 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1135 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 1136 // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1137 // CHECK9: cond.true: 1138 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1139 // CHECK9-NEXT: br label [[COND_END:%.*]] 1140 // CHECK9: cond.false: 1141 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1142 // CHECK9-NEXT: br label [[COND_END]] 1143 // CHECK9: cond.end: 1144 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 1145 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1146 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1147 // CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 1148 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1149 // CHECK9: omp.inner.for.cond: 1150 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1151 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1152 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 1153 // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1154 // CHECK9: omp.inner.for.body: 1155 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1156 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1157 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 1158 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1159 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1160 // CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1161 // CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 1162 // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1163 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1164 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1165 // CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 1166 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1167 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1168 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1169 // CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 1170 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1171 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1172 // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1173 // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 1174 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1175 // CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 1176 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1177 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1178 // CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1179 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1180 // CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 1181 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1182 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1183 // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1184 // CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 1185 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 1186 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 1187 // CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 1188 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] 1189 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 1190 // CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 1191 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] 1192 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 1193 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1194 // CHECK9: omp.body.continue: 1195 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1196 // CHECK9: omp.inner.for.inc: 1197 // CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1198 // CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 1199 // CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 1200 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1201 // CHECK9: omp.inner.for.end: 1202 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1203 // CHECK9: omp.loop.exit: 1204 // CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1205 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 1206 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 1207 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 1208 // CHECK9: omp.precond.end: 1209 // CHECK9-NEXT: ret void 1210 // 1211 // 1212 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1213 // CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { 1214 // CHECK9-NEXT: entry: 1215 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1216 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1217 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1218 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1219 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1220 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1221 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1222 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1223 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1224 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1225 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 1226 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1227 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1228 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 1229 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1230 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 1231 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1232 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1233 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1234 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1235 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1236 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1237 // CHECK9: omp_offload.failed: 1238 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 1239 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1240 // CHECK9: omp_offload.cont: 1241 // CHECK9-NEXT: ret i32 0 1242 // 1243 // 1244 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 1245 // CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1246 // CHECK9-NEXT: entry: 1247 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1248 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1249 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1250 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1251 // CHECK9-NEXT: ret void 1252 // 1253 // 1254 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 1255 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1256 // CHECK9-NEXT: entry: 1257 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1258 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1259 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1260 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1261 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1262 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1263 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1264 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1265 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1266 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1267 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1268 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1269 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1270 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1271 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1272 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1273 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1274 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1275 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1276 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1277 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1278 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1279 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1280 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1281 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1282 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1283 // CHECK9: cond.true: 1284 // CHECK9-NEXT: br label [[COND_END:%.*]] 1285 // CHECK9: cond.false: 1286 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1287 // CHECK9-NEXT: br label [[COND_END]] 1288 // CHECK9: cond.end: 1289 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1290 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1291 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1292 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1293 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1294 // CHECK9: omp.inner.for.cond: 1295 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1296 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1297 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1298 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1299 // CHECK9: omp.inner.for.body: 1300 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1301 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1302 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1303 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1304 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1305 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1306 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1307 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1308 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1309 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1310 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1311 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1312 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 1313 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1314 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1315 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1316 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 1317 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1318 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1319 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 1320 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1321 // CHECK9: omp.body.continue: 1322 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1323 // CHECK9: omp.inner.for.inc: 1324 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1325 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1326 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 1327 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1328 // CHECK9: omp.inner.for.end: 1329 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1330 // CHECK9: omp.loop.exit: 1331 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1332 // CHECK9-NEXT: ret void 1333 // 1334 // 1335 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1336 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] { 1337 // CHECK9-NEXT: entry: 1338 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1339 // CHECK9-NEXT: ret void 1340 // 1341 // 1342 // CHECK10-LABEL: define {{[^@]+}}@main 1343 // CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1344 // CHECK10-NEXT: entry: 1345 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1346 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1347 // CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 1348 // CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 1349 // CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 1350 // CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1351 // CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1352 // CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1353 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1354 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 1355 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1356 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1357 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1358 // CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1359 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1360 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1361 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1362 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 1363 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 1364 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1365 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1366 // CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1367 // CHECK10-NEXT: store i32 100, i32* [[N]], align 4 1368 // CHECK10-NEXT: store i32 2, i32* [[M]], align 4 1369 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1370 // CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1371 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1372 // CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1373 // CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1374 // CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1375 // CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1376 // CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1377 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1378 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1379 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1380 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1381 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 1382 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 1383 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 1384 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1385 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 1386 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 1387 // CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1388 // CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 1389 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1390 // CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1391 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8 1392 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1393 // CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1394 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8 1395 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1396 // CHECK10-NEXT: store i64 4, i64* [[TMP16]], align 8 1397 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1398 // CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 1399 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1400 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1401 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 1402 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1403 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1404 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 1405 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 1406 // CHECK10-NEXT: store i64 4, i64* [[TMP22]], align 8 1407 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1408 // CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 1409 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1410 // CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1411 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8 1412 // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1413 // CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1414 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 1415 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 1416 // CHECK10-NEXT: store i64 8, i64* [[TMP28]], align 8 1417 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1418 // CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 1419 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1420 // CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1421 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 1422 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1423 // CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64* 1424 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8 1425 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1426 // CHECK10-NEXT: store i64 8, i64* [[TMP34]], align 8 1427 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1428 // CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8 1429 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1430 // CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32** 1431 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8 1432 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1433 // CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32** 1434 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8 1435 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1436 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8 1437 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1438 // CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8 1439 // CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1440 // CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1441 // CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1442 // CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4 1443 // CHECK10-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4 1444 // CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4 1445 // CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4 1446 // CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1447 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0 1448 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1449 // CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 1450 // CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 1451 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0 1452 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1453 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1454 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 1455 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1456 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 1457 // CHECK10-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 1458 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1 1459 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1460 // CHECK10-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1461 // CHECK10-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 1462 // CHECK10-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1463 // CHECK10: omp_offload.failed: 1464 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 1465 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1466 // CHECK10: omp_offload.cont: 1467 // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1468 // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) 1469 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1470 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1471 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) 1472 // CHECK10-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4 1473 // CHECK10-NEXT: ret i32 [[TMP54]] 1474 // 1475 // 1476 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 1477 // CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1478 // CHECK10-NEXT: entry: 1479 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1480 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1481 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1482 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1483 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1484 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1485 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1486 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1487 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1488 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1489 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1490 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1491 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1492 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1493 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1494 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 1495 // CHECK10-NEXT: ret void 1496 // 1497 // 1498 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 1499 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1500 // CHECK10-NEXT: entry: 1501 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1502 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1503 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 1504 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 1505 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1506 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1507 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1508 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1509 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1510 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1511 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1512 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1513 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1514 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1515 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1516 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1517 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1518 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1519 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1520 // CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4 1521 // CHECK10-NEXT: [[J12:%.*]] = alloca i32, align 4 1522 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1523 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1524 // CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 1525 // CHECK10-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 1526 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1527 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1528 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1529 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 1530 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 1531 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1532 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1533 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1534 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 1535 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 1536 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 1537 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1538 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1539 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1540 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1541 // CHECK10-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1542 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1543 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1544 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1545 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1546 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1547 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1548 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1549 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 1550 // CHECK10-NEXT: store i32 0, i32* [[J]], align 4 1551 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1552 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1553 // CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1554 // CHECK10: land.lhs.true: 1555 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1556 // CHECK10-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1557 // CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1558 // CHECK10: omp.precond.then: 1559 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1560 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1561 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 1562 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1563 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1564 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1565 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 1566 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1567 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1568 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1569 // CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 1570 // CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1571 // CHECK10: cond.true: 1572 // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1573 // CHECK10-NEXT: br label [[COND_END:%.*]] 1574 // CHECK10: cond.false: 1575 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1576 // CHECK10-NEXT: br label [[COND_END]] 1577 // CHECK10: cond.end: 1578 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 1579 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1580 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1581 // CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 1582 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1583 // CHECK10: omp.inner.for.cond: 1584 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1585 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1586 // CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 1587 // CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1588 // CHECK10: omp.inner.for.body: 1589 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1590 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1591 // CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 1592 // CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1593 // CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1594 // CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1595 // CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 1596 // CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1597 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1598 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1599 // CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 1600 // CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1601 // CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1602 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1603 // CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 1604 // CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1605 // CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1606 // CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1607 // CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 1608 // CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1609 // CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 1610 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1611 // CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1612 // CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1613 // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1614 // CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 1615 // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1616 // CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1617 // CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1618 // CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 1619 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 1620 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 1621 // CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 1622 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] 1623 // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 1624 // CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 1625 // CHECK10-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] 1626 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 1627 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1628 // CHECK10: omp.body.continue: 1629 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1630 // CHECK10: omp.inner.for.inc: 1631 // CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1632 // CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 1633 // CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 1634 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 1635 // CHECK10: omp.inner.for.end: 1636 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1637 // CHECK10: omp.loop.exit: 1638 // CHECK10-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1639 // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 1640 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 1641 // CHECK10-NEXT: br label [[OMP_PRECOND_END]] 1642 // CHECK10: omp.precond.end: 1643 // CHECK10-NEXT: ret void 1644 // 1645 // 1646 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1647 // CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { 1648 // CHECK10-NEXT: entry: 1649 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1650 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1651 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1652 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1653 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1654 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1655 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1656 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1657 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1658 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1659 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 1660 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1661 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1662 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 1663 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1664 // CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 1665 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1666 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1667 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1668 // CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1669 // CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1670 // CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1671 // CHECK10: omp_offload.failed: 1672 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 1673 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1674 // CHECK10: omp_offload.cont: 1675 // CHECK10-NEXT: ret i32 0 1676 // 1677 // 1678 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 1679 // CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1680 // CHECK10-NEXT: entry: 1681 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1682 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1683 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1684 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1685 // CHECK10-NEXT: ret void 1686 // 1687 // 1688 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 1689 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1690 // CHECK10-NEXT: entry: 1691 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1692 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1693 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1694 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1695 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1696 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1697 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1698 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1699 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1700 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1701 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1702 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1703 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1704 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1705 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1706 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1707 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1708 // CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1709 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1710 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1711 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1712 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1713 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1714 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1715 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1716 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1717 // CHECK10: cond.true: 1718 // CHECK10-NEXT: br label [[COND_END:%.*]] 1719 // CHECK10: cond.false: 1720 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1721 // CHECK10-NEXT: br label [[COND_END]] 1722 // CHECK10: cond.end: 1723 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1724 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1725 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1726 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1727 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1728 // CHECK10: omp.inner.for.cond: 1729 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1730 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1731 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1732 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1733 // CHECK10: omp.inner.for.body: 1734 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1735 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1736 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1737 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1738 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1739 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1740 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1741 // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1742 // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1743 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1744 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1745 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1746 // CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 1747 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1748 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1749 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1750 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 1751 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1752 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1753 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 1754 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1755 // CHECK10: omp.body.continue: 1756 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1757 // CHECK10: omp.inner.for.inc: 1758 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1759 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1760 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 1761 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 1762 // CHECK10: omp.inner.for.end: 1763 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1764 // CHECK10: omp.loop.exit: 1765 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1766 // CHECK10-NEXT: ret void 1767 // 1768 // 1769 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1770 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] { 1771 // CHECK10-NEXT: entry: 1772 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 1773 // CHECK10-NEXT: ret void 1774 // 1775 // 1776 // CHECK11-LABEL: define {{[^@]+}}@main 1777 // CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1778 // CHECK11-NEXT: entry: 1779 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1780 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1781 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1782 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 1783 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 1784 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1785 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1786 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1787 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1788 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1789 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1790 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1791 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1792 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1793 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1794 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1795 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1796 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1797 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1798 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1799 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1800 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1801 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4 1802 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4 1803 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1804 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1805 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1806 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1807 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1808 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1809 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1810 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1811 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1812 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 1813 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 1814 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 1815 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 1816 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 1817 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1818 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 1819 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 1820 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1821 // CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1822 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 1823 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1824 // CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1825 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 1826 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1827 // CHECK11-NEXT: store i64 4, i64* [[TMP15]], align 4 1828 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1829 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 1830 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1831 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1832 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 1833 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1834 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1835 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 1836 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 1837 // CHECK11-NEXT: store i64 4, i64* [[TMP21]], align 4 1838 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1839 // CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4 1840 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1841 // CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 1842 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 1843 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1844 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 1845 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 1846 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 1847 // CHECK11-NEXT: store i64 4, i64* [[TMP27]], align 4 1848 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1849 // CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 1850 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1851 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1852 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 1853 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1854 // CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 1855 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 1856 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1857 // CHECK11-NEXT: store i64 4, i64* [[TMP33]], align 4 1858 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1859 // CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4 1860 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1861 // CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 1862 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 1863 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1864 // CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** 1865 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 1866 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1867 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 1868 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1869 // CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 1870 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1871 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1872 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1873 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 1874 // CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 1875 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 1876 // CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1877 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1878 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 1879 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1880 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1881 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1882 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 1883 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1884 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1885 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1886 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1887 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1888 // CHECK11-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1889 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 1890 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1891 // CHECK11-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1892 // CHECK11-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 1893 // CHECK11-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1894 // CHECK11: omp_offload.failed: 1895 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 1896 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1897 // CHECK11: omp_offload.cont: 1898 // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1899 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) 1900 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1901 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1902 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) 1903 // CHECK11-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 1904 // CHECK11-NEXT: ret i32 [[TMP53]] 1905 // 1906 // 1907 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 1908 // CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1909 // CHECK11-NEXT: entry: 1910 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1911 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1912 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1913 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1914 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1915 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1916 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 1917 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1918 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1919 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1920 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1921 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1922 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1923 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 1924 // CHECK11-NEXT: ret void 1925 // 1926 // 1927 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 1928 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1929 // CHECK11-NEXT: entry: 1930 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1931 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1932 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 1933 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 1934 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1935 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1936 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1937 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1938 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1939 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1940 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1941 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1942 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1943 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1944 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1945 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1946 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1947 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1948 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1949 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 1950 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 1951 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1952 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1953 // CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 1954 // CHECK11-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 1955 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1956 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1957 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1958 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 1959 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 1960 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1961 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1962 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1963 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 1964 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 1965 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 1966 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1967 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1968 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1969 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1970 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1971 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1972 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1973 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1974 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1975 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1976 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1977 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1978 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 1979 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4 1980 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1981 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1982 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1983 // CHECK11: land.lhs.true: 1984 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1985 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1986 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1987 // CHECK11: omp.precond.then: 1988 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1989 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1990 // CHECK11-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 1991 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1992 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1993 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1994 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 1995 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1996 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1997 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1998 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 1999 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2000 // CHECK11: cond.true: 2001 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2002 // CHECK11-NEXT: br label [[COND_END:%.*]] 2003 // CHECK11: cond.false: 2004 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2005 // CHECK11-NEXT: br label [[COND_END]] 2006 // CHECK11: cond.end: 2007 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 2008 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2009 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2010 // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 2011 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2012 // CHECK11: omp.inner.for.cond: 2013 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2014 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2015 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 2016 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2017 // CHECK11: omp.inner.for.body: 2018 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2019 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2020 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 2021 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 2022 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 2023 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 2024 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 2025 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 2026 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 2027 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 2028 // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 2029 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2030 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2031 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2032 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 2033 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 2034 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 2035 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 2036 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 2037 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2038 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 2039 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 2040 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 2041 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 2042 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 2043 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 2044 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 2045 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 2046 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 2047 // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 2048 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 2049 // CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] 2050 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] 2051 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 2052 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] 2053 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 2054 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2055 // CHECK11: omp.body.continue: 2056 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2057 // CHECK11: omp.inner.for.inc: 2058 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2059 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 2060 // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 2061 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 2062 // CHECK11: omp.inner.for.end: 2063 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2064 // CHECK11: omp.loop.exit: 2065 // CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2066 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 2067 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 2068 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 2069 // CHECK11: omp.precond.end: 2070 // CHECK11-NEXT: ret void 2071 // 2072 // 2073 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2074 // CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { 2075 // CHECK11-NEXT: entry: 2076 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2077 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2078 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2079 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2080 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2081 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2082 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2083 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2084 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2085 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 2086 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 2087 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2088 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 2089 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 2090 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2091 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 2092 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2093 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2094 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 2095 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2096 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2097 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2098 // CHECK11: omp_offload.failed: 2099 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 2100 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2101 // CHECK11: omp_offload.cont: 2102 // CHECK11-NEXT: ret i32 0 2103 // 2104 // 2105 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 2106 // CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2107 // CHECK11-NEXT: entry: 2108 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2109 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2110 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2111 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 2112 // CHECK11-NEXT: ret void 2113 // 2114 // 2115 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2116 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2117 // CHECK11-NEXT: entry: 2118 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2119 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2120 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2121 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2122 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2123 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2124 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2125 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2126 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2127 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2128 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 2129 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 2130 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2131 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2132 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2133 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2134 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2135 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2136 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2137 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2138 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2139 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2140 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2141 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2142 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2143 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2144 // CHECK11: cond.true: 2145 // CHECK11-NEXT: br label [[COND_END:%.*]] 2146 // CHECK11: cond.false: 2147 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2148 // CHECK11-NEXT: br label [[COND_END]] 2149 // CHECK11: cond.end: 2150 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2151 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2152 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2153 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2154 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2155 // CHECK11: omp.inner.for.cond: 2156 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2157 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2158 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2159 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2160 // CHECK11: omp.inner.for.body: 2161 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2162 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 2163 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2164 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2165 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2166 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2167 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2168 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 2169 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2170 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 2171 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2172 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2173 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 2174 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2175 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 2176 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 2177 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 2178 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 2179 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2180 // CHECK11: omp.body.continue: 2181 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2182 // CHECK11: omp.inner.for.inc: 2183 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2184 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 2185 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 2186 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 2187 // CHECK11: omp.inner.for.end: 2188 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2189 // CHECK11: omp.loop.exit: 2190 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2191 // CHECK11-NEXT: ret void 2192 // 2193 // 2194 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2195 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] { 2196 // CHECK11-NEXT: entry: 2197 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 2198 // CHECK11-NEXT: ret void 2199 // 2200 // 2201 // CHECK12-LABEL: define {{[^@]+}}@main 2202 // CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2203 // CHECK12-NEXT: entry: 2204 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2205 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2206 // CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 2207 // CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 2208 // CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 2209 // CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2210 // CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2211 // CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2212 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2213 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 2214 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2215 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2216 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2217 // CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2218 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2219 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2220 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2221 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2222 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 2223 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2224 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2225 // CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 2226 // CHECK12-NEXT: store i32 100, i32* [[N]], align 4 2227 // CHECK12-NEXT: store i32 2, i32* [[M]], align 4 2228 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2229 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 2230 // CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2231 // CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2232 // CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2233 // CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 2234 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 2235 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 2236 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 2237 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 2238 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 2239 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 2240 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 2241 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 2242 // CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2243 // CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 2244 // CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 2245 // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2246 // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 2247 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4 2248 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2249 // CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 2250 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4 2251 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2252 // CHECK12-NEXT: store i64 4, i64* [[TMP15]], align 4 2253 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2254 // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 2255 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2256 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2257 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 2258 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2259 // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2260 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 2261 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 2262 // CHECK12-NEXT: store i64 4, i64* [[TMP21]], align 4 2263 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2264 // CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4 2265 // CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2266 // CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2267 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4 2268 // CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2269 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 2270 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 2271 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 2272 // CHECK12-NEXT: store i64 4, i64* [[TMP27]], align 4 2273 // CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2274 // CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 2275 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2276 // CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 2277 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 2278 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2279 // CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 2280 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 2281 // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2282 // CHECK12-NEXT: store i64 4, i64* [[TMP33]], align 4 2283 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2284 // CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4 2285 // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2286 // CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 2287 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4 2288 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2289 // CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32** 2290 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4 2291 // CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2292 // CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4 2293 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2294 // CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 2295 // CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2296 // CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2297 // CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2298 // CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4 2299 // CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 2300 // CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4 2301 // CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2302 // CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2303 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0 2304 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2305 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2306 // CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2307 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0 2308 // CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2309 // CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2310 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2311 // CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2312 // CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 2313 // CHECK12-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2314 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1 2315 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 2316 // CHECK12-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2317 // CHECK12-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 2318 // CHECK12-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2319 // CHECK12: omp_offload.failed: 2320 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 2321 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2322 // CHECK12: omp_offload.cont: 2323 // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2324 // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) 2325 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2326 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2327 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) 2328 // CHECK12-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4 2329 // CHECK12-NEXT: ret i32 [[TMP53]] 2330 // 2331 // 2332 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 2333 // CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 2334 // CHECK12-NEXT: entry: 2335 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2336 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2337 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2338 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2339 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2340 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2341 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2342 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2343 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2344 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2345 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2346 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2347 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2348 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 2349 // CHECK12-NEXT: ret void 2350 // 2351 // 2352 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2353 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 2354 // CHECK12-NEXT: entry: 2355 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2356 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2357 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 2358 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 2359 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2360 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2361 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2362 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2363 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2364 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2365 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2366 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 2367 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 2368 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2369 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2370 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2371 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2372 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2373 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2374 // CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 2375 // CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 2376 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2377 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2378 // CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 2379 // CHECK12-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 2380 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2381 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2382 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2383 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 2384 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 2385 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2386 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2387 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2388 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 2389 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 2390 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 2391 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 2392 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2393 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 2394 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2395 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2396 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2397 // CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 2398 // CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 2399 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 2400 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 2401 // CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 2402 // CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 2403 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 2404 // CHECK12-NEXT: store i32 0, i32* [[J]], align 4 2405 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2406 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 2407 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2408 // CHECK12: land.lhs.true: 2409 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2410 // CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 2411 // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2412 // CHECK12: omp.precond.then: 2413 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2414 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2415 // CHECK12-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 2416 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2417 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2418 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2419 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 2420 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2421 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2422 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2423 // CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 2424 // CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2425 // CHECK12: cond.true: 2426 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2427 // CHECK12-NEXT: br label [[COND_END:%.*]] 2428 // CHECK12: cond.false: 2429 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2430 // CHECK12-NEXT: br label [[COND_END]] 2431 // CHECK12: cond.end: 2432 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 2433 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2434 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2435 // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 2436 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2437 // CHECK12: omp.inner.for.cond: 2438 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2439 // CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2440 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 2441 // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2442 // CHECK12: omp.inner.for.body: 2443 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2444 // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2445 // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 2446 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 2447 // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 2448 // CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 2449 // CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 2450 // CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 2451 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 2452 // CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 2453 // CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 2454 // CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2455 // CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2456 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2457 // CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 2458 // CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 2459 // CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 2460 // CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 2461 // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 2462 // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2463 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 2464 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 2465 // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 2466 // CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 2467 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 2468 // CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 2469 // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 2470 // CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 2471 // CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 2472 // CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 2473 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 2474 // CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] 2475 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] 2476 // CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 2477 // CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] 2478 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 2479 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2480 // CHECK12: omp.body.continue: 2481 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2482 // CHECK12: omp.inner.for.inc: 2483 // CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2484 // CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 2485 // CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 2486 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 2487 // CHECK12: omp.inner.for.end: 2488 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2489 // CHECK12: omp.loop.exit: 2490 // CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2491 // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 2492 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 2493 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 2494 // CHECK12: omp.precond.end: 2495 // CHECK12-NEXT: ret void 2496 // 2497 // 2498 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2499 // CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { 2500 // CHECK12-NEXT: entry: 2501 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2502 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2503 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2504 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2505 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2506 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2507 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2508 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2509 // CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2510 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 2511 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 2512 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2513 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 2514 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 2515 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2516 // CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 2517 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2518 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2519 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 2520 // CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2521 // CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2522 // CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2523 // CHECK12: omp_offload.failed: 2524 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 2525 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2526 // CHECK12: omp_offload.cont: 2527 // CHECK12-NEXT: ret i32 0 2528 // 2529 // 2530 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 2531 // CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2532 // CHECK12-NEXT: entry: 2533 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2534 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2535 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2536 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 2537 // CHECK12-NEXT: ret void 2538 // 2539 // 2540 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2541 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2542 // CHECK12-NEXT: entry: 2543 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2544 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2545 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2546 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2547 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2548 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2549 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2550 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2551 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2552 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2553 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2554 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2555 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2556 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2557 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2558 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2559 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2560 // CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2561 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2562 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2563 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2564 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2565 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2566 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2567 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2568 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2569 // CHECK12: cond.true: 2570 // CHECK12-NEXT: br label [[COND_END:%.*]] 2571 // CHECK12: cond.false: 2572 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2573 // CHECK12-NEXT: br label [[COND_END]] 2574 // CHECK12: cond.end: 2575 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2576 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2577 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2578 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2579 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2580 // CHECK12: omp.inner.for.cond: 2581 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2582 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2583 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2584 // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2585 // CHECK12: omp.inner.for.body: 2586 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2587 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 2588 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2589 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2590 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2591 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2592 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2593 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 2594 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2595 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 2596 // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2597 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2598 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 2599 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2600 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 2601 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 2602 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 2603 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 2604 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2605 // CHECK12: omp.body.continue: 2606 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2607 // CHECK12: omp.inner.for.inc: 2608 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2609 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 2610 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 2611 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 2612 // CHECK12: omp.inner.for.end: 2613 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2614 // CHECK12: omp.loop.exit: 2615 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2616 // CHECK12-NEXT: ret void 2617 // 2618 // 2619 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2620 // CHECK12-SAME: () #[[ATTR5:[0-9]+]] { 2621 // CHECK12-NEXT: entry: 2622 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 2623 // CHECK12-NEXT: ret void 2624 // 2625 // 2626 // CHECK13-LABEL: define {{[^@]+}}@main 2627 // CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2628 // CHECK13-NEXT: entry: 2629 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2630 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2631 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 2632 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 2633 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 2634 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2635 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2636 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2637 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2638 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2639 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 2640 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2641 // CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 2642 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4 2643 // CHECK13-NEXT: store i32 2, i32* [[M]], align 4 2644 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2645 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2646 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 2647 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 2648 // CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 2649 // CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 2650 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 2651 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 2652 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2653 // CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 2654 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 2655 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 2656 // CHECK13: for.cond: 2657 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 2658 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 2659 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 2660 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] 2661 // CHECK13: for.body: 2662 // CHECK13-NEXT: store i32 0, i32* [[J]], align 4 2663 // CHECK13-NEXT: br label [[FOR_COND1:%.*]] 2664 // CHECK13: for.cond1: 2665 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 2666 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 2667 // CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] 2668 // CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2669 // CHECK13: for.body3: 2670 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 2671 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 2672 // CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 2673 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] 2674 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 2675 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 2676 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] 2677 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 2678 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 2679 // CHECK13: for.inc: 2680 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 2681 // CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 2682 // CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 2683 // CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] 2684 // CHECK13: for.end: 2685 // CHECK13-NEXT: br label [[FOR_INC6:%.*]] 2686 // CHECK13: for.inc6: 2687 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 2688 // CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 2689 // CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 2690 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2691 // CHECK13: for.end8: 2692 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2693 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) 2694 // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2695 // CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2696 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) 2697 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 2698 // CHECK13-NEXT: ret i32 [[TMP17]] 2699 // 2700 // 2701 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2702 // CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 2703 // CHECK13-NEXT: entry: 2704 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2705 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2706 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2707 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2708 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2709 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 2710 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 2711 // CHECK13: for.cond: 2712 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2713 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 2714 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] 2715 // CHECK13: for.body: 2716 // CHECK13-NEXT: store i32 0, i32* [[J]], align 4 2717 // CHECK13-NEXT: br label [[FOR_COND1:%.*]] 2718 // CHECK13: for.cond1: 2719 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 2720 // CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 2721 // CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2722 // CHECK13: for.body3: 2723 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2724 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2725 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 2726 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 2727 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 2728 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] 2729 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 2730 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 2731 // CHECK13: for.inc: 2732 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 2733 // CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 2734 // CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 2735 // CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] 2736 // CHECK13: for.end: 2737 // CHECK13-NEXT: br label [[FOR_INC6:%.*]] 2738 // CHECK13: for.inc6: 2739 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2740 // CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 2741 // CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 2742 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 2743 // CHECK13: for.end8: 2744 // CHECK13-NEXT: ret i32 0 2745 // 2746 // 2747 // CHECK14-LABEL: define {{[^@]+}}@main 2748 // CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2749 // CHECK14-NEXT: entry: 2750 // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2751 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2752 // CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 2753 // CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 2754 // CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 2755 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2756 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2757 // CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2758 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 2759 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 2760 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 2761 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2762 // CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 2763 // CHECK14-NEXT: store i32 100, i32* [[N]], align 4 2764 // CHECK14-NEXT: store i32 2, i32* [[M]], align 4 2765 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2766 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2767 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 2768 // CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 2769 // CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 2770 // CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 2771 // CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 2772 // CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 2773 // CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2774 // CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 2775 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 2776 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 2777 // CHECK14: for.cond: 2778 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 2779 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 2780 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 2781 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] 2782 // CHECK14: for.body: 2783 // CHECK14-NEXT: store i32 0, i32* [[J]], align 4 2784 // CHECK14-NEXT: br label [[FOR_COND1:%.*]] 2785 // CHECK14: for.cond1: 2786 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 2787 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 2788 // CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] 2789 // CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2790 // CHECK14: for.body3: 2791 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 2792 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 2793 // CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 2794 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] 2795 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 2796 // CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 2797 // CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] 2798 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 2799 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 2800 // CHECK14: for.inc: 2801 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 2802 // CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 2803 // CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 2804 // CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] 2805 // CHECK14: for.end: 2806 // CHECK14-NEXT: br label [[FOR_INC6:%.*]] 2807 // CHECK14: for.inc6: 2808 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 2809 // CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 2810 // CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 2811 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2812 // CHECK14: for.end8: 2813 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2814 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) 2815 // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2816 // CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2817 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) 2818 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 2819 // CHECK14-NEXT: ret i32 [[TMP17]] 2820 // 2821 // 2822 // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2823 // CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 2824 // CHECK14-NEXT: entry: 2825 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2826 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2827 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 2828 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 2829 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2830 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 2831 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 2832 // CHECK14: for.cond: 2833 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2834 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 2835 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] 2836 // CHECK14: for.body: 2837 // CHECK14-NEXT: store i32 0, i32* [[J]], align 4 2838 // CHECK14-NEXT: br label [[FOR_COND1:%.*]] 2839 // CHECK14: for.cond1: 2840 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 2841 // CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 2842 // CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2843 // CHECK14: for.body3: 2844 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2845 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2846 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 2847 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 2848 // CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 2849 // CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] 2850 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 2851 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 2852 // CHECK14: for.inc: 2853 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 2854 // CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 2855 // CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 2856 // CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] 2857 // CHECK14: for.end: 2858 // CHECK14-NEXT: br label [[FOR_INC6:%.*]] 2859 // CHECK14: for.inc6: 2860 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2861 // CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 2862 // CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 2863 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 2864 // CHECK14: for.end8: 2865 // CHECK14-NEXT: ret i32 0 2866 // 2867 // 2868 // CHECK15-LABEL: define {{[^@]+}}@main 2869 // CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2870 // CHECK15-NEXT: entry: 2871 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2872 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2873 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 2874 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 2875 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 2876 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2877 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2878 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2879 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 2880 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 2881 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 2882 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2883 // CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 2884 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4 2885 // CHECK15-NEXT: store i32 2, i32* [[M]], align 4 2886 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2887 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 2888 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2889 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2890 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2891 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 2892 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 2893 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 2894 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 2895 // CHECK15-NEXT: br label [[FOR_COND:%.*]] 2896 // CHECK15: for.cond: 2897 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 2898 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 2899 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] 2900 // CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] 2901 // CHECK15: for.body: 2902 // CHECK15-NEXT: store i32 0, i32* [[J]], align 4 2903 // CHECK15-NEXT: br label [[FOR_COND1:%.*]] 2904 // CHECK15: for.cond1: 2905 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 2906 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 2907 // CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 2908 // CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2909 // CHECK15: for.body3: 2910 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2911 // CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] 2912 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] 2913 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 2914 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] 2915 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 2916 // CHECK15-NEXT: br label [[FOR_INC:%.*]] 2917 // CHECK15: for.inc: 2918 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 2919 // CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 2920 // CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 2921 // CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] 2922 // CHECK15: for.end: 2923 // CHECK15-NEXT: br label [[FOR_INC5:%.*]] 2924 // CHECK15: for.inc5: 2925 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 2926 // CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 2927 // CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 2928 // CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2929 // CHECK15: for.end7: 2930 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2931 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) 2932 // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2933 // CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2934 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) 2935 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 2936 // CHECK15-NEXT: ret i32 [[TMP15]] 2937 // 2938 // 2939 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2940 // CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 2941 // CHECK15-NEXT: entry: 2942 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2943 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2944 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 2945 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 2946 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2947 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 2948 // CHECK15-NEXT: br label [[FOR_COND:%.*]] 2949 // CHECK15: for.cond: 2950 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2951 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 2952 // CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] 2953 // CHECK15: for.body: 2954 // CHECK15-NEXT: store i32 0, i32* [[J]], align 4 2955 // CHECK15-NEXT: br label [[FOR_COND1:%.*]] 2956 // CHECK15: for.cond1: 2957 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 2958 // CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 2959 // CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2960 // CHECK15: for.body3: 2961 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2962 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] 2963 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 2964 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] 2965 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 2966 // CHECK15-NEXT: br label [[FOR_INC:%.*]] 2967 // CHECK15: for.inc: 2968 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 2969 // CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 2970 // CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 2971 // CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] 2972 // CHECK15: for.end: 2973 // CHECK15-NEXT: br label [[FOR_INC5:%.*]] 2974 // CHECK15: for.inc5: 2975 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2976 // CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 2977 // CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 2978 // CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2979 // CHECK15: for.end7: 2980 // CHECK15-NEXT: ret i32 0 2981 // 2982 // 2983 // CHECK16-LABEL: define {{[^@]+}}@main 2984 // CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2985 // CHECK16-NEXT: entry: 2986 // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2987 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2988 // CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 2989 // CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 2990 // CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 2991 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2992 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2993 // CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2994 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 2995 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 2996 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 2997 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2998 // CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 2999 // CHECK16-NEXT: store i32 100, i32* [[N]], align 4 3000 // CHECK16-NEXT: store i32 2, i32* [[M]], align 4 3001 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 3002 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 3003 // CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3004 // CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3005 // CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 3006 // CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 3007 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 3008 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 3009 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4 3010 // CHECK16-NEXT: br label [[FOR_COND:%.*]] 3011 // CHECK16: for.cond: 3012 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 3013 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 3014 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] 3015 // CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] 3016 // CHECK16: for.body: 3017 // CHECK16-NEXT: store i32 0, i32* [[J]], align 4 3018 // CHECK16-NEXT: br label [[FOR_COND1:%.*]] 3019 // CHECK16: for.cond1: 3020 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 3021 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 3022 // CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 3023 // CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 3024 // CHECK16: for.body3: 3025 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3026 // CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] 3027 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] 3028 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 3029 // CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] 3030 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 3031 // CHECK16-NEXT: br label [[FOR_INC:%.*]] 3032 // CHECK16: for.inc: 3033 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 3034 // CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 3035 // CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 3036 // CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] 3037 // CHECK16: for.end: 3038 // CHECK16-NEXT: br label [[FOR_INC5:%.*]] 3039 // CHECK16: for.inc5: 3040 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 3041 // CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 3042 // CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 3043 // CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 3044 // CHECK16: for.end7: 3045 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 3046 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) 3047 // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3048 // CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3049 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) 3050 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 3051 // CHECK16-NEXT: ret i32 [[TMP15]] 3052 // 3053 // 3054 // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 3055 // CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 3056 // CHECK16-NEXT: entry: 3057 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3058 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 3059 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 3060 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 3061 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3062 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4 3063 // CHECK16-NEXT: br label [[FOR_COND:%.*]] 3064 // CHECK16: for.cond: 3065 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3066 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 3067 // CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] 3068 // CHECK16: for.body: 3069 // CHECK16-NEXT: store i32 0, i32* [[J]], align 4 3070 // CHECK16-NEXT: br label [[FOR_COND1:%.*]] 3071 // CHECK16: for.cond1: 3072 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 3073 // CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 3074 // CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 3075 // CHECK16: for.body3: 3076 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3077 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] 3078 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 3079 // CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] 3080 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 3081 // CHECK16-NEXT: br label [[FOR_INC:%.*]] 3082 // CHECK16: for.inc: 3083 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 3084 // CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 3085 // CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 3086 // CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] 3087 // CHECK16: for.end: 3088 // CHECK16-NEXT: br label [[FOR_INC5:%.*]] 3089 // CHECK16: for.inc5: 3090 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3091 // CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 3092 // CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 3093 // CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3094 // CHECK16: for.end7: 3095 // CHECK16-NEXT: ret i32 0 3096 // 3097