1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute simd private(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global, bound tid and loop vars 78 g = 1; 79 g1 = 1; 80 sivar = 2; 81 [&]() { 82 g = 2; 83 g1 = 2; 84 sivar = 4; 85 86 }(); 87 } 88 }(); 89 return 0; 90 #else 91 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var, sivar) 92 for (int i = 0; i < 2; ++i) { 93 vec[i] = t_var; 94 s_arr[i] = var; 95 sivar += i; 96 } 97 return tmain<int>(); 98 #endif 99 } 100 101 102 103 // Skip global, bound tid and loop vars 104 105 // private(s_arr) 106 107 // private(var) 108 109 110 111 112 113 // Skip global, bound tid and loop vars 114 115 // private(s_arr) 116 117 118 // private(var) 119 120 121 #endif 122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 124 // CHECK1-NEXT: entry: 125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 126 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 127 // CHECK1-NEXT: ret void 128 // 129 // 130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 131 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 132 // CHECK1-NEXT: entry: 133 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 134 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 135 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 136 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 137 // CHECK1-NEXT: ret void 138 // 139 // 140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 141 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 142 // CHECK1-NEXT: entry: 143 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 144 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 145 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 146 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 151 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 157 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 158 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 159 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 164 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: ret void 170 // 171 // 172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 173 // CHECK1-SAME: () #[[ATTR0]] { 174 // CHECK1-NEXT: entry: 175 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 176 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 177 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 178 // CHECK1-NEXT: ret void 179 // 180 // 181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 182 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 183 // CHECK1-NEXT: entry: 184 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 185 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 186 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 187 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 190 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 191 // CHECK1-NEXT: ret void 192 // 193 // 194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 195 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 196 // CHECK1-NEXT: entry: 197 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 198 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 199 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 200 // CHECK1: arraydestroy.body: 201 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 202 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 204 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 205 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 206 // CHECK1: arraydestroy.done1: 207 // CHECK1-NEXT: ret void 208 // 209 // 210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 211 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 212 // CHECK1-NEXT: entry: 213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 217 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 218 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 219 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 220 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 221 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 222 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 223 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 224 // CHECK1-NEXT: ret void 225 // 226 // 227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 228 // CHECK1-SAME: () #[[ATTR0]] { 229 // CHECK1-NEXT: entry: 230 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 231 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 232 // CHECK1-NEXT: ret void 233 // 234 // 235 // CHECK1-LABEL: define {{[^@]+}}@main 236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 237 // CHECK1-NEXT: entry: 238 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 240 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 241 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 242 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 243 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 244 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 245 // CHECK1: omp_offload.failed: 246 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 247 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 248 // CHECK1: omp_offload.cont: 249 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 250 // CHECK1-NEXT: ret i32 [[CALL]] 251 // 252 // 253 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 254 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 255 // CHECK1-NEXT: entry: 256 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 261 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 264 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 265 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 266 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 273 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 274 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 275 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 277 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 278 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 279 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 280 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 281 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 282 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 283 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 284 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 285 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 286 // CHECK1: arrayctor.loop: 287 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 288 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 289 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 290 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 291 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 292 // CHECK1: arrayctor.cont: 293 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 294 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 295 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 296 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 297 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 298 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 299 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 300 // CHECK1: cond.true: 301 // CHECK1-NEXT: br label [[COND_END:%.*]] 302 // CHECK1: cond.false: 303 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 304 // CHECK1-NEXT: br label [[COND_END]] 305 // CHECK1: cond.end: 306 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 307 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 308 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 309 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 311 // CHECK1: omp.inner.for.cond: 312 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 313 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 314 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 315 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 316 // CHECK1: omp.inner.for.cond.cleanup: 317 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 318 // CHECK1: omp.inner.for.body: 319 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 320 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 321 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 322 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 323 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5 324 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 325 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 326 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 327 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 328 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 329 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 330 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 331 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 332 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 333 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5 334 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 335 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5 336 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 337 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5 338 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 339 // CHECK1: omp.body.continue: 340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 341 // CHECK1: omp.inner.for.inc: 342 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 343 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 344 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 345 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 346 // CHECK1: omp.inner.for.end: 347 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 348 // CHECK1: omp.loop.exit: 349 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 350 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 351 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 352 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 353 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 354 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 355 // CHECK1: .omp.final.then: 356 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 357 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 358 // CHECK1: .omp.final.done: 359 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 360 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 361 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 362 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 363 // CHECK1: arraydestroy.body: 364 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 365 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 366 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 367 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 368 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 369 // CHECK1: arraydestroy.done7: 370 // CHECK1-NEXT: ret void 371 // 372 // 373 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 374 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat { 375 // CHECK1-NEXT: entry: 376 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 377 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 378 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 379 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 380 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 381 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 382 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 384 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 385 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 386 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 387 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 388 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 389 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 390 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 391 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 392 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 393 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 394 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 395 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 396 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 397 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 398 // CHECK1: omp_offload.failed: 399 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 400 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 401 // CHECK1: omp_offload.cont: 402 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 403 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 404 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 405 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 406 // CHECK1: arraydestroy.body: 407 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 408 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 409 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 410 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 411 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 412 // CHECK1: arraydestroy.done2: 413 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 414 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 415 // CHECK1-NEXT: ret i32 [[TMP4]] 416 // 417 // 418 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 419 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 420 // CHECK1-NEXT: entry: 421 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 422 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 423 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 424 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 425 // CHECK1-NEXT: ret void 426 // 427 // 428 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 429 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 430 // CHECK1-NEXT: entry: 431 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 432 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 433 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 434 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 435 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 436 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 437 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 438 // CHECK1-NEXT: ret void 439 // 440 // 441 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 442 // CHECK1-SAME: () #[[ATTR4]] { 443 // CHECK1-NEXT: entry: 444 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 445 // CHECK1-NEXT: ret void 446 // 447 // 448 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 449 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 450 // CHECK1-NEXT: entry: 451 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 452 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 453 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 455 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 456 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 457 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 458 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 459 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 460 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 461 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 462 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 463 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 464 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 465 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 466 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 467 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 468 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 469 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 470 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 471 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 472 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 473 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 474 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 475 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 476 // CHECK1: arrayctor.loop: 477 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 478 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 479 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 480 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 481 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 482 // CHECK1: arrayctor.cont: 483 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 484 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 485 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 486 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 487 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 488 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 489 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 490 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 491 // CHECK1: cond.true: 492 // CHECK1-NEXT: br label [[COND_END:%.*]] 493 // CHECK1: cond.false: 494 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 495 // CHECK1-NEXT: br label [[COND_END]] 496 // CHECK1: cond.end: 497 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 498 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 499 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 500 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 501 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 502 // CHECK1: omp.inner.for.cond: 503 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 504 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 505 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 506 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 507 // CHECK1: omp.inner.for.cond.cleanup: 508 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 509 // CHECK1: omp.inner.for.body: 510 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 511 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 512 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 513 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 514 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 515 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 516 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 517 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 518 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 519 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11 520 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 521 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 522 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] 523 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 524 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 525 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11 526 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 527 // CHECK1: omp.body.continue: 528 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 529 // CHECK1: omp.inner.for.inc: 530 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 531 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 532 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 533 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 534 // CHECK1: omp.inner.for.end: 535 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 536 // CHECK1: omp.loop.exit: 537 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 538 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 539 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 540 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 541 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 542 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 543 // CHECK1: .omp.final.then: 544 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 545 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 546 // CHECK1: .omp.final.done: 547 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 548 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 549 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 550 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 551 // CHECK1: arraydestroy.body: 552 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 553 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 554 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 555 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 556 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 557 // CHECK1: arraydestroy.done8: 558 // CHECK1-NEXT: ret void 559 // 560 // 561 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 562 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 563 // CHECK1-NEXT: entry: 564 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 565 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 566 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 567 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 568 // CHECK1-NEXT: ret void 569 // 570 // 571 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 572 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 573 // CHECK1-NEXT: entry: 574 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 575 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 576 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 577 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 578 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 579 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 580 // CHECK1-NEXT: ret void 581 // 582 // 583 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 584 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 585 // CHECK1-NEXT: entry: 586 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 587 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 588 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 589 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 590 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 591 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 592 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 593 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 594 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 595 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 596 // CHECK1-NEXT: ret void 597 // 598 // 599 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 600 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 601 // CHECK1-NEXT: entry: 602 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 603 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 604 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 605 // CHECK1-NEXT: ret void 606 // 607 // 608 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp 609 // CHECK1-SAME: () #[[ATTR0]] { 610 // CHECK1-NEXT: entry: 611 // CHECK1-NEXT: call void @__cxx_global_var_init() 612 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 613 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 614 // CHECK1-NEXT: ret void 615 // 616 // 617 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 618 // CHECK1-SAME: () #[[ATTR0]] { 619 // CHECK1-NEXT: entry: 620 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 621 // CHECK1-NEXT: ret void 622 // 623 // 624 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 625 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 626 // CHECK3-NEXT: entry: 627 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 628 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 629 // CHECK3-NEXT: ret void 630 // 631 // 632 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 633 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 634 // CHECK3-NEXT: entry: 635 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 636 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 637 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 638 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 639 // CHECK3-NEXT: ret void 640 // 641 // 642 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 643 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 644 // CHECK3-NEXT: entry: 645 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 646 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 647 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 648 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 649 // CHECK3-NEXT: ret void 650 // 651 // 652 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 653 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 654 // CHECK3-NEXT: entry: 655 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 656 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 657 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 658 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 659 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 660 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 661 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 662 // CHECK3-NEXT: ret void 663 // 664 // 665 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 666 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 667 // CHECK3-NEXT: entry: 668 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 669 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 670 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 671 // CHECK3-NEXT: ret void 672 // 673 // 674 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 675 // CHECK3-SAME: () #[[ATTR0]] { 676 // CHECK3-NEXT: entry: 677 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 678 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 679 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 680 // CHECK3-NEXT: ret void 681 // 682 // 683 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 684 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 685 // CHECK3-NEXT: entry: 686 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 687 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 688 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 689 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 690 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 691 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 692 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 693 // CHECK3-NEXT: ret void 694 // 695 // 696 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 697 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 698 // CHECK3-NEXT: entry: 699 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 700 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 701 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 702 // CHECK3: arraydestroy.body: 703 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 704 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 705 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 706 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 707 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 708 // CHECK3: arraydestroy.done1: 709 // CHECK3-NEXT: ret void 710 // 711 // 712 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 713 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 714 // CHECK3-NEXT: entry: 715 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 716 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 717 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 718 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 719 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 720 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 721 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 722 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 723 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 724 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 725 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 726 // CHECK3-NEXT: ret void 727 // 728 // 729 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 730 // CHECK3-SAME: () #[[ATTR0]] { 731 // CHECK3-NEXT: entry: 732 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 733 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 734 // CHECK3-NEXT: ret void 735 // 736 // 737 // CHECK3-LABEL: define {{[^@]+}}@main 738 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 739 // CHECK3-NEXT: entry: 740 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 741 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 742 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 743 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 744 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 745 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 746 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 747 // CHECK3: omp_offload.failed: 748 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 749 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 750 // CHECK3: omp_offload.cont: 751 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 752 // CHECK3-NEXT: ret i32 [[CALL]] 753 // 754 // 755 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 756 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 757 // CHECK3-NEXT: entry: 758 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 759 // CHECK3-NEXT: ret void 760 // 761 // 762 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 763 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { 764 // CHECK3-NEXT: entry: 765 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 766 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 767 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 768 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 769 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 770 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 771 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 772 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 773 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 774 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 775 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 776 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 777 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 778 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 779 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 780 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 781 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 782 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 783 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 784 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 785 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 786 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 787 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 788 // CHECK3: arrayctor.loop: 789 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 790 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 791 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 792 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 793 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 794 // CHECK3: arrayctor.cont: 795 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 796 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 797 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 798 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 799 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 800 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 801 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 802 // CHECK3: cond.true: 803 // CHECK3-NEXT: br label [[COND_END:%.*]] 804 // CHECK3: cond.false: 805 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 806 // CHECK3-NEXT: br label [[COND_END]] 807 // CHECK3: cond.end: 808 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 809 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 810 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 811 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 812 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 813 // CHECK3: omp.inner.for.cond: 814 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 815 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 816 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 817 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 818 // CHECK3: omp.inner.for.cond.cleanup: 819 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 820 // CHECK3: omp.inner.for.body: 821 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 822 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 823 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 824 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 825 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 826 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 827 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 828 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 829 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 830 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] 831 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 832 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 833 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6 834 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 835 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6 836 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 837 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6 838 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 839 // CHECK3: omp.body.continue: 840 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 841 // CHECK3: omp.inner.for.inc: 842 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 843 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 844 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 845 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 846 // CHECK3: omp.inner.for.end: 847 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 848 // CHECK3: omp.loop.exit: 849 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 850 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 851 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 852 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 853 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 854 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 855 // CHECK3: .omp.final.then: 856 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 857 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 858 // CHECK3: .omp.final.done: 859 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 860 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 861 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 862 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 863 // CHECK3: arraydestroy.body: 864 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 865 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 866 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 867 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 868 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 869 // CHECK3: arraydestroy.done6: 870 // CHECK3-NEXT: ret void 871 // 872 // 873 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 874 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat { 875 // CHECK3-NEXT: entry: 876 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 877 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 878 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 879 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 880 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 881 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 882 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 883 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 884 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 885 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 886 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 887 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 888 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 889 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 890 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 891 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 892 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 893 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 894 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 895 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1) 896 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 897 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 898 // CHECK3: omp_offload.failed: 899 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 900 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 901 // CHECK3: omp_offload.cont: 902 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 903 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 904 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 905 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 906 // CHECK3: arraydestroy.body: 907 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 908 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 909 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 910 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 911 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 912 // CHECK3: arraydestroy.done2: 913 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 914 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 915 // CHECK3-NEXT: ret i32 [[TMP4]] 916 // 917 // 918 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 919 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 920 // CHECK3-NEXT: entry: 921 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 922 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 923 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 924 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 925 // CHECK3-NEXT: ret void 926 // 927 // 928 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 929 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 930 // CHECK3-NEXT: entry: 931 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 932 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 933 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 934 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 935 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 936 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 937 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 938 // CHECK3-NEXT: ret void 939 // 940 // 941 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 942 // CHECK3-SAME: () #[[ATTR4]] { 943 // CHECK3-NEXT: entry: 944 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 945 // CHECK3-NEXT: ret void 946 // 947 // 948 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 949 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 950 // CHECK3-NEXT: entry: 951 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 952 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 953 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 954 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 955 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 956 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 957 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 958 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 959 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 960 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 961 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 962 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 963 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 964 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 965 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 966 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 967 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 968 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 969 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 970 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 971 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 972 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 973 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 974 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 975 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 976 // CHECK3: arrayctor.loop: 977 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 978 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 979 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 980 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 981 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 982 // CHECK3: arrayctor.cont: 983 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 984 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 985 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 986 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 987 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 988 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 989 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 990 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 991 // CHECK3: cond.true: 992 // CHECK3-NEXT: br label [[COND_END:%.*]] 993 // CHECK3: cond.false: 994 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 995 // CHECK3-NEXT: br label [[COND_END]] 996 // CHECK3: cond.end: 997 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 998 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 999 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1000 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1001 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1002 // CHECK3: omp.inner.for.cond: 1003 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1004 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1005 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1006 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1007 // CHECK3: omp.inner.for.cond.cleanup: 1008 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1009 // CHECK3: omp.inner.for.body: 1010 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1011 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1012 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1013 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1014 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12 1015 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1016 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1017 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 1018 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12 1019 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1020 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 1021 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1022 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1023 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12 1024 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1025 // CHECK3: omp.body.continue: 1026 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1027 // CHECK3: omp.inner.for.inc: 1028 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1029 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1030 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1031 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1032 // CHECK3: omp.inner.for.end: 1033 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1034 // CHECK3: omp.loop.exit: 1035 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1036 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1037 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1038 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1039 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 1040 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1041 // CHECK3: .omp.final.then: 1042 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1043 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1044 // CHECK3: .omp.final.done: 1045 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1046 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1047 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1048 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1049 // CHECK3: arraydestroy.body: 1050 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1051 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1052 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1053 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1054 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1055 // CHECK3: arraydestroy.done7: 1056 // CHECK3-NEXT: ret void 1057 // 1058 // 1059 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1060 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1061 // CHECK3-NEXT: entry: 1062 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1063 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1064 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1065 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1066 // CHECK3-NEXT: ret void 1067 // 1068 // 1069 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1070 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1071 // CHECK3-NEXT: entry: 1072 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1073 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1074 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1075 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1076 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1077 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1078 // CHECK3-NEXT: ret void 1079 // 1080 // 1081 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1082 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1083 // CHECK3-NEXT: entry: 1084 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1085 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1086 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1087 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1088 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1089 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1090 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1091 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1092 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1093 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1094 // CHECK3-NEXT: ret void 1095 // 1096 // 1097 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1098 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1099 // CHECK3-NEXT: entry: 1100 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1101 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1102 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1103 // CHECK3-NEXT: ret void 1104 // 1105 // 1106 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp 1107 // CHECK3-SAME: () #[[ATTR0]] { 1108 // CHECK3-NEXT: entry: 1109 // CHECK3-NEXT: call void @__cxx_global_var_init() 1110 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1111 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1112 // CHECK3-NEXT: ret void 1113 // 1114 // 1115 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1116 // CHECK3-SAME: () #[[ATTR0]] { 1117 // CHECK3-NEXT: entry: 1118 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1119 // CHECK3-NEXT: ret void 1120 // 1121 // 1122 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1123 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1124 // CHECK5-NEXT: entry: 1125 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1126 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1127 // CHECK5-NEXT: ret void 1128 // 1129 // 1130 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1131 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1132 // CHECK5-NEXT: entry: 1133 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1134 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1135 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1136 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1137 // CHECK5-NEXT: ret void 1138 // 1139 // 1140 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1141 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1142 // CHECK5-NEXT: entry: 1143 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1144 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1145 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1146 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1147 // CHECK5-NEXT: ret void 1148 // 1149 // 1150 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1151 // CHECK5-SAME: () #[[ATTR0]] { 1152 // CHECK5-NEXT: entry: 1153 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1154 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1155 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1156 // CHECK5-NEXT: ret void 1157 // 1158 // 1159 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1160 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1161 // CHECK5-NEXT: entry: 1162 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1163 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1164 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1165 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1166 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1167 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1168 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1169 // CHECK5-NEXT: ret void 1170 // 1171 // 1172 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1173 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1174 // CHECK5-NEXT: entry: 1175 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1176 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1177 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1178 // CHECK5: arraydestroy.body: 1179 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1180 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1181 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1182 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1183 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1184 // CHECK5: arraydestroy.done1: 1185 // CHECK5-NEXT: ret void 1186 // 1187 // 1188 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1189 // CHECK5-SAME: () #[[ATTR0]] { 1190 // CHECK5-NEXT: entry: 1191 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1192 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1193 // CHECK5-NEXT: ret void 1194 // 1195 // 1196 // CHECK5-LABEL: define {{[^@]+}}@main 1197 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1198 // CHECK5-NEXT: entry: 1199 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1200 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1201 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1202 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1203 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1204 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1205 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1206 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1207 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1208 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1209 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1210 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1211 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1212 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1213 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1214 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1215 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1216 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1217 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1218 // CHECK5: arrayctor.loop: 1219 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1220 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1221 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 1222 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1223 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1224 // CHECK5: arrayctor.cont: 1225 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1226 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1227 // CHECK5: omp.inner.for.cond: 1228 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1229 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1230 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1231 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1232 // CHECK5: omp.inner.for.cond.cleanup: 1233 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1234 // CHECK5: omp.inner.for.body: 1235 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1236 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1237 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1238 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1239 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2 1240 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1241 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1242 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 1243 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2 1244 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1245 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1246 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 1247 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1248 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1249 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2 1250 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1251 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 1252 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1253 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2 1254 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1255 // CHECK5: omp.body.continue: 1256 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1257 // CHECK5: omp.inner.for.inc: 1258 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1259 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1260 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1261 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1262 // CHECK5: omp.inner.for.end: 1263 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1264 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1265 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1266 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 1267 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1268 // CHECK5: arraydestroy.body: 1269 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1270 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1271 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1272 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1273 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1274 // CHECK5: arraydestroy.done6: 1275 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1276 // CHECK5-NEXT: ret i32 [[CALL]] 1277 // 1278 // 1279 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1280 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 1281 // CHECK5-NEXT: entry: 1282 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1283 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1284 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1285 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1286 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1287 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1288 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1289 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 1290 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1291 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1292 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1293 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1294 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1295 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1296 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1297 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 1298 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 1299 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1300 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 1301 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1302 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1303 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1304 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 1305 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1306 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1307 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1308 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 1309 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1310 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1311 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1312 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1313 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1314 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1315 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1316 // CHECK5: arrayctor.loop: 1317 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1318 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1319 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 1320 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1321 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1322 // CHECK5: arrayctor.cont: 1323 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1324 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 1325 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1326 // CHECK5: omp.inner.for.cond: 1327 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1328 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1329 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1330 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1331 // CHECK5: omp.inner.for.cond.cleanup: 1332 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1333 // CHECK5: omp.inner.for.body: 1334 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1335 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1336 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1337 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1338 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6 1339 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1340 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 1341 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] 1342 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 1343 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6 1344 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1345 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64 1346 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]] 1347 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* 1348 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 1349 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6 1350 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1351 // CHECK5: omp.body.continue: 1352 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1353 // CHECK5: omp.inner.for.inc: 1354 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1355 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1 1356 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1357 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1358 // CHECK5: omp.inner.for.end: 1359 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1360 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1361 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1362 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 1363 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1364 // CHECK5: arraydestroy.body: 1365 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1366 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1367 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1368 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1369 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1370 // CHECK5: arraydestroy.done11: 1371 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1372 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1373 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 1374 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] 1375 // CHECK5: arraydestroy.body13: 1376 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] 1377 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 1378 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] 1379 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] 1380 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] 1381 // CHECK5: arraydestroy.done17: 1382 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1383 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 1384 // CHECK5-NEXT: ret i32 [[TMP14]] 1385 // 1386 // 1387 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1388 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1389 // CHECK5-NEXT: entry: 1390 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1391 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1392 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1393 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1394 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1395 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1396 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 1397 // CHECK5-NEXT: ret void 1398 // 1399 // 1400 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1401 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1402 // CHECK5-NEXT: entry: 1403 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1404 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1405 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1406 // CHECK5-NEXT: ret void 1407 // 1408 // 1409 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1410 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1411 // CHECK5-NEXT: entry: 1412 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1413 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1414 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1415 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1416 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1417 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1418 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1419 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1420 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1421 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1422 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 1423 // CHECK5-NEXT: ret void 1424 // 1425 // 1426 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1427 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1428 // CHECK5-NEXT: entry: 1429 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1430 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1431 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1432 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1433 // CHECK5-NEXT: ret void 1434 // 1435 // 1436 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1437 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1438 // CHECK5-NEXT: entry: 1439 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1440 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1441 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1442 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1443 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1444 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1445 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1446 // CHECK5-NEXT: ret void 1447 // 1448 // 1449 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1450 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1451 // CHECK5-NEXT: entry: 1452 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1453 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1454 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1455 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1456 // CHECK5-NEXT: ret void 1457 // 1458 // 1459 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1460 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1461 // CHECK5-NEXT: entry: 1462 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1463 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1464 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1465 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1466 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1467 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1468 // CHECK5-NEXT: ret void 1469 // 1470 // 1471 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1472 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1473 // CHECK5-NEXT: entry: 1474 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1475 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1476 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1477 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1478 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1479 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1480 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1481 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1482 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1483 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1484 // CHECK5-NEXT: ret void 1485 // 1486 // 1487 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1488 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1489 // CHECK5-NEXT: entry: 1490 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1491 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1492 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1493 // CHECK5-NEXT: ret void 1494 // 1495 // 1496 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp 1497 // CHECK5-SAME: () #[[ATTR0]] { 1498 // CHECK5-NEXT: entry: 1499 // CHECK5-NEXT: call void @__cxx_global_var_init() 1500 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 1501 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 1502 // CHECK5-NEXT: ret void 1503 // 1504 // 1505 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 1506 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1507 // CHECK7-NEXT: entry: 1508 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1509 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1510 // CHECK7-NEXT: ret void 1511 // 1512 // 1513 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1514 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1515 // CHECK7-NEXT: entry: 1516 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1517 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1518 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1519 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1520 // CHECK7-NEXT: ret void 1521 // 1522 // 1523 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1524 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1525 // CHECK7-NEXT: entry: 1526 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1527 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1528 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1529 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1530 // CHECK7-NEXT: ret void 1531 // 1532 // 1533 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1534 // CHECK7-SAME: () #[[ATTR0]] { 1535 // CHECK7-NEXT: entry: 1536 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 1537 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 1538 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1539 // CHECK7-NEXT: ret void 1540 // 1541 // 1542 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1543 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1544 // CHECK7-NEXT: entry: 1545 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1546 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1547 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1548 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1549 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1550 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1551 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1552 // CHECK7-NEXT: ret void 1553 // 1554 // 1555 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1556 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1557 // CHECK7-NEXT: entry: 1558 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1559 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1560 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1561 // CHECK7: arraydestroy.body: 1562 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1563 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1564 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1565 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1566 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1567 // CHECK7: arraydestroy.done1: 1568 // CHECK7-NEXT: ret void 1569 // 1570 // 1571 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1572 // CHECK7-SAME: () #[[ATTR0]] { 1573 // CHECK7-NEXT: entry: 1574 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1575 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1576 // CHECK7-NEXT: ret void 1577 // 1578 // 1579 // CHECK7-LABEL: define {{[^@]+}}@main 1580 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 1581 // CHECK7-NEXT: entry: 1582 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1583 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1584 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1585 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1586 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1587 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1588 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1589 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1590 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1591 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1592 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1593 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 1594 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1595 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1596 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1597 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1598 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1599 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1600 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1601 // CHECK7: arrayctor.loop: 1602 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1603 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1604 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1605 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1606 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1607 // CHECK7: arrayctor.cont: 1608 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1609 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1610 // CHECK7: omp.inner.for.cond: 1611 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1612 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 1613 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1614 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1615 // CHECK7: omp.inner.for.cond.cleanup: 1616 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1617 // CHECK7: omp.inner.for.body: 1618 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1619 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1620 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1621 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 1622 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3 1623 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1624 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]] 1625 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3 1626 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1627 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]] 1628 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 1629 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1630 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3 1631 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1632 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 1633 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1634 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3 1635 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1636 // CHECK7: omp.body.continue: 1637 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1638 // CHECK7: omp.inner.for.inc: 1639 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1640 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 1641 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1642 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1643 // CHECK7: omp.inner.for.end: 1644 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1645 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1646 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1647 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 1648 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1649 // CHECK7: arraydestroy.body: 1650 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1651 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1652 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1653 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1654 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1655 // CHECK7: arraydestroy.done5: 1656 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1657 // CHECK7-NEXT: ret i32 [[CALL]] 1658 // 1659 // 1660 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1661 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 1662 // CHECK7-NEXT: entry: 1663 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1664 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1665 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1666 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1667 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1668 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1669 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1670 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1671 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1672 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1673 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1674 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1675 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1676 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1677 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1678 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 1679 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 1680 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1681 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 1682 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1683 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1684 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1685 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 1686 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1687 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1688 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1689 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1690 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1691 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1692 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1693 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1694 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1695 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1696 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1697 // CHECK7: arrayctor.loop: 1698 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1699 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1700 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1701 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1702 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1703 // CHECK7: arrayctor.cont: 1704 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1705 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 1706 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1707 // CHECK7: omp.inner.for.cond: 1708 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1709 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1710 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1711 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1712 // CHECK7: omp.inner.for.cond.cleanup: 1713 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1714 // CHECK7: omp.inner.for.body: 1715 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1716 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1717 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1718 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1719 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7 1720 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1721 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]] 1722 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 1723 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7 1724 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1725 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]] 1726 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1727 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 1728 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7 1729 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1730 // CHECK7: omp.body.continue: 1731 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1732 // CHECK7: omp.inner.for.inc: 1733 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1734 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1 1735 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1736 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1737 // CHECK7: omp.inner.for.end: 1738 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1739 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1740 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 1741 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 1742 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1743 // CHECK7: arraydestroy.body: 1744 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1745 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1746 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1747 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 1748 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 1749 // CHECK7: arraydestroy.done10: 1750 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 1751 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1752 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 1753 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] 1754 // CHECK7: arraydestroy.body12: 1755 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] 1756 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 1757 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] 1758 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] 1759 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] 1760 // CHECK7: arraydestroy.done16: 1761 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1762 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 1763 // CHECK7-NEXT: ret i32 [[TMP14]] 1764 // 1765 // 1766 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1767 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1768 // CHECK7-NEXT: entry: 1769 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1770 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1771 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1772 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1773 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1774 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1775 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 1776 // CHECK7-NEXT: ret void 1777 // 1778 // 1779 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1780 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1781 // CHECK7-NEXT: entry: 1782 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1783 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1784 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1785 // CHECK7-NEXT: ret void 1786 // 1787 // 1788 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1789 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1790 // CHECK7-NEXT: entry: 1791 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1792 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1793 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1794 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1795 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1796 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1797 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1798 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1799 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1800 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1801 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 1802 // CHECK7-NEXT: ret void 1803 // 1804 // 1805 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1806 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1807 // CHECK7-NEXT: entry: 1808 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1809 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1810 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1811 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1812 // CHECK7-NEXT: ret void 1813 // 1814 // 1815 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1816 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1817 // CHECK7-NEXT: entry: 1818 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1819 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1820 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1821 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1822 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1823 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1824 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1825 // CHECK7-NEXT: ret void 1826 // 1827 // 1828 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1829 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1830 // CHECK7-NEXT: entry: 1831 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1832 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1833 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1834 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1835 // CHECK7-NEXT: ret void 1836 // 1837 // 1838 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1839 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1840 // CHECK7-NEXT: entry: 1841 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1842 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1843 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1844 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1845 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1846 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1847 // CHECK7-NEXT: ret void 1848 // 1849 // 1850 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1851 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1852 // CHECK7-NEXT: entry: 1853 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1854 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1855 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1856 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1857 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1858 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1859 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1860 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1861 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1862 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1863 // CHECK7-NEXT: ret void 1864 // 1865 // 1866 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1867 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1868 // CHECK7-NEXT: entry: 1869 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1870 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1871 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1872 // CHECK7-NEXT: ret void 1873 // 1874 // 1875 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp 1876 // CHECK7-SAME: () #[[ATTR0]] { 1877 // CHECK7-NEXT: entry: 1878 // CHECK7-NEXT: call void @__cxx_global_var_init() 1879 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 1880 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 1881 // CHECK7-NEXT: ret void 1882 // 1883 // 1884 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1885 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1886 // CHECK9-NEXT: entry: 1887 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1888 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1889 // CHECK9-NEXT: ret void 1890 // 1891 // 1892 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1893 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1894 // CHECK9-NEXT: entry: 1895 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1896 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1897 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1898 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1899 // CHECK9-NEXT: ret void 1900 // 1901 // 1902 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1903 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1904 // CHECK9-NEXT: entry: 1905 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1906 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1907 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1908 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1909 // CHECK9-NEXT: ret void 1910 // 1911 // 1912 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1913 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1914 // CHECK9-NEXT: entry: 1915 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1916 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1917 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1918 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1919 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1920 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1921 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 1922 // CHECK9-NEXT: ret void 1923 // 1924 // 1925 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1926 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1927 // CHECK9-NEXT: entry: 1928 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1929 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1930 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1931 // CHECK9-NEXT: ret void 1932 // 1933 // 1934 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1935 // CHECK9-SAME: () #[[ATTR0]] { 1936 // CHECK9-NEXT: entry: 1937 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1938 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1939 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1940 // CHECK9-NEXT: ret void 1941 // 1942 // 1943 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1944 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1945 // CHECK9-NEXT: entry: 1946 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1947 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1948 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1949 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1950 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1951 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1952 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1953 // CHECK9-NEXT: ret void 1954 // 1955 // 1956 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1957 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1958 // CHECK9-NEXT: entry: 1959 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1960 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1961 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1962 // CHECK9: arraydestroy.body: 1963 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1964 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1965 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1966 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1967 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1968 // CHECK9: arraydestroy.done1: 1969 // CHECK9-NEXT: ret void 1970 // 1971 // 1972 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1973 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1974 // CHECK9-NEXT: entry: 1975 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1976 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1977 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1978 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1979 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1980 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1981 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1982 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1983 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1984 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1985 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 1986 // CHECK9-NEXT: ret void 1987 // 1988 // 1989 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1990 // CHECK9-SAME: () #[[ATTR0]] { 1991 // CHECK9-NEXT: entry: 1992 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1993 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1994 // CHECK9-NEXT: ret void 1995 // 1996 // 1997 // CHECK9-LABEL: define {{[^@]+}}@main 1998 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1999 // CHECK9-NEXT: entry: 2000 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2001 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2002 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 2003 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2004 // CHECK9-NEXT: ret i32 0 2005 // 2006 // 2007 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 2008 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] { 2009 // CHECK9-NEXT: entry: 2010 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2011 // CHECK9-NEXT: ret void 2012 // 2013 // 2014 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2015 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] { 2016 // CHECK9-NEXT: entry: 2017 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2018 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2019 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2020 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2021 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 2022 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2023 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2024 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2025 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2026 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 2027 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 2028 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 2029 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2030 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2031 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2032 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2033 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2034 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 2035 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2036 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2037 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2038 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2039 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 2040 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2041 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2042 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2043 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2044 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2045 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2046 // CHECK9: cond.true: 2047 // CHECK9-NEXT: br label [[COND_END:%.*]] 2048 // CHECK9: cond.false: 2049 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2050 // CHECK9-NEXT: br label [[COND_END]] 2051 // CHECK9: cond.end: 2052 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2053 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2054 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2055 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2056 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2057 // CHECK9: omp.inner.for.cond: 2058 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2059 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 2060 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2061 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2062 // CHECK9: omp.inner.for.body: 2063 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2064 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2065 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2066 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 2067 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4 2068 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 2069 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 2070 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4 2071 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2072 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4 2073 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 2074 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 2075 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 2076 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 2077 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 2078 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 2079 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2080 // CHECK9: omp.body.continue: 2081 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2082 // CHECK9: omp.inner.for.inc: 2083 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2084 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 2085 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2086 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2087 // CHECK9: omp.inner.for.end: 2088 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2089 // CHECK9: omp.loop.exit: 2090 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2091 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2092 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2093 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2094 // CHECK9: .omp.final.then: 2095 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 2096 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2097 // CHECK9: .omp.final.done: 2098 // CHECK9-NEXT: ret void 2099 // 2100 // 2101 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp 2102 // CHECK9-SAME: () #[[ATTR0]] { 2103 // CHECK9-NEXT: entry: 2104 // CHECK9-NEXT: call void @__cxx_global_var_init() 2105 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2106 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2107 // CHECK9-NEXT: ret void 2108 // 2109 // 2110 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2111 // CHECK9-SAME: () #[[ATTR0]] { 2112 // CHECK9-NEXT: entry: 2113 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2114 // CHECK9-NEXT: ret void 2115 // 2116 // 2117 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2118 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2119 // CHECK11-NEXT: entry: 2120 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2121 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2122 // CHECK11-NEXT: ret void 2123 // 2124 // 2125 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2126 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2127 // CHECK11-NEXT: entry: 2128 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2129 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2130 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2131 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2132 // CHECK11-NEXT: ret void 2133 // 2134 // 2135 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2136 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2137 // CHECK11-NEXT: entry: 2138 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2139 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2140 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2141 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2142 // CHECK11-NEXT: ret void 2143 // 2144 // 2145 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2146 // CHECK11-SAME: () #[[ATTR0]] { 2147 // CHECK11-NEXT: entry: 2148 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2149 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2150 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2151 // CHECK11-NEXT: ret void 2152 // 2153 // 2154 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2155 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2156 // CHECK11-NEXT: entry: 2157 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2158 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2159 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2160 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2161 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2162 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2163 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2164 // CHECK11-NEXT: ret void 2165 // 2166 // 2167 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2168 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2169 // CHECK11-NEXT: entry: 2170 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2171 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2172 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2173 // CHECK11: arraydestroy.body: 2174 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2175 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2176 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2177 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2178 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2179 // CHECK11: arraydestroy.done1: 2180 // CHECK11-NEXT: ret void 2181 // 2182 // 2183 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2184 // CHECK11-SAME: () #[[ATTR0]] { 2185 // CHECK11-NEXT: entry: 2186 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2187 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2188 // CHECK11-NEXT: ret void 2189 // 2190 // 2191 // CHECK11-LABEL: define {{[^@]+}}@main 2192 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2193 // CHECK11-NEXT: entry: 2194 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2195 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2196 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2197 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2198 // CHECK11-NEXT: ret i32 0 2199 // 2200 // 2201 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2202 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2203 // CHECK11-NEXT: entry: 2204 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2205 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2206 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2207 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2208 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2209 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2210 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 2211 // CHECK11-NEXT: ret void 2212 // 2213 // 2214 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2215 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2216 // CHECK11-NEXT: entry: 2217 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2218 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2219 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2220 // CHECK11-NEXT: ret void 2221 // 2222 // 2223 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2224 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2225 // CHECK11-NEXT: entry: 2226 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2227 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2228 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2229 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2230 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2231 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2232 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2233 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2234 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2235 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2236 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2237 // CHECK11-NEXT: ret void 2238 // 2239 // 2240 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp 2241 // CHECK11-SAME: () #[[ATTR0]] { 2242 // CHECK11-NEXT: entry: 2243 // CHECK11-NEXT: call void @__cxx_global_var_init() 2244 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2245 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2246 // CHECK11-NEXT: ret void 2247 // 2248