1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
15
16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var)
57 for (int i = 0; i < 2; ++i) {
58 vec[i] = t_var;
59 s_arr[i] = var;
60 }
61 return T();
62 }
63
64 S<float> test;
65 int t_var = 333;
66 int vec[] = {1, 2};
67 S<float> s_arr[] = {1, 2};
68 S<float> var(3);
69
main()70 int main() {
71 static int sivar;
72 #ifdef LAMBDA
73 [&]() {
74 #pragma omp target teams distribute simd private(g, g1, sivar)
75 for (int i = 0; i < 2; ++i) {
76
77 // Skip global, bound tid and loop vars
78 g = 1;
79 g1 = 1;
80 sivar = 2;
81 [&]() {
82 g = 2;
83 g1 = 2;
84 sivar = 4;
85
86 }();
87 }
88 }();
89 return 0;
90 #else
91 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var, sivar)
92 for (int i = 0; i < 2; ++i) {
93 vec[i] = t_var;
94 s_arr[i] = var;
95 sivar += i;
96 }
97 return tmain<int>();
98 #endif
99 }
100
101
102
103 // Skip global, bound tid and loop vars
104
105 // private(s_arr)
106
107 // private(var)
108
109
110
111
112
113 // Skip global, bound tid and loop vars
114
115 // private(s_arr)
116
117
118 // private(var)
119
120
121 #endif
122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
124 // CHECK1-NEXT: entry:
125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
126 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
127 // CHECK1-NEXT: ret void
128 //
129 //
130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
131 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
132 // CHECK1-NEXT: entry:
133 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
134 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
135 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
136 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
137 // CHECK1-NEXT: ret void
138 //
139 //
140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
141 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
142 // CHECK1-NEXT: entry:
143 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
144 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
145 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
146 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
147 // CHECK1-NEXT: ret void
148 //
149 //
150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
151 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
152 // CHECK1-NEXT: entry:
153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
156 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
157 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
158 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
159 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
160 // CHECK1-NEXT: ret void
161 //
162 //
163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
164 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
165 // CHECK1-NEXT: entry:
166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
169 // CHECK1-NEXT: ret void
170 //
171 //
172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
173 // CHECK1-SAME: () #[[ATTR0]] {
174 // CHECK1-NEXT: entry:
175 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
176 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
177 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
178 // CHECK1-NEXT: ret void
179 //
180 //
181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
182 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
183 // CHECK1-NEXT: entry:
184 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
185 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
186 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
187 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
189 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
190 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
191 // CHECK1-NEXT: ret void
192 //
193 //
194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
195 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
196 // CHECK1-NEXT: entry:
197 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
198 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
199 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
200 // CHECK1: arraydestroy.body:
201 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
202 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
204 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
205 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
206 // CHECK1: arraydestroy.done1:
207 // CHECK1-NEXT: ret void
208 //
209 //
210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
211 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
212 // CHECK1-NEXT: entry:
213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
216 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
217 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
218 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
219 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
220 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
221 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
222 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
223 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
224 // CHECK1-NEXT: ret void
225 //
226 //
227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
228 // CHECK1-SAME: () #[[ATTR0]] {
229 // CHECK1-NEXT: entry:
230 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
231 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
232 // CHECK1-NEXT: ret void
233 //
234 //
235 // CHECK1-LABEL: define {{[^@]+}}@main
236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
237 // CHECK1-NEXT: entry:
238 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
241 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
242 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
243 // CHECK1-NEXT: store i32 1, i32* [[TMP0]], align 4
244 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
245 // CHECK1-NEXT: store i32 0, i32* [[TMP1]], align 4
246 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
247 // CHECK1-NEXT: store i8** null, i8*** [[TMP2]], align 8
248 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
249 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
250 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
251 // CHECK1-NEXT: store i64* null, i64** [[TMP4]], align 8
252 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
253 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
254 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
255 // CHECK1-NEXT: store i8** null, i8*** [[TMP6]], align 8
256 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
257 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
258 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
259 // CHECK1-NEXT: store i64 2, i64* [[TMP8]], align 8
260 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
261 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
262 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
263 // CHECK1: omp_offload.failed:
264 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
265 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
266 // CHECK1: omp_offload.cont:
267 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
268 // CHECK1-NEXT: ret i32 [[CALL]]
269 //
270 //
271 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
272 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
273 // CHECK1-NEXT: entry:
274 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
275 // CHECK1-NEXT: ret void
276 //
277 //
278 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
279 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
280 // CHECK1-NEXT: entry:
281 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
282 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
283 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
284 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
285 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
286 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
287 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
288 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
289 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
290 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
291 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
292 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
293 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
294 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
295 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
296 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
297 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
298 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
299 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
300 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
301 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
302 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
303 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
304 // CHECK1: arrayctor.loop:
305 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
306 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
307 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
308 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
309 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
310 // CHECK1: arrayctor.cont:
311 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
312 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
313 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
314 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
315 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
316 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
317 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
318 // CHECK1: cond.true:
319 // CHECK1-NEXT: br label [[COND_END:%.*]]
320 // CHECK1: cond.false:
321 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
322 // CHECK1-NEXT: br label [[COND_END]]
323 // CHECK1: cond.end:
324 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
325 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
326 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
327 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
328 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
329 // CHECK1: omp.inner.for.cond:
330 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
331 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
332 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
333 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
334 // CHECK1: omp.inner.for.cond.cleanup:
335 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
336 // CHECK1: omp.inner.for.body:
337 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
338 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
339 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
340 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
341 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5
342 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
343 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
344 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
345 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
346 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
347 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
348 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
349 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8*
350 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
351 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5
352 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
353 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5
354 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
355 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5
356 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
357 // CHECK1: omp.body.continue:
358 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
359 // CHECK1: omp.inner.for.inc:
360 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
361 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
362 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
363 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
364 // CHECK1: omp.inner.for.end:
365 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
366 // CHECK1: omp.loop.exit:
367 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
368 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
369 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
370 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
371 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
372 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
373 // CHECK1: .omp.final.then:
374 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
375 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
376 // CHECK1: .omp.final.done:
377 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
378 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
379 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2
380 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
381 // CHECK1: arraydestroy.body:
382 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
383 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
384 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
385 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
386 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
387 // CHECK1: arraydestroy.done7:
388 // CHECK1-NEXT: ret void
389 //
390 //
391 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
392 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat {
393 // CHECK1-NEXT: entry:
394 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
395 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
396 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
397 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
398 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
399 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
400 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
401 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
402 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
403 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
404 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
405 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
406 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
407 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
408 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
409 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
410 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
411 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
412 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
413 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
414 // CHECK1-NEXT: store i32 1, i32* [[TMP1]], align 4
415 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
416 // CHECK1-NEXT: store i32 0, i32* [[TMP2]], align 4
417 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
418 // CHECK1-NEXT: store i8** null, i8*** [[TMP3]], align 8
419 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
420 // CHECK1-NEXT: store i8** null, i8*** [[TMP4]], align 8
421 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
422 // CHECK1-NEXT: store i64* null, i64** [[TMP5]], align 8
423 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
424 // CHECK1-NEXT: store i64* null, i64** [[TMP6]], align 8
425 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
426 // CHECK1-NEXT: store i8** null, i8*** [[TMP7]], align 8
427 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
428 // CHECK1-NEXT: store i8** null, i8*** [[TMP8]], align 8
429 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
430 // CHECK1-NEXT: store i64 2, i64* [[TMP9]], align 8
431 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
432 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
433 // CHECK1-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
434 // CHECK1: omp_offload.failed:
435 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
436 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
437 // CHECK1: omp_offload.cont:
438 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
439 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
440 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
441 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
442 // CHECK1: arraydestroy.body:
443 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
444 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
445 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
446 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
447 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
448 // CHECK1: arraydestroy.done2:
449 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
450 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
451 // CHECK1-NEXT: ret i32 [[TMP13]]
452 //
453 //
454 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
455 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
456 // CHECK1-NEXT: entry:
457 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
458 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
459 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
460 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
461 // CHECK1-NEXT: ret void
462 //
463 //
464 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
465 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
466 // CHECK1-NEXT: entry:
467 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
468 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
469 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
470 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
471 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
472 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
473 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
474 // CHECK1-NEXT: ret void
475 //
476 //
477 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
478 // CHECK1-SAME: () #[[ATTR4]] {
479 // CHECK1-NEXT: entry:
480 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
481 // CHECK1-NEXT: ret void
482 //
483 //
484 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
485 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
486 // CHECK1-NEXT: entry:
487 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
488 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
489 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
490 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
491 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
492 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
493 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
494 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
495 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
496 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
497 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
498 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
499 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
500 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
501 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
502 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
503 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
504 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
505 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
506 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
507 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
508 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
509 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
510 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
511 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
512 // CHECK1: arrayctor.loop:
513 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
514 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
515 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
516 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
517 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
518 // CHECK1: arrayctor.cont:
519 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
520 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
521 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
522 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
523 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
524 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
525 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
526 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
527 // CHECK1: cond.true:
528 // CHECK1-NEXT: br label [[COND_END:%.*]]
529 // CHECK1: cond.false:
530 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
531 // CHECK1-NEXT: br label [[COND_END]]
532 // CHECK1: cond.end:
533 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
534 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
535 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
536 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
537 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
538 // CHECK1: omp.inner.for.cond:
539 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
540 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
541 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
542 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
543 // CHECK1: omp.inner.for.cond.cleanup:
544 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
545 // CHECK1: omp.inner.for.body:
546 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
547 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
548 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
549 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
550 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11
551 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
552 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
553 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
554 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
555 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11
556 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
557 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
558 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
559 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8*
560 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
561 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11
562 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
563 // CHECK1: omp.body.continue:
564 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
565 // CHECK1: omp.inner.for.inc:
566 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
567 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
568 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
569 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
570 // CHECK1: omp.inner.for.end:
571 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
572 // CHECK1: omp.loop.exit:
573 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
574 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
575 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
576 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
577 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
578 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
579 // CHECK1: .omp.final.then:
580 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
581 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
582 // CHECK1: .omp.final.done:
583 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
584 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
585 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2
586 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
587 // CHECK1: arraydestroy.body:
588 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
589 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
590 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
591 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
592 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
593 // CHECK1: arraydestroy.done8:
594 // CHECK1-NEXT: ret void
595 //
596 //
597 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
598 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
599 // CHECK1-NEXT: entry:
600 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
601 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
602 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
603 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
604 // CHECK1-NEXT: ret void
605 //
606 //
607 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
608 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
609 // CHECK1-NEXT: entry:
610 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
611 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
612 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
613 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
614 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
615 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
616 // CHECK1-NEXT: ret void
617 //
618 //
619 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
620 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
621 // CHECK1-NEXT: entry:
622 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
623 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
624 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
625 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
626 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
627 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
628 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
629 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
630 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
631 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
632 // CHECK1-NEXT: ret void
633 //
634 //
635 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
636 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
637 // CHECK1-NEXT: entry:
638 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
639 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
640 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
641 // CHECK1-NEXT: ret void
642 //
643 //
644 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
645 // CHECK1-SAME: () #[[ATTR0]] {
646 // CHECK1-NEXT: entry:
647 // CHECK1-NEXT: call void @__cxx_global_var_init()
648 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
649 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
650 // CHECK1-NEXT: ret void
651 //
652 //
653 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
654 // CHECK1-SAME: () #[[ATTR0]] {
655 // CHECK1-NEXT: entry:
656 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
657 // CHECK1-NEXT: ret void
658 //
659 //
660 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
661 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
662 // CHECK3-NEXT: entry:
663 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
664 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
665 // CHECK3-NEXT: ret void
666 //
667 //
668 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
669 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
670 // CHECK3-NEXT: entry:
671 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
672 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
673 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
674 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
675 // CHECK3-NEXT: ret void
676 //
677 //
678 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
679 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
680 // CHECK3-NEXT: entry:
681 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
682 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
683 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
684 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
685 // CHECK3-NEXT: ret void
686 //
687 //
688 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
689 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
690 // CHECK3-NEXT: entry:
691 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
692 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
693 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
694 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
695 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
696 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
697 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
698 // CHECK3-NEXT: ret void
699 //
700 //
701 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
702 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
703 // CHECK3-NEXT: entry:
704 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
705 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
706 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
707 // CHECK3-NEXT: ret void
708 //
709 //
710 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
711 // CHECK3-SAME: () #[[ATTR0]] {
712 // CHECK3-NEXT: entry:
713 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
714 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
715 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
716 // CHECK3-NEXT: ret void
717 //
718 //
719 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
720 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
721 // CHECK3-NEXT: entry:
722 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
723 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
724 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
725 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
726 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
727 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
728 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
729 // CHECK3-NEXT: ret void
730 //
731 //
732 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
733 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
734 // CHECK3-NEXT: entry:
735 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
736 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
737 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
738 // CHECK3: arraydestroy.body:
739 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
740 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
741 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
742 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
743 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
744 // CHECK3: arraydestroy.done1:
745 // CHECK3-NEXT: ret void
746 //
747 //
748 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
749 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
750 // CHECK3-NEXT: entry:
751 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
752 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
753 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
754 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
755 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
756 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
757 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
758 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
759 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
760 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
761 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
762 // CHECK3-NEXT: ret void
763 //
764 //
765 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
766 // CHECK3-SAME: () #[[ATTR0]] {
767 // CHECK3-NEXT: entry:
768 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
769 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
770 // CHECK3-NEXT: ret void
771 //
772 //
773 // CHECK3-LABEL: define {{[^@]+}}@main
774 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
775 // CHECK3-NEXT: entry:
776 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
777 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
778 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
779 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
780 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
781 // CHECK3-NEXT: store i32 1, i32* [[TMP0]], align 4
782 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
783 // CHECK3-NEXT: store i32 0, i32* [[TMP1]], align 4
784 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
785 // CHECK3-NEXT: store i8** null, i8*** [[TMP2]], align 4
786 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
787 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
788 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
789 // CHECK3-NEXT: store i64* null, i64** [[TMP4]], align 4
790 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
791 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
792 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
793 // CHECK3-NEXT: store i8** null, i8*** [[TMP6]], align 4
794 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
795 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
796 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
797 // CHECK3-NEXT: store i64 2, i64* [[TMP8]], align 8
798 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
799 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
800 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
801 // CHECK3: omp_offload.failed:
802 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
803 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
804 // CHECK3: omp_offload.cont:
805 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
806 // CHECK3-NEXT: ret i32 [[CALL]]
807 //
808 //
809 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
810 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
811 // CHECK3-NEXT: entry:
812 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
813 // CHECK3-NEXT: ret void
814 //
815 //
816 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
817 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
818 // CHECK3-NEXT: entry:
819 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
820 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
821 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
822 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
823 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
824 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
825 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
826 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
827 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
828 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
829 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
830 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
831 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
832 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
833 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
834 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
835 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
836 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
837 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
838 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
839 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
840 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
841 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
842 // CHECK3: arrayctor.loop:
843 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
844 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
845 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
846 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
847 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
848 // CHECK3: arrayctor.cont:
849 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
850 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
851 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
852 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
853 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
854 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
855 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
856 // CHECK3: cond.true:
857 // CHECK3-NEXT: br label [[COND_END:%.*]]
858 // CHECK3: cond.false:
859 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
860 // CHECK3-NEXT: br label [[COND_END]]
861 // CHECK3: cond.end:
862 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
863 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
864 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
865 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
866 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
867 // CHECK3: omp.inner.for.cond:
868 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
869 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
870 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
871 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
872 // CHECK3: omp.inner.for.cond.cleanup:
873 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
874 // CHECK3: omp.inner.for.body:
875 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
876 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
877 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
878 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
879 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
880 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
881 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
882 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
883 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
884 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]]
885 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
886 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
887 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6
888 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
889 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6
890 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
891 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6
892 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
893 // CHECK3: omp.body.continue:
894 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
895 // CHECK3: omp.inner.for.inc:
896 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
897 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
898 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
899 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
900 // CHECK3: omp.inner.for.end:
901 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
902 // CHECK3: omp.loop.exit:
903 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
904 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
905 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
906 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
907 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
908 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
909 // CHECK3: .omp.final.then:
910 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
911 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
912 // CHECK3: .omp.final.done:
913 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
914 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
915 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
916 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
917 // CHECK3: arraydestroy.body:
918 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
919 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
920 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
921 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
922 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
923 // CHECK3: arraydestroy.done6:
924 // CHECK3-NEXT: ret void
925 //
926 //
927 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
928 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat {
929 // CHECK3-NEXT: entry:
930 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
931 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
932 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
933 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
934 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
935 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
936 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
937 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
938 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
939 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
940 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
941 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
942 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
943 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
944 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
945 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
946 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
947 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
948 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
949 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
950 // CHECK3-NEXT: store i32 1, i32* [[TMP1]], align 4
951 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
952 // CHECK3-NEXT: store i32 0, i32* [[TMP2]], align 4
953 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
954 // CHECK3-NEXT: store i8** null, i8*** [[TMP3]], align 4
955 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
956 // CHECK3-NEXT: store i8** null, i8*** [[TMP4]], align 4
957 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
958 // CHECK3-NEXT: store i64* null, i64** [[TMP5]], align 4
959 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
960 // CHECK3-NEXT: store i64* null, i64** [[TMP6]], align 4
961 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
962 // CHECK3-NEXT: store i8** null, i8*** [[TMP7]], align 4
963 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
964 // CHECK3-NEXT: store i8** null, i8*** [[TMP8]], align 4
965 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
966 // CHECK3-NEXT: store i64 2, i64* [[TMP9]], align 8
967 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
968 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
969 // CHECK3-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
970 // CHECK3: omp_offload.failed:
971 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
972 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
973 // CHECK3: omp_offload.cont:
974 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
975 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
976 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
977 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
978 // CHECK3: arraydestroy.body:
979 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
980 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
981 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
982 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
983 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
984 // CHECK3: arraydestroy.done2:
985 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
986 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4
987 // CHECK3-NEXT: ret i32 [[TMP13]]
988 //
989 //
990 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
991 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
992 // CHECK3-NEXT: entry:
993 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
994 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
995 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
996 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
997 // CHECK3-NEXT: ret void
998 //
999 //
1000 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1001 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1002 // CHECK3-NEXT: entry:
1003 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1004 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1005 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1006 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1007 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1008 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1009 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1010 // CHECK3-NEXT: ret void
1011 //
1012 //
1013 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1014 // CHECK3-SAME: () #[[ATTR4]] {
1015 // CHECK3-NEXT: entry:
1016 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
1017 // CHECK3-NEXT: ret void
1018 //
1019 //
1020 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1021 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1022 // CHECK3-NEXT: entry:
1023 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1024 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1025 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1026 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1027 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1028 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1029 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1030 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1031 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1032 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1033 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1034 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1035 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1036 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1037 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1038 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1039 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1040 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1041 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1042 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1043 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1044 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1045 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1046 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1047 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1048 // CHECK3: arrayctor.loop:
1049 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1050 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1051 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1052 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1053 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1054 // CHECK3: arrayctor.cont:
1055 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1056 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1057 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1058 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1059 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1060 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1061 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1062 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1063 // CHECK3: cond.true:
1064 // CHECK3-NEXT: br label [[COND_END:%.*]]
1065 // CHECK3: cond.false:
1066 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1067 // CHECK3-NEXT: br label [[COND_END]]
1068 // CHECK3: cond.end:
1069 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1070 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1071 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1072 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1073 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1074 // CHECK3: omp.inner.for.cond:
1075 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1076 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
1077 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1078 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1079 // CHECK3: omp.inner.for.cond.cleanup:
1080 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1081 // CHECK3: omp.inner.for.body:
1082 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1083 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1084 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1085 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
1086 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12
1087 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
1088 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1089 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
1090 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12
1091 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
1092 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
1093 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
1094 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
1095 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12
1096 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1097 // CHECK3: omp.body.continue:
1098 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1099 // CHECK3: omp.inner.for.inc:
1100 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1101 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1102 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1103 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1104 // CHECK3: omp.inner.for.end:
1105 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1106 // CHECK3: omp.loop.exit:
1107 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1108 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
1109 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
1110 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1111 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1112 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1113 // CHECK3: .omp.final.then:
1114 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1115 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1116 // CHECK3: .omp.final.done:
1117 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1118 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1119 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
1120 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1121 // CHECK3: arraydestroy.body:
1122 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1123 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1124 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1125 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1126 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1127 // CHECK3: arraydestroy.done7:
1128 // CHECK3-NEXT: ret void
1129 //
1130 //
1131 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1132 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1133 // CHECK3-NEXT: entry:
1134 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1135 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1136 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1137 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1138 // CHECK3-NEXT: ret void
1139 //
1140 //
1141 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1142 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1143 // CHECK3-NEXT: entry:
1144 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1145 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1146 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1147 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1148 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1149 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1150 // CHECK3-NEXT: ret void
1151 //
1152 //
1153 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1154 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1155 // CHECK3-NEXT: entry:
1156 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1157 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1158 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1159 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1160 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1161 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1162 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1163 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1164 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1165 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1166 // CHECK3-NEXT: ret void
1167 //
1168 //
1169 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1170 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1171 // CHECK3-NEXT: entry:
1172 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1173 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1174 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1175 // CHECK3-NEXT: ret void
1176 //
1177 //
1178 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1179 // CHECK3-SAME: () #[[ATTR0]] {
1180 // CHECK3-NEXT: entry:
1181 // CHECK3-NEXT: call void @__cxx_global_var_init()
1182 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
1183 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
1184 // CHECK3-NEXT: ret void
1185 //
1186 //
1187 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1188 // CHECK3-SAME: () #[[ATTR0]] {
1189 // CHECK3-NEXT: entry:
1190 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1191 // CHECK3-NEXT: ret void
1192 //
1193 //
1194 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
1195 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1196 // CHECK5-NEXT: entry:
1197 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1198 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1199 // CHECK5-NEXT: ret void
1200 //
1201 //
1202 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1203 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1204 // CHECK5-NEXT: entry:
1205 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1206 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1207 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1208 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1209 // CHECK5-NEXT: ret void
1210 //
1211 //
1212 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1213 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1214 // CHECK5-NEXT: entry:
1215 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1216 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1217 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1218 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1219 // CHECK5-NEXT: ret void
1220 //
1221 //
1222 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1223 // CHECK5-SAME: () #[[ATTR0]] {
1224 // CHECK5-NEXT: entry:
1225 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
1226 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
1227 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1228 // CHECK5-NEXT: ret void
1229 //
1230 //
1231 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1232 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1233 // CHECK5-NEXT: entry:
1234 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1235 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1236 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1237 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1238 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1239 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1240 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1241 // CHECK5-NEXT: ret void
1242 //
1243 //
1244 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1245 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1246 // CHECK5-NEXT: entry:
1247 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1248 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1249 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1250 // CHECK5: arraydestroy.body:
1251 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1252 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1253 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1254 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1255 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1256 // CHECK5: arraydestroy.done1:
1257 // CHECK5-NEXT: ret void
1258 //
1259 //
1260 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1261 // CHECK5-SAME: () #[[ATTR0]] {
1262 // CHECK5-NEXT: entry:
1263 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1264 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1265 // CHECK5-NEXT: ret void
1266 //
1267 //
1268 // CHECK5-LABEL: define {{[^@]+}}@main
1269 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1270 // CHECK5-NEXT: entry:
1271 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1272 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1273 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1274 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1275 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1276 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1277 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1278 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1279 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1280 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1281 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1282 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1283 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1284 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1285 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1286 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1287 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1288 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1289 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1290 // CHECK5: arrayctor.loop:
1291 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1292 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1293 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1294 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1295 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1296 // CHECK5: arrayctor.cont:
1297 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1298 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1299 // CHECK5: omp.inner.for.cond:
1300 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1301 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
1302 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1303 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1304 // CHECK5: omp.inner.for.cond.cleanup:
1305 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1306 // CHECK5: omp.inner.for.body:
1307 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1308 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1309 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1310 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
1311 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
1312 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1313 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1314 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1315 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
1316 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1317 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
1318 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
1319 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1320 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1321 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
1322 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1323 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
1324 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
1325 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
1326 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1327 // CHECK5: omp.body.continue:
1328 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1329 // CHECK5: omp.inner.for.inc:
1330 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1331 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
1332 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1333 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1334 // CHECK5: omp.inner.for.end:
1335 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1336 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1337 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1338 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
1339 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1340 // CHECK5: arraydestroy.body:
1341 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1342 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1343 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1344 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1345 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1346 // CHECK5: arraydestroy.done6:
1347 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1348 // CHECK5-NEXT: ret i32 [[CALL]]
1349 //
1350 //
1351 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1352 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1353 // CHECK5-NEXT: entry:
1354 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1355 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1356 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1357 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1358 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1359 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1360 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1361 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1362 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1363 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1364 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1365 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1366 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1367 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1368 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1369 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1370 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
1371 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1372 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
1373 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1374 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1375 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1376 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1377 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1378 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1379 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1380 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1381 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1382 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1383 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1384 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1385 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1386 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1387 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1388 // CHECK5: arrayctor.loop:
1389 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1390 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1391 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1392 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1393 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1394 // CHECK5: arrayctor.cont:
1395 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1396 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
1397 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1398 // CHECK5: omp.inner.for.cond:
1399 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1400 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
1401 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1402 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1403 // CHECK5: omp.inner.for.cond.cleanup:
1404 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1405 // CHECK5: omp.inner.for.body:
1406 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1407 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1408 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1409 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
1410 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
1411 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1412 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1413 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
1414 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
1415 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
1416 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1417 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
1418 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
1419 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
1420 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
1421 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
1422 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1423 // CHECK5: omp.body.continue:
1424 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1425 // CHECK5: omp.inner.for.inc:
1426 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1427 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
1428 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1429 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1430 // CHECK5: omp.inner.for.end:
1431 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
1432 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1433 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1434 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
1435 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1436 // CHECK5: arraydestroy.body:
1437 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1438 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1439 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1440 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1441 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1442 // CHECK5: arraydestroy.done11:
1443 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1444 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1445 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
1446 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
1447 // CHECK5: arraydestroy.body13:
1448 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1449 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1450 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
1451 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1452 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1453 // CHECK5: arraydestroy.done17:
1454 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1455 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
1456 // CHECK5-NEXT: ret i32 [[TMP14]]
1457 //
1458 //
1459 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1460 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1461 // CHECK5-NEXT: entry:
1462 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1463 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1464 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1465 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1466 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1467 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1468 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
1469 // CHECK5-NEXT: ret void
1470 //
1471 //
1472 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1473 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1474 // CHECK5-NEXT: entry:
1475 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1476 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1477 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1478 // CHECK5-NEXT: ret void
1479 //
1480 //
1481 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1482 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1483 // CHECK5-NEXT: entry:
1484 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1485 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1486 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1487 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1488 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1489 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1490 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1491 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1492 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1493 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1494 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
1495 // CHECK5-NEXT: ret void
1496 //
1497 //
1498 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1499 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1500 // CHECK5-NEXT: entry:
1501 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1502 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1503 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1504 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1505 // CHECK5-NEXT: ret void
1506 //
1507 //
1508 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1509 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1510 // CHECK5-NEXT: entry:
1511 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1512 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1513 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1514 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1515 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1516 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1517 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1518 // CHECK5-NEXT: ret void
1519 //
1520 //
1521 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1522 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1523 // CHECK5-NEXT: entry:
1524 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1525 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1526 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1527 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1528 // CHECK5-NEXT: ret void
1529 //
1530 //
1531 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1532 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1533 // CHECK5-NEXT: entry:
1534 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1535 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1536 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1537 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1538 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1539 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1540 // CHECK5-NEXT: ret void
1541 //
1542 //
1543 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1544 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1545 // CHECK5-NEXT: entry:
1546 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1547 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1548 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1549 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1550 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1551 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1552 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1553 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1554 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1555 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1556 // CHECK5-NEXT: ret void
1557 //
1558 //
1559 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1560 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1561 // CHECK5-NEXT: entry:
1562 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1563 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1564 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1565 // CHECK5-NEXT: ret void
1566 //
1567 //
1568 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1569 // CHECK5-SAME: () #[[ATTR0]] {
1570 // CHECK5-NEXT: entry:
1571 // CHECK5-NEXT: call void @__cxx_global_var_init()
1572 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
1573 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
1574 // CHECK5-NEXT: ret void
1575 //
1576 //
1577 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
1578 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1579 // CHECK7-NEXT: entry:
1580 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1581 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1582 // CHECK7-NEXT: ret void
1583 //
1584 //
1585 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1586 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1587 // CHECK7-NEXT: entry:
1588 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1589 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1590 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1591 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1592 // CHECK7-NEXT: ret void
1593 //
1594 //
1595 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1596 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1597 // CHECK7-NEXT: entry:
1598 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1599 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1600 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1601 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1602 // CHECK7-NEXT: ret void
1603 //
1604 //
1605 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1606 // CHECK7-SAME: () #[[ATTR0]] {
1607 // CHECK7-NEXT: entry:
1608 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00)
1609 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00)
1610 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1611 // CHECK7-NEXT: ret void
1612 //
1613 //
1614 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1615 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1616 // CHECK7-NEXT: entry:
1617 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1618 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1619 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1620 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1621 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1622 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1623 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1624 // CHECK7-NEXT: ret void
1625 //
1626 //
1627 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1628 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
1629 // CHECK7-NEXT: entry:
1630 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1631 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1632 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1633 // CHECK7: arraydestroy.body:
1634 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1635 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1636 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1637 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1638 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1639 // CHECK7: arraydestroy.done1:
1640 // CHECK7-NEXT: ret void
1641 //
1642 //
1643 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1644 // CHECK7-SAME: () #[[ATTR0]] {
1645 // CHECK7-NEXT: entry:
1646 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1647 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1648 // CHECK7-NEXT: ret void
1649 //
1650 //
1651 // CHECK7-LABEL: define {{[^@]+}}@main
1652 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
1653 // CHECK7-NEXT: entry:
1654 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1655 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1656 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1657 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1658 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1659 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1660 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1661 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1662 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1663 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1664 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1665 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
1666 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1667 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1668 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1669 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1670 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1671 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1672 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1673 // CHECK7: arrayctor.loop:
1674 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1675 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1676 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1677 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1678 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1679 // CHECK7: arrayctor.cont:
1680 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]])
1681 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1682 // CHECK7: omp.inner.for.cond:
1683 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1684 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
1685 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1686 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1687 // CHECK7: omp.inner.for.cond.cleanup:
1688 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1689 // CHECK7: omp.inner.for.body:
1690 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1691 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1692 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1693 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
1694 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
1695 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1696 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
1697 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
1698 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1699 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
1700 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
1701 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1702 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
1703 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1704 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
1705 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
1706 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
1707 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1708 // CHECK7: omp.body.continue:
1709 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1710 // CHECK7: omp.inner.for.inc:
1711 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1712 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
1713 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1714 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1715 // CHECK7: omp.inner.for.end:
1716 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
1717 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1718 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1719 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
1720 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1721 // CHECK7: arraydestroy.body:
1722 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1723 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1724 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1725 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1726 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1727 // CHECK7: arraydestroy.done5:
1728 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1729 // CHECK7-NEXT: ret i32 [[CALL]]
1730 //
1731 //
1732 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1733 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
1734 // CHECK7-NEXT: entry:
1735 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1736 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1737 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1738 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1739 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1740 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1741 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1742 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1743 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1744 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1745 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1746 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1747 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1748 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1749 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1750 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1751 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
1752 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]])
1753 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
1754 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1755 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1756 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1757 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1758 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1759 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1760 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1761 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1762 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1763 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1764 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1765 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
1766 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1767 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1768 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1769 // CHECK7: arrayctor.loop:
1770 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1771 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1772 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1773 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1774 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1775 // CHECK7: arrayctor.cont:
1776 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1777 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
1778 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1779 // CHECK7: omp.inner.for.cond:
1780 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1781 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
1782 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1783 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1784 // CHECK7: omp.inner.for.cond.cleanup:
1785 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1786 // CHECK7: omp.inner.for.body:
1787 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1788 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
1789 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1790 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
1791 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
1792 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
1793 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
1794 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
1795 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
1796 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
1797 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
1798 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
1799 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
1800 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
1801 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1802 // CHECK7: omp.body.continue:
1803 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1804 // CHECK7: omp.inner.for.inc:
1805 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1806 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
1807 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
1808 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1809 // CHECK7: omp.inner.for.end:
1810 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
1811 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1812 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
1813 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
1814 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1815 // CHECK7: arraydestroy.body:
1816 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1817 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1818 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1819 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
1820 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
1821 // CHECK7: arraydestroy.done10:
1822 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
1823 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1824 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
1825 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
1826 // CHECK7: arraydestroy.body12:
1827 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
1828 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
1829 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
1830 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
1831 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
1832 // CHECK7: arraydestroy.done16:
1833 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1834 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
1835 // CHECK7-NEXT: ret i32 [[TMP14]]
1836 //
1837 //
1838 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1839 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1840 // CHECK7-NEXT: entry:
1841 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1842 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1843 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1844 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1845 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1846 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1847 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
1848 // CHECK7-NEXT: ret void
1849 //
1850 //
1851 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1852 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1853 // CHECK7-NEXT: entry:
1854 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1855 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1856 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1857 // CHECK7-NEXT: ret void
1858 //
1859 //
1860 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1861 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1862 // CHECK7-NEXT: entry:
1863 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1864 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1865 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1866 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1867 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1868 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1869 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1870 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1871 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1872 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1873 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
1874 // CHECK7-NEXT: ret void
1875 //
1876 //
1877 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1878 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1879 // CHECK7-NEXT: entry:
1880 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1881 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1882 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1883 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1884 // CHECK7-NEXT: ret void
1885 //
1886 //
1887 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1888 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1889 // CHECK7-NEXT: entry:
1890 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1891 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1892 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1893 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1894 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1895 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1896 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1897 // CHECK7-NEXT: ret void
1898 //
1899 //
1900 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1901 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1902 // CHECK7-NEXT: entry:
1903 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1904 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1905 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1906 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1907 // CHECK7-NEXT: ret void
1908 //
1909 //
1910 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1911 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1912 // CHECK7-NEXT: entry:
1913 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1914 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1915 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1916 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1917 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1918 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1919 // CHECK7-NEXT: ret void
1920 //
1921 //
1922 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1923 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1924 // CHECK7-NEXT: entry:
1925 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1926 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1927 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1928 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1929 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1930 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1931 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1932 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1933 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1934 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1935 // CHECK7-NEXT: ret void
1936 //
1937 //
1938 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1939 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1940 // CHECK7-NEXT: entry:
1941 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1942 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1943 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1944 // CHECK7-NEXT: ret void
1945 //
1946 //
1947 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1948 // CHECK7-SAME: () #[[ATTR0]] {
1949 // CHECK7-NEXT: entry:
1950 // CHECK7-NEXT: call void @__cxx_global_var_init()
1951 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
1952 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
1953 // CHECK7-NEXT: ret void
1954 //
1955 //
1956 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
1957 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1958 // CHECK9-NEXT: entry:
1959 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
1960 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1961 // CHECK9-NEXT: ret void
1962 //
1963 //
1964 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1965 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1966 // CHECK9-NEXT: entry:
1967 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1968 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1969 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1970 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1971 // CHECK9-NEXT: ret void
1972 //
1973 //
1974 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1975 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1976 // CHECK9-NEXT: entry:
1977 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1978 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1979 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1980 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1981 // CHECK9-NEXT: ret void
1982 //
1983 //
1984 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1985 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1986 // CHECK9-NEXT: entry:
1987 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1988 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1989 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1990 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1991 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1992 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1993 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
1994 // CHECK9-NEXT: ret void
1995 //
1996 //
1997 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1998 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1999 // CHECK9-NEXT: entry:
2000 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2001 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2002 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2003 // CHECK9-NEXT: ret void
2004 //
2005 //
2006 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2007 // CHECK9-SAME: () #[[ATTR0]] {
2008 // CHECK9-NEXT: entry:
2009 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2010 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2011 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2012 // CHECK9-NEXT: ret void
2013 //
2014 //
2015 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2016 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2017 // CHECK9-NEXT: entry:
2018 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2019 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2020 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2021 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2022 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2023 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2024 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2025 // CHECK9-NEXT: ret void
2026 //
2027 //
2028 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2029 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2030 // CHECK9-NEXT: entry:
2031 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2032 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2033 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2034 // CHECK9: arraydestroy.body:
2035 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2036 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2037 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2038 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2039 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2040 // CHECK9: arraydestroy.done1:
2041 // CHECK9-NEXT: ret void
2042 //
2043 //
2044 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2045 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2046 // CHECK9-NEXT: entry:
2047 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2048 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2049 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2050 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2051 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2052 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2053 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2054 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2055 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2056 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2057 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
2058 // CHECK9-NEXT: ret void
2059 //
2060 //
2061 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2062 // CHECK9-SAME: () #[[ATTR0]] {
2063 // CHECK9-NEXT: entry:
2064 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2065 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2066 // CHECK9-NEXT: ret void
2067 //
2068 //
2069 // CHECK9-LABEL: define {{[^@]+}}@main
2070 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2071 // CHECK9-NEXT: entry:
2072 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2073 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2074 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
2075 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2076 // CHECK9-NEXT: ret i32 0
2077 //
2078 //
2079 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74
2080 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] {
2081 // CHECK9-NEXT: entry:
2082 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2083 // CHECK9-NEXT: ret void
2084 //
2085 //
2086 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
2087 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] {
2088 // CHECK9-NEXT: entry:
2089 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2090 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2091 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2092 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
2093 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
2094 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2095 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2096 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2097 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2098 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
2099 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
2100 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
2101 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2102 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2103 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2104 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2105 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2106 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
2107 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2108 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2109 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2110 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2111 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
2112 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2113 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2114 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2115 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2116 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2117 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2118 // CHECK9: cond.true:
2119 // CHECK9-NEXT: br label [[COND_END:%.*]]
2120 // CHECK9: cond.false:
2121 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2122 // CHECK9-NEXT: br label [[COND_END]]
2123 // CHECK9: cond.end:
2124 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2125 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2126 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2127 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2128 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2129 // CHECK9: omp.inner.for.cond:
2130 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2131 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
2132 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2133 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2134 // CHECK9: omp.inner.for.body:
2135 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2136 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2137 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2138 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
2139 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4
2140 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
2141 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
2142 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4
2143 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
2144 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4
2145 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
2146 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
2147 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
2148 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
2149 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4
2150 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
2151 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2152 // CHECK9: omp.body.continue:
2153 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2154 // CHECK9: omp.inner.for.inc:
2155 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2156 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
2157 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
2158 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2159 // CHECK9: omp.inner.for.end:
2160 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2161 // CHECK9: omp.loop.exit:
2162 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2163 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2164 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
2165 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2166 // CHECK9: .omp.final.then:
2167 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
2168 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
2169 // CHECK9: .omp.final.done:
2170 // CHECK9-NEXT: ret void
2171 //
2172 //
2173 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
2174 // CHECK9-SAME: () #[[ATTR0]] {
2175 // CHECK9-NEXT: entry:
2176 // CHECK9-NEXT: call void @__cxx_global_var_init()
2177 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
2178 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
2179 // CHECK9-NEXT: ret void
2180 //
2181 //
2182 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2183 // CHECK9-SAME: () #[[ATTR0]] {
2184 // CHECK9-NEXT: entry:
2185 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
2186 // CHECK9-NEXT: ret void
2187 //
2188 //
2189 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
2190 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2191 // CHECK11-NEXT: entry:
2192 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test)
2193 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2194 // CHECK11-NEXT: ret void
2195 //
2196 //
2197 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2198 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2199 // CHECK11-NEXT: entry:
2200 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2201 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2202 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2203 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2204 // CHECK11-NEXT: ret void
2205 //
2206 //
2207 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2208 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2209 // CHECK11-NEXT: entry:
2210 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2211 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2212 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2213 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2214 // CHECK11-NEXT: ret void
2215 //
2216 //
2217 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2218 // CHECK11-SAME: () #[[ATTR0]] {
2219 // CHECK11-NEXT: entry:
2220 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00)
2221 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00)
2222 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2223 // CHECK11-NEXT: ret void
2224 //
2225 //
2226 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2227 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2228 // CHECK11-NEXT: entry:
2229 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2230 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2231 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2232 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2233 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2234 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2235 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2236 // CHECK11-NEXT: ret void
2237 //
2238 //
2239 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2240 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] {
2241 // CHECK11-NEXT: entry:
2242 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2243 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2244 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2245 // CHECK11: arraydestroy.body:
2246 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2247 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2248 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2249 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2250 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2251 // CHECK11: arraydestroy.done1:
2252 // CHECK11-NEXT: ret void
2253 //
2254 //
2255 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2256 // CHECK11-SAME: () #[[ATTR0]] {
2257 // CHECK11-NEXT: entry:
2258 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2259 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2260 // CHECK11-NEXT: ret void
2261 //
2262 //
2263 // CHECK11-LABEL: define {{[^@]+}}@main
2264 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
2265 // CHECK11-NEXT: entry:
2266 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2267 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2268 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
2269 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2270 // CHECK11-NEXT: ret i32 0
2271 //
2272 //
2273 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2274 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2275 // CHECK11-NEXT: entry:
2276 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2277 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2278 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2279 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2280 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2281 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2282 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
2283 // CHECK11-NEXT: ret void
2284 //
2285 //
2286 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2287 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2288 // CHECK11-NEXT: entry:
2289 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2290 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2291 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2292 // CHECK11-NEXT: ret void
2293 //
2294 //
2295 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2296 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2297 // CHECK11-NEXT: entry:
2298 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2299 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2300 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2301 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2302 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2303 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2304 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2305 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2306 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2307 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2308 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
2309 // CHECK11-NEXT: ret void
2310 //
2311 //
2312 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
2313 // CHECK11-SAME: () #[[ATTR0]] {
2314 // CHECK11-NEXT: entry:
2315 // CHECK11-NEXT: call void @__cxx_global_var_init()
2316 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
2317 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
2318 // CHECK11-NEXT: ret void
2319 //
2320